A double pulse test structure for a power semiconductor

Abstract

The utility model relates to power semiconductor's test technical field especially, and more particularly to a kind of double-pulse test structure of power semiconductor, the structure includes: laminated busbar and the protection mechanism being set on the laminated busbar;The protection mechanism includes: switch tube, auxiliary diode, first accommodating groove and second accommodating groove;The switch tube is connected with the auxiliary diode, the first accommodating groove and the second accommodating groove are all set on the laminated busbar, the switch tube is located in the first accommodating groove, the auxiliary diode is located in the second accommodating groove.By the structure, avoid the failure of the device under test when double-pulse test is carried out to the device under test to exert larger voltage and current, to avoid making the test loop be in short-circuit uncontrollable state, test loop current is constantly increasing until the device burns, prevent the entire test system from burning, improve the reliability and security in the double-pulse test process to the device under test.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor testing technology, and in particular to a dual-pulse testing structure for power semiconductors. Background Technology

[0002] Currently, the circuit schematic for double-pulse testing of power semiconductor devices is as follows: Figure 1 As shown. In Figure 1 In this test, the DC power supply provides a suitable DC voltage for the main circuit. Capacitor C1 stores energy to provide a large current for the entire circuit. Transistor G1 is turned off by applying a voltage of 0 to -30V between its gate (G) and emitter (E). Transistor G2 is tested by applying two positive pulses between its gate (G) and emitter (E). During the test, applying a large voltage and current to the power semiconductor device (G2) requires a double-pulse test (i.e., a double-pulse test using a pulse generator). This can lead to device failure. A failed power semiconductor device will be in a short-circuit, uncontrollable state, causing the circuit current to increase continuously until the device burns out. This uncontrollable state can also damage the drive circuit, the test equipment, and even cause personal injury. Utility Model Content

[0003] This application provides a dual-pulse test structure for power semiconductors to at least solve the aforementioned technical problems in the prior art. It achieves the technical effect of avoiding the failure of the device under test due to the application of large voltage and current during dual-pulse testing, thereby avoiding the situation where the entire test circuit is in a short-circuit and uncontrollable state after the device under test fails, and the test circuit current continuously increases until the device burns out. It prevents the entire test circuit and the components in the test circuit from burning out, and improves the reliability and safety of the dual-pulse testing process of the device under test.

[0004] In a first aspect, this utility model provides a dual-pulse test structure for power semiconductors, comprising: a stacked busbar and a protection mechanism disposed on the stacked busbar;

[0005] The protection mechanism includes: a switching transistor, an auxiliary diode, a first receiving slot, and a second receiving slot; the switching transistor is connected to the auxiliary diode, and both the first receiving slot and the second receiving slot are formed on the stacked busbar, with the switching transistor located in the first receiving slot and the auxiliary diode located in the second receiving slot.

[0006] Optionally, the stacked busbar includes: a positive electrode metal layer, an interlayer insulating layer and a negative electrode metal layer stacked sequentially, an external insulating layer, a positive electrode input terminal and a positive electrode output terminal integrated with the positive electrode metal layer, and a negative electrode input terminal and a negative electrode output terminal integrated with the negative electrode metal layer;

[0007] The outer insulating layer encloses the positive electrode metal layer, the interlayer insulating layer, and the negative electrode metal layer;

[0008] The positive input terminal, the positive output terminal, the negative input terminal, and the negative output terminal all protrude through the outer insulating layer for electrical connection with external devices.

[0009] Optionally, the protection mechanism further includes: an electrical penetration groove, which sequentially cuts through the outer insulation layer, the positive electrode metal layer and the interlayer insulation layer, and the bottom of the electrical penetration groove is in contact with the negative electrode metal layer;

[0010] The first receiving groove is located on one side of the electrical penetration groove, and the second receiving groove is located on the other side of the electrical penetration groove. The first receiving groove and the second receiving groove penetrate the outer insulation layer, and the bottom of the first receiving groove and the second receiving groove are in contact with the positive electrode metal layer.

[0011] Optionally, the protection mechanism further includes an electrical transition groove located between the electrical penetration groove and the second receiving groove, the electrical transition groove penetrating the outer insulation layer, and the bottom of the electrical transition groove contacting the positive electrode metal layer.

[0012] Optionally, the protection mechanism further includes: an electrical metal layer located above the positive electrode metal layer and disposed on the side of the outer insulating layer away from the positive electrode metal layer, and the electrical metal layer located on the side of the first receiving groove away from the electrical penetration groove.

[0013] Optionally, the electrical metal layer includes: a control metal layer and a sampling metal layer;

[0014] The control metal layer is located on the side of the first receiving groove away from the electrical penetration groove;

[0015] The sampling metal layer is located on the side of the control metal layer away from the first receiving groove;

[0016] The protection mechanism further includes: the control terminal and sampling terminal of the switching transistor;

[0017] The control terminal is disposed on the control metal layer and is used to make electrical connections with external devices, transmit control signals, and control the state of the switching transistor based on the control signals;

[0018] The sampling terminal is disposed on the sampling metal layer and is used to make electrical connections with external devices to transmit the sampling signal of the switching transistor.

[0019] Optionally, the protection mechanism further includes: a bonding wire;

[0020] The bonding wire is disposed between the auxiliary diode and the negative metal layer at the bottom of the electrical penetration groove, for connecting the auxiliary diode and the negative metal layer at the bottom of the electrical penetration groove;

[0021] The bonding wire is disposed between the positive metal layer at the bottom of the switching transistor and the electrical transition groove, for connecting the switching transistor and the positive metal layer at the bottom of the electrical transition groove;

[0022] The bonding wire is disposed between the switching transistor and the control metal layer, and between the switching transistor and the sampling metal layer, for connecting the switching transistor to the control terminal, and connecting the switching transistor to the sampling terminal;

[0023] The bonding wires are positioned close to the positive electrode metal layer.

[0024] Optionally, it may also include: an encapsulating colloid; the encapsulating colloid encapsulates and wraps the protective mechanism.

[0025] Optional features also include: capacitor mounting holes and capacitors;

[0026] The capacitor mounting hole is configured to penetrate the stacked busbar and is located on one side of the protection mechanism;

[0027] The capacitor is disposed inside the capacitor mounting hole.

[0028] Optionally, the switching transistor is any one of the following connected in parallel: an IGBT power device and a fast recovery diode, a MOSFET power device, a silicon carbide MOSFET power device, and a gallium nitride power device; the auxiliary diode is a Schottky diode or a fast recovery diode.

[0029] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:

[0030] This embodiment of the invention integrates a switching transistor and an auxiliary diode within a stacked busbar structure, thereby integrating the protection switching circuit into the dual-pulse test circuit. Through this structure, the problem of applying excessive voltage and current to the device under test (DUT) during dual-pulse testing is solved, addressing the issue of DUT failure caused by excessive voltage and current. Furthermore, it resolves the problem of the entire test circuit becoming uncontrollable due to short circuit after DUT failure, leading to a continuous increase in current and ultimately burning out the entire circuit and system. Moreover, in... Figure 1 In existing dual-pulse test schemes, conventionally packaged IGBT devices are typically added outside the DC power supply. These conventionally packaged IGBT devices generate significant stray inductance throughout the test circuit. This stray inductance causes a high voltage spike when the device under test (DUT) is turned off. If this voltage spike exceeds the DUT's withstand voltage, it can lead to DUT failure. The structure of this embodiment avoids the large stray inductance generated by conventionally packaged IGBT devices, preventing the DUT from being subjected to overvoltage during testing and thus avoiding DUT failure. Therefore, the structure of this embodiment integrates the protection mechanism and the multilayer busbar into a single package, improving the safety and reliability of dual-pulse testing of the DUT while maintaining the low stray inductance of the multilayer busbar, without compromising its low stray inductance structure. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference figures denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 The circuit schematic for performing a double-pulse test on a power semiconductor device in the prior art is shown;

[0033] Figure 2 A schematic diagram of the overall structure of the dual-pulse test structure for power semiconductors in an embodiment of this utility model is shown.

[0034] Figure 3 A side-view cross-sectional schematic diagram of the dual-pulse test structure for power semiconductors in an embodiment of the present invention is shown.

[0035] Figure 4 This diagram shows an unpackaged schematic of a dual-pulse test structure for power semiconductors according to an embodiment of the present invention.

[0036] Figure 5 This diagram shows an unpackaged top view of the dual-pulse test structure of the power semiconductor in an embodiment of the present invention.

[0037] Figure 6 A schematic diagram of the back structure of the dual-pulse test structure of the power semiconductor in an embodiment of the present invention is shown.

[0038] Figure 7 The circuit topology diagram of the dual-pulse test structure of the power semiconductor in the embodiment of this utility model is shown.

[0039] In the attached drawings, 110 is a stacked busbar; 120 is a protection mechanism; 1301 is a capacitor mounting hole; and 1302 is a capacitor.

[0040] 111. Positive electrode metal layer; 112. Interlayer insulation layer; 113. Negative electrode metal layer; 114. External insulation layer; 115. Positive input terminal; 116. Positive output terminal; 117. Negative input terminal; 118. Negative output terminal;

[0041] 121. Switching transistor; 122. First receiving slot; 123. Auxiliary diode; 124. Second receiving slot; 125. Electrical through slot; 126. Electrical transition slot; 127. Electrical metal layer; 1271. Control metal layer; 1272. Sampling metal layer; 1281. Control terminal; 1282. Sampling terminal; 129. Bonding wire; 1201. Encapsulating colloid. Detailed Implementation

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0043] Example 1

[0044] The first embodiment of this utility model provides a dual-pulse test structure for power semiconductors, such as... Figure 2 As shown, the system includes a multilayer busbar 110 and a protection mechanism 120 disposed on the multilayer busbar 110. The protection mechanism 120 includes a switching transistor 121, an auxiliary diode 123, a first receiving groove 122, and a second receiving groove 124. The switching transistor 121 is connected to the auxiliary diode 123. Both the first receiving groove 122 and the second receiving groove 124 are formed on the multilayer busbar 110. The switching transistor 121 is located in the first receiving groove 122, and the auxiliary diode 123 is located in the second receiving groove 124.

[0045] This embodiment integrates a switching transistor 121 and an auxiliary diode 123 into the stacked busbar 110 structure to integrate the protection switching circuit into the dual-pulse test circuit. Through this structure, the problem of applying excessive voltage and current to the device under test (DUT) during dual-pulse testing is solved, addressing the issue of DUT failure caused by excessive voltage and current. Furthermore, it resolves the problem of the entire test circuit being in a short-circuit, uncontrollable state after DUT failure, leading to a continuous increase in current and ultimately burning out the entire circuit and system. Moreover, in... Figure 1 In existing dual-pulse test schemes, conventionally packaged IGBT devices are typically added outside the DC power supply. These conventionally packaged IGBT devices generate significant stray inductance throughout the test circuit. The introduction of stray inductance causes the device under test (DUT) to generate a high voltage spike when turned off. If this voltage spike exceeds the DUT's withstand voltage, it will lead to DUT failure. The structure of this embodiment avoids the large stray inductance generated by conventionally packaged IGBT devices, which could cause the DUT to be in an overvoltage state during testing, thus preventing DUT failure. Therefore, the structure of this embodiment integrates the protection mechanism 120 and the multilayer busbar 110 into a single package. This improves the safety and reliability of dual-pulse testing of the DUT while maintaining the low stray inductance of the multilayer busbar 110, without compromising its low stray inductance structure.

[0046] Below, in conjunction with Figure 2 The dual-pulse test structure for power semiconductors in this embodiment is described in detail:

[0047] In this embodiment, the switching transistor 121 can be any one of the following connected in parallel: an IGBT (Insulated Gate Bipolar Transistor) power device, a fast recovery diode (FRD diode), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) power device, a silicon carbide MOSFET power device, and a gallium nitride power device. The auxiliary diode 123 is a Schottky diode or a fast recovery diode. It should be noted that the accompanying drawings of this embodiment illustrate the example using a parallel connection of an IGBT power device and a fast recovery diode as the switching transistor 121.

[0048] like Figure 3As shown, the stacked busbar 110 includes: a positive metal layer 111, an interlayer insulating layer 112, and a negative metal layer 113 stacked sequentially; an outer insulating layer 114; a positive input terminal 115 and a positive output terminal 116 integrated with the positive metal layer 111; and a negative input terminal 117 and a negative output terminal 118 integrated with the negative metal layer 113. The outer insulating layer 114 covers the positive metal layer 111, the interlayer insulating layer 112, and the negative metal layer 113. The positive input terminal 115, the positive output terminal 116, the negative input terminal 117, and the negative output terminal 118 all protrude through the outer insulating layer 114 for electrical connection with external devices. Specifically, as shown... Figure 3 As shown, the positive input terminal 115 is located at one end of the positive metal layer 111, and the positive output terminal 116 is located at the other end of the positive metal layer 111, with the positive input terminal 115 and the positive output terminal 116 corresponding to each other. Similarly, the negative input terminal 117 is located at one end of the negative metal layer 113, and the negative output terminal 118 is located at the other end of the negative metal layer 113, with the negative input terminal 117 and the negative output terminal 118 corresponding to each other. The positive input terminal 115 and the negative input terminal 117 are located on the same side of the stacked busbar 110, and the positive output terminal 116 and the negative output terminal 118 are located on the corresponding other side of the stacked busbar 110.

[0049] In this embodiment, the stacked busbar 110 is constructed by laminating a multi-layer composite structure consisting of an insulating layer, a conductive layer (i.e., a metal layer), an insulating layer, a conductive layer, and an insulating layer together. The structure of the stacked busbar 110 reduces the spacing between the positive and negative conductive layers (i.e., the positive metal layer 111 and the negative metal layer 113), further reducing the area of ​​the entire test circuit and thus lowering stray inductance.

[0050] like Figure 3 and Figure 4 As shown, the protection mechanism 120 also includes an electrical penetration groove 125. The electrical penetration groove 125 sequentially cuts through the outer insulating layer 114, the positive electrode metal layer 111, and the interlayer insulating layer 112, with the bottom of the electrical penetration groove 125 contacting the negative electrode metal layer 113. Specifically, the electrical penetration groove 125 is a dividing groove, dividing the positive electrode metal layer 111 into two completely independent left and right parts. An insulating film or encapsulating colloid is attached to the inner wall of the electrical penetration groove 125 to provide insulation. The lateral length of the interlayer insulating layer 112 is greater than the lateral length of the electrical penetration groove 125 to achieve insulation between the positive electrode metal layer 111 and the negative electrode metal layer 113 within the electrical penetration groove 125. The electrical penetration groove 125 is used to electrically connect the auxiliary diode 123 to the negative electrode metal layer 113 at the bottom of the electrical penetration groove 125 via a bonding wire 129.

[0051] The first receiving slot 122 is located on one side of the electrical through slot 125, and the second receiving slot 124 is located on the other side of the electrical through slot 125. The first receiving slot 122 and the second receiving slot 124 penetrate the outer insulating layer 114, and their bottoms contact the positive electrode metal layer 111. Specifically, the first receiving slot 122 is located between the electrical through slot 125 and the positive input terminal 115, and the second receiving slot 124 is located between the electrical through slot 125 and the positive output terminal 116. The first receiving slot 122 houses the soldered switching transistor 121, and the second receiving slot 124 houses the soldered auxiliary diode 123, eliminating the height difference caused by the packaging and reducing stray inductance. This makes wiring between devices more convenient and the circuit simpler. In this embodiment, taking the switching transistor 121 as an IGBT power device and an FRD diode connected in parallel as an example, for each switching transistor 121, there are two first receiving slots 122, one housing the IGBT device and the other housing the FRD diode. If we take the switching transistor 121 as a MOSFET power device in this embodiment as an example, for each switching transistor 121, there is one first receiving slot 122, which can accommodate the MOSFET power device.

[0052] like Figure 3 and Figure 4 As shown, the protection mechanism 120 further includes an electrical transition groove 126. The electrical transition groove 126 is located between the electrical through groove 125 and the second receiving groove 124. The electrical transition groove 126 penetrates the outer insulating layer 114, and its bottom contacts the positive electrode metal layer 111. The electrical transition groove 126 is used to electrically connect the switching transistor 121 to the positive electrode metal layer 111 at the bottom of the electrical transition groove 126 via a bonding wire 129. In this embodiment, the switching transistor 121 is an IGBT power device and a fast recovery diode connected in parallel. The IGBT power device in the first receiving groove 122 is electrically connected to the positive electrode metal layer 111 at the bottom of the electrical transition groove 126 via the bonding wire 129. Through the setting of the electrical transition groove 126 in this embodiment, the current of the device under test flows through the IGBT device and other switching transistors 121 to the positive electrode metal layer 111, achieving electrical connection and transition, ensuring the functional integrity of the stacked busbar 110.

[0053] The protection mechanism 120 further includes an electrical metal layer 127. The electrical metal layer 127 is located above the positive electrode metal layer 111 and is disposed on the side of the outer insulating layer 114 away from the positive electrode metal layer 111, and on the side of the first receiving groove 122 away from the electrical through groove 125. Specifically, the electrical metal layer 127 is disposed on the outer insulating layer 114 above the positive electrode metal layer 111 and is located between the first receiving groove 122 and the positive input terminal 115. The electrical metal layer 127 is used to control and sample the switching transistor 121 by providing the control terminal 1281 and the sampling terminal 1282 of the switching transistor 121.

[0054] like Figures 3-5 As shown, the electrical metal layer 127 includes a control metal layer 1271 and a sampling metal layer 1272. The control metal layer 1271 is located on the side of the first receiving groove 122 away from the electrical through groove 125, that is, the control metal layer 1271 is located between the first receiving groove 122 and the positive input terminal 115. The sampling metal layer 1272 is located on the side of the control metal layer 1271 away from the first receiving groove 122, that is, the sampling metal layer 1272 is located between the control metal layer 1271 and the positive input terminal 115.

[0055] The protection mechanism 120 further includes a control terminal 1281 and a sampling terminal 1282 for the switching transistor 121. The control terminal 1281 is disposed on the control metal layer 1271 and is used for electrical connection with external devices, transmitting control signals, and controlling the state of the switching transistor 121 based on the control signals. The sampling terminal 1282 is disposed on the sampling metal layer 1272 and is used for electrical connection with external devices to transmit sampling signals from the switching transistor 121. The control terminal 1281 and the sampling terminal 1282 can be in the form of pins.

[0056] This embodiment uses a parallel-connected IGBT power device (switch 121) and an FRD diode as an example. The control metal layer 1271 is electrically connected to the IGBT device via bonding wire 129, allowing control of the IGBT device's state via control terminal 1281. Similarly, the sampling metal layer 1272 is electrically connected to the FRD diode via bonding wire 129, allowing sampling of the IGBT device via sampling terminal 1282. The IGBT device and the FRD diode are electrically connected via bonding wire 129. Control terminal 1281 is presented as the gate (G) of the IGBT device, and sampling terminal 1282 is presented as the emitter (E) of the IGBT device.

[0057] This embodiment forms a complete structure for the switching transistor 121 by configuring the switching transistor 121, the control metal layer 1271, the sampling metal layer 1272, the control terminal 1281, and the sampling terminal 1282, thereby realizing the function of the switching transistor 121. Combined with the auxiliary diode 123, a protection switching circuit is integrated in the stacked busbar 110. During the double-pulse test of the device under test (DUT), the problem of DUT failure caused by applying large voltages and currents is solved. Furthermore, it solves the problem that after DUT failure, the entire test circuit becomes short-circuited and uncontrollable, leading to a continuous increase in current and ultimately burning out the entire circuit and system. Moreover, in the case of… Figure 1 In existing dual-pulse test schemes, conventionally packaged IGBT devices are typically added outside the DC power supply. Because these devices have large packages, long pins, and excessively wide or narrow pin distributions, they introduce significant stray inductance when inserted into the test circuit. This stray inductance causes a high voltage spike when the device under test (DUT) is turned off. If this voltage spike exceeds the DUT's withstand voltage, it can lead to DUT failure. The structure of this embodiment avoids the large stray inductance generated by conventionally packaged IGBT devices, preventing the DUT from being in an overvoltage state during testing and thus avoiding DUT failure. Therefore, this embodiment integrates the protection mechanism 120 and the multilayer busbar 110 into a single package, improving the safety and reliability of dual-pulse testing of the DUT while maintaining the low stray inductance of the multilayer busbar 110, without compromising its low stray inductance structure.

[0058] like Figure 3 and Figure 5 As shown, the protection mechanism 120 further includes: a bonding wire 129. The bonding wire 129 is disposed between the auxiliary diode 123 and the negative metal layer 113 at the bottom of the electrical through-slot 125, for connecting the auxiliary diode 123 and the negative metal layer 113 at the bottom of the electrical through-slot 125. The bonding wire 129 is disposed between the switching transistor 121 and the positive metal layer 111 at the bottom of the electrical transition slot 126, for connecting the switching transistor 121 and the positive metal layer 111 at the bottom of the electrical transition slot 126. The bonding wire 129 is disposed between the switching transistor 121 and the control metal layer 1271, and between the switching transistor 121 and the sampling metal layer 1272, for connecting the switching transistor 121 to the control terminal 1281, and connecting the switching transistor 121 to the sampling terminal 1282. The bonding wire 129 is positioned close to the positive metal layer 111. During the connection and binding process, the bonding wire 129 needs to have its height and span reduced so that it is as close as possible to the positive metal layer 111. This reduces the current loop area and improves test reliability and stability. This reasonable wiring enables the integrated protection switch circuit in the stacked busbar 110, simplifies the circuit, and improves the circuit integration.

[0059] The dual-pulse test structure for power semiconductors in this embodiment further includes an encapsulating colloid 1201. The encapsulating colloid 1201 encapsulates and protects the protection mechanism 120. Specifically, the encapsulating colloid 1201 partially encapsulates the area from the auxiliary diode 123 to the sampling metal layer 1272, thereby achieving encapsulation of the entire protection mechanism 120. The control terminal 1281 and the sampling terminal 1282 pass through the encapsulating colloid 1201 to achieve connection with external devices. The encapsulating colloid 1201 not only provides structural protection for the protection mechanism 120 and stabilizes its structure, but also strengthens the insulation of the protection mechanism 120, improving its safety, electrical performance, and reliability.

[0060] The dual-pulse test structure for power semiconductors in this embodiment further includes: a capacitor mounting hole 1301 and a capacitor 1302. The capacitor mounting hole 1301 is disposed through the stacked busbar 110 and is located on one side of the protection mechanism 120. Figures 4-6 As shown, the capacitor mounting hole 1301 is located between the protection mechanism 120 and the positive input terminal 115, and extends through the stacked busbar 110. The capacitor 1302 is located inside the capacitor mounting hole 1301.

[0061] For example, the materials of the positive electrode metal layer 111, negative electrode metal layer 113, and electrical metal layer 127 in this application include, but are not limited to, copper, copper alloy, aluminum, and aluminum alloy. The thickness of the positive electrode metal layer 111 and the negative electrode metal layer 113 is the same, and can be calculated according to the current carrying capacity, preferably set to 1mm-3mm. The electrical metal layer 127 is set on the outer insulating layer 114 above the positive electrode metal layer 111 by a polyimide film and an adhesive resin (the adhesive resin is not required if a hot pressing process is used). The thickness of the electrical metal layer 127 is preferably 0.5mm-1.5mm, but can also be set according to actual needs. The interlayer insulating layer 112 is an insulating film, such as polyester film, polyimide film, polyethylene naphthalate film, polyamide-imide film, or epoxy resin. The polyester film can be directly pressed together with the metal by a hot pressing process without additional adhesive. In this embodiment, it is preferably set to hot pressing of polyimide film, and its thickness is preferably 0.025mm-0.15mm.

[0062] Taking the IGBT device and FRD diode connected in parallel by switching transistor 121, and the FRD diode by auxiliary diode 123 as an example, as follows: Figure 7The circuit topology diagram of the dual-pulse test structure for power semiconductors in this embodiment is shown. Capacitor C3 is capacitor 1302 located on the stacked busbar 110, and the FRD diode below the IGBT device and the FRD diode is auxiliary diode 123 connected in parallel. By directly soldering the IGBT device, FRD diode, and other chips onto the metal layer of the stacked busbar 110, the current loop follows the sequence of positive input (positive input terminal 115) of capacitor 1302 – positive output terminal 116 – negative output terminal 118 – negative input (negative input terminal 117) of capacitor 1302, reducing the path area and loop strays. The structural design of this embodiment reduces the package stray inductance during application and improves the stray performance of the test system. Compared to traditional busbars, the stacked busbar 110 in this embodiment adds protection functions, realizing an integrated protection circuit-busbar design, simplifying the test system, improving the overall structural system safety, and retaining low stray inductance characteristics. This embodiment adopts an integrated design of protection structure and stacked busbar 110, which improves system integration and reduces the overall size compared with traditional packaging structure. It can solve the problem that adding protection circuit to test system will greatly increase system stray emissions.

[0063] The application of the dual-pulse test structure for power semiconductors in this embodiment involves directly connecting the entire structure to the device under test (DUT) to perform dual-pulse testing. This demonstrates the advantages of this embodiment, including ease of use, high test reliability, and high test safety.

[0064] Furthermore, the stacked busbar 110 in this embodiment can be replaced with a multi-layer PCB board, resulting in lower costs. Simultaneously, when using a multi-layer PCB board as the substrate, copper clip packaging technology can be used instead of aluminum wire bonding technology for the chip, achieving lower loop straying. For example, a three-layer PCB board (i.e., a stacked positive metal layer 111 + interlayer insulating layer 112 + negative metal layer 113) has the same structure as the stacked busbar 110. The principle of integrating the protection circuit of this embodiment on this PCB board is the same as the principle of integrating the protection circuit of this embodiment on the stacked busbar 110, and will not be repeated here. A four-layer PCB board, i.e., a PCB board containing four metal layers, can have the bottom layer being the negative metal layer. Based on the principle and structure of integrating the protection circuit of this embodiment on the stacked busbar 110, the remaining three layers can be set according to actual needs.

[0065] One or more technical solutions in the embodiments of this utility model have at least the following technical effects or advantages:

[0066] This embodiment adopts an integrated packaging design for the stacked busbar and IGBT devices. While maintaining the stray inductance of the stacked busbar structure, the protection switching circuit (i.e., the protection mechanism formed by the switching transistor and auxiliary diode) is integrated into the test circuit, which improves the safety of the double-pulse test without damaging the low stray inductance structure of the stacked busbar.

[0067] The overall structural design of this embodiment reduces stray inductance during application and improves the stray performance of the test system. Compared to traditional busbars, this embodiment adds protection functions, improving the overall structural system safety while retaining the low stray inductance characteristic. The overall structural design of this embodiment adopts an integrated design of the protection mechanism and the stacked busbar, improving the system integration and reducing the overall size compared to traditional packaging technology. This solves the problem that adding protection circuitry to the test system would significantly increase stray inductance.

[0068] Those skilled in the art will understand that although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0069] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. A dual-pulse test structure for power semiconductors, characterized in that, include: A stacked busbar and a protective mechanism disposed on the stacked busbar; The protection mechanism includes: a switching transistor, an auxiliary diode, a first receiving slot, and a second receiving slot; The switching transistor is connected to the auxiliary diode. Both the first and second receiving slots are formed on the stacked busbar. The switching transistor is located in the first receiving slot, and the auxiliary diode is located in the second receiving slot.

2. The dual-pulse test structure for power semiconductors as described in claim 1, characterized in that, The stacked busbar includes: a positive metal layer, an interlayer insulating layer and a negative metal layer stacked sequentially, an external insulating layer, a positive input terminal and a positive output terminal integrated with the positive metal layer, and a negative input terminal and a negative output terminal integrated with the negative metal layer; The outer insulating layer encloses the positive electrode metal layer, the interlayer insulating layer, and the negative electrode metal layer; The positive input terminal, the positive output terminal, the negative input terminal, and the negative output terminal all protrude through the outer insulating layer for electrical connection with external devices.

3. The dual-pulse test structure for power semiconductors as described in claim 2, characterized in that, The protection mechanism further includes an electrical penetration groove, which sequentially cuts off the outer insulation layer, the positive electrode metal layer and the interlayer insulation layer, and the bottom of the electrical penetration groove is in contact with the negative electrode metal layer; The first receiving groove is located on one side of the electrical penetration groove, and the second receiving groove is located on the other side of the electrical penetration groove. The first receiving groove and the second receiving groove penetrate the outer insulation layer, and the bottom of the first receiving groove and the second receiving groove are in contact with the positive electrode metal layer.

4. The dual-pulse test structure for power semiconductors as described in claim 3, characterized in that, The protection mechanism further includes an electrical transition groove located between the electrical penetration groove and the second receiving groove, the electrical transition groove penetrating the outer insulation layer, and the bottom of the electrical transition groove contacting the positive electrode metal layer.

5. The dual-pulse test structure for power semiconductors as described in claim 4, characterized in that, The protection mechanism further includes: an electrical metal layer located above the positive electrode metal layer and disposed on the side of the outer insulating layer away from the positive electrode metal layer, and the electrical metal layer located on the side of the first receiving groove away from the electrical penetration groove.

6. The dual-pulse test structure for power semiconductors as described in claim 5, characterized in that, The electrical metal layer includes: a control metal layer and a sampling metal layer; The control metal layer is located on the side of the first receiving groove away from the electrical penetration groove; The sampling metal layer is located on the side of the control metal layer away from the first receiving groove; The protection mechanism further includes: the control terminal and sampling terminal of the switching transistor; The control terminal is disposed on the control metal layer and is used to make electrical connections with external devices, transmit control signals, and control the state of the switching transistor based on the control signals; The sampling terminal is disposed on the sampling metal layer and is used to make electrical connections with external devices to transmit the sampling signal of the switching transistor.

7. The dual-pulse test structure for power semiconductors as described in claim 6, characterized in that, The protection mechanism also includes: bonding wire; The bonding wire is disposed between the auxiliary diode and the negative metal layer at the bottom of the electrical penetration groove, for connecting the auxiliary diode and the negative metal layer at the bottom of the electrical penetration groove; The bonding wire is disposed between the positive metal layer at the bottom of the switching transistor and the electrical transition groove, for connecting the switching transistor and the positive metal layer at the bottom of the electrical transition groove; The bonding wire is disposed between the switching transistor and the control metal layer, and between the switching transistor and the sampling metal layer, for connecting the switching transistor to the control terminal, and connecting the switching transistor to the sampling terminal; The bonding wires are positioned close to the positive electrode metal layer.

8. The dual-pulse test structure for power semiconductors as described in any one of claims 1-7, characterized in that, Also includes: Encapsulating colloid; The encapsulating colloid encapsulates and wraps the protective mechanism.

9. The dual-pulse test structure for power semiconductors as described in any one of claims 1-7, characterized in that, Also includes: Capacitor mounting holes and capacitors; The capacitor mounting hole is configured to penetrate the stacked busbar and is located on one side of the protection mechanism; The capacitor is disposed inside the capacitor mounting hole.

10. The dual-pulse test structure for power semiconductors as described in any one of claims 1-7, characterized in that, The switching transistor is any one of the following connected in parallel: IGBT power device and fast recovery diode, MOSFET power device, silicon carbide MOSFET power device and gallium nitride power device; the auxiliary diode is a Schottky diode or a fast recovery diode.

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