Stacked package structure and computing system

Abstract

The application relates to a stacked packaging structure and a computing system, the stacked packaging structure comprising: a first substrate comprising a first surface and a second surface facing away from each other, the first surface being provided with first pads, the second surface being provided with second pads, and the first substrate being provided with first wirings; a plurality of first chips being welded to the first pads, the first chips being interconnected through the corresponding first pads and the first wirings; a second substrate comprising a third surface and a fourth surface, the third surface being provided with third pads, the fourth surface being provided with fourth pads, and the second substrate being provided with second wirings; a plurality of second chips being welded to the fourth pads, the second chips being interconnected through the corresponding fourth pads and the second wirings; and a ring-shaped interposer being arranged between the first substrate and the second substrate, and interconnecting the first substrate and the second substrate through the ring-shaped interposer. The signal integrity is improved, and the power consumption and warping are reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to a stacked packaging structure and a computing system. Background Technology

[0002] Due to the rapid development of technologies such as Artificial Intelligence (AI), server systems can be built using a multi-chip architecture, including memory chips (such as High Bandwidth Memory (HBM), Random Access Memory (RAM), and Non-Volatile Hard Disk (NAND SSD) for processing exponentially growing data), processor chips (such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), and Deep Computing Unit (DCU)), Application Specific Integrated Circuit (ASIC), Integrated Voltage Regulator (IVR), and Field Programmable Gate Array (FPGA).

[0003] Currently, key components such as processor chips and memory chips are first packaged and then integrated onto a large motherboard, where they are interconnected to form a complete server system. However, this approach can lead to signal integrity issues, higher power consumption, and warping problems. Utility Model Content

[0004] Based on this, this application provides a stacked packaging structure and computing system that can improve signal integrity and reduce power consumption and warpage.

[0005] In a first aspect, embodiments of this application provide a stacked packaging structure, including:

[0006] A first substrate includes a first surface and a second surface that are opposite to each other. The first surface has a plurality of discrete first pads, and the second surface has a plurality of discrete second pads. The first substrate has a first trace that electrically connects the corresponding first pads to each other and the corresponding first pads to the second pads.

[0007] Multiple first chips are soldered to corresponding first pads on a first surface, and the first chips are interconnected through corresponding first pads and first traces;

[0008] The second substrate, located below the first substrate, includes a third surface and a fourth surface facing away from each other, with the third surface facing the second surface. The third surface has a plurality of discrete third pads, and the fourth surface has a plurality of discrete fourth pads. The second substrate has a second trace that interconnects the corresponding fourth pads with each other and the corresponding third pads with each fourth pad.

[0009] Multiple second chips are soldered to corresponding fourth pads on the fourth surface, and the second chips are interconnected through corresponding fourth pads and second traces.

[0010] An annular interposer, located between a first substrate and a second substrate, includes a fifth surface and a sixth surface facing away from each other. The fifth surface faces the second surface and has a plurality of discrete fifth pads. The sixth surface has a plurality of discrete sixth pads. A third trace is provided in the annular interposer to electrically connect the corresponding fifth and sixth pads. The fifth pads are soldered to the corresponding second pads, and the sixth pads are soldered to the corresponding third pads, thereby interconnecting the first substrate and the second substrate.

[0011] In some embodiments of this application, the first substrate also has a plurality of discrete first vias penetrating the first surface and the second surface;

[0012] The stacked packaging structure further includes: a first fixing component, the first fixing component including a first backplate, a first connector and a first support, the first backplate being disposed on the second surface, the first support being disposed on the first surface, and the first connector passing through the first through hole and fixing the first support and the first backplate;

[0013] The stacked package structure further includes: a first heat sink, which is fixed on a first support member, and the side of the first heat sink near the first substrate is in contact with the surface of the first chip away from the first substrate.

[0014] In some embodiments of this application, the surface of the first support member that is away from the first substrate is higher than the surface of the first chip that is away from the first substrate, and the first support member includes an annular structure, and the first support member surrounds at least one first chip.

[0015] The side of the first heat sink closest to the first substrate contacts the surface of the first chip furthest from the first substrate through a thermal interface material.

[0016] In some embodiments of this application, the first connector includes a first bolt, which includes a male head and a female head located at both ends;

[0017] The first support member has a first screw hole at one end near the first substrate and a second screw hole at one end away from the first substrate. The female head of the first bolt passes through the first through hole and is screwed into the first screw hole, and the male head of the first bolt is fixed to the first back plate.

[0018] The first radiator has a second through-hole that extends through the upper and lower surfaces;

[0019] The first fixing component further includes a second bolt, which passes through a second through hole in the first radiator and is screwed into a second screw hole in the first support member to fix the first radiator.

[0020] In some embodiments of this application, the first connector includes a first bolt, which includes a male head and a female head located at both ends;

[0021] The first support member has a third through hole that extends through the upper and lower surfaces;

[0022] The first heat sink has a third screw hole on the side near the first substrate;

[0023] The female head of the first bolt passes through the first through hole and the third through hole and is screwed into the third screw hole to fix the first radiator.

[0024] In some embodiments of this application, the second substrate also has a plurality of discrete fourth vias penetrating the third and fourth surfaces;

[0025] The stacked packaging structure also includes: a second fixing component, which includes a second backplate, a second connector and a second support, the second backplate being disposed on a third surface, the second support being disposed on a fourth surface, and the second connector passing through a fourth via and fixing the second support and the second backplate.

[0026] The stacked package structure also includes a second heat sink, which is fixed on the second support member, and the side of the second heat sink near the second substrate is in contact with the surface of the second chip away from the second substrate.

[0027] In some embodiments of this application, the surface of the second support member that is away from the second substrate is higher than the surface of the second chip that is away from the second substrate, and the second support member includes an annular structure and surrounds at least one second chip.

[0028] The side of the second heat sink closest to the second substrate contacts the surface of the second chip furthest from the second substrate through a thermal interface material.

[0029] In some embodiments of this application, the second connector includes a third bolt, which includes a male head and a female head located at both ends;

[0030] The second support member has a fourth screw hole at one end near the second substrate and a fifth screw hole at one end away from the second substrate. The female head of the third bolt passes through the fourth through hole and is screwed into the fourth screw hole. The male head of the third bolt is fixed to the second back plate.

[0031] The second radiator has a fifth through hole that runs through the upper and lower surfaces;

[0032] The second fixing component also includes a fourth bolt, which passes through a fifth through hole in the radiator and is screwed into a fifth screw hole in the second support member to fix the second radiator.

[0033] In some embodiments of this application, the second connector includes a third bolt, which includes a male head and a female head located at both ends;

[0034] The second support member has a sixth through hole that extends through both the upper and lower surfaces;

[0035] The second heat sink has a sixth screw hole on the side closest to the first substrate;

[0036] The female head of the third bolt passes through the fourth and sixth through holes and is screwed into the sixth screw hole to fix the second radiator.

[0037] In some embodiments of this application, the annular interposer includes a cutout area and an annular body area surrounding the cutout area, with the fifth pad, the sixth pad, and the third trace located in the annular body area.

[0038] In some embodiments of this application, the annular intermediate plate further includes a blank area surrounding the outer side of the annular body region and connected to the outer side wall of the annular body region. The outer side wall of the blank area extends beyond the outer side walls of the first substrate and the second substrate. The blank area is used to fix the annular intermediate plate by pressing a jig onto the fifth and sixth surfaces of the blank area during the fabrication of the stacked packaging structure.

[0039] In some embodiments of this application, at least a portion of the first chips do not have a packaging substrate; the plurality of first chips include one or a combination of: a central processing unit chip, an input / output interface chip, a first integrated power chip, a random access memory chip, a non-volatile memory chip, and an optoelectronic co-package chip;

[0040] Furthermore, neither the central processing unit chip nor the input / output interface chip has a packaging substrate.

[0041] In some embodiments of this application, at least a portion of the second chips do not have a packaging substrate; the plurality of second chips include one or a combination of: a deep computing processor chip, a switching chip, and a second integrated power chip;

[0042] Furthermore, neither the deep computing processor chip nor the switching chip has a packaging substrate.

[0043] In some embodiments of this application, the stacked packaging structure further includes:

[0044] The first decoupling capacitor is soldered to the second pad corresponding to the second surface of the first substrate;

[0045] The second decoupling capacitor is soldered to the third pad corresponding to the third surface of the second substrate.

[0046] In some embodiments of this application, the stacked packaging structure further includes:

[0047] The first connector is soldered to a first pad corresponding to a first surface of the first substrate;

[0048] The second connector is soldered to the fourth pad corresponding to the fourth surface of the second substrate.

[0049] In some embodiments of this application, the first substrate and the second substrate include an add-on substrate, and the first substrate includes a first core board and a first add-on wiring layer and a second add-on wiring layer respectively located on both sides of the first core board.

[0050] The second substrate includes a second core board and a third and a fourth additional wiring layer located on both sides of the second core board, respectively.

[0051] In some embodiments of this application, the first substrate and the second substrate are square substrates. The length of the first substrate ranges from 100mm to 650mm, the width of the first substrate ranges from 100mm to 650mm, the length of the second substrate ranges from 100mm to 650mm, and the width of the second substrate ranges from 100mm to 650mm.

[0052] In a first aspect, embodiments of this application also provide a computing system, including:

[0053] The aforementioned stacked packaging structure.

[0054] The embodiments of this application may have, or at least have, the following advantages:

[0055] This application embodiment includes a stacked packaging structure and a computing system. The stacked packaging structure includes: a first substrate, the first substrate including a first surface and a second surface facing away from each other, the first surface having a plurality of discrete first pads, the second surface having a plurality of discrete second pads, and a first trace in the first substrate electrically connecting corresponding first pads to each other and corresponding first pads to second pads; a plurality of first chips, respectively soldered to corresponding first pads on the first surface, the first chips being interconnected through corresponding first pads and first traces; and a second substrate located below the first substrate, the second substrate including a third surface and a fourth surface facing away from each other, the third surface having a plurality of discrete third pads, and the fourth surface having a plurality of discrete... The second substrate has a fourth pad and a second trace, which interconnects the corresponding fourth pads with each other and with the corresponding third pads with the fourth pad. Multiple second chips are soldered to corresponding fourth pads on the fourth surface, and are interconnected via corresponding fourth pads and second traces. An annular interposer is located between the first and second substrates, including a fifth and a sixth surface facing away from each other. The fifth surface faces the second surface and has multiple discrete fifth pads. The sixth surface has multiple discrete sixth pads. The annular interposer has a third trace, which electrically connects the corresponding fifth and sixth pads. The fifth pad is soldered to the corresponding second pad, and the sixth pad is soldered to the corresponding third pad, interconnecting the first and second substrates. Since at least a portion of the first chips are not soldered to the first substrate through the packaging substrate, but are directly soldered to the first substrate, and the first traces in the first substrate interconnect the corresponding first chips, there are no via connection structures in the packaging substrate or ball grid arrays on the surface of the packaging substrate in the signal link from the first chip to the first substrate in this application. This reduces impedance discontinuities in the signal link, avoids a large number of reflections, thereby ensuring the integrity of the signal and power supply, and also reduces the length of the signal link, thereby reducing the loss in the signal link. In addition, since the first chip does not need to be soldered to the packaging substrate and does not need to form a ball grid array, at least one reflow process can be reduced, thus preventing warping of the first substrate caused by multiple reflow processes.

[0056] Furthermore, since at least a portion of the second chips are not soldered to the second substrate through the packaging substrate, but are directly soldered to the second substrate, and the second traces in the second substrate interconnect the corresponding second chips, including signal interconnection between the second chips and power / ground interconnection between the second chips, there are no via connection structures in the packaging substrate or ball grid arrays on the surface of the packaging substrate in the signal link from the second chip to the second substrate in this application. This reduces impedance discontinuities in the signal link, avoids a large number of reflections, thereby ensuring the integrity of the signal and power, and also reduces the length of the signal link, thereby reducing the loss in the signal link. In addition, since the second chips do not need to be soldered to the packaging substrate and do not need to form a ball grid array, at least one reflow process can be reduced, thus preventing warping of the second substrate caused by multiple reflow processes.

[0057] Furthermore, the stacked packaging structure also includes an annular interposer plate, which interconnects the first substrate and the second substrate. The third wiring in the annular interposer plate can have a high wiring density to facilitate the interconnection between the first substrate and the second substrate. The annular interposer plate also serves to support the first substrate and the second substrate.

[0058] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a cross-sectional schematic diagram of a stacked packaging structure provided in some embodiments of this application;

[0061] Figure 2 A cross-sectional view of the first substrate in a stacked packaging structure provided in some embodiments of this application;

[0062] Figure 3 This is a top view of the first surface of the first substrate in a stacked packaging structure provided in some embodiments of this application;

[0063] Figure 4 A bottom view of the second surface of the first substrate in a stacked packaging structure provided in some embodiments of this application;

[0064] Figure 5A schematic cross-sectional view of the second substrate in a stacked packaging structure provided in some embodiments of this application;

[0065] Figure 6 A top view of the third surface of the second substrate in a stacked packaging structure provided in some embodiments of this application;

[0066] Figure 7 A bottom view of the fourth surface of the second substrate in a stacked packaging structure provided in some embodiments of this application;

[0067] Figure 8 This is a cross-sectional view of the stacked packaging structure provided in some embodiments of this application when the first and second heat sinks are not installed.

[0068] Figure 9 This is a top view of the fifth surface of the annular interposer in a stacked packaging structure provided in some embodiments of this application.

[0069] Figure 10 This is a bottom view of the sixth surface of the annular interposer in a stacked packaging structure provided in some embodiments of this application.

[0070] Explanation of reference numerals in the attached figures:

[0071] First substrate-101; First core board-101a; First add-on wiring layer-101b; Second add-on wiring layer-101c; First trace-102; First chip-103; Central processing unit chip-103a, Input / output interface chip-103b, Non-volatile memory chip-103c, First integrated power chip-103d, Random access memory chip-103e, and Optoelectronic co-packaged chip-103f; First backplane-104; First connector-105; First support member-106; First fixing component-107; First soldering protrusion-108; First connector-109; Second bolt-110; First heat sink-111;

[0072] Second substrate - 201; Second trace - 202; Second chip - 203; Depth computing processor chip - 203a, Switching chip - 203b, Second integrated power chip - 203c; Second backplane - 204; Second connector - 205; Second support component - 206; Second fixing assembly - 207; Second welding protrusion - 208; Second connector - 209; Fourth bolt - 210; Second heat sink - 211;

[0073] Annular intermediate plate-301; Annular body area-301a; Hollowed-out area-301b; Blank area-301c; Fifth pad-302; Sixth pad-303;

[0074] First surface -11; Second surface -12; Third surface -23; Fourth surface -24; Fifth surface -35; Sixth surface -36. Detailed Implementation

[0075] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0076] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0077] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0078] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0079] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0080] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but should include shape deviations due to, for example, manufacturing techniques.

[0081] In current server system construction, key components such as processor chips and memory chips are first packaged on their respective substrates, and then integrated onto a large motherboard. These components are then interconnected on the motherboard to form a complete server system. However, this approach has the following drawbacks:

[0082] I. Key components such as processor chips (CPU and DCU) and memory chips (RAM, NAND SSD, HBM) require a large amount of data transmission, placing extremely high demands on data bandwidth and speed. However, high-speed signals are very sensitive to impedance discontinuities in the link. In existing solutions, both processor chips (CPU and DCU) and memory chips (RAM, NAND SSD, HBM) need to be soldered onto the corresponding packaging substrate, and via connection structures are formed in the packaging substrate, as well as a ball grid array (BGA) is formed on one surface of the packaging substrate. The corresponding signals and power supplies in the processor chip (or memory chip) can be brought out through the packaging substrate and the ball grid array. Furthermore, the packaging substrate can also be used to integrate the processor chip (or memory chip) with other devices. However, since the via connection structure and the ball grid array are impedance discontinuities in the signal link, they will cause a large number of reflections, resulting in high-speed signal integrity problems.

[0083] Second, the clock speed and computing power of key components such as processor chips (CPU and DCU) have increased significantly, and the power consumption required has increased significantly to hundreds of watts or even thousands of watts. The corresponding supply current has also increased significantly to hundreds of amperes or even thousands of amperes. Due to the need for additional packaging substrates, the length of the power supply link has increased, which in turn has increased significantly. According to the power formula, the power loss of the link is equal to the DC resistance multiplied by the square of the current. Therefore, the DC power loss brought by the link is proportional to the square of the current. Even if the link is only tens of milliohms or even a few milliohms, the loss of the link will reach tens of watts.

[0084] Third, existing key components require an additional packaging substrate for encapsulation before being integrated onto the motherboard. The packaging substrate undergoes a high-temperature soldering process (soldering the pads of the key components onto the substrate), and integration onto the motherboard requires another high-temperature soldering process (soldering the ball grid array from the packaging substrate onto the motherboard). As the integration density of processor chips (CPU and DCU) increases, their area also grows. Each high-temperature soldering process leads to greater warpage of the chip and package, significantly increasing reliability risks and reducing yield.

[0085] Therefore, embodiments of this application provide a stacked packaging structure. Figure 1 This is a three-dimensional structural diagram of a stacked packaging structure provided in some embodiments of this application.

[0086] refer to Figure 1 Stacked packaging structure, including:

[0087] A first substrate 101 includes a first surface 11 and a second surface 12 that are opposite to each other. The first surface 11 has a plurality of discrete first pads (not shown in the figure), and the second surface 12 has a plurality of discrete second pads (not shown in the figure). The first substrate 101 has a first trace 102 that electrically connects the corresponding first pads to each other and the corresponding first pads to the second pads.

[0088] Multiple first chips 103 are soldered to corresponding first pads on the first surface 11, and the first chips 103 are interconnected through corresponding first pads and first traces 102.

[0089] The second substrate 201 is located below the first substrate 101. The second substrate 201 includes a third surface 23 and a fourth surface 24 that are opposite to each other. The third surface 23 faces the second surface 12. The third surface 23 has a plurality of discrete third pads (not shown in the figure), and the fourth surface 24 has a plurality of discrete fourth pads (not shown in the figure). The second substrate 201 has a second trace that interconnects the corresponding fourth pads with each other and the corresponding third pads with each fourth pad.

[0090] Multiple second chips 203 are soldered to corresponding fourth pads on the fourth surface 24, and the second chips 203 are interconnected through corresponding fourth pads and second traces 202.

[0091] An annular interposer 301 is located between the first substrate 101 and the second substrate 201. The annular interposer 301 includes a fifth surface 35 and a sixth surface 36 that are opposite to each other. The fifth surface 35 faces the second surface 12 and has a plurality of discrete fifth pads 302 (see reference). Figure 9 The sixth surface 36 has multiple discrete sixth pads 303 (see reference). Figure 10 The annular intermediate plate 301 has a third trace (not shown in the figure), which electrically connects the corresponding fifth pad 302 and sixth pad 302. The fifth pad 302 of the fifth surface 35 of the annular intermediate plate 301 is soldered to the corresponding second pad of the second surface 12 of the first substrate 101, and the sixth pad 302 of the sixth surface 36 of the annular intermediate plate 301 is soldered to the corresponding third pad of the third surface 23 of the second substrate 201, thereby interconnecting the first substrate 101 and the second substrate 201.

[0092] Specifically, the first substrate 101 is used for interconnection between the first chips 103 and with the second substrate 201, and also serves as a support.

[0093] The first substrate 101 includes a first surface 11 and a second surface 12 that are opposite to or opposite to each other. The first surface 11 of the first substrate 101 has a plurality of discrete first pads (not shown in the figure), which are soldered to corresponding first chips 103. In one example, the first pads are soldered to the first connection terminals of the first chips 103 via solder (the first connection terminals are used to transmit electrical signals from inside the first chips 103 or to transmit external electrical signals to the inside of the first chips 103). The second surface 12 of the first substrate 101 has a plurality of discrete second pads (not shown in the figure), which are soldered to the fifth pads corresponding to the fifth surface of the corresponding annular intermediate plate 301. In one example, the second pads are electrically connected to the fifth pads via solder. The first substrate 101 has a first trace 102, which electrically connects corresponding first pads to each other and corresponding first pads to second pads. The first trace 102 can be a multilayer structure. Some first traces 102 can electrically connect or interconnect two or more first pads, some first traces 102 can electrically connect or interconnect corresponding first pads to second pads, and some first traces 102 can also electrically connect or interconnect two or more second pads. In one example, the materials of the first pads, second pads, and first traces 102 include one or more of copper, aluminum, nickel, tin, tungsten, platinum, titanium, chromium, tantalum, gold, silver, titanium nitride, tantalum nitride, and tungsten nitride. The materials of the solder include one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0094] In some embodiments, reference Figure 1 or Figure 2 The first substrate 101 includes an add-on substrate. Using an add-on substrate can increase the density of the first wiring 102 in the first substrate 101, reduce the loss of high-speed signals, and improve the strength of the first substrate 101 to prevent warping. In a specific example, the first substrate 101 may include a first core board 101a and a first add-on wiring layer 101b and a second add-on wiring layer 101c respectively located on both sides of the first core board 101a. Both the first add-on wiring layer 101b and the second add-on wiring layer 101c may include an add-on film and a metal wiring layer stacked sequentially. The add-on film may be made of a material with low dielectric loss and low coefficient of thermal expansion, such as a resin material with low dielectric loss and low coefficient of thermal expansion, to reduce high-speed signal loss and prevent warping of the first substrate 101. The metal wiring layer may be made of one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni. In one example, to further ensure the transmission quality of high-speed signals and reduce losses, in the three adjacent metal wiring layers, the middle metal wiring layer is used as a signal layer, and the other two metal wiring layers are used as power and ground plane layers. Through preventive simulation, the spacing and line width between metal wirings in the signal layer, as well as the thickness of the metal wiring layer, metal layer, and add-on film, can be confirmed. Each signal layer requires a corresponding power and ground plane layer for reference, return current, and isolation. Therefore, the first add-on wiring layer 101b and the second add-on wiring layer 101c include a power and ground plane layer and a signal layer, which are stacked sequentially. Adjacent signal layers can be electrically connected through a first via connection structure that penetrates the corresponding add-on film and the corresponding metal wiring layer. The bottom signal layer in the first add-on wiring layer 101b and the top signal layer in the second add-on wiring layer 101c can be electrically connected through a second via connection structure that penetrates the first core board 101a. That is, the first trace 102 can include several signal layers and a first via connection structure and a second via connection structure that electrically connects the corresponding signal layers.

[0095] In some embodiments, reference Figure 2 and Figure 4 The second pad on the second surface 12 of the first substrate 101 may have a first solder bump 108. The first solder bump 108 may be a C4 solder bump (Controlled Collapse Chip Connection bump). The first solder bump 108 is used to solder the second pad on the second surface 12 of the first substrate 101 to the corresponding fifth pad on the fifth surface 35 of the annular intermediate plate 301.

[0096] The first substrate 101 is a large-size substrate, so more first chips 103 can be soldered on the first surface 11 of the first substrate 101 to realize more functions of the stacked package structure and improve the performance of the stacked package structure. When the size of the first substrate 101 is larger, more first traces 102 can be laid in the first substrate 101 to better realize the interconnection between the first chips 103.

[0097] In some embodiments, reference Figure 3 or Figure 4 The first substrate 101 is a square substrate, which can be rectangular or square. The length of the first substrate 101 ranges from 100mm to 650mm, and the width of the first substrate 101 also ranges from 100mm to 650mm. In one specific example, the length of the first substrate 101 is 512mm, and the width of the first substrate 101 is 512mm * 512mm. In another specific example, the size of the first substrate 101 is 240mm * 240mm.

[0098] There are multiple first chips 103, and at least a portion of the first chips 103 are chips excluding the packaging substrate. That is, the portion of the first chips 103 are not soldered to the first substrate 101 through the packaging substrate, but are directly soldered to the first substrate 101. The first traces 102 in the first substrate 101 interconnect the corresponding first chips 103. The interconnection includes the interconnection of signals between the first chips 103 and the interconnection of power and ground between the first chips 103. Therefore, in this application, there are no via connection structures in the packaging substrate and ball grid arrays on the surface of the packaging substrate on the signal link from the first chip 103 to the first substrate 101. This reduces impedance discontinuities in the signal link, avoids a large number of reflections, thereby ensuring the integrity of signals and power, and also reduces the length of the signal link, thereby reducing the loss in the signal link. In addition, since the first chips 103 do not need to be soldered to the packaging substrate and do not need to form a ball grid array, at least one reflow process can be reduced, thus preventing warping of the first substrate 101 caused by multiple reflow processes. The stacked packaging structure of this application adopts large-scale integration technology. Multiple pads (such as multiple first pads) are left on a large-sized first substrate 101. Multiple first chips 103 are correspondingly soldered onto the pads. Signal and power ground interconnection is achieved in the first substrate 101 through the first trace 102. Therefore, it is not necessary to package the first chip into a BGA (Ball Grid Array) to bring out the signal and power and then solder it onto the motherboard, and interconnection is performed at the motherboard level.

[0099] The first chips 103 are all soldered onto corresponding first pads on the first surface 11 of the first substrate 101 using a flip-chip process. The plurality of first chips 103 include multiple chips with different functions. In some embodiments, reference is made to... Figure 1 , Figure 2 and Figure 3 The plurality of first chips 103 include one or a combination of a central processing unit (CPU) chip 103a, an input / output interface (IO) chip 103b, a non-volatile memory chip (NAND Flash, or NAND SSD, or 3D NAND SSD) 103c, a first integrated power supply (IVR) chip 103d, a random access memory chip (RAM or 3D RAM) 103e, and a co-packaged optoelectronic chip (CPO) 103f. The number of the CPU chip 103a, the I / O interface chip 103b, the non-volatile memory chip 103c, the first integrated power supply chip 103d, the random access memory chip 103e, and the co-packaged optoelectronic chip 103f can be one or more. The co-packaged optoelectronic chip 103f has an interface, and an optical fiber can be installed at the interface of the co-packaged optoelectronic chip 103f to realize signal transmission between the stacked package structure and the outside through the light.

[0100] In one specific embodiment, among the plurality of first chips 101, the central processing unit chip 103a and the input / output interface chip 103b do not have a packaging substrate. That is, the central processing unit chip 103a and the input / output interface chip 103b are not soldered to the first substrate 101 through a packaging substrate, but are directly soldered to the first substrate 101. Since the central processing unit chip 103a and the input / output interface chip 103b will process a large number of chips, there will be no via connection structures in the packaging substrate or ball grid arrays on the surface of the packaging substrate in the signal link from the aforementioned central processing unit chip 103a and the input / output interface chip 103b to the second substrate 201. This reduces impedance discontinuities in the signal link and avoids a large number of reflections, thereby ensuring the integrity of the signals and power supply of the central processing unit chip 103a and the input / output interface chip 103b. It also reduces the length of the signal link, thereby reducing the loss in the signal link. When the aforementioned central processing unit chip 103a and the input / output interface chip 103b are applied to a computing system (such as a server system), the performance of the computing system is improved. In some embodiments, the first integrated power chip 103d, the random access memory chip 103e, and the optoelectronic co-packaged chip 103f may or may not have a packaging substrate. In other embodiments, the first chip 103 may include chips with other functions in addition to the aforementioned chips, such as graphics processing units (GPUs) or field-programmable gate arrays (FPGAs).

[0101] In some embodiments, continue to refer to Figure 1 and Figure 2 and in conjunction with references Figure 3 and Figure 4 The first substrate 101 also has a plurality of discrete first vias penetrating the first surface 11 and the second surface 12;

[0102] The stacked packaging structure also includes: a first fixing component 107, which includes a first back plate 104, a first connector 105 and a first support 106. The first back plate 104 is disposed on the second surface 12, the first support 106 is disposed on the first surface 11, and the first connector 105 passes through the first through hole and fixes the first support 106 and the first back plate 104.

[0103] The stacked package structure also includes: a first heat sink 111 (reference) Figure 1The first heat sink 111 is fixed to the first support member 106, and the side of the first heat sink 111 near the first substrate 101 is in contact with the surface of the first chip 103 away from the first substrate 101, so that the heat generated by the first chip 103 is released through the first heat sink 111. The first fixing component 107 fixes and supports the first heat sink 111, which on the one hand can lock the first heat sink 111, ensure the contact performance between the first heat sink 111 and the multiple first chips 103, reduce thermal resistance, and improve heat dissipation efficiency. On the other hand, the supporting effect of the first support member 106 on the first heat sink 111 can prevent the first chip 103 from bearing excessive pressure. Furthermore, the cooperation of the first back plate 104, the first connector 105 and the first support member 106 can not only lock the heat sink 111 but also overcome the warping of the first substrate 101.

[0104] In some embodiments, the surface of the first support member 106 away from the first substrate 101 is higher than the surface of the first chip 103 away from the first substrate 101. The first support member 106 includes an annular structure and surrounds at least one first chip 103 to reduce the area of ​​the first surface of the first substrate 101 occupied by the first support member 106, improve the utilization rate of the first surface 11 of the first substrate 101, and the first heat sink 111 can be better locked by the corresponding first support member 106. Therefore, the first chip 103 surrounded by the first support member 106 and the first heat sink 111 have better contact performance, thereby further reducing thermal resistance. In one example, the first chip 103 surrounded by the first support member 106 is a high-power chip.

[0105] The side of the first heat sink 111 closest to the first substrate 101 contacts the surface of the first chip 103 furthest from the first substrate 101 through a thermal interface material. The thermal interface material can effectively reduce the contact thermal resistance between different structures, thereby further reducing thermal resistance and improving heat dissipation efficiency.

[0106] In some embodiments, continue to refer to Figure 1 The first connector 105 includes a first bolt, which includes a male head and a female head located at both ends;

[0107] The first support member 106 has a first screw hole at one end near the first substrate 101 and a second screw hole at the other end away from the first substrate 101. The female head of the first bolt passes through the first through hole and is screwed into the first screw hole, and the male head of the first bolt is fixed on the first back plate 104.

[0108] The first radiator 111 has a second through hole that extends through the upper and lower surfaces;

[0109] The first fixing component 107 further includes a second bolt 110, which passes through a second through hole in the first radiator 111 and is screwed into a second threaded hole in the first support member 106 to fix the first radiator 111. This method can better fix the first radiator 111.

[0110] In other embodiments, the first connector 105 includes a first bolt, which includes a male head and a female head located at both ends;

[0111] The first support member 106 has a third through hole that penetrates the upper and lower surfaces;

[0112] The first heat sink 111 has a third screw hole on the side near the first substrate 101;

[0113] The female head of the first bolt passes through the first through hole and the third through hole and is screwed into the third screw hole to fix the first radiator 111. This method also allows for better fixation of the first radiator 111.

[0114] Continue to refer to Figure 1 The second substrate 201 is used for interconnection between the second chips 203 and with the first substrate 101, and also serves as a support.

[0115] refer to Figure 1 as well as Figures 5-7The second substrate 201 includes a third surface 23 and a fourth surface 24 that are opposite to or opposite to each other. The third surface 23 of the second substrate 201 has a plurality of discrete third pads (not shown in the figure), and the fourth surface 24 of the second substrate 201 has a plurality of discrete fourth pads (not shown in the figure). The fourth pads are soldered to corresponding second chips 203. In one example, the fourth pads are soldered to second connection terminals of the second chips 203 via solder (the second connection terminals are used to transmit electrical signals from inside the second chips 203 or to transmit external electrical signals to the inside of the second chips 203). The third pads are soldered to corresponding sixth pads. In one example, the third pads are electrically connected to the corresponding sixth pads on the sixth surface of the annular interposer 301 via solder. The second substrate 201 has a second trace 202, which electrically connects corresponding fourth pads to each other and to corresponding fourth pads and third pads. The second trace 202 can be a multilayer structure. Some second traces 202 can electrically connect or interconnect two or more fourth pads, some second traces 202 can electrically connect or interconnect corresponding fourth pads and third pads, and some second traces 202 can also electrically connect or interconnect two or more third pads. In one example, the materials of the third pads, fourth pads, and second trace 202 include one or more of copper, aluminum, nickel, tin, tungsten, platinum, titanium, chromium, tantalum, gold, silver, titanium nitride, tantalum nitride, and tungsten nitride. The materials of the solder include one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.

[0116] In some embodiments, reference Figure 1 or Figure 5The second substrate 201 includes an add-on substrate. Using an add-on substrate can increase the density of the second wiring 202 in the second substrate 201, reduce the loss of high-speed signals, and improve the strength of the second substrate 201 to prevent warping. In a specific example, the second substrate 201 may include a second core board 201a and a third add-on wiring layer 201b and a fourth add-on wiring layer 201c respectively located on both sides of the second core board 201a. Both the third add-on wiring layer 201b and the fourth add-on wiring layer 201c may include an add-on film and a metal wiring layer stacked sequentially. The add-on film may be made of a material with low dielectric loss and low coefficient of thermal expansion, such as a resin material with low dielectric loss and low coefficient of thermal expansion, to reduce high-speed signal loss and prevent warping of the second substrate 201. The metal wiring layer may be made of one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni. In one example, to further ensure the transmission quality of high-speed signals and reduce losses, in three adjacent metal wiring layers, the middle metal wiring layer is used as the signal layer, and the remaining two metal wiring layers are used as power and ground plane layers. Preventive simulation can be used to confirm the spacing and line width between metal wirings in the signal layer, as well as the thickness of the metal wiring layers, metal layers, and add-on films. Each signal layer requires a corresponding power and ground plane layer for reference, return current, and isolation. Therefore, the third add-on wiring layer 201b and the fourth add-on wiring layer 201c include one power and ground plane layer and one signal layer. In this stacked structure, adjacent signal layers can be electrically connected through a third via connection structure that penetrates the corresponding add-on film and the corresponding metal wiring layer. The bottom signal layer in the third add-on wiring layer 201b and the top signal layer in the fourth add-on wiring layer 201c can be electrically connected through a fourth via connection structure that penetrates the second core board 201a. That is, the second trace 202 can include several signal layers (second signal layers) and a third via connection structure and a fourth via connection structure that electrically connect the corresponding signal layers (second signal layers).

[0117] The second substrate 201 is a large-size substrate, and the size of the second substrate 201 is the same as that of the first substrate 101. Therefore, more second chips 203 can be soldered on the fourth surface 24 of the second substrate 201 to realize more functions of the stacked package structure and improve the performance of the stacked package structure. When the size of the second substrate 201 is larger, more second traces 202 can be laid in the second substrate 201 to better realize the interconnection between the second chips 203.

[0118] In some embodiments, reference Figure 5 and Figure 6The third pad on the third surface 23 of the second substrate 201 may have a second solder bump 208. The second solder bump 208 may be a C4 solder bump (Controlled Collapse Chip Connection bump). The second solder bump 208 may be used to solder the third pad on the third surface 23 of the second substrate 201 to the corresponding sixth pad on the sixth surface 36 of the annular intermediate plate 301.

[0119] In some embodiments, reference Figure 6 or Figure 7 The second substrate 201 is a square substrate, which can be rectangular or square. The length of the second substrate 201 ranges from 100mm to 650mm, and the width of the second substrate 201 also ranges from 100mm to 650mm. In one specific example, the length of the second substrate 201 is 512mm, and the width of the second substrate 201 is 512mm * 512mm. In another specific example, the size of the second substrate 201 is 240mm * 240mm.

[0120] There are multiple second chips 203, and at least a portion of the second chips 203 are chips excluding the packaging substrate. That is, these second chips 203 are not soldered to the second substrate 201 through the packaging substrate, but are directly soldered to the second substrate 201. The second traces 202 in the second substrate 201 interconnect the corresponding second chips 203. The interconnection includes the interconnection of signals between the second chips 203 and the interconnection of power and ground between the second chips 203. Therefore, in this application, there are no via connection structures in the packaging substrate and ball grid arrays on the surface of the packaging substrate on the signal link from the second chip 203 to the second substrate 201. This reduces impedance discontinuities in the signal link, avoids a large number of reflections, thereby ensuring the integrity of signals and power, and also reduces the length of the signal link, thereby reducing the loss in the signal link. In addition, since the second chips 203 do not need to be soldered to the packaging substrate and do not need to form a ball grid array, at least one reflow process can be reduced, thus preventing warping of the second substrate 201 caused by multiple reflow processes. The stacked packaging structure of this application adopts large-scale integration technology. Multiple pads (such as multiple fourth pads) are left on a larger second substrate 201. Multiple second chips 203 are correspondingly soldered onto the pads. Signal and power ground interconnection is achieved in the second substrate 201 through the second trace 202. Therefore, it is not necessary to package the second chips into BGA (Ball Grid Array) to bring out signals and power and then solder them onto the motherboard, and interconnection is performed at the motherboard level.

[0121] The second chips 203 are all soldered onto the corresponding fourth pads on the fourth surface 24 of the second substrate 201 using a flip-chip process. The plurality of second chips 203 include multiple chips with different functions. In some embodiments, reference is made to... Figure 1 , Figure 7 and Figure 7 The multiple second chips 203 include one or a combination of a deep computing unit (DCU) chip 203a, a switch chip 203b, and a second integrated power supply (IVR) chip 203c. The number of deep computing unit (DCU) chips 203a, switch chips 203b, and second integrated power supply (IVR) chips 203c can be one or more. In other embodiments, the first chip 103 may include chips with other functions in addition to the aforementioned chips, such as input / output interface chips (IO), non-volatile memory chips (NAND Flash, or NAND SSD, or 3D NAND SSD), random access memory chips (RAM or 3D RAM), and co-packaged optoelectronic chips (CPO). In one specific embodiment, among the plurality of second chips 201, the depth computing processor chip 203a and the switching chip 203b do not have a packaging substrate. That is, the depth computing processor chip 203a and the switching chip 203b are not soldered to the second substrate 201 through a packaging substrate, but are directly soldered to the second substrate 201. Since the depth computing processor chip 203a and the switching chip 203b process a large number of signals, there are no via connection structures in the packaging substrate or ball grid arrays on the surface of the packaging substrate in the signal link from the aforementioned depth computing processor chip 203a and the switching chip 203b to the second substrate 201. This reduces impedance discontinuities in the signal link, avoids a large number of reflections, thereby ensuring the integrity of the signal and power of the depth computing processor chip 203a and the switching chip 203b, and also reduces the length of the signal link, thereby reducing the loss in the signal link. When the aforementioned depth computing processor chip 203a and the switching chip 203b are applied to a computing system (such as a server system), the performance of the computing system is improved. In some embodiments, the second integrated power chip 203c may or may not have a packaging substrate. Therefore, in the stacked packaging structure of this application, a computing system can be constructed by the aforementioned first substrate 101, second substrate 201, first chip 103, second chip 203, and annular intermediate plate 301. Furthermore, by setting the first chip 103 and second chip 203 with different functions on the first substrate 101 and the second substrate 201 respectively, the area occupied by the stacked packaging structure can be effectively reduced.

[0122] In some embodiments, in conjunction with reference Figure 1 and Figure 5 and in conjunction with references Figure 6 and Figure 7 The second substrate 201 also has a plurality of discrete fourth vias penetrating the third surface 23 and the fourth surface 24;

[0123] The stacked packaging structure also includes: a second fixing component 207, which includes a second back plate 204, a second connector 205 and a second support 206. The second back plate 204 is disposed on the third surface 23, the second support 206 is disposed on the fourth surface 24, and the second connector 205 passes through the fourth through hole and fixes the second support 206 and the second back plate 204.

[0124] The stacked package structure also includes: a second heat sink 211 (reference) Figure 1 The second heat sink 211 is fixed to the second support member 206, and the side of the second heat sink 211 near the second substrate 201 is in contact with the surface of the second chip 203 away from the second substrate 201. The second fixing component 207 fixes and supports the second heat sink 211, which on the one hand locks the second heat sink 211, ensures the contact performance between the second heat sink 211 and the multiple second chips 203, reduces thermal resistance, and improves heat dissipation efficiency. On the other hand, the supporting effect of the second support member 206 on the second heat sink 211 can prevent the second chip 203 from bearing excessive pressure. Furthermore, the cooperation of the second back plate 204, the second connector 205, and the second support member 206 can not only lock the heat sink 211 but also overcome the warping of the second substrate 201.

[0125] In some embodiments, the surface of the second support member 206 away from the second substrate 201 is higher than the surface of the second chip 203 away from the second substrate 201. The second support member 206 includes an annular structure and surrounds at least one second chip 203 to reduce the area of ​​the fourth surface of the second substrate 201 occupied by the second support member 206, improve the utilization rate of the fourth surface 24 of the second substrate 201, and the second heat sink 211 can be better locked by the corresponding second support member 206. Therefore, the second chip 203 surrounded by the second support member 206 has better contact performance with the second heat sink 211, thereby further reducing thermal resistance. In one example, the second chip 203 surrounded by the second support member 206 is a high-power chip.

[0126] The side of the second heat sink 211 closest to the second substrate 201 contacts the surface of the second chip 203 furthest from the second substrate 201 through a thermal interface material. The thermal interface material can effectively reduce the contact thermal resistance between different structures, thereby further reducing thermal resistance and improving heat dissipation efficiency.

[0127] In some embodiments, the second connector 205 includes a third bolt, which includes a male head and a female head located at both ends;

[0128] The second support member 206 has a fourth screw hole at one end near the second substrate 201 and a fifth screw hole at the other end away from the second substrate 201. The female head of the third bolt passes through the fourth through hole and is screwed into the fourth screw hole. The male head of the third bolt is fixed on the second back plate 204.

[0129] The second radiator 211 has a fifth through hole that penetrates the upper and lower surfaces;

[0130] The second fixing component 207 further includes a fourth bolt 210, which passes through a fifth through hole in the radiator and is screwed into a fifth screw hole in the second support member 206 to fix the second radiator 211.

[0131] In other embodiments, the second connector 205 includes a third bolt, which includes a male head and a female head located at both ends;

[0132] The second support member 206 has a sixth through hole that extends through the upper and lower surfaces;

[0133] The second heat sink 211 has a sixth screw hole on the side near the first substrate 101;

[0134] The female head of the third bolt passes through the fourth and sixth through holes and is screwed into the sixth screw hole to fix the second radiator 211.

[0135] Continue to refer to Figure 1 The stacked packaging structure also includes an annular interposer 301, located between the first substrate 101 and the second substrate 201. The fifth pad of the fifth surface 35 of the annular interposer 301 is soldered to the corresponding second pad of the second surface 12 of the first substrate 101, and the sixth pad of the sixth surface 36 of the annular interposer 301 is soldered to the corresponding third pad of the third surface 23 of the second substrate 201, thereby interconnecting the first substrate 101 and the second substrate 201 through the annular interposer 301. Furthermore, the third wiring in the annular interposer 301 can have a high wiring density to facilitate the interconnection between the first substrate 101 and the second substrate 201. The annular interposer 301 also serves to support the first substrate 101 and the second substrate 201.

[0136] In some embodiments, reference Figure 1 In conjunction with references Figure 9 and Figure 10The annular interposer 301 includes a cutout area 301b and an annular body area 301a surrounding the cutout area 301b. The fifth pad 302, the sixth pad 303, and the third trace are located in the annular body area 301a. A portion of the annular interposer 301 is cut out, allowing semiconductor devices or chips (such as coupling capacitors) to be soldered onto the second surface of the first substrate 101 corresponding to the cutout area 301b, and the third surface of the second substrate 201 corresponding to the cutout area 301b, thereby further improving the performance of the stacked package structure. In some embodiments, the number of cutout areas 301b can be one or more.

[0137] In some embodiments, continue to refer to Figure 1 In conjunction with references Figure 9 and Figure 10 The annular intermediate plate 301 further includes a blank area 301c surrounding the outer side of the annular body region 301a and connected to the outer wall of the annular body region 301a. The outer wall of the blank area 301c extends beyond the outer walls of the first substrate 101 and the second substrate 201 (see reference). Figure 1 or Figure 8 The blank area 301c is used during the fabrication of the stacked package structure. A jig presses onto the fifth and sixth surfaces of the blank area to fix the annular intermediate plate 301. Specifically, during the fabrication of the stacked package structure, the first substrate 101 and the second substrate 201 are used as devices, and the annular intermediate plate 301 is used as the mother plate. First, a magnetic jig presses onto the blank area 301c of the annular intermediate plate 301 to fix the annular intermediate plate 301 and control warpage. After aligning the first substrate 101 with the annular intermediate plate 301, the first substrate 101 is reflow soldered onto the fifth surface of the annular intermediate plate 301. After soldering the first substrate 101, the second substrate 201 is aligned with the annular intermediate plate 301, and the second substrate 201 is reflow soldered onto the sixth surface of the annular intermediate plate 301.

[0138] In some embodiments, the materials of the annular body region 301a and the blank region 301c in the annular intermediate plate 301 include silicon, glass or resin, and the material of the third wiring in the annular body region 301a includes one or more of copper, aluminum, nickel, tin, tungsten, platinum, titanium, chromium, tantalum, gold, silver, titanium nitride, tantalum nitride and tungsten nitride.

[0139] In some embodiments, the stacked package structure further includes: a first decoupling capacitor, soldered to a second pad corresponding to the second surface 12 of the first substrate 101; the number of first decoupling capacitors can be multiple to facilitate high power voltage drop; a second decoupling capacitor, soldered to a third pad corresponding to the third surface 23 of the second substrate 201; the number of first decoupling capacitors can be multiple to facilitate high power voltage drop; and a first connector 109 (reference). Figure 1 or Figure 2 The first connector 109 is soldered to the first pad corresponding to the first surface 11 of the first substrate 101, and is used for external electrical connection of the corresponding first cable to supply power to the first substrate 101 in the stacked package structure via the first cable; the second connector 209 (refer to...) Figure 1 or Figure 5 The second connector 209 is used for electrical connection with the corresponding fourth pad on the fourth surface 24 of the second substrate 201, and is used for electrical connection with the corresponding external second cable to supply power to the second substrate 201 in the stacked package structure via the second cable.

[0140] This application embodiment also includes a computing system, characterized in that it comprises:

[0141] In the aforementioned stacked packaging structure, the plurality of first chips 103 include one or a combination of a central processing unit (CPU) chip 103a, an input / output interface (IO) chip 103b, a non-volatile memory chip (NAND Flash, or NAND SSD, or 3D NAND SSD) 103c, a first integrated power supply (IVR) chip 103d, a random access memory (RAM or 3D RAM) chip 103e, and a co-packaged optoelectronic chip (CPO) 103f. The number of the CPU chip 103a, the input / output interface chip 103b, the non-volatile memory chip 103c, the first integrated power supply chip 103d, the random access memory chip 103e, and the co-packaged optoelectronic chip 103f can be one or more.

[0142] The multiple second chips 203 include one or a combination of a deep computing unit (DCU) chip 203a, a switch chip 203b, and a second integrated power supply chip (IVR) 203c, and the number of deep computing unit (DCU) chip 203a, switch chip 203b, and second integrated power supply chip 203c can be one or more.

[0143] In some embodiments, the computing system includes a server system.

[0144] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A stacked packaging structure, characterized in that, include: A first substrate includes a first surface and a second surface that are opposite to each other. The first surface has a plurality of discrete first pads, and the second surface has a plurality of discrete second pads. The first substrate has a first trace that electrically connects the corresponding first pads to each other and the corresponding first pads to the second pads. Multiple first chips are soldered to corresponding first pads on the first surface, and the first chips are interconnected through corresponding first pads and first traces. The second substrate, located below the first substrate, includes a third surface and a fourth surface facing away from each other, with the third surface facing the second surface. The third surface has a plurality of discrete third pads, and the fourth surface has a plurality of discrete fourth pads. The second substrate has a second trace that interconnects the corresponding fourth pads with each other and the corresponding third pads with each fourth pad. Multiple second chips are soldered to corresponding fourth pads on the fourth surface, and the second chips are interconnected through corresponding fourth pads and second traces. An annular interposer, located between a first substrate and a second substrate, includes a fifth surface and a sixth surface facing away from each other. The fifth surface faces the second surface. The fifth surface has a plurality of discrete fifth pads, and the sixth surface has a plurality of discrete sixth pads. The annular interposer has a third trace that electrically connects the corresponding fifth and sixth pads. The fifth pads are soldered to the corresponding second pads, and the sixth pads are soldered to the corresponding third pads, thereby interconnecting the first substrate and the second substrate.

2. The stacked packaging structure according to claim 1, characterized in that, The first substrate also has a plurality of discrete first vias penetrating the first surface and the second surface; The stacked packaging structure further includes: a first fixing component, the first fixing component including a first back plate, a first connector and a first support member, the first back plate being disposed on the second surface, the first support member being disposed on the first surface, and the first connector passing through the first through hole and fixing the first support member and the first back plate; The stacked packaging structure further includes: a first heat sink, which is fixed on the first support member, and the side of the first heat sink near the first substrate is in contact with the surface of the first chip away from the first substrate.

3. The stacked packaging structure according to claim 2, characterized in that, The surface of the first support member away from the first substrate is higher than the surface of the first chip away from the first substrate. The first support member includes an annular structure and surrounds at least one of the first chips. The side of the first heat sink closest to the first substrate is in contact with the surface of the first chip furthest from the first substrate through a thermal interface material.

4. The stacked packaging structure according to claim 2, characterized in that, The first connector includes a first bolt, which includes a male head and a female head located at both ends; The first support member has a first screw hole at one end near the first substrate and a second screw hole at one end away from the first substrate. The female head of the first bolt passes through the first through hole and is screwed into the first screw hole, and the male head of the first bolt is fixed to the first back plate. The first heat sink has a second through hole that penetrates the upper and lower surfaces; The first fixing component further includes a second bolt, which passes through a second through hole in the first radiator and is screwed into a second screw hole in the first support member to fix the first radiator.

5. The stacked packaging structure according to claim 2, characterized in that, The first connector includes a first bolt, which includes a male head and a female head located at both ends; The first support member has a third through hole that extends through the upper and lower surfaces; The first heat sink has a third screw hole on the side near the first substrate; The female head of the first bolt passes through the first through hole and the third through hole and is screwed into the third screw hole to fix the first heat sink.

6. The stacked packaging structure according to claim 1, characterized in that, The second substrate also has a plurality of discrete fourth vias penetrating the third and fourth surfaces; The stacked packaging structure further includes: a second fixing component, the second fixing component including a second back plate, a second connector and a second support member, the second back plate being disposed on the third surface, the second support member being disposed on the fourth surface, and the second connector passing through the fourth through hole and fixing the second support member and the second back plate; The stacked packaging structure further includes a second heat sink, which is fixed on the second support member, and the side of the second heat sink near the second substrate is in contact with the surface of the second chip away from the second substrate.

7. The stacked packaging structure according to claim 6, characterized in that, The surface of the second support member away from the second substrate is higher than the surface of the second chip away from the second substrate. The second support member includes a ring structure and surrounds at least one of the second chips. The side of the second heat sink closest to the second substrate is in contact with the surface of the second chip furthest from the second substrate through a thermal interface material.

8. The stacked packaging structure according to claim 6, characterized in that, The second connector includes a third bolt, which includes a male head and a female head located at both ends; The second support member has a fourth screw hole at one end near the second substrate and a fifth screw hole at one end away from the second substrate. The female head of the third bolt passes through the fourth through hole and is screwed into the fourth screw hole, and the male head of the third bolt is fixed to the second back plate. The second heat sink has a fifth through hole that extends through the upper and lower surfaces; The second fixing component further includes a fourth bolt, which passes through a fifth through hole in the radiator and is screwed into a fifth screw hole in the second support member to fix the second radiator.

9. The stacked packaging structure according to claim 6, characterized in that, The second connector includes a third bolt, which includes a male head and a female head located at both ends; The second support member has a sixth through hole that extends through the upper and lower surfaces; The second heat sink has a sixth screw hole on the side near the first substrate; The female head of the third bolt passes through the fourth through hole and the sixth through hole and is screwed into the sixth screw hole to fix the second radiator.

10. The stacked packaging structure according to claim 1, characterized in that, The annular interposer includes a cutout area and an annular body area surrounding the cutout area, and the fifth pad, the sixth pad, and the third trace are located in the annular body area.

11. The stacked packaging structure according to claim 10, characterized in that, The annular intermediate plate also includes a blank area surrounding the outer side of the annular body region and connected to the outer wall of the annular body region. The outer wall of the blank area extends beyond the outer walls of the first substrate and the second substrate. The blank area is used to fix the annular intermediate plate by pressing a jig onto the fifth and sixth surfaces of the blank area during the fabrication of the stacked packaging structure.

12. The stacked packaging structure according to claim 1, characterized in that, At least a portion of the first chips do not have a packaging substrate; The plurality of the first chips include one or a combination of: a central processing unit chip, an input / output interface chip, a first integrated power supply chip, a random access memory chip, a non-volatile memory chip, and an optoelectronic co-packaged chip; Furthermore, neither the central processing unit chip nor the input / output interface chip has a packaging substrate.

13. The stacked packaging structure according to claim 1 or 12, characterized in that, At least a portion of the second chips do not have a packaging substrate; The plurality of the second chips include one or a combination of a deep computing processor chip, a switching chip, and a second integrated power chip; Furthermore, neither the depth computing processor chip nor the switching chip has a packaging substrate.

14. The stacked packaging structure according to claim 1, characterized in that, The stacked packaging structure further includes: A first decoupling capacitor is soldered to a second pad corresponding to the second surface of the first substrate; The second decoupling capacitor is soldered to the third pad corresponding to the third surface of the second substrate.

15. The stacked packaging structure according to claim 1 or 14, characterized in that, The stacked packaging structure further includes: A first connector is soldered to a first pad corresponding to a first surface of the first substrate; The second connector is soldered to the fourth pad corresponding to the fourth surface of the second substrate.

16. The stacked packaging structure according to claim 1, characterized in that, The first substrate and the second substrate include an add-on substrate, and the first substrate includes a first core board and a first add-on wiring layer and a second add-on wiring layer respectively located on both sides of the first core board. The second substrate includes a second core board and a third and a fourth additional wiring layer located on both sides of the second core board, respectively.

17. The stacked packaging structure according to claim 1 or 16, characterized in that, The first substrate and the second substrate are square substrates. The length of the first substrate is in the range of 100mm-650mm, and the width of the first substrate is in the range of 100mm-650mm. The length of the second substrate is in the range of 100mm-650mm, and the width of the second substrate is in the range of 100mm-650mm.

18. A computing system, characterized in that, include: The stacked packaging structure according to any one of claims 1-17.

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