An electronic signal triggered on-off circuit

Abstract

The utility model discloses an electronic signal trigger formula switch circuit, including system power supply, control circuit, button circuit and main control module, system power supply's output end connects control circuit's first input and button circuit's input, control circuit's output end connects main control module's power end, button circuit's first output end connects control circuit's second input, button circuit's second output end connects main control module's first general input output, main control module's second general input output connects control circuit's third input. In the utility model, control circuit is under the double control of button and main control module, decides whether to supply power to main control module, button circuit is user input interface, and button action is converted into electric signal and is sent to control circuit and main control module, and main control module runs system and maintains the state of starting up or executes shutdown through GPIO mouth after obtaining power supply, has the remarkable advantage that stability is high, and universality is strong and cost is low.

Description

Technical Field

[0001] This utility model relates to the field of power on / off circuit technology, and in particular to an electronic signal triggered power on / off circuit. Background Technology

[0002] In the field of electronic devices, traditional power-on and power-off methods mainly rely on physical buttons to trigger mechanical switches, directly cutting off or connecting the power circuit to turn the device on or off. However, this method has many limitations: on the one hand, frequent pressing can easily lead to wear and tear on the mechanical contacts, reducing the lifespan of the switch and affecting the reliability of the device; on the other hand, physical switches lack flexible control logic and cannot meet the diverse usage scenarios of modern smart devices, such as timed power-on and power-off, low-power wake-up, and automatic restart in abnormal states.

[0003] Therefore, a new solution is needed. Utility Model Content

[0004] The purpose of this invention is to address the problems of high cost, complex circuit structure, and high power consumption caused by the current market's power-on / off circuits that mainly rely on complex power management chips, and to provide an electronic signal triggered power-on / off circuit.

[0005] To achieve the above objectives, this utility model provides an electronic signal triggered power-on / off circuit, including a system power supply, a control circuit, a button circuit, and a main control module. The output terminal of the system power supply is connected to the first input terminal of the control circuit and the input terminal of the button circuit. The output terminal of the control circuit is connected to the power supply terminal of the main control module. The first output terminal of the button circuit is connected to the second input terminal of the control circuit. The second output terminal of the button circuit is connected to the first general-purpose input / output terminal of the main control module. The second general-purpose input / output terminal of the main control module is connected to the third input terminal of the control circuit.

[0006] In the electronic signal triggered power-on / off circuit provided by this utility model, the control circuit includes a PMOS transistor Q1, an NMOS transistor Q2, a diode D1, a first voltage divider resistor R1, a second voltage divider resistor R2, and a first current-limiting resistor R3. The source of the PMOS transistor Q1 is connected to the output terminal of the system power supply and the first terminal of the first voltage divider resistor R1. The gate of the PMOS transistor Q1 is connected to the second terminal of the first voltage divider resistor R1 and the first terminal of the second voltage divider resistor R2. The drain of the PMOS transistor Q1 is connected to the power supply terminal of the main control module. The drain of the NMOS transistor Q2 is connected to the second terminal of the second voltage divider resistor R2. The gate of the NMOS transistor Q2 is connected to the output terminal of the diode D1 via the first current-limiting resistor R3. The source of the NMOS transistor Q2 is grounded. The first input terminal of the diode D1 is connected to the first output terminal of the button circuit, and the second input terminal of the diode D1 is connected to the second general-purpose input / output terminal of the main control module.

[0007] In the electronic signal triggered power-on / off circuit provided by this utility model, the control circuit further includes a first pull-down resistor R5, the first end of the first pull-down resistor R5 is connected to the second input terminal of the diode D1, and the second end of the first pull-down resistor R5 is grounded.

[0008] In the electronic signal triggered power-on / off circuit provided by this utility model, the control circuit further includes a first filter capacitor C1, a second filter capacitor C2, a third filter capacitor C3, and a fourth filter capacitor C4. The first end of the first filter capacitor C1 and the first end of the second filter capacitor C2 are connected to the source of the PMOS transistor Q1. The first end of the third filter capacitor C3 and the first end of the fourth filter capacitor C4 are connected to the drain of the PMOS transistor Q1. The second end of the second filter capacitor C2 is connected to the gate of the PMOS transistor Q1. The second ends of the first filter capacitor C1, the third filter capacitor C3, and the fourth filter capacitor C4 are grounded.

[0009] In the electronic signal triggered power-on / off circuit provided by this utility model, the button circuit includes a touch switch KEY1, a second pull-down resistor R4, and a second current-limiting resistor R6. The first end of the touch switch KEY1 is connected to the output terminal of the system power supply, and the second end of the touch switch KEY1 is connected to the first input terminal of the diode D1, the first end of the second pull-down resistor R4, and the first end of the second current-limiting resistor R6. The second end of the second current-limiting resistor R6 is the first general-purpose input / output terminal of the main control module, and the second end of the second pull-down resistor R4 is grounded.

[0010] In the electronic signal triggered power on / off circuit provided by this utility model, the button circuit further includes a fifth filter capacitor C5. The first end of the fifth filter capacitor C5 is connected to the second end of the touch switch KEY1, and the second end of the fifth filter capacitor C5 is grounded.

[0011] The electronic signal-triggered power-on / off circuit provided by this utility model has the following advantages: In this utility model, the system power supply is usually a battery or power adapter, which is always powered; the control circuit is the main switch of the main control module power supply, which is controlled by both the button and the main control module, and determines whether to supply power to the main control module; the button circuit is the user input interface, which converts the button action (press, release, long press) into electrical signals and sends them to the control circuit and the main control module; after the main control module receives power, it runs the system and maintains the power-on state or performs power-off through the GPIO port; it has significant advantages of high stability, strong versatility and low cost. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Figure 1 The diagram shown is a schematic diagram of an electronic signal triggered power-on / off circuit according to an embodiment of the present invention. Figure 2 The diagram shown is a circuit diagram of an electronic signal triggered power-on / off circuit provided in an embodiment of this utility model. Detailed Implementation

[0013] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate typical embodiments of this utility model. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this utility model more thorough and complete.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0015] Figure 1 The diagram shown is a schematic of an electronic signal-triggered power-on / off circuit according to an embodiment of this utility model. Figure 1As shown, the electronic signal-triggered power-on / off circuit provided by this utility model includes a system power supply 100, a control circuit 200, a button circuit 300, and a main control module 400. The output terminal of the system power supply 100 is connected to the first input terminal of the control circuit 200 and the input terminal of the button circuit 300. The output terminal of the control circuit 200 is connected to the power supply terminal of the main control module 400. The first output terminal of the button circuit 300 is connected to the second input terminal of the control circuit 200. The second output terminal of the button circuit 300 is connected to the first general-purpose input / output terminal of the main control module 400. The second general-purpose input / output terminal of the main control module 400 is connected to the third input terminal of the control circuit 200. Specifically, the system power supply 100 provides the operating voltage for the entire system, and its output terminal is connected to the first input terminal of the control circuit, while also providing power to the button circuit. The core function of the control circuit 200 is to control the power supply to the main control module, receive control signals from the button circuit and the main control module, and implement the power-on / off logic; its output terminal is connected to the power supply terminal of the main control module, realizing the physical switching of the power supply. The button circuit 300 serves as the user interface, sending control signals via button operations. Its first output terminal connects to the second input terminal of the control circuit; the second output terminal connects to the first general-purpose input / output terminal of the main control module, enabling the transmission of wake-up or power-off commands. This is the system's brain, responsible for executing power-on / off logic, maintaining state, and managing low power consumption. The main control module's first general-purpose input / output terminal (GPIO1) receives button commands; its second general-purpose input / output terminal (GPIO2) outputs control signals to the control circuit, enabling power maintenance or disconnection.

[0016] The working principle of this utility model is explained in detail below: Power-on process (long press): With the system completely powered off, the user presses and holds the button. From a hardware perspective, an enable signal generated by the button circuit is directly sent to the second input of the control circuit. This signal drives the control circuit to conduct at the hardware level, thus supplying power to the main control module. After the main control module powers on, its second general-purpose input / output port is pulled up by hardware or set to a default high-level output state through circuitry (this is basic hardware knowledge). This high level is fed back to the third input of the control circuit, achieving self-locking at the hardware level and maintaining power supply. Therefore, even if the button is released, the system remains powered on. This process is automatically completed by the hardware connection sequence and circuit state, without relying on any software initialization.

[0017] Short-press wake-up process: When the system is in standby mode, the user briefly presses a button. A high-level pulse signal is sent directly to the first general-purpose input / output (PIO) of the main control module through the output of the button circuit. This port can be configured as a hardware interrupt wake-up pin (this is a common hardware feature of the MCU and not an innovation of this invention). The main control module is woken up based on its inherent, pre-existing hardware interrupt mechanism, and then resumes full-speed operation. The 'wake-up' function here utilizes the general-purpose hardware capabilities of the main control module. The innovation of this invention lies in providing a trigger signal for this hardware capability through a specific circuit connection.

[0018] Long press shutdown process: While the system is running, the user presses and holds the button. A continuous high-level signal is sent to the first general-purpose input / output (GPIO) terminal of the main control module. After the main control module detects that the signal duration has reached a threshold, it outputs a low-level signal through its second GPIO terminal. This low-level signal breaks the self-locking sustaining loop of the control circuit, causing the control circuit to disconnect in hardware, thus achieving power-off shutdown. Here, the main control module only performs two extremely simple, conventional operations in the field: 'detecting the high-level duration' and 'outputting a low level'. This invention protects the hardware circuit affected by the low-level signal and the technical effect of the signal in achieving shutdown within the overall hardware logic, not the detection and output program code itself.

[0019] Furthermore, in one embodiment of this utility model, as Figure 2As shown, the control circuit 200 includes a PMOS transistor Q1, an NMOS transistor Q2, a diode D1, a first voltage divider resistor R1, a second voltage divider resistor R2, a first current limiting resistor R3, a first pull-down resistor R5, a first filter capacitor C1, a second filter capacitor C2, a third filter capacitor C3, and a fourth filter capacitor C4. The source of the PMOS transistor Q1 is connected to the output terminal of the system power supply 100 and the first terminal of the first voltage divider resistor R1. The gate of the PMOS transistor Q1 is connected to the second terminal of the first voltage divider resistor R1 and the first terminal of the second voltage divider resistor R2. The drain of the PMOS transistor Q1 is connected to the power supply terminal of the main control module 400. The drain of the NMOS transistor Q2 is connected to the second terminal of the second voltage divider resistor R2. The gate of the NMOS transistor Q2 is connected to the output terminal of the diode D1 via the first current limiting resistor R3. The source of the NMOS transistor Q2 is grounded. The first input terminal of the diode D1 is connected to the first output terminal of the button circuit 300. The second input terminal of the diode D1 is connected to the second general-purpose input / output terminal of the main control module 400. The first terminal of the first pull-down resistor R5 is connected to the second input terminal of the diode D1. The second terminal of the first pull-down resistor R5 is grounded. The first terminal of the first filter capacitor C1 and the first terminal of the second filter capacitor C2 are connected to the source of the PMOS transistor Q1. The first terminal of the third filter capacitor C3 and the first terminal of the fourth filter capacitor C4 are connected to the drain of the PMOS transistor Q1. The second terminal of the second filter capacitor C2 is connected to the gate of the PMOS transistor Q1. The second terminals of the first filter capacitor C1, the third filter capacitor C3, and the fourth filter capacitor C4 are grounded.

[0020] In this embodiment, the control circuit is an electronic switch and self-locking circuit composed of a PMOS transistor (Q1) and an NMOS transistor (Q2). The source of the PMOS transistor Q1 is connected to the system power supply, and its drain serves as the output, supplying power to the main control module, essentially acting as a controlled high-side switch. The gate voltage of Q1 is determined by the voltage division point of the first voltage divider resistor (R1) and the second voltage divider resistor (R2). Whether this voltage division point is pulled low is controlled by the on / off state of the NMOS transistor Q2. A diode (D1) forms an OR gate logic. Its output is connected to the gate of the NMOS transistor Q2 through a first current-limiting resistor (R3). The two inputs of D1 receive the first output signal from the button circuit and the sustain signal from the second general-purpose input / output terminal (GPIO2) of the main control module, respectively. A first pull-down resistor (R5) ensures that the gate of the NMOS transistor Q2 is low when there is no valid signal, preventing false turn-on. Multiple filter capacitors (C1-C4) are deployed at the system power input, the gate of PMOS transistor Q1, and the output, respectively, to filter out power supply noise and interference and ensure stable circuit operation.

[0021] Furthermore, in one embodiment of this utility model, as Figure 2 As shown, the button circuit 300 includes a touch switch KEY1, a second pull-down resistor R4, a second current-limiting resistor R6, and a fifth filter capacitor C5. The first end of the touch switch KEY1 is connected to the output terminal of the system power supply 100. The second end of the touch switch KEY1 is connected to the first input terminal of the diode D1, the first end of the second pull-down resistor R4, and the first end of the second current-limiting resistor R6. The second end of the second current-limiting resistor R6 is the first general-purpose input / output terminal of the main control module 400. The second end of the second pull-down resistor R4 is grounded. The first end of the fifth filter capacitor C5 is connected to the second end of the touch switch KEY1, and the second end of the fifth filter capacitor C5 is grounded.

[0022] In this embodiment, the button circuit includes a touch switch (KEY1). When KEY1 is pressed, the high level of the system power supply is directly sent to the first input terminal of the diode D1 (as a power-on trigger signal), and simultaneously sent to the first general-purpose input / output terminal (GPIO1) of the main control module (as a function signal) through the second current-limiting resistor (R6). The second pull-down resistor (R4) ensures that the potential at this point is reliably pulled low when the button is not pressed, preventing interference introduced by the floating pin. The fifth filter capacitor (C5) is used to filter out glitches caused by button bounce and improve signal quality.

[0023] The working process of this utility model is as follows: 1. Press and hold to power on (hardware self-lock established): With the power off, press and hold the touch switch KEY1. The high-level signal from the system power supply is divided into two paths: the first path (trigger path): the high level passes through diode D1 and resistor R3, turning on NMOS transistor Q2; the second path (functional path): the high level passes through resistor R6 and is sent to GPIO1 of the main control module (this path is ineffective when the main control module is not powered on). After Q2 turns on, it pulls the gate voltage of PMOS transistor Q1 low to ground. According to the characteristics of PMOS transistors, Q1 turns on, the system power supply begins to supply power to the main control module, and the system starts up. After the main control module is powered on and initialized, its GPIO2 port outputs a high level set by the hardware circuit design or simple initialization code (this is the standard operation). This high level, through the second input terminal of diode D1, also keeps Q2 conducting via R3. At this time, even if KEY1 is released, due to the maintenance of the high level of GPIO2, a self-locking circuit has been formed, and the system remains powered on.

[0024] 2. Short press to wake up: In standby mode, a short press of KEY1 sends a high-level pulse through R6 to the GPIO1 port of the main control module. This GPIO1 port can be configured as a hardware interrupt wake-up source in the main control module software (this is a common function of MCUs). This pulse signal triggers an interrupt at the hardware level, waking up the main control module.

[0025] 3. Press and hold to power off: With the device powered on, press and hold KEY1. The main control module's GPIO1 port detects a continuous high level. After a set time, the main control module executes the shutdown sequence, finally outputting a low level from its GPIO2 port. This low-level signal cuts off the self-locking sustaining loop of the control circuit, turning off NMOS transistor Q2, which in turn causes PMOS transistor Q1 to turn off, completely cutting off the power supply to the main control module in hardware, thus achieving shutdown.

[0026] Compared with existing technologies, the electronic signal-triggered power-on / off circuit provided by this utility model has the following significant advantages by optimizing the hardware connection relationship between the system power supply, control circuit, button circuit and main control module: 1. Hardware logic implements power on / off, ensuring stability, reliability, and extremely low power consumption. The core power-on and power-off logic of this invention (especially power-on and state maintenance) is implemented by pure hardware circuitry. During the initial power-on and state maintenance phases, it does not rely on the initialization and operation of the main control module software, fundamentally avoiding the systemic risks of "unable to power on" or "unable to power off" caused by software crashes or program malfunctions, and greatly improving the stability and reliability of the system.

[0027] When powered off, the main control module is completely de-energized, with zero power consumption. In standby mode, only one I / O port interrupt function of the main control module is needed to maintain monitoring, resulting in extremely low overall circuit power consumption, making it particularly suitable for battery-powered portable devices.

[0028] 2. High versatility, not dependent on specific main control chips and software platforms. Since the innovation of this invention lies in the connection structure of the peripheral hardware circuit, there are no special requirements for the internal software architecture of the main control module. The main control module only needs to have the most basic GPIO output high and low levels and interrupt wake-up capability, which are standard functions of all general-purpose microcontrollers.

[0029] Therefore, this circuit can be widely used in various main control chips based on different cores without the need for deep adaptation to specific software platforms, which greatly improves the versatility and portability of the circuit solution and reduces R&D costs.

[0030] 3. Optimized user experience and clear interaction logic By using a single physical button and leveraging the difference in hardware timing between "long press" and "short press", the system reliably distinguishes between the three functions of "power on", "power off", and "wake up" at the hardware level. The user interaction logic is clear, intuitive, and effectively prevents accidental operation.

[0031] 4. Simple structure, easy to implement and promote This invention does not require complex dedicated power management chips. It can construct control circuits using only common discrete components (such as transistors and MOSFETs) or basic logic chips. The structure is simple and the cost is low, which is very conducive to its implementation and promotion in productization.

[0032] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0033] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspect lies in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0034] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0035] It should be noted that the above embodiments are illustrative of the present invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. An electronic signal triggered power-on / off circuit, characterized in that, The system includes a system power supply (100), a control circuit (200), a button circuit (300), and a main control module (400). The output terminal of the system power supply (100) is connected to the first input terminal of the control circuit (200) and the input terminal of the button circuit (300). The output terminal of the control circuit (200) is connected to the power supply terminal of the main control module (400). The first output terminal of the button circuit (300) is connected to the second input terminal of the control circuit (200). The second output terminal of the button circuit (300) is connected to the first general-purpose input / output terminal of the main control module (400). The second general-purpose input / output terminal of the main control module (400) is connected to the third input terminal of the control circuit (200).

2. The electronic signal triggered power-on / off circuit as described in claim 1, characterized in that, The control circuit (200) includes a PMOS transistor Q1, an NMOS transistor Q2, a diode D1, a first voltage divider resistor R1, a second voltage divider resistor R2, and a first current-limiting resistor R3. The source of the PMOS transistor Q1 is connected to the output terminal of the system power supply (100) and the first terminal of the first voltage divider resistor R1. The gate of the PMOS transistor Q1 is connected to the second terminal of the first voltage divider resistor R1 and the first terminal of the second voltage divider resistor R2. The drain of the PMOS transistor Q1 is connected to the power supply terminal of the main control module (400). The drain of the NMOS transistor Q2 is connected to the second terminal of the second voltage divider resistor R2. The gate of the NMOS transistor Q2 is connected to the output terminal of the diode D1 via the first current-limiting resistor R3. The source of the NMOS transistor Q2 is grounded. The first input terminal of the diode D1 is connected to the first output terminal of the button circuit (300), and the second input terminal of the diode D1 is connected to the second general-purpose input / output terminal of the main control module (400).

3. The electronic signal triggered power-on / off circuit as described in claim 2, characterized in that, The control circuit (200) further includes a first pull-down resistor R5, the first end of which is connected to the second input terminal of the diode D1, and the second end of which is grounded.

4. The electronic signal triggered power-on / off circuit as described in claim 2, characterized in that, The control circuit (200) further includes a first filter capacitor C1, a second filter capacitor C2, a third filter capacitor C3, and a fourth filter capacitor C4. The first end of the first filter capacitor C1 and the first end of the second filter capacitor C2 are connected to the source of the PMOS transistor Q1. The first end of the third filter capacitor C3 and the first end of the fourth filter capacitor C4 are connected to the drain of the PMOS transistor Q1. The second end of the second filter capacitor C2 is connected to the gate of the PMOS transistor Q1. The second ends of the first filter capacitor C1, the third filter capacitor C3, and the fourth filter capacitor C4 are grounded.

5. The electronic signal triggered power-on / off circuit as described in claim 2, characterized in that, The button circuit (300) includes a touch switch KEY1, a second pull-down resistor R4, and a second current-limiting resistor R6. The first end of the touch switch KEY1 is connected to the output end of the system power supply (100). The second end of the touch switch KEY1 is connected to the first input end of the diode D1, the first end of the second pull-down resistor R4, and the first end of the second current-limiting resistor R6. The second end of the second current-limiting resistor R6 is the first general-purpose input / output terminal of the main control module (400). The second end of the second pull-down resistor R4 is grounded.

6. The electronic signal triggered power-on / off circuit as described in claim 5, characterized in that, The button circuit (300) also includes a fifth filter capacitor C5, the first end of which is connected to the second end of the touch switch KEY1, and the second end of which is grounded.

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