High-precision multi-channel intelligent calibrator

Abstract

The utility model discloses a kind of high-precision multi-path intelligent calibrators, it includes power panel, logic export input board, acquisition board, data processing board and backplate;Backplate is equipped with backplate data bus and two pairs of differential lines;Acquisition board includes FPGA chip and communication module, communication module includes two-way gigabit ethernet port;Data processing board includes storage unit, 2-way gigabit ethernet unit, GPIO unit and CPU processing module.The two-way gigabit ethernet port of acquisition board is connected to the two gigabit ethernet units of data processing board by the two pairs of differential lines on backplate respectively.The utility model is through above-mentioned scheme, realize single calibrator can cover the channel scale that traditional need multiple instruments can complete, thoroughly solve the pain point of "channel shortage, repeatedly wiring" in field.At the same time, through double power supply hot backup scheme, solve the verification interruption problem caused by no mains electricity or temporary power failure in field.

Description

Technical Field

[0001] This utility model relates to the field of power system relay protection testing technology, and in particular to a portable calibrator that can synchronously collect all trip logic outputs of the main transformer protection device in a substation under a single trigger condition. Background Technology

[0002] In recent years, with the increasing intelligence of substations, the number of intelligent devices within the stations has been increasing year by year. The functions of relay protection and automation devices in modern integrated automated substations are becoming increasingly integrated. For example, the trip outputs and signal output channels of main transformer protection devices are becoming increasingly complex and numerous. When verifying protection devices, a large amount of verification work is required to check the correctness of the logic outputs. If there are problems with the logic outputs, especially the trip outputs, the damage to primary equipment is often quite serious.

[0003] Currently, conventional relay protection testers have not made breakthroughs in verifying the logic and operating time of multi-channel protection contacts. They typically rely on rudimentary methods like using multimeters to test pulses or testing the operating time of individual output contacts. Since various types of protection devices typically reset the entire system within 3-5 seconds after activation, protection personnel must repeatedly introduce fault parameters to test the operating time of other contacts and thus determine the operating logic. For devices involving numerous output contact circuits and complex operating logic, such as main transformers, bus differentials, and automatic transfer switches, existing testers cannot measure all output pulses and times when a protection device operates only once. Therefore, repeated protection tests are necessary, continuously testing the pulses and operating times of each output pressure plate and repeatedly introducing fault parameters. This consumes a significant amount of time for protection personnel in testing the protection's operating time and logic. Furthermore, some protection devices may not even have pulses at the output pressure plate during testing, leading personnel to mistakenly believe the entire system has reset, thus failing to detect potential wiring and logic errors and potentially causing the relay protection device to malfunction. Therefore, it is imperative to install intelligent verification equipment for the main transformer protection trip logic output in substations. Utility Model Content

[0004] A brief overview of embodiments of the present invention is provided below to provide a basic understanding of certain aspects of the invention. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0005] To address the shortcomings of existing relay protection testing equipment, which mostly adopts single-channel or limited-channel sequential detection methods, making it impossible to simultaneously acquire more than 64 switch quantities and 512 GOOSE signals under a single trigger condition, and making it difficult to operate when there is no external power supply on site, this utility model provides a high-precision multi-channel intelligent calibrator to solve the above-mentioned deficiencies.

[0006] Specifically, the present invention provides a high-precision multi-channel intelligent calibrator, comprising: a power board, a logic output input board, a data acquisition board, a data processing board, and a backplane; the backplane is provided with a backplane data bus (PCIe / custom parallel bus) and two pairs of differential lines (compliant with 1000BASE-KX specifications), the two pairs of differential lines being independent of the backplane data bus; The power board, logic output input board, acquisition board, and data processing board are respectively connected to the backplane data bus; the acquisition board and the data processing board are electrically connected to each other. The logic output input board includes a multi-channel opto-isolator, a voltage interference suppression circuit, a first-stage buffer, a complex programmable logic device (CPLD), and a second-stage buffer. The multi-channel opto-isolator and the voltage interference suppression circuit are connected accordingly. The first-stage buffer is located between the multi-channel voltage interference suppression circuit and the CPLD. The second-stage buffer is located between the CPLD and the backplane data bus. The CPLD outputs parallel data to the backplane data bus via the second-stage buffer. The acquisition board includes an FPGA chip and a communication module electrically connected to the FPGA chip. The communication module includes two gigabit Ethernet ports, and the FPGA chip is connected to the backplane data bus. The data processing board includes a storage unit, two gigabit Ethernet units, a GPIO unit, and a CPU processing module. The storage unit, two gigabit Ethernet units, and GPIO unit are all electrically connected to the CPU processing module. The two gigabit Ethernet ports of the acquisition board are connected to the two gigabit Ethernet units of the data processing board via the two pairs of differential lines on the backplane.

[0007] As a feasible solution, the logic output input board includes 64 opto-isolators, 64 TVS arrays, 4 first general-purpose buffers, a complex programmable logic device (CPLD), and 2 second general-purpose buffers. The 64 TVS arrays are connected in parallel to the input terminals of the corresponding 64 opto-isolators. The output terminals of the 64 opto-isolators are connected to the input terminals of the CPLDs through the 4 first general-purpose buffers. The output terminals of the CPLDs are connected to the backplane data bus through the 2 second general-purpose buffers. The 4 first general-purpose buffers divide the 64 switching signals into 4 groups of eight signals. After the CPLD completes protocol parsing, the parallel data is output to the backplane data bus through the second general-purpose buffers.

[0008] More preferably, the multi-channel opto-isolator is implemented using a TLP121 device, and the voltage interference suppression circuit is implemented using a TVS array of model P6SMB43CA.

[0009] Furthermore, the power board is equipped with an AC / DC input port, a power isolation module, and an external lithium battery pack. The power supplied through the AC / DC input port is converted by the power isolation module and outputs isolated multiple DC buses (e.g., +24V±5%, +12V±5%, and +5V±3%). The external lithium battery pack is hot-backed up with the DC buses via an OR-ing circuit, with a power failure switching time of <10ms, which is used to solve the problem of insufficient power supply in the field of integrated equipment.

[0010] Furthermore, the acquisition board also includes: The power status monitoring circuit is used to monitor the power supply status of the acquisition board in real time and output a status indication signal; The first relay unit has its coil controlled by the GPIO signal of the data processing board, and its contacts are used to switch or enable the power supply of the acquisition board. The second relay unit has its coil connected to the output of the power status monitoring circuit and its contacts connected to the detection terminals of the data processing board, thereby isolating and feeding back the power operation status of the acquisition board to the data processing board to achieve electrical isolation.

[0011] The first relay unit is a normally closed (NC) or normally open (NO) relay with a contact rated current ≥5A; the second relay unit uses dry contacts with a contact capacity ≥250V / 5A to achieve complete isolation. As a specific implementation, the first relay unit can be implemented using a normally closed relay of model DSP1-DC24V-F, whose coil is controlled by GPIO, and whose contacts switch the main power supply of the acquisition board; the second relay unit can be implemented using a relay of model DSP2a-DC24VF, which is a dry contact, with its coil driven by a power status monitoring circuit, and which feeds back an isolated normal power signal to the data processing board when the contacts are closed.

[0012] Furthermore, the FPGA chip is implemented using a chip with the model number XC6SLX45T-2FGG484I.

[0013] Furthermore, the data processing board also includes an LVDS display unit.

[0014] Furthermore, the CPU processing module is implemented using a J1900 processor. The driver chip for the GPIO interface is an SN74LVC8T24. The CPU processing module performs calculations, data storage, network communication, full-duplex serial communication, PCI bus communication, CRT display, and keyboard and mouse input.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. Multiple conventional outputs + several GOOSE parallel accesses: Through the two gigabit Ethernet ports on the acquisition board and the four gigabit Ethernet units on the data processing board, as well as the collaboration of the FPGA chip and the complex programmable logic device CPLD dual chip, a single calibrator can cover the channel scale that traditionally requires multiple instruments, completely solving the pain points of "insufficient channels and repeated wiring" on site.

[0016] 2. Dual power supply hot backup without power failure: AC / DC and external lithium battery are connected in parallel via OR-ing circuit, with a switching time of <10ms, which completely solves the problem of verification interruption caused by no mains power or temporary power failure on site, and improves the continuity of operation.

[0017] 3. High-speed backplane interconnect: PCIe / custom parallel bus + 1000BASE-KX differential line work in parallel to realize μs-level data exchange between CPU and FPGA, and can guarantee 512 channels of GOOSE messages online simultaneously without packet loss.

[0018] 4. Improved overall reliability: Through triple isolation of TVS array + opto-isolation + relay dry contact, the common mode / differential mode surge immunity reaches ±4kV, significantly enhancing the safety and stability of online equipment and reducing maintenance workload. Attached Figure Description

[0019] This invention can be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar parts. These drawings, together with the following detailed description, are incorporated in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention. In the drawings: Figure 1This is a block diagram of the high-precision multi-channel intelligent calibrator according to an embodiment of the present invention; Figure 2 This is a block diagram of the logic output input board in an embodiment of this utility model; Figure 3 is a block diagram of the composition of the acquisition board in an embodiment of this utility model; Figure 4 This is a block diagram of the data processing board in an embodiment of this utility model. Detailed Implementation

[0020] Embodiments of the present invention will now be described with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for clarity, representations and descriptions of components and processes unrelated to the present invention and known to those skilled in the art have been omitted from the drawings and description.

[0021] In the description of this utility model, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, the terms "installation," "connection," and "linking" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0022] This utility model embodiment provides a portable calibrator for multi-channel synchronous acquisition of trip logic outputs of substation main transformer protection. (See also...) Figures 1-4 It includes a power board, logic output input board, acquisition board, data processing board, and backplane. The backplane has a backplane data bus (PCIe / custom parallel bus) and two pairs of differential lines conforming to the 1000BASE-KX specification. The two pairs of differential lines are independent of the backplane data bus.

[0023] The power board is equipped with an AC / DC input port, which can be connected to AC220V, AC110V, DC220V, or DC110V; after passing through the power isolation module, it outputs three DC buses: +24V, +12V, and +5V. An external lithium battery pack is connected in parallel with the buses via an OR-ing circuit, with a power failure switching time of <10ms, enabling continuous power supply in the absence of mains power on site.

[0024] The logic output input board includes 64 opto-isolators (TLP121), 64 TVS arrays (P6SMB43CA), 4 first-level buffers, a complex programmable logic device (CPLD), and 2 second-level buffers. The 64 TVS arrays are connected in parallel to the input terminals of the corresponding 64 opto-isolators. The output terminals are fed into the CPLD via 4 first-level general-purpose buffers to form 4 groups of eight signals. After the CPLD completes protocol parsing, it outputs 32-bit parallel data to the backplane data bus through 2 second-level general-purpose buffers.

[0025] The acquisition board includes a GOOSE input module, an FPGA chip, a communication module, two relays, and a power status monitoring circuit. The communication module provides two Gigabit Ethernet ports, which are connected to two Gigabit Ethernet ports on the data processing board via two pairs of 1000BASE-KX differential lines on the backplane. The remaining two Gigabit Ethernet ports are used for external uplink or cascading expansion. The FPGA chip module uses an XC6SLX45T-2FGG484I chip. It reads discrete voltage and current data from the backplane data bus, adds an absolute time stamp to each sampling point according to GPS time, packages the data packets according to a predefined data structure type, and sends them to the data processing board via the network port.

[0026] The time synchronization circuit is connected to the FPGA chip to realize the B-code time synchronization function. To generate a high-precision clock signal, a counter and comparator are used to divide the high-precision crystal oscillator to generate a crystal oscillator second clock signal. The FPGA chip then corrects the comparison value to generate a corrected second clock. The arrival time of the B-code second clock, i.e., the phase difference between the corrected second clock and the B-code second clock, is latched by a latch. By analyzing this phase difference and the correction value of the comparison value, a deviation sequence between the B-code second clock and the crystal oscillator second clock is generated. This deviation includes the random drift error of the B-code clock and the cumulative error of the crystal oscillator. A univariate quadratic regression analysis model is used to estimate the two errors, separate their respective errors, and correct the cumulative error of the crystal oscillator, thus constructing a simple high-precision clock generation device. The comparison value is set once per second, and the comparison value to be set this time is calculated from the historical data of the B-code second clock error measured in the previous n times and the comparison value set in the previous n times.

[0027] The power status monitoring circuit of the acquisition board works in conjunction with two relays. When the data processing board sends a self-test command via GPIO, the relays send the operating status of the device to the outside world, and the output information is "start" or "abnormal".

[0028] The acquisition board also includes multiple network debugging modules. Each network debugging module includes a network debugging interface RJ45 and a network debugging chip PHY (Marvell 88E1512). The network debugging interface RJ45 is connected to the FPGA chip through the network debugging chip PHY.

[0029] The data processing board includes a flash mSATA card / hard drive, two Gigabit Ethernet units, a GPIO interface, and an LVDS touch display (G121SN01). The flash mSATA card / hard drive, four Gigabit Ethernet units, the GPIO interface, and the LVDS display are all connected to the CPU processing module. In this embodiment, the CPU processing module is model J1900. The driver chip for the GPIO interface is model SN74LVC8T24. The board runs a Linux system and has a built-in client background management program, providing functions for recording and analyzing logical output information, file management, setting configuration, historical records, data saving, display, and printing.

[0030] This invention adopts the above-mentioned solution, allowing a single device to connect 64 conventional outputs + 512 GOOSE outputs, completely solving the problem of insufficient channels in traditional calibrators. The FPGA+CPLD collaborative architecture achieves millisecond-level real-time status updates, shortening the verification cycle from 30 minutes to <3 seconds, eliminating missed and false tests. Targeted UI: all complex logic is encapsulated, allowing users to complete verification with a single click, requiring zero training. AC / DC and lithium battery hot backups enable continuous operation even without mains power, improving operational continuity. Multiple isolation (TVS + opto-isolation + relay dry contacts) ensures ±4kV surge immunity, significantly improving the safety and stability of online equipment.

[0031] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0032] Although the present invention has been disclosed above through the description of specific embodiments, it should be understood that all the embodiments and examples described above are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the present invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the present invention.

Claims

1. A high-precision multi-channel intelligent calibrator, characterized in that: include: The system includes a power supply board, a logic output input board, a data acquisition board, a data processing board, and a backplane; the backplane is equipped with a backplane data bus and two pairs of differential lines. The power board, logic output input board, acquisition board, and data processing board are respectively connected to the backplane data bus; the acquisition board and the data processing board are electrically connected to each other. The acquisition board includes an FPGA chip and a communication module electrically connected to the FPGA chip. The communication module includes two gigabit Ethernet ports, and the FPGA chip is connected to the backplane data bus. The data processing board includes a storage unit, two gigabit Ethernet units, a GPIO unit, and a CPU processing module. The storage unit, two gigabit Ethernet units, and GPIO unit are all electrically connected to the CPU processing module. The two gigabit Ethernet ports of the acquisition board are connected to the two gigabit Ethernet units of the data processing board via the two pairs of differential lines on the backplane.

2. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The logic output input board includes a multi-channel opto-isolator, a voltage interference suppression circuit, a first-stage buffer, a complex programmable logic device (CPLD), and a second-stage buffer. The multi-channel opto-isolator and the voltage interference suppression circuit are connected accordingly. The first-stage buffer is located between the multi-channel voltage interference suppression circuit and the CPLD. The second-stage buffer is located between the CPLD and the backplane data bus. The CPLD outputs parallel data to the backplane data bus via the second-stage buffer.

3. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The logic output input board includes 64 opto-isolators, 64 TVS arrays, 4 first general-purpose buffers, a complex programmable logic device (CPLD), and 2 second general-purpose buffers. The 64 TVS arrays are connected in parallel to the inputs of the corresponding 64 opto-isolators. The outputs of the 64 opto-isolators are connected to the inputs of the CPLDs through the 4 first general-purpose buffers. The outputs of the CPLDs are connected to the backplane data bus through the 2 second general-purpose buffers. The 4 first general-purpose buffers divide the 64 switching signals into 4 groups of eight signals. After the CPLD completes protocol parsing, the parallel data is output to the backplane data bus through the second general-purpose buffers.

4. The high-precision multi-channel intelligent calibrator according to claim 2, characterized in that: The multi-channel opto-isolator is implemented using a TLP121 device, and the voltage interference suppression circuit is implemented using a TVS array of model P6SMB43CA.

5. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The power board is equipped with an AC / DC input port, a power isolation module, and an external lithium battery pack. The AC / DC input port outputs multiple DC buses through the power isolation module. The external lithium battery pack is connected in parallel with the DC buses to achieve hot backup.

6. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The acquisition board also includes: The power status monitoring circuit is used to monitor the power supply status of the acquisition board in real time and output a status indication signal; The first relay unit has its coil controlled by the GPIO signal of the data processing board, and its contacts are used to switch or enable the power supply of the acquisition board. The second relay unit has its coil connected to the output of the power status monitoring circuit and its contacts connected to the detection terminals of the data processing board, thereby isolating and feeding back the power operation status of the acquisition board to the data processing board for electrical isolation.

7. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The FPGA chip is implemented using a chip with model number XC6SLX45T-2FGG484I.

8. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The data processing board also includes an LVDS display unit.

9. The high-precision multi-channel intelligent calibrator according to claim 1, characterized in that: The CPU processing module is implemented using a J1900 processor.

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