A nationalization task management master board

Abstract

This utility model provides a fully domestically produced task management main control board. The main control board consists of a 2K1000 carrier board and a YX5F200T baseboard, connected via a COME connector to achieve bus interface information exchange. The main control board has an 800MHz CPU, 1GB of memory, and external expansion via a J30J connector: two RS232 serial interfaces, one RS232 debug serial port, two 10 / 100 / 1000base-T adaptive Ethernet interfaces, and two CAN interfaces. An additional ISA bus interface for task management is provided via a PDS-90JW connector. The baseboard includes an mSATA interface for mounting an mSATA hard drive. The baseboard also has one HDMI interface and four USB interfaces. All components used in the task management main control board are 100% developed and delivered by domestic manufacturers, meeting the requirements of independent controllability.

Description

Technical Field

[0001] This utility model belongs to the field of main control boards, specifically relating to a fully domestically produced task management main control board. Background Technology

[0002] In high-reliability applications such as computer systems, embedded systems, avionics systems, and industrial control, the task management main control board needs to simultaneously handle high-performance computing and highly real-time tasks. Existing solutions mostly adopt a pure processor or a processor-embedded general-purpose interface chip architecture. This architecture lacks real-time performance when handling multiple heterogeneous tasks, and it is difficult to provide stable ISA bus driving capabilities while simultaneously enabling flexible reconfiguration of interface functions and parallel processing with other real-time tasks. Utility Model Content

[0003] To address the aforementioned technical issues, this utility model provides a fully domestically produced task management main control board. It adopts an architecture based on a 2K1000 processor and a YX5F200T FPGA as its core. The 2K1000 serves as the CPU for resource scheduling and interface expansion, while the FPGA expands the ISA bus, bringing advantages such as high integration, high real-time performance, and high flexibility to the task management main control board. This utility model consists of a carrier board based on the 2K1000 processor and a baseboard based on the YX5F200T processor. The two boards are connected via a COME Type 10 standard connector to achieve bus interface information exchange. The main control board has an 800MHz CPU and 1GB of memory. It expands externally via a J30J connector to include two RS232 serial interfaces, one RS232 debug serial port, two 10 / 100 / 1000base-T adaptive Ethernet interfaces, and two CAN interfaces. It also expands externally via a PDS-90JW connector to include one ISA bus interface. The baseboard expands with an mSATA interface for mounting an mSATA hard drive. The baseboard has one HDMI port and four USB ports. All components used in the task management main control board are 100% developed and delivered by domestic manufacturers, meeting the requirements for independent control.

[0004] To achieve the above functions, the present invention adopts the following technical solution:

[0005] A fully domestically produced task management main control board consists of a carrier board based on the 2K1000 core and a baseboard based on the YX5F200T core. The two boards are connected via a COME Type 10 standard connector to achieve bus interface information exchange. The main control board has an 800MHz CPU and 1GB of memory. It expands externally via a J30JA1C1-37ZJW connector to include two RS232 serial interfaces, one RS232 debug serial port, two 10 / 100 / 1000base-T adaptive Ethernet interfaces, and two CAN interfaces. It also expands externally via a PDS-90JW connector to include one ISA bus interface. The baseboard includes one mSATA interface for mounting an mSATA hard drive. The baseboard also has one HDMI interface and four USB interfaces.

[0006] Furthermore, the CPU chip on the carrier board is a Loongson 2K1000 processor. This processor has a CPU clock speed of 800MHz. The processor is connected to four DDR3 chips via an integrated 64-bit 533MHz DDR3 controller. The preferred DDR3 chip is the Shenzhen Guowei SM41J256M16EIP, with a single memory chip capacity of 256MB, a 16-bit data bus, and a total capacity of 1GB.

[0007] Furthermore, the Loongson 2K1000 processor integrates two x4 PCIe 2.0 interfaces on-chip, using PCIe 1 interfaces. The PCIe 1 interface supports one x4 and two x1 modes; it is configured in x4 mode. The PCIe differential signals are AC-coupled via a 100nF coupling capacitor and then connected to the inter-board connector, with the AC coupling capacitor positioned close to the transmitting end of the inter-board connector. The PCIe reset output signal is pulled up and connected to the COME connector for use as the reset signal input for the baseboard PCIe devices.

[0008] Furthermore, the 2K1000 processor integrates two GMAC controllers, configured in RGMII interface mode. The RGMII signal is output to the baseboard via a COME connector. The baseboard uses two B88E1111NYB PHY chips from the Beijing Microelectronics Technology Research Institute to convert the two RGMII signals into two 10 / 100 / 1000M adaptive Ethernet interface signals, which are then output to the network transformer. The PHY chip reset signal is controlled by the baseboard FPGA chip, and the MDCK / MDIO signals are pulled up to RSM2.5V near the 2K1000 chip using a 4.7K resistor. The RGMII clock delay is configured by the CPU using the relevant PHY registers. PHY0 address is 0x0001, and PHY1 address is 0x0010. The network transformer is an NWT type network transformer from Shenzhen Zhenhua Fu Electronics Co., Ltd., model JWNWT161002-1-C. The PHY chip output is current-type, and the transformer's center tap is connected to the power supply.

[0009] Furthermore, the Loongson 2K1000 processor integrates four USB 2.0 ports. These four USB signals are connected to a COME connector; the USB clock is configured with an external 12MHz active crystal oscillator. The USB controller, USB clock, and USB port power supply utilize RSM domain power. The differential signals from the four USB ports output by the 2K1000 are connected to the COME connector via a common-mode inductor and an ESD protection transistor to provide electrostatic discharge (ESD) and overcurrent protection for these ports.

[0010] Furthermore, the reset chip for the carrier board is the SM706TEIP from Shenzhen Guowei, which integrates a watchdog function. Simultaneously, the LS2K_WDI watchdog input signal of the 2K1000 is connected to the COME connector, allowing for heartbeat monitoring of the main control board via an external watchdog.

[0011] Furthermore, in the clock circuit of the carrier board, the PCIe reference input clock of the Loongson 2K1000 is provided by the chip's internal system clock, and the reference input clock of the PCIe sub-devices is provided by the PCIe interface differential output clock of the LS2K1000. The 12MHz clock for USB is provided by the LS2K1000's built-in clock source. The SATA clock source is provided by the LS2K1000's internal system clock. The core module's RTC clock is provided by a 32.768kHz crystal.

[0012] Furthermore, the Loongson 2K1000 processor integrates one SATA 2.0 interface and one NAND controller. The SATA interface signal from the 2K1000 is output to the underlying mSATA connector via the COME connector for mounting an mSATA hard drive. The SATA data cable is output via AC coupling, with a 10nF coupling capacitor, positioned near the transmitter connector. The SATA clock uses the 2K1000's internal clock.

[0013] Furthermore, the carrier board is designed with an onboard NAND flash. The NAND flash chip selected is the Fudan Microelectronics FM29G04C, with a capacity of 4Gbit.

[0014] Furthermore, the carrier board outputs the 2K1000 DVO signal to the baseboard via an inter-board COME connector, with a 22-ohm resistor connected in series at the DVO signal output for impedance matching. The baseboard then converts the DVO signal into an HDMI signal for external display output via a DVO-to-HDMI converter chip. The converter chip used is the GM7510 from Chengdu Zhenxin Technology Co., Ltd.

[0015] Furthermore, the FLASH chip model is SM25QH256EIP.

[0016] Furthermore, the baseboard FPGA is the YX5F200T-676I from Wuxi Zhongwei Yixin Co., Ltd., which includes 215,360 logic units, 740 DSP48 Slices, and 13,140Kb of programmable Block RAM. The FPGA's external clock is generated by a crystal oscillator at a frequency of 48MHz. The operating clocks of each functional module are multiplied and divided by the FPGA's internal DCM. The FPGA's external clock crystal oscillator is a Wuhan Haichuang crystal oscillator, model ZA70-DB-3-G-48M00000 (JW).

[0017] Furthermore, the baseboard FPGA is equipped with a non-volatile serial Nor Flash chip, specifically the Shenzhen Guowei Electronics SM25QH256M chip, to store the FPGA's power-on startup program. By pulling up and down the FPGA configuration signal lines M2 to M0, they are configured to a 001 state, thus configuring the FPGA's power-on startup in master serial SPI mode.

[0018] Furthermore, the FPGA reset chip used on the baseboard is the SM706TEIP from Shenzhen Guowei, which integrates a watchdog function. Approximately 120ms after power-on on the baseboard, the FPGA's pro_b signal is de-reset, and the reset chip resets the FPGA 2.25 seconds after the FPGA heartbeat stops.

[0019] Furthermore, the NVRAM (Novel Virtual Random Access Memory) is selected from Hunan Rongchuang Microelectronics Co., Ltd. The RC5NP256K16-PSODW is a 256K×16bit non-volatile static random access memory (SRAM). The RC5NP256K16-PSODW has two operating modes: SRAM mode and non-volatile mode. In SRAM mode, the RC5NP256K16-PSODW performs various read and write operations like a static random access memory. In non-volatile mode, data is stored from SRAM to non-volatile cells (STORE operation) or read from non-volatile cells to SRAM (RECALL operation). In non-volatile mode, SRAM interface access operations are prohibited; the host is not allowed to initiate any address read or write operations on the SRAM interface or cause abnormal toggling of the SRAM interface signals, thus avoiding unknown problems. The NVRAM is configured in non-volatile mode and connected to the FPGA BANK13.

[0020] Furthermore, a button battery is placed on the board to provide a VBAT voltage signal, which provides continuous power to the RTC circuit of the 2K1000 chip on the carrier board through the inter-board COME connector.

[0021] Furthermore, the main control board outputs two RS232 serial ports and one 2K1000 debug serial port via a J30J connector. The serial transceiver used is the HCE3232MJ from Sevenstar Technology. The RX and TX signals of the carrier board's UART0, UART1, and UART2 are connected to the base FPGA via an inter-board COME connector, and then the FPGA transfers them to the serial transceiver, enabling flexible switching between the three externally output RS232 interfaces for the 2K1000 debug serial port. The HCE3232MJ employs a proprietary low-dropout transmitter input stage, utilizing a dual charge pump to achieve RS232 performance from a 3.0V to 5.5V power supply, ensuring consistent output level at a data rate of 250kbps. To protect subsequent circuitry, a TVS transient suppression diode is connected in parallel within the circuit. The transient voltage suppressor diode selected is model SMBJ15CA, with a VRWM of 15V. When a transient voltage is generated in the circuit, the TVS uses the avalanche principle to instantly shunt and limit the voltage with a P-second response speed.

[0022] Furthermore, the CAN transceiver selected is the SMUM3055MP from Shenzhen Guowei Technology Co., Ltd. This chip integrates the CAN transceiver and DC-DC converter into a single IC chip, achieving a data rate of up to 12Mbps and an isolation withstand voltage of 2.5KV. Two CAN bus interface signals are reserved, simultaneously led out via the J30J aviation connector and the baseboard connector. A transient voltage suppressor diode NUP2105L from Zhenhua Yongguang is added between the connector and the transceiver to protect the CAN bus. This device has a reverse operating voltage of 24V, a breakdown voltage of 26.2V, a maximum peak pulse current of 8A, and a maximum peak pulse power of 350W.

[0023] Furthermore, the baseboard FPGA outputs the ISA bus signal to the PDS-90JW connector. Four HWD16T245ESOP48 chips from Chengdu Huawi Electronics Technology Co., Ltd. are used for the 3.3V to 5V level conversion of the ISA bus. The HWD16T245 is a 16-bit dual-supply in-phase bidirectional level converter; VCCA and VCCB can be powered by 3.3V and 5.5V power supplies respectively, and can convert between 3.3V and 5V signals.

[0024] Furthermore, the carrier board power module uses two ACT4644 chips and one XC5121 chip to provide 1.1V, 3.3V, 2.5V, 1.5V, 1.15V and 1.2V voltage signals to the core board respectively.

[0025] Furthermore, the baseboard power module uses one ACT4644 and two ACT4622 to provide 1.0V, 1.8V, 3.3V, 2.5V, 1.2V and 0.85V voltage signals to the baseboard respectively.

[0026] Beneficial effects:

[0027] The fully domestically produced task management main control board developed using this invention supports 2 RS232 serial interfaces, 1 RS232 debug serial port, 2 10 / 100 / 1000base-T adaptive Ethernet interfaces, 2 CAN interfaces, 1 ISA bus interface, one additional mSATA interface, 1 HDMI interface, and 4 USB interfaces. All components used in this task management main control board are 100% developed and delivered by domestic manufacturers, meeting the requirements of independent controllability. It features high-performance general-purpose computing, strong real-time processing, and highly flexible interface expansion. It overcomes the shortcomings of existing technologies, such as insufficient real-time performance and poor flexibility, and can be applied in computer systems, embedded systems, avionics systems, industrial control, and other fields. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a domestically produced task management main control board according to the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present utility model and are not intended to limit the present utility model. Furthermore, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0030] like Figure 1 As shown in this embodiment, the main chips of this utility model, a fully domestically produced task management main control board, include 2K1000, YX5F200T, SM41J256M16EIP, B88E1111NYB, SM706TEIP, JWNWT161002-1-C, FM29G04C, GM7510, YX5F200T-676I, SM25QH256M, SM706TEIP, RC5NP256K16-PSODW, HCE3232MJ, SMUM3055MP, HWD16T245ESOP48, ACT4644, ACT4622, and XC5121.

[0031] The main control board consists of a carrier board based on the 2K1000 core and a baseboard based on the YX5F200T core. The two boards are connected via a COME_TYPE 10 standard interface connector to achieve bus interface information exchange. The main control board expands externally via a J30JA1C1-37ZJW connector to include two RS232 serial interfaces, one RS232 debug serial port, two 10 / 100 / 1000base-T adaptive Ethernet interfaces, and two CAN interfaces. It also expands externally via a PDS-90JW connector to include one ISA bus interface. The baseboard includes one mSATA interface for mounting an mSATA hard drive. The baseboard has one reserved HDMI interface and four USB interfaces. The carrier board uses a Loongson 2K1000 processor. The processor is connected to four DDR3 chips via an integrated 64-bit 533MHz DDR3 controller. The Loongson 2K1000 processor integrates two x4 PCIe 2.0 interfaces, using a PCIe 1 interface configured in x4 mode. PCIe differential signals are AC-coupled via a 100nF coupling capacitor and then connected to the inter-board connector. The PCIe reset output signal is pulled up and connected to the COME connector for inputting the PCIe device reset signal on the baseboard. The 2K1000 processor integrates two GMAC controllers, configured in RGMII interface mode. The RGMII signal is output to the baseboard via the COME connector. The baseboard uses two PHY chips to convert the two RGMII signals into two 10 / 100 / 1000M adaptive Ethernet interface signals, which are output to the network transformer. The PHY chip reset signal is controlled by the baseboard FPGA chip. The RGMII clock delay is configured by the CPU using PHY-related registers. PHY0 address is 0x0001, and PHY1 address is 0x0010. The Loongson 2K1000 processor integrates four USB 2.0 interfaces. Four USB signals are connected to the COME connector. The USB clock is configured with an external 12MHz active crystal oscillator. The USB controller, USB clock, and USB interface power supply are powered by RSM domain power. The differential signals of the four USB interfaces output by the 2K1000 are connected to the COME connector after passing through a common-mode inductor and an ESD transistor. The board reset chip is the SM706TEIP, which integrates watchdog functionality. The PCIe reference input clock of the 2K1000 carrier board is provided by the chip's internal system clock, and the reference input clock of the PCIe sub-devices is provided by the PCIe interface differential output clock of the LS2K1000. The 12MHz clock for USB is provided by the LS2K1000's internal clock source. The SATA clock source is provided by the LS2K1000's internal system clock. The core module RTC clock is provided by a 32.768kHz crystal. The Loongson 2K1000 processor integrates one SATA 2.0 interface and one NAND controller.The SATA interface signal of the 2K1000 is output to the baseboard's mSATA connector via a COME connector for mounting an mSATA hard drive. The SATA data cable is output via AC coupling. The SATA clock uses the 2K1000's internal clock. The carrier board features an onboard NAND flash. The NAND flash chip used is the Fudan Microelectronics FM29G04C, with a capacity of 4Gbit. The carrier board outputs the 2K1000's DVO signal to the baseboard via an inter-board COME connector, with a 22-ohm resistor connected in series at the DVO signal output for impedance matching. The baseboard uses a DVO-to-HDMI chip to convert the DVO signal into an HDMI signal for external display output. A FLASH chip on the carrier board stores the 2K1000's UEFI program. The baseboard's FPGA is the YX5F200T-676I from Wuxi Zhongwei Yixin Co., Ltd., with an external clock generated by a crystal oscillator at a frequency of 48MHz. The operating clocks of each functional module are multiplied and divided by the FPGA's internal DCM. The FPGA's external clock is provided by a crystal oscillator. The baseboard FPGA is equipped with a non-volatile serial Nor Flash to store the FPGA power-on startup program. The FPGA power-on startup is configured in master string SPI mode. The baseboard FPGA reset chip is an SM706TEIP, which resets the FPGA's pro_b signal approximately 120ms after power-on and resets the FPGA 2.25s after the FPGA heartbeat stops. The NVRAM is configured in non-volatile mode and connected to FPGA BANK13. A button battery is placed on the baseboard to provide the VBAT voltage signal, which provides continuous power to the RTC circuit of the 2K1000 chip on the carrier board through the inter-board COME connector. The main control board outputs two RS232 serial ports and one 2K1000 debug serial port through the J30JA1C1-37ZJW connector. By connecting the RX and TX signals of UART0, UART1, and UART2 on the carrier board to the baseboard FPGA via the inter-board COME connector, and then having the FPGA transfer them to the serial transceiver, the 2K1000 debug serial port can flexibly switch between the three external RS232 interfaces. The serial transceiver uses a proprietary low-dropout transmitter input stage, utilizing a dual charge pump to achieve RS232 performance with a power supply ranging from 3.0V to 5.5V, ensuring consistent output level at a data rate of 250kbps. To protect the subsequent circuitry, a TVS transient voltage suppressor diode is connected in parallel. The transient voltage suppressor diode is model SMBJ15CA, with a VRWM of 15V. When transient voltages occur in the circuit, the TVS utilizes the avalanche principle to instantly shunt and limit the voltage with a p-second response time. Two CAN bus interface signals are simultaneously brought out via the J30JA1C1-37ZJW aviation plug and the baseboard connector. A transient suppression diode is added between the connector and the transceiver to protect the CAN bus.The baseboard FPGA outputs ISA bus signals to the PDS-90JW connector. The carrier board power module uses two ACT4644 chips and one XC5121 chip to provide 1.1V, 3.3V, 2.5V, 1.5V, 1.15V, and 1.2V voltage signals to the core board, respectively. The baseboard power module uses one ACT4644 chip and two ACT4622 chips to provide 1.0V, 1.8V, 3.3V, 2.5V, 1.2V, and 0.85V voltage signals to the baseboard, respectively.

[0032] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings. However, it should be understood that the above description is merely exemplary. Those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A fully domestically produced task management main control board, characterized in that, It includes a carrier board based on the 2K1000 core and a baseboard based on the YX5F200T core. The two boards are connected via a COME Type 10 standard connector to realize bus interface information exchange function. The main control board has a CPU with a main frequency of 800MHz and 1GB of memory. It expands externally through the J30JA1C1-37ZJW connector to have 2 RS232 serial interfaces, 1 RS232 debug serial port, 2 10 / 100 / 1000base-T adaptive Ethernet interfaces, and 2 CAN interfaces. It also expands externally through the PDS-90JW connector to have 1 ISA bus interface. The baseboard includes an additional mSATA interface for mounting an mSATA hard drive. The baseboard has one HDMI port and four USB ports; all components used in the task management main control board are 100% domestically produced.

2. The fully domestically produced task management main control board according to claim 1, characterized in that: The CPU chip on the carrier board is a Loongson 2K1000 processor with a CPU frequency of 800MHz. The processor is connected to four DDR3 chips through an integrated 64-bit 533MHz DDR3 controller. The DDR3 chips are Shenzhen Guowei's SM41J256M16EIP, with a single memory chip capacity of 256MB, a 16-bit data bus, and a total capacity of 1GB. The Loongson 2K1000 processor integrates two x4 PCIe 2.0 interfaces and uses the PCIe 1 interface. The PCIe1 interface supports 1-way x4 and 2-way x1 modes. Configure the PCIe1 interface to x4 mode. The PCIe differential signal is AC coupled through a 100nF coupling capacitor and then connected to the inter-board connector. The AC coupling capacitor is placed close to the inter-board connector at the transmitting end. The PCIe reset output signal is pulled up and connected to the COME Type 10 standard connector for use as a reset signal input for PCIe devices on the backplane.

3. The fully domestically produced task management main control board according to claim 1, characterized in that: The 2K1000 processor on the carrier board integrates two GMAC controllers. These controllers are configured for RGMII interface mode, with RGMII signals output to the baseboard via a COME Type 10 standard connector. The baseboard uses two B88E1111NYB chips from the Beijing Microelectronics Technology Research Institute. The PHY chip converts two RGMII signals into two 10 / 100 / 1000M adaptive Ethernet interface signals and outputs them to the network transformer. The PHY chip reset signal is controlled by the baseboard FPGA chip, and the MDCK / MDIO signals are pulled up to RSM2.5V near the 2K1000 chip using a 4.7K resistor. The RGMII clock delay is implemented by the CPU configuring the relevant PHY registers. The PHY0 address is 0x0001, and the PHY1 address is 0x0010. The network transformer is an NWT type network transformer from Shenzhen Zhenhua Fu Electronics Co., Ltd., model JWNWT161002-1-C. The PHY chip output is current-type, and the transformer's center tap is connected to the power supply. The Loongson 2K1000 processor integrates four USB 2.0 interfaces, connecting the four USB signals to the COME Type. 10 standard connectors; USB clock configured with an external 12MHz active crystal oscillator; USB controller, USB clock, and USB interface power supply use RSM domain power supply; the differential signals of the 4 USB interfaces output by 2K1000 are connected to the COME connector after passing through a common-mode inductor and an ESD transistor to implement the electrostatic discharge protection and overcurrent protection functions of the interface.

4. The fully domestically produced task management main control board according to claim 1, characterized in that: The COMe carrier board reset chip uses Shenzhen Guowei's SM706TEIP, which integrates a watchdog function. At the same time, the LS2K_WDI watchdog input signal of the 2K1000 is connected to the COMe connector to monitor the heartbeat of the main control board through an external watchdog. The PCIe reference input clock of the Loongson 2K1000 is provided by the chip's internal system clock, and the reference input clock of the PCIe sub-devices is provided by the differential output clock of the 2K1000's PCIe interface. The 12MHz clock for USB is provided by the LS2K1000's built-in clock source; the SATA clock source is provided by the LS2K1000's internal system clock; the core module's RTC clock is provided by a 32.768kHz crystal; the Loongson 2K1000 processor integrates one SATA 2.0 interface and one NAND controller; the SATA interface signal of the 2K1000 is output to the underlying mSATA connector via the COME connector for mounting mSATA hard drives; the SATA data cable is output via AC coupling, with a coupling capacitor of 10nF, and the connector is placed close to the transmitting end; the SATA clock uses the 2K1000's internal clock; the carrier board is designed with an onboard NAND flash; the NAND flash chip selected is the Fudan Microelectronics FM29G04C, with a capacity of 4Gbit; The carrier board outputs the 2K1000 DVO signal to the baseboard through the inter-board COME connector. A 22-ohm resistor is connected in series at the DVO signal output terminal for impedance matching. The baseboard converts the DVO signal into an HDMI signal for external display output through a DVO-to-HDMI chip. The conversion chip is the GM7510 from Chengdu Zhenxin Technology Co., Ltd. The carrier board uses a FLASH chip to store the 2K1000 UEFI program. The FLASH chip model is SM25QH256EIP.

5. The fully domestically produced task management main control board according to claim 1, characterized in that: The baseboard FPGA uses the YX5F200T-676I from Wuxi Zhongwei Yixin Co., Ltd., which contains 215,360 logic units, 740 DSP48 Slices, and 13,140Kb of programmable Block RAM. The external clock of the FPGA is generated by a crystal oscillator with a frequency of 48MHz. The operating clock of each functional module is implemented by frequency multiplication and division of the FPGA's internal DCM. The external clock crystal oscillator of the FPGA is the ZA70-DB-3-G-48M00000 (JW) crystal oscillator from Wuhan Haichuang. The baseboard FPGA is equipped with a non-volatile serial Nor Flash, which uses the SM25QH256M chip from Shenzhen Guowei Electronics, to store the FPGA's power-on startup program. By pulling up and pulling down the FPGA configuration signal lines M2 to M0, they are configured to the 001 state, that is, the FPGA's power-on startup is configured as the master serial SPI mode.

6. The fully domestically produced task management main control board according to claim 1, characterized in that: The FPGA reset chip used on the baseboard is the SM706TEIP from Shenzhen Guowei, which integrates a watchdog function. Approximately 120ms after power-on on the baseboard, the FPGA's pro_b signal is de-reset. The reset chip will reset the FPGA 2.25s after the FPGA heartbeat stops.

7. The fully domestically produced task management main control board according to claim 1, characterized in that: The NVRAM used on the baseboard is the RC5NP256K16-PSODW from Hunan Rongchuang Microelectronics Co., Ltd. The RC5NP256K16-PSODW is a 256K×16bit non-volatile static random access memory (SRAM). The RC5NP256K16-PSODW has two operating modes: SRAM mode and non-volatile mode. In SRAM mode, the RC5NP256K16-PSODW performs various read and write operations like a static random access memory. In non-volatile mode, data is stored in non-volatile cells from SRAM, or read from non-volatile cells into SRAM. In non-volatile mode, SRAM interface access operations are prohibited, and the host is not allowed to initiate any address read or write operations on the SRAM interface or cause abnormal toggling of the SRAM interface signals, in order to avoid unknown problems. Configure the NVRAM to non-volatile mode and connect it to the FPGA BANK13.

8. The fully domestically produced task management main control board according to claim 1, characterized in that: A button battery is placed on the base plate to provide the VBAT voltage signal, and the RTC circuit of the 2K1000 chip on the carrier board is continuously powered through the COME Type 10 standard connector between the boards. The main control board outputs two RS232 serial ports and one 2K1000 debug serial port via a J30J connector; the serial transceiver used is the HCE3232MJ from Sevenstar Technology; by connecting the RX and TX signals of the carrier board's UART0, UART1, and UART2 to the base FPGA via the inter-board COME connector, and then having the FPGA transfer them to the serial transceiver, the 2K1000 debug serial port can be flexibly switched between the three externally exposed RS232 interfaces; HCE3 The 232MJ employs a low-dropout transmitter input stage, utilizing a dual charge pump to achieve RS232 performance when powered by a 3.0V to 5.5V supply, ensuring output level is maintained at a data rate of 250kbps. To protect subsequent circuitry, a TVS transient voltage suppressor diode is connected in parallel. The selected transient voltage suppressor diode is model SMBJ15CA with a VRWM of 15V. When transient voltages are generated in the circuit, the TVS utilizes the avalanche principle to instantly shunt and limit the voltage with a picosecond-level response speed.

9. A fully domestically produced task management main control board according to claim 1, characterized in that: The CAN transceiver selected is the SMUM3055MP from Shenzhen Guowei Technology Co., Ltd. This chip integrates the CAN transceiver and DC-DC converter into a single IC chip, with a data rate of up to 12Mbps and an isolation withstand voltage of 2.5KV. It has reserved two CAN bus interface signals, which are brought out simultaneously through the J30J aviation connector and the baseboard connector. A transient suppression diode NUP2105L from Zhenhua Yongguang is added between the connector and the transceiver to protect the CAN bus. The device has a reverse working voltage of 24V, a breakdown voltage of 26.2V, a maximum peak pulse current of 8A, and a maximum peak pulse power of 350W.

10. A fully domestically produced task management main control board according to claim 1, characterized in that: The ISA bus signals are output to the PDS-90JW connector via the baseboard FPGA. Four HWD16T245ESOP48 chips from Chengdu Huawi Electronics Technology Co., Ltd. are used for the 3.3V to 5V level conversion of the ISA bus. The HWD16T245 is a 16-bit dual-supply in-phase bidirectional level converter; VCCA and VCCB are powered by 3.3V and 5.5V power supplies, respectively, and convert between 3.3V and 5V signals. The carrier board power module uses two ACT4644 chips and one XC5121 chip to provide 1.1V, 3.3V, 2.5V, 1.5V, 1.15V, and 1.2V voltage signals to the core board, respectively. The baseboard power module uses one ACT4644 chip and two ACT4622 chips to provide 1.0V, 1.8V, 3.3V, 2.5V, 1.2V, and 0.85V voltage signals to the baseboard, respectively.

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