Path switching device

Abstract

The application discloses a path switching device and belongs to the field of electronic equipment. The path switching device comprises a master control chip, a path switcher, a device insertion detector, a signal detector and a universal serial bus C type interface; the device insertion detector is connected with the master control chip and the C type interface respectively; the signal detector is connected with the master control chip and the path switcher respectively; the path switcher is connected with the master control chip and the C type interface respectively; wherein the master control chip is connected with the path switcher via a group of USB signal paths, and the path switcher is connected with the C type interface via two groups of USB signal paths.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment, and specifically relates to a path switching device. Background Technology

[0002] Currently, the Universal Serial Bus Type-C (USB Type-C) interface, as a universal and reversible pluggable interface, has been widely used in various electronic devices such as smartphones and laptops, becoming the main interface for the next generation and future electronic devices.

[0003] Because the TYPE-C interface supports reversible insertion, it connects to the main control chip through two sets of Universal Serial Bus (USB) signal paths. One set of USB signal paths supports reversible insertion, while the other set supports reverse insertion, ensuring normal communication when peripherals are randomly inserted.

[0004] In related technologies, the main control chip is connected to two sets of USB signal paths respectively, which requires the main control chip to support two sets of USB signal paths, thus increasing the requirements for the main control chip. Utility Model Content

[0005] This application provides a path switching device that can solve the problem that related technologies have high requirements for the main control chip.

[0006] In a first aspect, embodiments of this application provide a path switching device, including: a main control chip, a path switcher, a device insertion detector, a signal detector, and a Universal Serial Bus Type-C interface; The device insertion detector is connected to the main control chip and the C-type interface respectively; the signal detector is connected to the main control chip and the path switch respectively; the path switch is connected to the main control chip and the C-type interface respectively. The main control chip is connected to the channel switcher via a set of USB signal paths, and the channel switcher is connected to the C-type interface via two sets of USB signal paths. The USB signal paths between the main control chip and the path switcher include a first transmitting signal path, a second transmitting signal path, a first receiving signal path, and a second receiving signal path. The first set of USB signal paths in the two sets of USB signal paths includes a first transmitting path, a second transmitting path, a first receiving path, and a second receiving path; the second set of USB signal paths in the two sets of USB signal paths includes a third transmitting path, a fourth transmitting path, a third receiving path, and a fourth receiving path. The first transmission signal path is connected to the first target transmission path via the path switcher, and the first target transmission path is either the first transmission path or the third transmission path. The second transmission signal path is connected to the second target transmission path via the path switcher, and the second target transmission path is either the second transmission path or the fourth transmission path; The first receiving signal path is connected to the first target receiving path via the path switcher, and the first target receiving path is either the first receiving path or the third receiving path. The second receiving signal path is connected to the second target receiving path via the path switcher, and the second target receiving path is either the second receiving path or the fourth receiving path.

[0007] This application provides a path switching device. The main control chip only needs to support one set of USB signal paths to connect with the two sets of USB signal paths of the TYPE-C interface. It can realize the reversible insertion function of the TYPE-C interface without supporting two sets of USB signal paths, which reduces the requirements for the main control chip and solves the problem of high requirements for the main control chip in related technologies. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a TYPE-C interface provided in an embodiment of this application; Figure 2 This is a schematic diagram of a path switching device provided in an embodiment of this application; Figure 3 This is a schematic diagram of another path switching device provided in an embodiment of this application; Figure 4 This is a schematic diagram of another path switching device provided in an embodiment of this application; Figure 5 This is a schematic diagram of a transmission channel switching module provided in an embodiment of this application; Figure 6 This is a schematic diagram of a receiving channel switching module provided in an embodiment of this application; Figure 7 This is a schematic diagram of a single-coil latching relay provided in an embodiment of this application; Figure 8 This is a schematic diagram of a signal detector provided in an embodiment of this application; Figure 9 This is a schematic diagram of a device insertion detector provided in an embodiment of this application; Figure 10 This is a schematic diagram of a path switching device provided in an embodiment of this application; Figure 11 This is a schematic diagram of a path switching method provided in an embodiment of this application.

[0009] Explanation of reference numerals in the attached figures: Path switching device-100; Main control chip-200; Path switcher-300; First relay-310; Second relay-320; Third relay-330; Fourth relay-340; TYPE-C interface-400; TX1+ pin-401; TX2+ pin-402; TX1- pin-403; TX2- pin-404; RX1+ pin-405; RX2+ pin-406; RX1- pin-407; RX2- pin-408; GND1 pin-409; GND2 pin-410; Signal detector-500; Voltage sampler-510; First resistor-520; Second resistor-530; Device insertion detector-600; First MOSFET-610; Second MOSFET-620; Fifth relay-630; Sixth relay-640; Third MOSFET-650; Fourth MOSFET-660. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0011] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0012] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0013] The path switching device provided in this application embodiment is applied to the path switching process of the TYPE-C interface. The main control chip in the path switching device does not need to support two sets of USB signal paths to realize the reversible insertion function of the TYPE-C interface, which can reduce the design cost of the entire device.

[0014] The following section introduces the pins of the TYPE-C interface. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of a TYPE-C interface provided in an embodiment of this application. For example... Figure 1 As shown, the pins of the TYPE-C interface are divided into two symmetrical rows (A and B sides). The A side has 12 pins (pin numbers A1-A12) and the B side has 12 pins (pin numbers B1-B12).

[0015] Pins A1, A12, B1, and B12 are ground (GND) pins, used to provide a current loop. Pins A2, A3, B2, and B3 are transmit channel pins, namely the positive terminal (TX1+) of the first transmit channel, the negative terminal (TX1-) of the first transmit channel, the positive terminal (TX2+) of the second transmit channel, and the negative terminal (TX2-) of the second transmit channel, respectively, used to provide a high-speed data transmission path for transmitters in USB or DP Alt (DisplayPort Alternate) mode. Pins A4, A9, B4, and B9 are voltage bus (VBUS) pins, used to power peripherals; the dual VBUS pin design enhances current carrying capacity. Pins A5 and B5 are configuration channel pins, namely pin CC1 and pin CC2, used for plug configuration detection to detect the device insertion direction (positive or negative) and connection type, etc. Only one of the two pins is used as a power supply pin (Vconn) to power the cable, and the other is used for the configuration channel for USB Power Delivery (PD) communication.

[0016] Pins A6, A7, B6, and B7 are USB 2.0 pins, including the D+ and D- pins. The D+ and D- pins are USB 2.0 signal pins; USB 3.0 requires backward compatibility with USB 2.0, meaning it supports connecting USB 2.0 devices. Pins A8 and B8 are Side Band Use (SBU) pins, specifically SBU1 and SBU2, used for special modes (e.g., transmitting AUX signals in DP Alt mode). Pins A10, A11, B10, and B11 are receive channel pins, namely the second receive channel negative terminal (RX2-), the second receive channel positive terminal (RX2+), the first receive channel negative terminal (RX1-), and the first receive channel positive terminal (RX1+), providing a high-speed data transmission path for USB or DP Alt mode receivers.

[0017] The path switching device provided in this application will be described below with reference to the accompanying drawings and specific embodiments.

[0018] For reference Figure 2 , Figure 2 This is a schematic diagram of a path switching device provided in an embodiment of this application. Figure 2 As shown, the path switching device 100 includes a main control chip 200, a path switcher 300, a TYPE-C interface 400, a signal detector 500, and a device insertion detector 600. The device insertion detector 600 is connected to both the main control chip 200 and the TYPE-C interface 400; the signal detector 500 is connected to both the main control chip 200 and the path switcher 300; and the path switcher 300 is connected to both the main control chip 200 and the TYPE-C interface 400.

[0019] The main control chip is connected to the channel switcher via a set of USB signal paths, and the channel switcher is connected to the TYPE-C interface via two sets of USB signal paths. The set of USB signal paths between the main control chip and the channel switcher includes a first transmitting signal path, a second transmitting signal path, a first receiving signal path, and a second receiving signal path. The first set of USB signal paths includes a first transmitting path, a second transmitting path, a first receiving path, and a second receiving path. The second set of USB signal paths includes a third transmitting path, a fourth transmitting path, a third receiving path, and a fourth receiving path.

[0020] The first transmitting signal path is connected to a first target transmitting path via the path switcher, where the first target transmitting path is either the first transmitting path or the third transmitting path. The second transmitting signal path is connected to a second target transmitting path via the path switcher, where the second target transmitting path is either the second transmitting path or the fourth transmitting path. The first receiving signal path is connected to a first target receiving path via the path switcher, where the first target receiving path is either the first receiving path or the third receiving path. The second receiving signal path is connected to a second target receiving path via the path switcher, where the second target receiving path is either the second receiving path or the fourth receiving path.

[0021] The device insertion detector is used to determine whether a peripheral device is connected to the TYPE-C interface. The signal detector is used to detect the insertion direction (correct or incorrect) of the USB signal of the TYPE-C interface to determine whether the main control chip is connected to the TYPE-C interface via a first set of USB signal paths or a second set of USB signal paths. In other words, the first target transmission path, the second target transmission path, the first target reception path, and the second target reception path can be determined based on the detection results of the signal detector.

[0022] The TYPE-C interface can be a standard 24-pin TYPE-C interface. The definition of each pin can be found in the description of the standard TYPE-C interface, for example, the above-mentioned pin definitions. Figure 1 The main control chip may include a general-purpose processor, such as a System on Chip (SoC) chip. The main control chip may support only one USB 3.0 communication interface, and does not need to support two USB 3.0 communication interfaces.

[0023] In this embodiment, the main control chip only needs to support one set of USB signal paths to connect with the two sets of USB signal paths of the TYPE-C interface. It does not need to support two sets of USB signal paths to realize the reversible insertion function of the TYPE-C interface, which reduces the requirements for the main control chip and solves the problem of high requirements for the main control chip in related technologies.

[0024] In one embodiment of this application, in Figure 2 Based on this, the TYPE-C interface includes a first pair of receive pins, a second pair of receive pins, a first pair of transmit pins, and a second pair of transmit pins. See details for further information. Figure 3 , Figure 3 This is a schematic diagram of another path switching device provided in an embodiment of this application. Figure 3As shown, the first pair of transmit pins includes a first transmit channel positive terminal (TX1+) pin 401 and a second transmit channel positive terminal (TX2+) pin 402, and the second pair of transmit pins includes a first transmit channel negative terminal (TX1-) pin 403 and a second transmit channel negative terminal (TX2-) pin 404; the first pair of receive pins includes a first receive channel positive terminal (RX1+) pin 405 and a second receive channel positive terminal (RX2+) pin 406, and the second pair of receive pins includes a first receive channel negative terminal (RX1-) pin 407 and a second receive channel negative terminal (RX2-) pin 408.

[0025] Specifically, the path switcher 300 is connected to the TX1+ pin 401 via the first transmit path; the path switcher 300 is connected to the TX1- pin 403 via the second transmit path; the path switcher 300 is connected to the RX1+ pin 405 via the first receive path; and the path switcher 300 is connected to the RX1- pin 407 via the second receive path. The path switcher 300 is connected to the TX2+ pin 402 via the third transmit path; the path switcher 300 is connected to the TX2- pin 404 via the fourth transmit path; the path switcher 300 is connected to the RX2+ pin 406 via the third receive path; and the path switcher 300 is connected to the RX2- pin 408 via the fourth receive path. In this way, when the main control chip is connected to the TYPE-C interface via the first set of USB signal paths, the main control chip can communicate through the USB TX1± / RX1± signal paths; when the main control chip is connected to the TYPE-C interface via the second set of USB signal paths, the main control chip can communicate through the USB TX2± / RX2± signal paths, so as to realize the reversible insertion function of the TYPE-C interface.

[0026] In one embodiment of this application, in Figure 3 Based on this, the path switcher includes a first relay, a second relay, a third relay, and a fourth relay. See also... Figure 4 , Figure 4 This is a schematic diagram of another path switching device provided in an embodiment of this application. Figure 4 As shown, the first terminal of the first relay 310 is coupled to the first transmitting signal path, and the second and third terminals of the first relay 310 are respectively coupled to two pins in the first pair of transmitting pins. For example Figure 4The second terminal of the first relay 310 is connected to the TX1+ pin, and the third terminal of the first relay 310 is connected to the TX2+ pin. The fourth terminal of the first relay 310 is coupled to the second transmitting signal path, and the fifth and sixth terminals of the first relay 310 are respectively coupled to two pins in the second pair of transmitting pins. For example... Figure 4 The fifth terminal of the first relay 310 is coupled to the TX1 pin, and the sixth terminal of the first relay 310 is coupled to the TX2 pin. The coupling in this embodiment can be understood as a direct connection or an indirect connection via other components.

[0027] The first terminal of the second relay 320 is coupled to the first receiving signal path, and the second and third terminals of the second relay 320 are respectively coupled to two pins of the first pair of receiving pins. For example Figure 4 The second terminal of the second relay 320 is connected to the RX1+ pin, and the third terminal of the second relay 320 is connected to the RX2+ pin. The fourth terminal of the second relay 320 is coupled to the second received signal path, and the fifth and sixth terminals of the second relay 320 are respectively coupled to two pins of the second pair of received pins. For example... Figure 4 The fifth terminal of the second relay 320 is coupled to the RX1 pin, and the sixth terminal of the second relay 320 is coupled to the RX2 pin.

[0028] The first terminal of the third relay 330 is connected to the first terminal of the first relay 310; the first terminal of the signal detector 500 is connected to the main control chip 200; the second terminal of the third relay 330 is connected to the second terminal of the signal detector 500; and the third terminal of the third relay 330 is connected to the first transmitting signal path. The fourth terminal of the third relay 330 is connected to the fourth terminal of the first relay 310; the fifth terminal of the third relay 330 is connected to the third terminal of the signal detector 500; and the sixth terminal of the third relay 330 is connected to the second transmitting signal path.

[0029] The first terminal of the fourth relay 340 is connected to the first terminal of the second relay 320. The second terminal of the fourth relay 340 is floating, meaning it is not connected to a signal. The third terminal of the fourth relay 340 is connected to the first receiving signal path, meaning it is connected to the main control chip 200. The fourth terminal of the fourth relay 340 is connected to the fourth terminal of the second relay 320. The fifth terminal of the fourth relay 340 is floating, meaning it is not connected to a signal. The sixth terminal of the fourth relay 340 is connected to the second receiving signal path, meaning it is connected to the main control chip 200.

[0030] The first terminal and the fourth terminal of the first relay are common terminals of the first relay. The first terminal and the fourth terminal of the second relay are common terminals of the second relay. The first terminal and the fourth terminal of the third relay are common terminals of the third relay. The first terminal and the fourth terminal of the fourth relay can also be common terminals of the fourth relay. All relays—the first, second, third, and fourth—can be in either a first state or a second state. The first and second states represent two connection states of the common terminals of the relays. Taking the first relay 310 as an example, in the first state, the first terminal of the first relay is connected to the second terminal, and the fourth terminal is connected to the fifth terminal. In the second state, the first terminal is connected to the third terminal, and the fourth terminal is connected to the sixth terminal. The second and fifth terminals of the first relay are static contacts, and the third and sixth terminals are dynamic contacts. By default, all relays—the first, second, third, and fourth—are in the first state.

[0031] Specifically, when the first relay is in the first state, the first terminal of the first relay is connected to the second terminal, and the fourth terminal of the first relay is connected to the fifth terminal. At this time, the main control chip is connected to the TX1+ pin of the TYPE-C interface via the first relay and the first transmission path, and the main control chip is connected to the TX1- pin of the TYPE-C interface via the first relay and the second transmission path. When the first relay is in the second state, the first terminal of the first relay is connected to the third terminal, and the fourth terminal of the first relay is connected to the sixth terminal. At this time, the main control chip is connected to the TX2+ pin of the TYPE-C interface via the first relay and the third transmission path, and the main control chip is connected to the TX2- pin of the TYPE-C interface via the first relay and the fourth transmission path.

[0032] When the second relay is in the first state, the first terminal of the second relay is connected to the second terminal, and the fourth terminal of the second relay is connected to the fifth terminal. At this time, the main control chip is connected to the RX1+ pin of the TYPE-C interface via the second relay and the first receiving path, and the main control chip is connected to the RX1- pin of the TYPE-C interface via the second relay and the second receiving path. When the second relay is in the second state, the first terminal of the second relay is connected to the third terminal, and the fourth terminal of the second relay is connected to the sixth terminal. At this time, the main control chip is connected to the RX2+ pin of the TYPE-C interface via the second relay and the third receiving path, and the main control chip is connected to the RX2- pin of the TYPE-C interface via the second relay and the fourth receiving path.

[0033] When the third relay is in its first state, its first terminal is connected to its second terminal, and its fourth terminal is connected to its fifth terminal. In this state, the signal detector communicates with either the USB TX1± or USB TX2± path via the third and first relays, and can detect whether a peripheral connected to the TYPE-C interface is accessed via the USB TX1± or USB TX2± path. When the third relay is in its second state, its first terminal is connected to its third terminal, and its fourth terminal is connected to its sixth terminal. In this state, the main control chip can perform normal enumeration communication with the peripheral via the third and first relays through either the USB TX1± or USB TX2± path.

[0034] When the fourth relay is in the first state, its first terminal is connected to its second terminal, and its fourth terminal is connected to its fifth terminal. At this time, the RX channel of the TYPE-C interface is not connected to the main control chip. When the fourth relay is in the second state, its first terminal is connected to its third terminal, and its fourth terminal is connected to its sixth terminal. At this time, the main control chip can perform normal enumeration communication with peripherals via the fourth and second relays through the USB RX1± or USB RX2± channels.

[0035] In this way, the peripheral access signal detection can be realized by controlling the third relay to be in the first state, that is, detecting whether the peripheral is connected to the USB TX1± channel or the USB TX2± channel. Normal enumeration communication between the peripheral and the main control chip can be realized through the first relay, the second relay and the fourth relay.

[0036] In one embodiment of this application, the first relay, second relay, third relay, and fourth relay in the above embodiments are all double-open, double-closed relays. The main control chip is coupled to the seventh terminal of the first relay, the seventh terminal of the second relay, the seventh terminal of the third relay, and the seventh terminal of the fourth relay, respectively. The seventh terminals of the first relay, the second relay, the third relay, and the fourth relay are all control terminals. The main control chip can receive information transmitted from other modules (e.g., signal detectors and device insertion detectors) and control the control terminals of the four relays (first relay, second relay, third relay, and fourth relay) according to the information transmitted by other modules, thereby indirectly controlling the relays to be in a first state or a second state.

[0037] In this embodiment, the double-pole double-throw relay can be understood as a double-pole double-throw relay, which is equivalent to two single-pole single-throw switches that can be controlled simultaneously. By using the double-pole double-throw relay, two independent circuits can be switched synchronously with a single control signal.

[0038] In this embodiment, the channel switcher includes a transmitting channel switching module and a receiving channel switching module. See details below. Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of a transmission channel switching module provided in an embodiment of this application. Figure 6 This is a schematic diagram of a receiving channel switching module provided in an embodiment of this application. The transmitting channel switching module includes, as shown below: Figure 5The first capacitor C1, the second capacitor C2, the first relay 310, and the third relay 330 shown are used in the transmit channel switching module to switch between the main control chip and the TX1 and TX2 channels of the TYPE-C interface. The receive channel switching module includes, as shown in the diagram... Figure 6 The second relay 320 and the fourth relay 340 shown are used to switch the receiving channel switching module between the main control chip and the RX1 and RX2 channels of the TYPE-C interface.

[0039] According to the USB protocol, two coupling capacitors can be placed between the main control chip and the third relay, namely... Figure 5 The first capacitor C1 and the second capacitor C2 are shown. Specifically, the TX- channel of the main control chip 200 is connected to the sixth terminal of the third relay 330 via the first capacitor C1, and the TX+ channel of the main control chip 200 is connected to the third terminal of the third relay 330 via the second capacitor C2.

[0040] like Figure 5 As shown, the main control chip can be connected to the seventh terminal of the first relay via the sixth MOSFET Q6, and the main control chip can be connected to the seventh terminal of the third relay via the fifth MOSFET Q5. The eighth terminals of the first and third relays are connected to the third power supply terminal, which is the positive power supply voltage terminal of the circuit (i.e., Vcc terminal). The main control chip can indirectly control the on / off state of the first relay by controlling the sixth MOSFET Q6, thereby controlling the first relay to be in the first state or the second state.

[0041] Taking the control logic of the first relay as an example, the sixth MOS transistor Q6 can be either an NMOS transistor or a PMOS transistor. The following example uses an NMOS transistor. Figure 5 As shown, the main control chip is connected to the gate (G) of the sixth MOSFET Q6, the source (S) of the sixth MOSFET Q6 is grounded, and the drain (D) of the sixth MOSFET Q6 is connected to the seventh terminal of the first relay. Furthermore, the drain of the fifth MOSFET Q5 can also be connected via a diode (…). Figure 5 The first relay (as shown in D4) is connected to the third power supply terminal (Vcc). The main control chip sends a control signal to the seventh terminal of the first relay via the sixth MOSFET Q6. When the control signal is low, the first relay is in the first state; when the control signal is high, the first relay is in the second state. When the main control chip needs to control the first relay to be in the second state, it can output a high-level signal to the sixth MOSFET Q6, causing the sixth MOSFET Q6 to be turned on, thereby outputting a high-level signal to the seventh terminal of the first relay, causing the first relay to be in the second state.

[0042] Similarly, the main control chip can indirectly control the control terminal of the third relay by controlling the fifth MOSFET Q5, thereby controlling the third control terminal to be in the first state or the second state. The control logic of the second relay, the third relay, and the fourth relay is the same as the control logic of the first relay, and can be referred to the control logic of the first relay, which will not be repeated here. Furthermore, Figure 5 as well as Figure 6 The connection relationship of the fifth MOSFET Q5, the seventh MOSFET Q7, and the eighth MOSFET Q8 can be referred to the sixth MOSFET Q6, and will not be repeated here. For the introduction of diodes D3, D5, and D6, please refer to diode D4, and will not be elaborated here.

[0043] In one embodiment of this application, the first relay, the second relay, the third relay, and the fourth relay in the above embodiments are all single-coil latching relays. A single-coil latching relay is a relay with a memory function; its state can be changed by applying a current pulse. Once the current stops, the single-coil latching relay can remain in its last state until a current pulse in the opposite direction is applied again. In other words, a single-coil latching relay can maintain its state even without continuous current, offering the advantage of low power consumption.

[0044] For reference Figure 7 , Figure 7 This is a schematic diagram of a single-coil latching relay provided in an embodiment of this application. Figure 7 As shown, a single-coil latching relay includes a switch and a channel. The switch is the control terminal of the single-coil latching relay, including, for example... Figure 7 Terminals A1 and A8 are shown. The channel is the controlled terminal of the single-coil latching relay, including, for example... Figure 7 The two switches shown. The first switch is... Figure 7 The diagram shows terminals A2, A3, and A4, with A3 being the common terminal. The second switch is... Figure 7 The A5, A6, and A7 terminals are shown, with A6 being the common terminal.

[0045] The signal detector described in the above embodiments will be introduced below. The signal detector is used to detect the insertion direction of the USB signal of the TYPE-C interface to determine whether to switch the signal path to USB TX1 / RX1 or USB TX2 / RX2.

[0046] Both the third relay and the first relay are in the first state by default. For example... Figure 4As shown, when the main control chip determines that a device has been inserted (i.e., the device insertion detector detects a device insertion), since the main control chip is connected to the TX1+ and TX1- pins of the TYPE-C interface via a signal detector, a third relay, and a first relay, the signal detector can detect whether the main control chip is communicating with the peripheral via the TX1+ and TX1- pins. When the signal detector detects that the main control chip is communicating with the peripheral via the TX1± pins, the third relay can be controlled to be in a second state, thereby connecting the main control chip to the TX1+ and TX1- pins via the third relay and the first relay, allowing the main control chip to perform normal enumeration communication with the peripheral via the TX1± pins of the TYPE-C interface. Furthermore, the fourth relay can be simultaneously controlled to be in a second state, allowing the main control chip to connect to the RX1+ and RX1- pins via the fourth relay and the second relay, enabling the main control chip to perform normal enumeration communication with the peripheral via the RX1± pins of the TYPE-C interface.

[0047] When the signal detector detects that the main control chip is not communicating with the peripheral via the TX1± pin, the first relay can be controlled to be in a second state. This allows the main control chip to connect to the TX2+ pin of the TYPE-C interface via the signal detector, the third relay, and the first relay. The signal detector can then detect whether the main control chip is communicating with the peripheral via the TX2+ and TX2- pins. When the signal detector detects that the main control chip is communicating with the peripheral via the TX2± pin, the third relay can be controlled to be in a second state. This allows the main control chip to connect to the TX2+ and TX2- pins via the third relay and the first relay, enabling the main control chip to perform normal enumeration communication with the peripheral via the TX2± pin of the TYPE-C interface. Furthermore, the second and fourth relays can be simultaneously controlled to be in a second state, allowing the main control chip to perform normal enumeration communication with the peripheral via the RX2± pin of the TYPE-C interface.

[0048] In this embodiment, a signal detector can determine whether the peripheral is connected to the TX1 / RX1 path of the TYPE-C interface or to the TX2 / RX2 path of the TYPE-C interface. This method can realize the detection and switching of signal paths without relying on the CC controller.

[0049] exist Figure 4 Based on this, in one embodiment of this application, the signal detector includes a voltage sampler, a first resistor, and a second resistor. See also... Figure 8 , Figure 8 This is a schematic diagram of a signal detector provided in an embodiment of this application. Figure 8As shown, the signal detector 500 includes a voltage sampler 510, a first resistor 520, and a second resistor 530. The voltage sampler 510 is coupled to the second and fifth terminals of the third relay 330, respectively. One end of the first resistor 520 is connected to the first power supply terminal (…). Figure 8 The circuit is connected as shown in the diagram (Vdd). The other end of the first resistor 520 is connected to the first connection point, which is located in the path between the voltage sampler 510 and the third relay 330. The first power supply terminal is the positive power supply voltage of the circuit. One end of the second resistor 530 is connected to the first power supply terminal, and the other end of the second resistor 530 is connected to the second connection point, which is located in the path between the voltage sampler 510 and the third relay 330.

[0050] In this embodiment, the voltage sampler may include an analog-to-digital converter (ADC). When the main control chip determines that a peripheral device has been inserted, i.e., the device insertion detector detects the insertion, the main control chip can control the voltage sampler to begin voltage sampling. Whether the peripheral device is connected to the circuit or not, the voltage on the peripheral's receiving path (RX±) will differ. The voltage sampler can be coupled to the second and fifth terminals of the third relay to collect the voltage on the peripheral's RX± channel, thus determining whether the peripheral device is connected to the current signal path.

[0051] The following will introduce the principle of signal path detection using a voltage sampler, a first resistor, and a second resistor. For example... Figure 8 As shown, after the peripheral device is connected to the TYPE-C interface, it is connected to the signal detector via the TYPE-C interface, the first relay, and the third relay. It should be noted that... Figure 8 The WRX+ and WRX- channels are the receiving channels of the peripheral device, not the receiving channels of the TYPE-C interface. The voltage sampler is connected to the receiving (WRX) channel of the peripheral device via the transmit (TX) channel of the TYPE-C interface.

[0052] After the main control chip determines that a peripheral device has been inserted, it controls the voltage sampler to begin sampling. Whether the main control chip is communicating with the peripheral device through the pin connected to the current signal path can be determined by detecting changes in the first and second voltage values ​​detected by the voltage sampler. The first voltage value is the voltage value on the WRX+ channel of the peripheral device collected by the voltage sampler, denoted as Vt1. The second voltage value is the voltage value on the WRX- channel of the peripheral device collected by the voltage sampler, denoted as Vt2. When the peripheral device is not connected to the current signal path, both the first and second voltage values ​​are the voltage values ​​at the first power supply terminal, i.e., Vt1 = Vdd, Vt2 = Vdd.

[0053] After the peripheral device is powered on, its WRX channel has two pull-down resistors connected to GND. The signal detector can use these two pull-down resistors to detect the signal path. Specifically, when the peripheral device is connected to the current signal path, such as... Figure 8 As shown, due to the existence of two pull-down voltages (i.e., ...) when designing the GND pin of the peripheral device. Figure 8 The first and second voltage values ​​sampled by the voltage sampler (using the third resistor R3 and the fourth resistor R4) will change. The first voltage value will change from the voltage value at the first power supply terminal to the voltage division value of the third resistor, i.e., Vt1 = Vdd * R3 / (R1 + R3), and the second voltage value will change from the voltage value at the first power supply terminal to the voltage division value of the fourth resistor, i.e., Vt2 = Vdd * R2 / (R2 + R4).

[0054] In an example, when the voltage sampler starts sampling, if both the first and third relays are in the first state, the current signal path is between the voltage sampler and the TX1+ and TX1- pins of the TYPE-C interface. If the first voltage value acquired by the voltage sampler changes from Vdd to Vdd*R3 / (R1+R3), and the second voltage value changes from Vdd to Vdd*R2 / (R2+R4), then it can be determined that the peripheral device is connected to the current signal path. That is, the peripheral device communicates with the main control chip through the TX1± channel of the TYPE-C interface, and no signal path switching is required at this time. Simultaneously, the four relays can be synchronously controlled to be in the second state, allowing the main control chip to perform normal enumeration communication with the peripheral device through the RX1± pin of the TYPE-C interface.

[0055] If the first and second voltage values ​​acquired by the voltage sampler do not change as described above (the first voltage value changes from Vdd to the voltage division value of the third resistor, and the second voltage value changes from Vdd to the voltage division value of the fourth resistor), it indicates that the peripheral is not communicating with the peripheral through the TX1± pin of the TYPE-C interface. In this case, the main control chip can control the first relay to be in the second state, thereby detecting whether the peripheral is communicating with the peripheral through the TX2± pin of the TYPE-C interface. The detection principle is as described above: detecting whether the first and second voltage values ​​acquired by the voltage sampler have undergone the aforementioned changes. If the aforementioned changes are detected in the first and second voltage values, it indicates that the peripheral is communicating with the main control chip through the TX2± channel of the TYPE-C interface. In this case, both the third and fourth relays can be controlled to be in the second state, allowing the main control chip to perform normal enumeration communication with the peripheral through the TX2± / RX2± pins of the TYPE-C interface.

[0056] The above method enables the detection of peripheral access signals, thereby allowing switching to the corresponding signal path to ensure that the main control chip can perform normal enumeration communication with peripherals connected via the TYPE-C interface.

[0057] Based on any of the above embodiments, the device inserts the detector and connects it to the ground pin of the TYPE-C interface. For example... Figure 1 As shown, the ground pin of the TYPE-C interface can, for example... Figure 1 The four pins are numbered A1, B1, A12, and B12.

[0058] In this embodiment, the device insertion detector is used to determine whether a peripheral device is connected to the TYPE-C interface. Since the GND pin of the TYPE-C interface is grounded when a peripheral device is connected to it, by connecting the device insertion detector to the GND pin of the TYPE-C interface, the presence of a peripheral device connected to the TYPE-C interface can be determined by utilizing this characteristic of the GND pin being grounded.

[0059] Related technologies typically detect the insertion of peripherals using two CC pins (CC1 and CC2) of the TYPE-C interface to determine the insertion direction and connection status. This usually requires an additional CC controller, which increases costs. This embodiment eliminates the need for CC pins for device insertion detection; it directly utilizes the GND pin of the TYPE-C interface, thus avoiding the need for an additional CC controller.

[0060] Furthermore, there is a certain gap between the plug and socket of the TYPE-C interface. When plugging or unplugging peripherals, it is necessary to align them vertically or horizontally with the interface; otherwise, some wobbling will occur during insertion. This wobbling will be more pronounced, especially when frequent plugging and unplugging causes wear on the internal contacts and deformation of the springs, leading to a decrease in the compatibility between the plug and socket. When a peripheral is inserted, power may be supplied before it is fully inserted, resulting in a momentary current surge and unstable power supply to the load.

[0061] Therefore, in one embodiment of this application, the grounding pin may include a first grounding pin and a second grounding pin. The first grounding pin and the second grounding pin may be located diagonally opposite each other on the TYPE-C interface. Specifically, as... Figure 1 As shown, the ground pin with pin number A1 and the ground pin with pin number B1 are located diagonally opposite each other on the TYPE-C interface. The ground pin with pin number B12 and the ground pin with pin number A12 are also located diagonally opposite each other on the TYPE-C interface. Therefore, the first ground pin and the second ground pin can be... Figure 1 The two pins are designated A1 and B1. The specific selection of the first and second grounding pins is not limited here. For example, the first grounding pin can be selected as pin A1, and the second grounding pin can be selected as pin B1. Alternatively, the first grounding pin can be selected as pin B1, and the second grounding pin can be selected as pin A1. Furthermore, the first and second grounding pins can also be selected from the two pins designated A12 and B12, which will not be discussed further here.

[0062] In this way, because the two selected grounding pins are diagonally opposite, the device is detected as fully inserted and in a fully contacted state when it is plugged in. This ensures that power is supplied to the peripheral only after it is fully inserted, which can prevent the peripheral from being plugged in at an angle and the power supply to the peripheral from starting before the TYPE-C interface is fully connected. This would cause a large inrush current when the peripheral power supply starts instantly, affecting the stability of the system.

[0063] See also Figure 9 , Figure 9 This is a schematic diagram of a device insertion detector provided in an embodiment of this application. In one embodiment of this application, the device insertion detector includes a first metal-oxide-semiconductor field-effect transistor (MOS) 610 and a second MOS transistor 620. The grounding pins include a first grounding pin 409 and a second grounding pin 410. A first terminal of the first MOS transistor 610 is coupled to the first grounding pin 409, a second terminal of the first MOS transistor 610 is grounded, a third terminal of the first MOS transistor 610 is coupled to a second power supply terminal, and the third terminal of the first MOS transistor 610 is connected to the main control chip via a first signal line. The second power supply terminal is the positive power supply voltage of the circuit, i.e., Vdd, and the first terminal of the first MOS transistor 610 is the gate. The first end of the second MOSFET 620 is coupled to the second ground pin 410, the second end of the second MOSFET 620 is grounded, the third end of the second MOSFET 620 is coupled to the second power supply terminal, and the third end of the second MOSFET 620 is connected to the main control chip via the second signal line; wherein, the first end of the second MOSFET 620 is the gate.

[0064] The first terminal of the first MOSFET can be directly connected to the first ground pin, or indirectly connected via other components. Similarly, the first terminal of the second MOSFET can be directly connected to the second ground pin, or indirectly connected via other components. The third terminal of the first MOSFET can be directly connected to the second power supply terminal, or the third terminal of the first MOSFET can be connected via a fifth resistor (such as...). Figure 9 The resistor R5 in the first resistor is indirectly connected to the second power supply terminal. Similarly, the third terminal of the second MOSFET can be directly connected to the second power supply terminal, or the third terminal of the second MOSFET can be connected via a sixth resistor (such as...). Figure 9 The fifth resistor (R6) is indirectly connected to the second power supply terminal. The fifth and sixth resistors can be pull-up resistors used for current limiting.

[0065] In this embodiment, the second terminal of the first MOS transistor can be either the source or the drain, and the third terminal of the first MOS transistor can be either the source or the drain. Correspondingly, the second terminal of the second MOS transistor can be either the source or the drain. Specifically, both the first and second MOS transistors can be N-channel metal-oxide-semiconductor field-effect transistors (NMOS), with the second terminal of the first and second MOS transistors serving as the source and the third terminal of the first and second MOS transistors serving as the drain.

[0066] The main control chip determines whether a device is inserted by detecting the level signals transmitted through the first and second signal lines. Specifically, the main control chip determines that a peripheral device is inserted into the TYPE-C interface when it detects a change in the level signals transmitted through the first and second signal lines from low to high (from 0 to Vdd) and remains stable for a certain period of time. The following describes the principle of detecting device insertion. Since the detection principle of the first ground pin is the same as that of the second ground pin, the following description uses the first ground pin as an example. The detection principle of the second ground pin can be referred to the first ground pin.

[0067] When the device is not plugged into the Type-C interface, the main control chip detects a low-level signal through the first signal line because the second terminal of the first MOSFET is grounded. When the device is plugged into the Type-C interface, the first ground pin is grounded. Since the gate of the first MOSFET is coupled to the first ground pin, the gate voltage of the first MOSFET changes from high to low. At this time, the first MOSFET is in an off state, that is, both the second and third terminals of the first MOSFET are open. Therefore, the main control chip detects a high-level signal through the first signal line. Thus, whether the main control chip detects a change in the signal level of the first signal line from low to high can be used to determine whether a device is plugged in.

[0068] Furthermore, the device insertion detector may also include a fifth relay, a sixth relay, a third MOSFET, and a fourth MOSFET. For example... Figure 9 As shown, the first terminal of the fifth relay 630 is connected to the first ground pin 409, the second terminal of the fifth relay 630 is connected to the first terminal of the first MOSFET 610, and the third terminal of the fifth relay 630 is grounded; the first terminal of the fifth relay 630 is also coupled to the main control chip 200 via the third MOSFET 650. The first terminal of the sixth relay 640 is connected to the second ground pin 410, the second terminal of the sixth relay 640 is connected to the first terminal of the second MOSFET 620, and the third terminal of the sixth relay 640 is grounded; the first terminal of the sixth relay 640 is also coupled to the main control chip 200 via the fourth MOSFET 660.

[0069] In this embodiment, the first terminal of the fifth relay can be the common terminal of the fifth relay, the second terminal of the fifth relay is the static contact of the fifth relay, and the third terminal of the fifth relay is the dynamic contact of the fifth relay. Similarly, the first terminal of the sixth relay can be the common terminal of the sixth relay, the second terminal of the sixth relay is the static contact of the sixth relay, and the third terminal of the sixth relay is the dynamic contact of the sixth relay. That is, the two ground pins of the TYPE-C interface can be connected to the common terminals of the two relays respectively. When the fifth relay is in a first state or a second state, its first and second terminals are connected; when it is in a second state, its first and third terminals are connected. Likewise, when the sixth relay is in a first state or a second state, its first and second terminals are connected; when it is in a second state, its first and third terminals are connected.

[0070] like Figure 9 As shown, the fourth terminal of the fifth relay 630 can be coupled to the main control chip 200 via the third MOSFET 650, and the fourth terminal of the sixth relay 640 can be coupled to the main control chip 200 via the fourth MOSFET 660. Specifically, the main control chip 200 can be connected to the gate of the third MOSFET and the gate of the fourth MOSFET, respectively. The fourth terminals of the fifth and sixth relays can be control terminals; the main control chip can indirectly control the fifth relay to be in a first or second state by controlling the fourth terminal of the fifth relay; similarly, the main control chip can indirectly control the sixth relay to be in a first or second state by controlling the fourth terminal of the sixth relay. The specific connection relationship between the third and fourth MOSFETs can be referred to the connection relationship of the sixth MOSFET Q6 described above. Figure 9 The diodes D1 and D2 in this section can be referred to in the previous description of diode D4, and will not be elaborated here.

[0071] Since the control logic of the fifth relay is the same as that of the sixth relay, they can be used interchangeably. Here, we will use the control logic of the fifth relay as an example. When the device is not inserted, the fifth relay is in the first state, and the first ground pin is connected to the gate of the first MOSFET via the fifth relay. When the device is inserted, the first ground pin is grounded, causing the gate voltage of the first MOSFET to change from high to low, thus turning the first MOSFET off. The main control chip can then detect the change in signal level of the first signal line from low to high, confirming the presence of a device inserted.

[0072] like Figure 9 As shown, when the main control chip 200 determines that a device has been inserted, it can control the fifth relay 630 and the sixth relay 640 to be in a second state, making the first and third terminals of the fifth relay 630 and the sixth relay 640 conductive. This grounds the first ground pin GND1 and the second ground pin GND2, ensuring that the original first and second ground pins of the TYPE-C interface are restored to their original definitions. Then, the power supply can be controlled to provide power to the inserted peripheral, thereby realizing device insertion detection and power supply.

[0073] See also Figure 10 , Figure 10 This is a schematic diagram of a path switching device provided in an embodiment of this application. Figure 10As shown, the path switching device 100 includes a main control chip 200, a path switcher 300, a TYPE-C interface, a signal detector 500, and a device insertion detector 600. The path switcher 300 includes a first relay 310, a second relay 320, a third relay 330, and a fourth relay 340. The TYPE-C interface includes pins TX1+ 401, TX2+ 402, TX1- 403, TX2- 404, RX1+ 405, RX2+ 406, RX1- 407, RX2- 408, GND1 409, and GND2 410.

[0074] The signal detector 500 includes a voltage sampler 510, a first resistor 520, and a second resistor 530. The device insertion detector 600 includes a first MOSFET 610, a second MOSFET 620, a fifth relay 630, a sixth relay 640, a third MOSFET 650, and a fourth MOSFET 660.

[0075] The descriptions of the same or similar elements in the above embodiments can be referenced to each other, for example... Figure 2 The descriptions of the first and second relays in the text are applicable to... Figure 10 The first relay and the second relay are not described in detail here, but the components in the embodiments of this application will not be described in detail.

[0076] To facilitate understanding of the path switching device provided in the embodiments of this application, the following description is provided with specific examples, taking a SOC chip as the main control chip as an example. (Refer to...) Figure 11 , Figure 11 This is a schematic diagram of a path switching method provided in an embodiment of this application. When the TYPE-C interface is in a state where no USB device is connected, the common terminal of the fifth and sixth relays is connected to the first and second MOSFETs by default. Figure 11 As shown, when a USB device is connected to the TYPE-C interface, the SOC chip can detect that the voltage signal on the first and second signal lines will jump from 0 to Vdd volts (V). At this time, the SOC chip can determine that a USB device is inserted into the TYPE-C interface and control the fifth and sixth relays to open, so that the fifth and sixth relays are in a second state, making the first and second ground pins of the TYPE-C interface grounded through the fifth and sixth relays. Then, the SOC chip controls the power supply module to turn on the power supply to the TYPE-C interface to power the USB device.

[0077] After the SOC chip detects a device inserted into the Type-C interface via the device insertion detector, it controls the voltage sampler to begin sampling. The first and third relays are both in the first state by default, thus connecting the TX1± signal of the Type-C interface to the signal detector. The voltage sampler then acquires the voltage of the TX1+ channel (Vt1) and the voltage of the TX1- channel (Vt2). If the device is not connected to the Type-C interface, Vt1 = Vdd, and Vt2 = Vdd. If a device is connected to the Type-C interface, the voltage acquired by the voltage sampler will change due to the presence of pull-down resistors R3 and R4 on the other end's design. The SOC chip can obtain the voltage value acquired by the voltage sampler and determine whether a USB 3.0 RX signal is present based on the voltage value.

[0078] If the SOC chip determines the presence of a USB 3.0 RX signal based on the voltage value, meaning the SOC chip's acquired Vt1 and Vt2 become: Vt1 = Vdd * R3 / (R1 + R3), Vt2 = Vdd * R2 / (R2 + R4), then it can be confirmed that the device communicates with the SOC chip through the TX1± pin. At this time, the SOC chip can open the third and fourth relays, while keeping the other relays in their original states. The USB signal channel switches to the SOC signal channel, and the main control chip can then perform normal enumeration communication with the peripheral device. The SOC chip's USB signal channel is connected to the TX1± / RX1± pins of the TYPE-C interface.

[0079] If the voltage value collected by the voltage sampler does not change, the SOC chip controls the first relay to open, placing it in the second state. This switches the channel between the signal detector and the TYPE-C interface to the TX2± channel to detect whether the device is connected to the TX2 / RX2 channel of the TYPE-C interface. The detection process is the same as above. If the voltage value collected by the voltage sampler changes, and the changed voltage value meets the following conditions: Vt1=Vdd*R3 / (R1+R3), Vt2=Vdd*R2 / (R2+R4), then it is considered that the peripheral USB channel is connected to the TX2 / RX2 channel of the TYPE-C interface. At this time, the SOC chip can control the second, third, and fourth relays to open, all in the second state, so that the USB signal of the SOC chip is connected to the TX2 / RX2 pin of the TYPE-C interface. If the voltage value collected by the voltage sampler does not change, or the changed voltage value does not meet the above conditions, it is considered that no USB 3.0 related signals are detected.

[0080] When an external device inserted into the TYPE-C interface is removed, the SOC chip will restore all relays to their default state (i.e., the first state) to facilitate detection of the next device insertion.

[0081] This application provides a path switching device. The main control chip only needs to support one set of USB signal paths to connect with the two sets of USB signal paths of the TYPE-C interface. It can realize the reversible insertion function of the TYPE-C interface without supporting two sets of USB signal paths, which reduces the requirements for the main control chip and solves the problem of high requirements for the main control chip in related technologies.

[0082] Meanwhile, it should be understood that the path switching device provided in this application embodiment has the following beneficial effects: First, this application embodiment provides a TYPE-C interface insertion detection scheme, which simultaneously detects the two diagonally opposite GND pins of the upper and lower layers of the TYPE-C interface, ensuring that the plug and socket of the TYPE-C interface are fully and stably in contact before powering the peripheral device. This eliminates, to a certain extent, the impact of instantaneous current generated when powering the device before the plug and socket of the TYPE-C interface are properly in contact on the system power supply. Second, this application embodiment provides a method for detecting the signal path of a device connected to the TYPE-C interface, which can determine whether the device is connected to the TX1 / RX1 path of the TYPE-C interface or the TX2 / RX2 path of the TYPE-C interface. This implementation scheme is relatively simple and easy to implement, and reduces design costs to a certain extent. Third, the main control chip can support a single USB TX / RX interface connected to the TYPE-C interface and can realize reversible insertion. The main control chip can determine which USB signal line the device is connected to based on the detection result of the signal detector, and then control the relay to realize the connection between the USB channel of the main control chip and the peripheral channel.

[0083] This application also provides an electronic device, which includes the path switching device shown in any of the above embodiments. In this application, the electronic device and the path switching device can achieve the same technical effects, and to avoid repetition, they will not be described again here.

[0084] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0085] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0086] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A path switching device, characterized in that, include: Main control chip, channel switcher, device insertion detector, signal detector, and universal serial bus C interface; The device insertion detector is connected to the main control chip and the C-type interface respectively; the signal detector is connected to the main control chip and the path switch respectively. The path switcher is connected to the main control chip and the C-type interface respectively; The main control chip is connected to the channel switcher via a set of USB signal paths, and the channel switcher is connected to the C-type interface via two sets of USB signal paths. The USB signal paths between the main control chip and the path switcher include a first transmitting signal path, a second transmitting signal path, a first receiving signal path, and a second receiving signal path. The first set of USB signal paths in the two sets of USB signal paths includes a first transmitting path, a second transmitting path, a first receiving path, and a second receiving path; the second set of USB signal paths in the two sets of USB signal paths includes a third transmitting path, a fourth transmitting path, a third receiving path, and a fourth receiving path. The first transmission signal path is connected to the first target transmission path via the path switcher, and the first target transmission path is either the first transmission path or the third transmission path. The second transmission signal path is connected to the second target transmission path via the path switcher, and the second target transmission path is either the second transmission path or the fourth transmission path; The first receiving signal path is connected to the first target receiving path via the path switcher, and the first target receiving path is either the first receiving path or the third receiving path. The second receiving signal path is connected to the second target receiving path via the path switcher, and the second target receiving path is either the second receiving path or the fourth receiving path.

2. The path switching device according to claim 1, characterized in that, The C-type interface includes a first pair of receive pins, a second pair of receive pins, a first pair of transmit pins, and a second pair of transmit pins; the first pair of transmit pins includes a first transmit channel positive terminal pin and a second transmit channel positive terminal pin, and the second pair of transmit pins includes a first transmit channel negative terminal pin and a second transmit channel negative terminal pin; the first pair of receive pins includes a first receive channel positive terminal pin and a second receive channel positive terminal pin, and the second pair of receive pins includes a first receive channel negative terminal pin and a second receive channel negative terminal pin; The path switcher is connected to the positive terminal pin of the first transmission channel via the first transmission path; the path switcher is connected to the negative terminal pin of the first transmission channel via the second transmission path; the path switcher is connected to the positive terminal pin of the first reception channel via the first reception path; the path switcher is connected to the negative terminal pin of the first reception channel via the second reception path. The path switcher is connected to the positive pin of the second transmission channel via the third transmission path; the path switcher is connected to the negative pin of the second transmission channel via the fourth transmission path; the path switcher is connected to the positive pin of the second reception channel via the third reception path; and the path switcher is connected to the negative pin of the second reception channel via the fourth reception path.

3. The path switching device according to claim 2, characterized in that, The path switcher includes a first relay, a second relay, a third relay, and a fourth relay; Wherein, the first terminal of the first relay is coupled to the first transmitting signal path, the second and third terminals of the first relay are respectively coupled to two pins of the first pair of transmitting pins; the fourth terminal of the first relay is coupled to the second transmitting signal path, and the fifth and sixth terminals of the first relay are respectively coupled to two pins of the second pair of transmitting pins. The first terminal of the second relay is coupled to the first receiving signal path, and the second and third terminals of the second relay are respectively coupled to two pins of the first pair of receiving pins; the fourth terminal of the second relay is coupled to the second receiving signal path, and the fifth and sixth terminals of the second relay are respectively coupled to two pins of the second pair of receiving pins. The first terminal of the third relay is connected to the first terminal of the first relay; the first terminal of the signal detector is connected to the main control chip; the second terminal of the third relay is connected to the second terminal of the signal detector; the third terminal of the third relay is connected to the first transmitting signal path; the fourth terminal of the third relay is connected to the fourth terminal of the first relay; the fifth terminal of the third relay is connected to the third terminal of the signal detector; and the sixth terminal of the third relay is connected to the second transmitting signal path. The first terminal of the fourth relay is connected to the first terminal of the second relay, the second terminal of the fourth relay is floating, the third terminal of the fourth relay is connected to the first receiving signal path; the fourth terminal of the fourth relay is connected to the fourth terminal of the second relay, the fifth terminal of the fourth relay is floating, and the sixth terminal of the fourth relay is connected to the second receiving signal path.

4. The path switching device according to claim 3, characterized in that, The first relay, the second relay, the third relay, and the fourth relay are all double-opening and double-closed relays; the main control chip is coupled to the seventh terminal of the first relay, the seventh terminal of the second relay, the seventh terminal of the third relay, and the seventh terminal of the fourth relay, respectively.

5. The path switching device according to claim 3, characterized in that, The first relay, the second relay, the third relay, and the fourth relay are all single-coil latching relays.

6. The path switching device according to claim 3, characterized in that, The signal detector includes a voltage sampler; the voltage sampler is coupled to the second and fifth terminals of the third relay, respectively.

7. The path switching device according to claim 6, characterized in that, The signal detector also includes a first resistor and a second resistor; One end of the first resistor is connected to the first power supply terminal, and the other end of the first resistor is connected to the first connection point, which is located in the path between the voltage sampler and the third relay. One end of the second resistor is connected to the first power supply terminal, and the other end of the second resistor is connected to a second connection point, which is located in the path between the voltage sampler and the third relay.

8. The path switching device according to any one of claims 1-7, characterized in that, The device inserts a detector that is connected to the ground pin of the C-type interface; the ground pin includes a first ground pin and a second ground pin, which are located diagonally opposite each other on the C-type interface.

9. The path switching device according to any one of claims 1-7, characterized in that, The device insertion detector is connected to the ground pin of the C-type interface; the ground pin includes a first ground pin and a second ground pin; the device insertion detector includes a first metal-oxide-semiconductor field-effect transistor (MOS transistor) and a second MOS transistor; The first terminal of the first MOSFET is coupled to the first ground pin, the second terminal of the first MOSFET is grounded, the third terminal of the first MOSFET is coupled to the second power supply terminal, and the third terminal of the first MOSFET is connected to the main control chip via the first signal line; wherein, the first terminal of the first MOSFET is the gate, the second terminal of the first MOSFET is one of the source and the drain, and the third terminal of the first MOSFET is the other of the source and the drain. The first end of the second MOSFET is coupled to the second ground pin, the second end of the second MOSFET is grounded, the third end of the second MOSFET is coupled to the second power supply terminal, and the third end of the second MOSFET is connected to the main control chip via the second signal line; wherein, the first end of the second MOSFET is the gate, the second end of the second MOSFET is one of the source and drain, and the third end of the second MOSFET is the other of the source and drain.

10. The path switching device according to claim 9, characterized in that, The device insertion detector further includes a fifth relay, a sixth relay, a third MOSFET, and a fourth MOSFET; both the fifth and sixth relays are single-open single-closed relays; both the fifth and sixth relays are single-coil latching relays. The first terminal of the fifth relay is connected to the first ground pin, the second terminal of the fifth relay is connected to the first terminal of the first MOS transistor, and the third terminal of the fifth relay is grounded; the fourth terminal of the fifth relay is coupled to the main control chip via the third MOS transistor. The first terminal of the sixth relay is connected to the second ground pin, the second terminal of the sixth relay is connected to the first terminal of the second MOS transistor, and the third terminal of the sixth relay is grounded; the fourth terminal of the sixth relay is coupled to the main control chip via the fourth MOS transistor.

Images