A circuit structure for generating a dithered frequency signal

Abstract

The utility model relates to the field of reducing power supply circuit electromagnetic interference. A kind of circuit structure generating jitter frequency signal, including RC filter, cathode-ray tube CRT, first diode D11 and second diode D12 connected in parallel, and the resistance R4 and the capacitor C3 that can generate fundamental frequency and are connected together;Still include first comparator U1A, second comparator U1B and resistance R2;The 3 feet of first comparator U1A are connected in positive direction Vref, the 2 feet of first comparator U1A are connected in reverse resistance R4, 3 feet and 2 feet compare and generate comparison signal, comparison signal can pull-down resistance R2 potential, negative feedback can generate superimposed signal PWM;Superimposed signal PWM is input to the 5 feet positive input end of second comparator U1B, then after the 7 feet of second comparator U1B is input to RC filter. Periodic frequency changeable jitter frequency signal can be generated near fundamental switching frequency efficiently and accurately;The peak value of transmission and radiation EMI can be significantly reduced;Filter cost can be greatly reduced;Simple structure, can easily pass EMC test.

Description

Technical Field

[0001] This utility model relates to the field of reducing electromagnetic interference in power supply circuits, and in particular to a circuit structure for generating frequency dithering signals. Background Technology

[0002] In recent years, industrial energy applications such as low-voltage, high-current electroplating, electrolysis, and metal smelting have placed increasingly stringent requirements on the electromagnetic interference and electromagnetic compatibility (EMC) certification of power supplies. Currently, most switching power supplies use a fixed switching frequency for their control power transistors, which has the following disadvantages:

[0003] 1. The presence of a resonant cavity with a fixed switching frequency due to the distributed inductive and capacitive parameters in the main circuit will generate strong periodic switching noise. The energy of this noise is highly concentrated at the fundamental frequency and its harmonic frequencies.

[0004] 2. It has fixed frequency bands of radiated spikes that interfere with the outside world, making it impossible to meet EMC certification requirements;

[0005] 3. The switching transistor has the disadvantages of high conduction loss and large power loss.

[0006] Therefore, it is necessary to provide a circuit structure for generating frequency dithering signals to solve the above-mentioned technical problems. Utility Model Content

[0007] To solve the above-mentioned technical problems, this utility model provides the following technical solution:

[0008] A circuit structure for generating a frequency dithering signal includes an RC filter, a cathode ray tube (CRT), a first diode D11 and a second diode D12 connected in parallel, and a resistor R4 and a capacitor C3 connected together to generate the fundamental frequency.

[0009] It also includes a first comparator U1A, a second comparator U1B, and a resistor R2;

[0010] The RC filter includes a capacitor C4 and a resistor R7 connected in series;

[0011] The resistor R2 and the resistor R4 are connected in series;

[0012] The second diode D12 is connected in series with Vref and in series with pin 1 of the first comparator U1A. The first diode D11 is connected in series with the resistor R2 and in series with pin 1 of the first comparator U1A.

[0013] The first comparator U1A has its 3rd pin connected to Vref in the forward direction and its 2nd pin connected to resistor R4 in the reverse direction. The comparison between the 3rd and 2nd pins of the first comparator U1A generates a comparison signal. The comparison signal can pull down the potential of resistor R2, and the negative feedback can generate a superimposed signal PWM.

[0014] The superimposed signal PWM is input to the positive input terminal of pin 5 of the second comparator U1B, and then input to the RC filter through pin 7 of the second comparator U1B.

[0015] As a further embodiment of this invention: one end of the capacitor C3 is connected to the resistor R4, and the other end is grounded.

[0016] As a further embodiment of this utility model, it also includes a resistor R9, one end of which is connected to pin 6 of the second comparator U1B, and the other end is grounded.

[0017] As a further aspect of this invention: a resistor R3 is provided between the Vref and pin 3 of the first comparator U1A.

[0018] As a further embodiment of this utility model, it also includes a resistor R6, which is connected in parallel with the first comparator U1A. One end of the resistor R6 is connected to the resistor R3, and the other end is grounded.

[0019] The beneficial effects of the circuit structure for generating frequency dithering signals involved in this utility model are as follows:

[0020] This invention employs the following structure: the circuit structure includes an RC filter, a cathode ray tube (CRT), a first diode D11 and a second diode D12 connected in parallel, a first comparator U1A, a second comparator U1B, and a resistor R2, as well as a resistor R4 and a capacitor C3 connected together to generate the fundamental frequency. Since resistor R4 and capacitor C3 generate the fundamental oscillation frequency, pins 3 and 2 of the first comparator U1A are compared to generate a comparator signal. This comparison signal is a pulse output waveform, which can pull down the resistor R2, thereby creating negative feedback that superimposes this signal onto the fundamental frequency to change the fundamental frequency. The superimposed signal (PWM) is input to the RC filter via the second comparator U1B. The oscillation frequency of the RC filter, composed of capacitor C4 and resistor R7, determines the frequency jitter range. The CRT signal can be connected to the PWM output signal of the control PWM chip, thus achieving efficient and accurate generation of a periodic frequency-changeable jitter signal near the fundamental switching frequency. This invention overcomes the following shortcomings of existing power supply control transistors with fixed switching frequencies: the strong periodic switching noise generated has its energy highly concentrated at the fundamental frequency, causing fixed-frequency radiated spikes of interference, failing to meet EMC certification requirements, and resulting in high switching transistor conduction losses and significant power consumption. It offers the following advantages: it can efficiently and accurately generate a periodic frequency-variable dithering signal near the fundamental switching frequency; it can significantly reduce the peak values ​​of conducted and radiated EMI; it can greatly reduce filter costs; and its simple structure allows for easy and low-cost EMC testing. Attached Figure Description

[0021] Figure 1 This is a circuit schematic diagram of an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0023] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0025] like Figure 1 As shown, a circuit structure for generating a frequency dithering signal includes an RC filter, a cathode ray tube (CRT), a first diode D11 and a second diode D12 connected in parallel, and a resistor R4 and a capacitor C3 connected together to generate the fundamental frequency.

[0026] It also includes a first comparator U1A, a second comparator U1B, and a resistor R2;

[0027] The RC filter includes a capacitor C4 and a resistor R7 connected in series;

[0028] The resistor R2 and the resistor R4 are connected in series;

[0029] The second diode D12 is connected in series with Vref and in series with pin 1 of the first comparator U1A. The first diode D11 is connected in series with the resistor R2 and in series with pin 1 of the first comparator U1A.

[0030] The first comparator U1A has its 3rd pin connected to Vref in the forward direction and its 2nd pin connected to resistor R4 in the reverse direction. The comparison between the 3rd and 2nd pins of the first comparator U1A generates a comparison signal. The comparison signal can pull down the potential of resistor R2, and the negative feedback can generate a superimposed signal PWM.

[0031] The superimposed signal PWM is input to the positive input terminal of pin 5 of the second comparator U1B, and then input to the RC filter through pin 7 of the second comparator U1B.

[0032] Example

[0033] The basic structure is the same as described above. Specifically, one end of capacitor C3 is connected to resistor R4, and the other end is grounded. A circuit structure for generating a frequency dithering signal also includes resistor R9, one end of which is connected to pin 6 of the second comparator U1B, and the other end is grounded. Resistor R3 is provided between Vref and pin 3 of the first comparator U1A. A circuit structure for generating a frequency dithering signal also includes resistor R6, which is connected in parallel with the first comparator U1A. One end of resistor R6 is connected to resistor R3, and the other end is grounded.

[0034] Significant benefits include: 1. It can efficiently and accurately generate periodic frequency-variable dithering signals near the fundamental switching frequency; 2. It can significantly reduce the peak values ​​of conducted and radiated EMI; 3. Due to the reduction in peak values, the size of the input filter can be reduced or shielding measures can be lessened, thereby greatly reducing the cost of the filter; 4. It has a simple structure and can easily pass EMC tests at low cost.

[0035] The above description of the utility model is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to preferred embodiments, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A circuit structure for generating a frequency dithering signal, characterized in that: It includes an RC filter, a cathode ray tube (CRT), a first diode D11 and a second diode D12 connected in parallel, and a resistor R4 and a capacitor C3 connected together to generate the fundamental frequency. It also includes a first comparator U1A, a second comparator U1B, and a resistor R2; The RC filter includes a capacitor C4 and a resistor R7 connected in series; The resistor R2 and the resistor R4 are connected in series; The second diode D12 is connected in series with Vref and in series with pin 1 of the first comparator U1A. The first diode D11 is connected in series with the resistor R2 and in series with pin 1 of the first comparator U1A. The first comparator U1A has its 3rd pin connected to Vref in the forward direction and its 2nd pin connected to resistor R4 in the reverse direction. The comparison between the 3rd and 2nd pins of the first comparator U1A generates a comparison signal. The comparison signal can pull down the potential of resistor R2, and the negative feedback can generate a superimposed signal PWM. The superimposed signal PWM is input to the positive input terminal of pin 5 of the second comparator U1B, and then input to the RC filter through pin 7 of the second comparator U1B.

2. The circuit structure for generating frequency dithering signals according to claim 1, characterized in that: One end of the capacitor C3 is connected to the resistor R4, and the other end is grounded.

3. The circuit structure for generating frequency dithering signals according to claim 2, characterized in that: It also includes a resistor R9, one end of which is connected to pin 6 of the second comparator U1B, and the other end is grounded.

4. The circuit structure for generating a frequency-dithering signal according to any one of claims 1 to 3, characterized in that: A resistor R3 is provided between Vref and pin 3 of the first comparator U1A.

5. The circuit structure for generating a frequency dithering signal according to claim 4, characterized in that: It also includes a resistor R6, which is connected in parallel with the first comparator U1A. One end of the resistor R6 is connected to the resistor R3, and the other end is grounded.

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