Transient current detection circuit and transient current testing device

Abstract

The application relates to the field of circuit design, in particular to a transient current detection circuit and a transient current testing device. The transient current detection circuit comprises a current sampling circuit which is used for collecting a transient voltage signal representing a transient current; a first voltage latch circuit which is connected with the current sampling circuit and is used for latching a peak voltage of the transient voltage signal; and a second voltage latch circuit which is connected with the first voltage latch circuit and is used for latching the peak voltage transferred by the first voltage latch circuit again; wherein the latching time of the first voltage latch circuit is less than the latching time of the second voltage latch circuit, the influence of low leakage on the peak voltage is reduced, and the detection precision of the transient current is improved.

Description

Technical Field

[0001] This application relates to the field of circuit design, and in particular to an instantaneous current detection circuit and an instantaneous current testing device. Background Technology

[0002] In various electronic devices, instantaneous current sensing is used to ensure that the IC has the appropriate short-circuit current capability and that the short-circuit current does not exceed the safety limit, thereby protecting circuit components.

[0003] Typically, a capacitor is used to latch the collected peak voltage, and then the corresponding instantaneous current is detected based on the latched peak voltage. Since the capacitor itself requires time to charge and discharge, a larger capacitor takes longer to reach the peak voltage. Currently, only instantaneous currents with a detection duration in the microsecond range can be detected. Existing solutions reduce the capacitor value to achieve a shorter detection duration for instantaneous currents. However, over time, low leakage current caused by the PCB and environment can significantly affect the latched peak voltage, thus impacting the accuracy of instantaneous current detection. Utility Model Content

[0004] Therefore, it is necessary to provide an instantaneous current detection circuit and an instantaneous current testing device to address the aforementioned technical problems.

[0005] In a first aspect, embodiments of this application provide an instantaneous current detection circuit, comprising: A current sampling circuit is used to acquire instantaneous voltage signals that characterize instantaneous current. A first-level voltage latch circuit, connected to the current sampling circuit, is used to latch the peak voltage of the instantaneous voltage signal; A secondary voltage latch circuit, connected to the primary voltage latch circuit, is used to latch the peak voltage transferred by the primary voltage latch circuit again; The latching time of the first-stage voltage latching circuit is shorter than that of the second-stage voltage latching circuit.

[0006] In some embodiments, the first-stage voltage latching circuit includes a controllable switch U1, a first-stage latching capacitor C6, and an isolation device U3. The input terminal of the controllable switch U1 is connected to the current sampling circuit, the output terminal is connected to one end of the first-stage latching capacitor C6 and the non-inverting input terminal of the isolation device U3, the control terminal is connected to the peak detection circuit, the other end of the first-stage latching capacitor C6 is connected to the common ground, and the inverting input terminal of the isolation device U3 is connected to the output terminal of the isolation device U3 and the second-stage voltage latching circuit.

[0007] The controllable switch U1 is turned off when it receives the first control signal from the peak detection circuit that detects the release of instantaneous current, and the first-stage latching capacitor C6 latches the peak voltage.

[0008] In some embodiments, the first-stage voltage latching circuit further includes a first current-limiting resistor R2, one end of which is connected to the output terminal of the controllable switch U1, and the other end is connected to one end of the first-stage latching capacitor C6 and the input terminal of the isolation device U3.

[0009] In some embodiments, the secondary voltage latching circuit includes a controllable switch U2, a secondary latching capacitor C7, and an isolation device U4. The input terminal of the controllable switch U2 is connected to the primary voltage latching circuit, the output terminal is connected to one end of the secondary latching capacitor C7 and the non-inverting input terminal of the isolation device U4, the control terminal is connected to a controller, the other end of the secondary latching capacitor C7 is connected to a common ground, and the inverting input terminal of the isolation device U4 is connected to the output terminal of the isolation device U4. When the controllable switch U1 is turned off, the controllable switch U2 receives the second control signal released by the controller and turns on. The peak voltage passes through the isolation device U3 and the controllable switch U2 in sequence and enters the secondary latching capacitor C7 for latching.

[0010] In some embodiments, the first-stage voltage latching circuit further includes a second current-limiting resistor R3, one end of which is connected to the output terminal of the controllable switch U2, and the other end is connected to one end of the second-stage latching capacitor C7 and the input terminal of the isolation device U4.

[0011] In some embodiments, the capacitance value of the primary latching capacitor C6 is smaller than the capacitance value of the secondary latching capacitor C7.

[0012] In some embodiments, the slew rate of the isolation device U3 is greater than or equal to the slew rate of the isolation device U4.

[0013] In some embodiments, the current sampling circuit includes: A sampling resistor is used to acquire the instantaneous voltage signal that characterizes the instantaneous current. A signal amplification circuit, connected across the sampling resistor, is used to amplify the instantaneous voltage signal.

[0014] In some embodiments, the signal amplification circuit includes an operational amplifier U5, resistors R1, R4, R6, and R7. The inverting input terminal of the operational amplifier U5 is connected to one end of the sampling resistor via resistor R4, and its non-inverting input terminal is connected to the other end of the sampling resistor via resistor R6. Resistor R1 is connected between the inverting input terminal and the output terminal of the operational amplifier U5, and resistor R7 is connected between the non-inverting input terminal and the common ground of the operational amplifier U5.

[0015] Secondly, embodiments of this application provide an instantaneous current testing device, comprising: an instantaneous current generating circuit, a peak detection circuit, a source testing device, a controller, and the instantaneous current detection circuit as described in the first aspect; the instantaneous current generating circuit is connected to the current sampling circuit; the peak detection circuit is connected to the first-stage voltage latching circuit; the source testing device and the controller are respectively connected to the second-stage voltage latching circuit.

[0016] The above-mentioned instantaneous current detection circuit and instantaneous current testing device have the following technical effects: the peak voltage transferred by the first-stage voltage latching circuit is latched again by the second-stage voltage latching circuit. Since the latching time of the first-stage voltage latching circuit is shorter than that of the second-stage voltage latching circuit, the low leakage current caused by the PCB and the environment will have a smaller impact on the peak voltage latched by the second-stage voltage latching circuit, thereby improving the detection accuracy of instantaneous current. Attached Figure Description

[0017] Figure 1 A schematic diagram of the instantaneous current detection circuit in one embodiment provided in this application; Figure 2 A circuit schematic diagram of an instantaneous current detection circuit provided in an example embodiment of this application; Figure 3 A schematic diagram of the instantaneous current testing device in one embodiment provided in this application.

[0018] Among them, 100 is the current sampling circuit; 200 is the first-stage voltage latch circuit; 300 is the second-stage voltage latch circuit; 101 is the signal amplification circuit; 10 is the instantaneous current detection circuit; 20 is the instantaneous current generation circuit; 30 is the source test equipment; 40 is the peak detection loop; and 50 is the controller. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0020] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0021] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0022] Figure 1 A schematic diagram of the instantaneous current detection circuit in one embodiment provided in this application is shown. Figure 1 As shown, the instantaneous current detection circuit includes a current sampling circuit 100 for acquiring an instantaneous voltage signal characterizing the instantaneous current; a first-stage voltage latching circuit 200 connected to the current sampling circuit 100 for latching the peak voltage of the instantaneous voltage signal; and a second-stage voltage latching circuit 300 connected to the first-stage voltage latching circuit 200 for re-latching the peak voltage transferred by the first-stage voltage latching circuit 200.

[0023] The latching time of the first-stage voltage latching circuit 200 is shorter than the latching time of the second-stage voltage latching circuit 300.

[0024] In this embodiment, the peak voltage transferred by the first-stage voltage latch circuit is latched again using a second-stage voltage latch circuit. Since the latching time of the first-stage voltage latch circuit is shorter than that of the second-stage voltage latch circuit, the low leakage current caused by the PCB and the environment has a smaller impact on the peak voltage latched by the second-stage voltage latch circuit, thereby improving the detection accuracy of instantaneous current.

[0025] Figure 2 The circuit diagram of the instantaneous current detection circuit in an example embodiment provided in this application is shown below. Figure 2 A detailed explanation of the specific circuit structure and principle of the instantaneous current detection circuit.

[0026] The current sampling circuit 100 includes a sampling resistor R5 and a signal amplification circuit 101. The sampling resistor R5 is used to acquire the instantaneous voltage signal characterizing the instantaneous current; the signal amplification circuit 101 is connected across the sampling resistor R5 and is used to amplify the instantaneous voltage signal.

[0027] The signal amplification circuit 101 includes an operational amplifier U5, resistors R1, R4, R6, and R7. The inverting input terminal of the operational amplifier U5 is connected to one end of the sampling resistor R5 through the resistor R4, and its non-inverting input terminal is connected to the other end of the sampling resistor R5 through the resistor R6. The resistor R1 is connected between the inverting input terminal and the output terminal of the operational amplifier U5, and the resistor R7 is connected between the non-inverting input terminal of the operational amplifier U5 and the common ground GND.

[0028] The instantaneous current signal flows through the sampling resistor R5. The instantaneous voltage signal across the sampling resistor R5 can characterize the instantaneous current signal. The instantaneous voltage signal is amplified by the signal amplification circuit 101.

[0029] The amplification gain of the signal amplifier circuit 101 can be adjusted by setting the amplification factor through the ratio of the resistance values ​​of resistors R4 and R6, and resistors R1 and R7.

[0030] The first-stage voltage latch circuit 200 includes a first-stage latching capacitor C6, a controllable switch U1, a first current-limiting resistor R2, and an isolation device U3. The input terminal of the controllable switch U1 is connected to the current sampling circuit 100, and its output terminal is connected to one end of the first current-limiting resistor R2. The other end of the first current-limiting resistor R2 is connected to one end of the first-stage latching capacitor C6 and the non-inverting input terminal of the isolation device U3. Its control terminal is connected to the peak detection circuit. The other end of the first-stage latching capacitor C6 is connected to the common ground GND. The inverting input terminal of the isolation device U3 is connected to the output terminal of the isolation device U3 and the second-stage voltage latch circuit 300.

[0031] The controllable switch U1 is turned off when it receives the first control signal from the peak detection circuit that detects the release of instantaneous current, and the first-stage latching capacitor C6 latches the peak voltage.

[0032] The peak detection circuit is used to detect instantaneous current. When the instantaneous current is detected and released, a first control signal is sent to control the controllable switch U1 to turn off. When the peak detection circuit does not detect instantaneous current, the controllable switch U1 is always in the on state.

[0033] In this example embodiment, the first current-limiting resistor R2 is used for current limiting and can be omitted when the instantaneous voltage signal is small. The isolation device U3 has a high input impedance, for example, an electrically isolated amplifier, which serves to isolate the signal from the subsequent stage circuit and enhance the driving capability of the peak voltage.

[0034] In this example embodiment, the controllable switch U1 can be, but is not limited to, a MOS transistor. Its IN pin is used to receive the first control signal DIO0, its S pin is connected to the output of the front current sampling circuit, and its D pin is connected to the first current limiting resistor R2.

[0035] It should be noted that the controllable switch U1 can also use switching transistors such as transistors or IGBTs to achieve the same function.

[0036] In one embodiment, the secondary voltage latch circuit 300 includes a secondary latching capacitor C7, a controllable switch U2, a second current-limiting resistor R3, and an isolation device U4. The input terminal of the controllable switch U2 is connected to the primary voltage latch circuit 200, and its output terminal is connected to one end of the second current-limiting resistor R3. The other end of the second current-limiting resistor R3 is connected to one end of the secondary latching capacitor C7 and the non-inverting input terminal of the isolation device U4. The control terminal is connected to a controller. The other end of the secondary latching capacitor C7 is connected to the common ground GND, and the inverting input terminal of the isolation device U4 is connected to its output terminal.

[0037] When the controllable switch U1 is turned off, the controllable switch U2 receives the second control signal released by the controller and turns on. The peak voltage passes through the isolation device U3 and the controllable switch U2 in sequence and enters the secondary latching capacitor C7 for latching.

[0038] The control program can be pre-written and burned into the controller. The controller will then control the controllable switch U2 in an orderly manner according to the control program. The controller can be, but is not limited to, chips such as FPGA, CPU, CPLD, or MCU. It controls the controllable switch U2 to turn on when the controllable switch U1 is turned off through the IO interface.

[0039] In this example embodiment, the second current-limiting resistor R3 is used for current limiting and can be omitted when the instantaneous voltage signal is small. The isolation device U4 has a high input impedance, for example, an electrically isolated amplifier, which serves to isolate the signal from the subsequent stage circuit and enhance the driving capability of the peak voltage for output to the source test equipment of the subsequent stage.

[0040] In this example embodiment, the controllable switch U2 can be, but is not limited to, a MOSFET. Its IN pin is used to receive the second control signal DIO1, its S pin is connected to the output of the first-stage voltage latch circuit, and its D pin is connected to the second current-limiting resistor R3.

[0041] It should be noted that the controllable switch U2 can also use transistors, IGBTs, or other switching transistors to achieve the same function.

[0042] In this example embodiment, the capacitance value of the first-stage latching capacitor C6 is smaller than the capacitance value of the second-stage latching capacitor C7. For example, the capacitance value of the first-stage latching capacitor C6 is in the pF range, and the capacitance value of the second-stage latching capacitor C7 is in the nF range, so that the latching time of the first-stage voltage latching circuit is shorter than the latching time of the second-stage voltage latching circuit. Specifically, the latching time of the first-stage latching capacitor C6 is in the nanoseconds range, and the latching time of the second-stage latching capacitor is in the microseconds range.

[0043] Because the capacitance of the first-stage latching capacitor C6 is small, it can detect instantaneous currents with shorter durations (or response times). The peak voltage latched by the first-stage latching capacitor C6 can remain constant within the nanosecond time frame. However, as time goes on, the peak voltage latched by the first-stage latching capacitor C6 will be affected by low leakage current caused by the PCB and the environment. The controllable switch U2 is turned on, and the peak voltage is quickly transferred to the second-stage latching capacitor C7 for latching again within the nanosecond time frame. Because the capacitance of the second-stage latching capacitor C7 is larger, it can maintain the peak voltage stably for a longer time, thereby reducing the continuous influence of leakage current during the instantaneous current signaling process and improving the accuracy of instantaneous current testing.

[0044] To accommodate transient current signals with shorter durations, some embodiments employ an isolation device U3 with a higher slew rate parameter, thereby enabling a rapid response to transient current signals and latching the peak voltage for a short period of time.

[0045] When a rapidly changing instantaneous voltage signal is input to isolator U3, if the slew rate of isolator U3 is insufficient, its output cannot keep up with the changes in the input signal, resulting in output signal distortion. The core function of using a high slew rate isolator U3 is to minimize signal distortion and ensure the accuracy of the output signal.

[0046] It should be noted that since the secondary voltage latch circuit 300 does not need to participate in the rapid response of the instantaneous current signal, it does not have the same parameter requirements for its isolation device U4. Therefore, the slew rate of the isolation device U3 can be greater than or equal to the slew rate of the isolation device U4.

[0047] This application also proposes an instantaneous current testing device, such as... Figure 3 As shown, it includes: an instantaneous current generation circuit 20, a peak detection circuit 40, a source test device 30, a controller 50, and an instantaneous current detection circuit 10 as described in the above embodiment; the instantaneous current generation circuit 20 is connected to the current sampling circuit; the peak detection circuit 40 is connected to the first-stage voltage latch circuit; the source test device 30 and the controller 50 are respectively connected to the second-stage voltage latch circuit.

[0048] The source test device 30 converts the peak voltage output by the instantaneous current detection circuit 10 into current to determine whether the instantaneous current signal is abnormal. The instantaneous current mentioned in this application can be the instantaneous short-circuit current.

[0049] It should be noted that the working principle and beneficial effects of the instantaneous current detection circuit have been described in detail in the above embodiments, so they will not be repeated in this embodiment.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A transient current detection circuit, characterized in that, include: A current sampling circuit is used to acquire instantaneous voltage signals that characterize instantaneous current. A first-level voltage latch circuit, connected to the current sampling circuit, is used to latch the peak voltage of the instantaneous voltage signal; A secondary voltage latch circuit, connected to the primary voltage latch circuit, is used to latch the peak voltage transferred by the primary voltage latch circuit again; The latching time of the first-stage voltage latching circuit is shorter than that of the second-stage voltage latching circuit.

2. The detection circuit according to claim 1, characterized in that, The first-stage voltage latching circuit includes a controllable switch U1, a first-stage latching capacitor C6, and an isolation device U3. The input terminal of the controllable switch U1 is connected to the current sampling circuit, the output terminal is connected to one end of the first-stage latching capacitor C6 and the non-inverting input terminal of the isolation device U3, the control terminal is connected to the peak detection circuit, the other end of the first-stage latching capacitor C6 is connected to the common ground, and the inverting input terminal of the isolation device U3 is connected to the output terminal of the isolation device U3 and the second-stage voltage latching circuit. The controllable switch U1 is turned off when it receives the first control signal from the peak detection circuit that detects the release of instantaneous current, and the first-stage latching capacitor C6 latches the peak voltage.

3. The detection circuit according to claim 2, characterized in that, The first-stage voltage latching circuit also includes a first current-limiting resistor R2, one end of which is connected to the output terminal of the controllable switch U1, and the other end is connected to one end of the first-stage latching capacitor C6 and the input terminal of the isolation device U3.

4. The detection circuit according to claim 2, characterized in that, The secondary voltage latching circuit includes a controllable switch U2, a secondary latching capacitor C7, and an isolation device U4. The input terminal of the controllable switch U2 is connected to the primary voltage latching circuit, the output terminal is connected to one end of the secondary latching capacitor C7 and the non-inverting input terminal of the isolation device U4, the control terminal is connected to a controller, the other end of the secondary latching capacitor C7 is connected to a common ground, and the inverting input terminal of the isolation device U4 is connected to the output terminal of the isolation device U4. When the controllable switch U1 is turned off, the controllable switch U2 receives the second control signal released by the controller and turns on. The peak voltage passes through the isolation device U3 and the controllable switch U2 in sequence and enters the secondary latching capacitor C7 for latching.

5. The detection circuit according to claim 4, characterized in that, The first-stage voltage latching circuit also includes a second current-limiting resistor R3. One end of the second current-limiting resistor R3 is connected to the output terminal of the controllable switch U2, and the other end is connected to one end of the second-stage latching capacitor C7 and the input terminal of the isolation device U4.

6. The detection circuit according to claim 4, characterized in that, The capacitance value of the primary latching capacitor C6 is less than the capacitance value of the secondary latching capacitor C7.

7. The detection circuit according to claim 4, characterized in that, The slew rate of the isolation device U3 is greater than or equal to the slew rate of the isolation device U4.

8. The detection circuit according to any one of claims 1-7, characterized in that, The current sampling circuit includes: A sampling resistor is used to acquire the instantaneous voltage signal that characterizes the instantaneous current. A signal amplification circuit, connected across the sampling resistor, is used to amplify the instantaneous voltage signal.

9. The detection circuit according to claim 8, characterized in that, The signal amplification circuit includes an operational amplifier U5, resistors R1, R4, R6, and R7. The inverting input of the operational amplifier U5 is connected to one end of the sampling resistor via resistor R4, and its non-inverting input is connected to the other end of the sampling resistor via resistor R6. Resistor R1 is connected between the inverting input and output of the operational amplifier U5, and resistor R7 is connected between the non-inverting input and common ground of the operational amplifier U5.

10. A device for testing instantaneous current, characterized in that, include: The system includes an instantaneous current generation circuit, a peak detection loop, a source testing device, a controller, and an instantaneous current detection circuit as described in any one of claims 1-9; the instantaneous current generation circuit is connected to the current sampling circuit; the peak detection loop is connected to the first-stage voltage latch circuit; and the source testing device and the controller are respectively connected to the second-stage voltage latch circuit.

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