Protection circuit and output protection circuit of plasma device

Abstract

The utility model provides a kind of output protection circuit of protection circuit and plasma equipment, comprising: for converting isolation type H bridge high frequency inverter circuit of direct current input into high frequency alternating current signal;For coupling and converting into direct current signal by full-bridge rectification after high frequency alternating current signal is coupled and is divided voltage filtered and obtains smooth direct current voltage signal Current sampling circuit;For receiving smooth direct current voltage signal and output comparison result signal and overcurrent signal after processing overcurrent comparison circuit;For converting into square wave zero crossing signal after high frequency alternating current signal voltage division processing Zero-crossing detection circuit;For output control signal to enable control when overcurrent signal and square wave zero crossing signal are simultaneously effective Short-circuit and gate control circuit;For receiving control signal, comparison result signal and overcurrent signal and obtaining adjusted system reactance after processing dynamic reactance regulating circuit.The mode, improve the equipment reliability and the working efficiency when using equipment.

Description

Technical Field

[0001] This utility model relates to the field of circuit protection technology, and in particular to a protection circuit and an output protection circuit for plasma equipment. Background Technology

[0002] Some devices require the generation of plasma arc light using radio frequency energy to achieve their function, therefore their core circuits must have both high energy output and short-circuit protection.

[0003] In related technologies, output short-circuit protection technology is mainly based on H-bridge inverter architecture and LC impedance matching network, triggering protection action through current threshold. However, with the increasing demands for equipment reliability, significant deficiencies have been exposed in terms of plasma arc excitation success rate, energy efficiency, and impedance adaptability. Not only are misjudgments occurring during the plasma arc excitation stage, but also issues arise such as power device switching stress accumulation and the need to suppress short-circuit current stress through dynamic impedance matching. This greatly reduces equipment reliability and indirectly affects the operating efficiency of the equipment. Utility Model Content

[0004] In view of this, the purpose of this utility model is to provide a protection circuit and an output protection circuit for plasma equipment, which avoids misjudgment during the plasma arc excitation stage, the accumulation of power device switching stress, and the problem of suppressing short-circuit current stress through impedance dynamic matching, thereby improving equipment reliability and working efficiency when using the equipment.

[0005] In a first aspect, this utility model embodiment provides a protection circuit, comprising: an isolated H-bridge high-frequency inverter circuit, connected to a short-circuit AND gate control circuit and receiving an external DC input, used to convert the DC input into a high-frequency AC signal; a current sampling circuit, connected to the isolated H-bridge high-frequency inverter circuit and receiving the high-frequency AC signal, used to couple the high-frequency AC signal and convert it into a DC signal through full-bridge rectification, and to obtain a smooth DC voltage signal after voltage division and filtering of the DC signal; and an overcurrent comparison circuit, connected to the current sampling circuit, used to receive the smooth DC voltage signal and compare it with a predetermined voltage threshold, and output a comparison result. The system comprises: a result signal and an overcurrent signal; a zero-crossing detection circuit, connected to an isolated H-bridge high-frequency inverter circuit and receiving a high-frequency AC signal, used to divide the high-frequency AC signal to generate a pulsating DC signal, and convert the pulsating DC signal into a square wave zero-crossing signal; a short-circuit AND gate control circuit, used to receive the overcurrent signal and the square wave zero-crossing signal, and output a control signal for enable control when both the overcurrent signal and the square wave zero-crossing signal are valid; and a dynamic reactance adjustment circuit, connected to the short-circuit AND gate control circuit and the overcurrent comparison circuit, used to receive the control signal, the comparison result signal, and the overcurrent signal, and obtain the adjusted system reactance based on the control signal, the comparison result signal, and the overcurrent signal.

[0006] In a preferred embodiment of this invention, the aforementioned isolated H-bridge high-frequency inverter circuit includes: a positive power supply terminal, a negative power supply terminal, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a high-frequency transformer, a first capacitor, a second capacitor, a first inductor, and a second inductor; the positive power supply terminal is connected to the drain of the first NMOS transistor, the first terminal of the first capacitor, and the drain of the third NMOS transistor; the gate of the first NMOS transistor is connected to a short-circuit AND gate control circuit and the first terminal of the fourth resistor; the source of the first NMOS transistor is connected to the second terminal of the fourth resistor, pin 2 of the high-frequency transformer, and the drain of the second NMOS transistor; the second terminal of the first capacitor is connected to the negative power supply terminal; the gate of the third NMOS transistor is connected to the first terminal of the first resistor and the short-circuit AND gate control circuit. Connections are made as follows: The source of the third NMOS transistor is connected to the second terminal of the first resistor and the drain of the fourth NMOS transistor; the gate of the second NMOS transistor is connected to the first terminal of the second resistor and the short-circuit gate control circuit; the source of the second NMOS transistor is connected to the second terminal of the second resistor and the negative power supply; the source of the fourth NMOS transistor is connected to pin 3 of the high-frequency transformer; the gate of the fourth NMOS transistor is connected to the first terminal of the third resistor; the drain of the fourth NMOS transistor is connected to the second terminal of the third resistor; the second terminal of the third resistor is connected to the negative power supply; pin 1 of the high-frequency transformer is connected to the first terminal of the second capacitor; the second terminal of the second capacitor is connected to the first terminal of the first inductor and the first terminal of the second inductor; pin 4 of the high-frequency transformer is connected to the current sampling circuit; the second terminals of both the first and second inductors are connected to the dynamic reactance adjustment circuit.

[0007] In a preferred embodiment of this utility model, the aforementioned current sampling circuit includes: a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth resistor, a third capacitor, a current transformer, and a first AC output side; the output of pin 4 of the high-frequency transformer passes through the current transformer and is correspondingly connected to the first AC output side; the first end of the secondary coil of the current transformer is connected to the negative terminal of the first diode and the positive terminal of the second diode; the second end of the secondary coil of the current transformer is connected to the positive terminal of the third diode and the negative terminal of the fourth diode; the positive terminal of the first diode is connected to the second end of the fifth resistor and the second end of the third capacitor; the second end of the fifth resistor and the second end of the third capacitor are both grounded; the negative terminal of the second diode is connected to the negative terminal of the third diode, the first end of the fifth resistor, and the first end of the sixth resistor; the positive terminal of the fourth diode is grounded; the second end of the sixth resistor is connected to the first end of the third capacitor and the overcurrent comparator circuit.

[0008] In a preferred embodiment of this utility model, the overcurrent comparison circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a fourth capacitor, a first driving module, and a first comparator; the non-inverting input of the first comparator is connected to the second terminal of the sixth resistor; the inverting input of the first comparator is connected to the first terminal of the fourth capacitor, the second terminal of the eighth resistor, and the first terminal of the ninth resistor; the second terminals of the fourth capacitor and the ninth resistor are both connected to a zero-crossing detection circuit; the output of the first comparator is connected to the first terminal of the seventh resistor, the enable pin of the first driving module, and a short-circuit AND gate control circuit; the second terminal of the seventh resistor is connected to the first terminal of the eighth resistor and the zero-crossing detection circuit; the driving signal of the first driving module is connected to a dynamic reactance adjustment circuit.

[0009] In a preferred embodiment of this invention, the zero-crossing detection circuit includes: a second comparator, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifth diode, a sixth diode, a seventh diode, an eighth diode, a fifth capacitor, a first AC output side, and a second AC output side; the first AC output side is connected to the negative terminal of the fifth diode and the positive terminal of the sixth diode; the negative terminal of the sixth diode is connected to the negative terminal of the seventh diode and the first end of the tenth resistor; the positive terminal of the seventh diode is connected to the negative terminal of the eighth diode and the second AC output side; the positive terminal of the eighth diode is grounded. The positive terminal of the fifth diode and the second terminal of the eleventh resistor are both grounded; the first terminal of the eleventh resistor and the second terminal of the tenth resistor are both connected to the inverting input terminal of the second comparator; the first terminal of the fifth capacitor is connected to the second terminal of the fourth capacitor and the first terminal of the twelfth resistor and grounded; the second terminal of the fifth capacitor is connected to the first terminal of the thirteenth resistor and connected to +5V; the second terminals of the thirteenth resistor and the second terminals of the twelfth resistor are both connected to the non-inverting input terminal of the second comparator; the output terminal of the second comparator is connected to the first terminal of the fourteenth resistor and the short-circuit AND gate control circuit; the second terminal of the fourteenth resistor is connected to the second terminal of the seventh resistor.

[0010] In a preferred embodiment of this utility model, the above-mentioned short-circuit AND gate control circuit includes: a sixth capacitor, an AND gate chip, a second driving module, a third driving module, and a fourth driving module; pin 1 of the AND gate chip is connected to the output terminal of the first comparator; pin 2 of the AND gate chip is connected to the output terminal of the second comparator; pin 3 of the AND gate chip is connected to the second terminal of the sixth capacitor and grounded; pin 5 of the AND gate chip is connected to the first terminal of the sixth capacitor and connected to +5V; pin 4 of the AND gate chip is connected to the enable pins of the second driving module, the third driving module, and the fourth driving module; the driving signal of the second driving module is connected to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor; the driving signal of the third driving module is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor; and the driving signal of the fourth driving module is connected to the dynamic reactance adjustment circuit.

[0011] In a preferred embodiment of this utility model, the aforementioned dynamic reactance adjustment circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a second AC output side, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and an eighteenth resistor; the drain of the fifth NMOS transistor is connected to the second terminal of the second inductor; the source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor, the second terminal of the eighteenth resistor, and the first terminal of the fifteenth resistor; the gate of the fifth NMOS transistor is connected to the first terminal of the eighteenth resistor and the drive signal of the fourth drive module; the sixth NMOS transistor... The gate of the S-channel MOSFET is connected to the second terminal of the fifteenth resistor and the drive signal of the fourth drive module; the drain of the sixth NMOS transistor is connected to the second AC output side and the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor is connected to the drive signal of the fourth drive module and the first terminal of the seventeenth resistor; the source of the eighth NMOS transistor is connected to the second terminal of the seventeenth resistor, the first terminal of the sixteenth resistor, and the source of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected to the second terminal of the first inductor; the gate of the seventh NMOS transistor is connected to the second terminal of the sixteenth resistor and the drive signal of the first drive module.

[0012] In a preferred embodiment of this invention, the driving signals of the first driving module include: driving signal HG1 and driving signal LG1; driving signal HG1 is connected to the gate of the seventh NMOS transistor; driving signal LG1 is connected to the gate of the eighth NMOS transistor; the driving signals of the second driving module include: driving signal HG2 and driving signal LG2; driving signal HG2 is connected to the gate of the third NMOS transistor, and driving signal LG2 is connected to the gate of the fourth NMOS transistor; the driving signals of the third driving module include: driving signal HG3 and driving signal LG3; driving signal HG3 is connected to the gate of the first NMOS transistor, and driving signal LG3 is connected to the gate of the second NMOS transistor; the driving signals of the fourth driving module include: driving signal HG4 and driving signal LG4; driving signal HG4 is connected to the gate of the fifth NMOS transistor, and driving signal LG4 is connected to the gate of the sixth NMOS transistor.

[0013] In a preferred embodiment of this invention, the full-bridge rectifier corresponds to the first diode, the second diode, the third diode, and the fourth diode.

[0014] Secondly, this utility model embodiment also provides an output protection circuit for a plasma device, comprising: a plasma device and the protection circuit described in the first aspect.

[0015] The present invention provides the following beneficial effects: This utility model embodiment provides a protection circuit and an output protection circuit for a plasma device. An isolated H-bridge high-frequency inverter circuit is connected to a short-circuit AND gate control circuit and receives an external DC input, used to convert the DC input into a high-frequency AC signal. A current sampling circuit is connected to the isolated H-bridge high-frequency inverter circuit and receives the high-frequency AC signal, used to couple the high-frequency AC signal and convert it into a DC signal through full-bridge rectification, and then perform voltage division and filtering on the DC signal to obtain a smooth DC voltage signal. An overcurrent comparator circuit is connected to the current sampling circuit, used to receive the smooth DC voltage signal and compare it with a predetermined voltage threshold, outputting a ratio. The system compares the result signal and the overcurrent signal; the zero-crossing detection circuit is connected to the isolated H-bridge high-frequency inverter circuit and receives the high-frequency AC signal. It is used to divide the high-frequency AC signal to generate a pulsating DC signal, and then convert the pulsating DC signal into a square wave zero-crossing signal; the short-circuit AND gate control circuit receives the overcurrent signal and the square wave zero-crossing signal, and outputs a control signal for enable control when both signals are valid; the dynamic reactance adjustment circuit is connected to the short-circuit AND gate control circuit and the overcurrent comparison circuit. It receives the control signal, the comparison result signal, and the overcurrent signal, and obtains the adjusted system reactance based on these signals. This method avoids misjudgment during the plasma arc excitation stage, the accumulation of switching stress in power devices, and the problem of suppressing short-circuit current stress through impedance dynamic matching, thus improving equipment reliability and operating efficiency.

[0016] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0017] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A structural diagram of a protection circuit provided in an embodiment of this utility model; Figure 2 A circuit diagram of an isolated H-bridge high-frequency inverter circuit provided for an embodiment of this utility model; Figure 3A circuit diagram of a current sampling circuit provided for an embodiment of this utility model; Figure 4 A circuit diagram of an overcurrent comparator circuit provided for an embodiment of this utility model; Figure 5 A circuit diagram of a zero-crossing detection circuit provided for an embodiment of this utility model; Figure 6 A circuit diagram of a short-circuit AND gate control circuit provided for an embodiment of this utility model; Figure 7 A circuit diagram of a dynamic reactance adjustment circuit provided for an embodiment of this utility model; Figure 8 An overall circuit diagram of a protection circuit provided for an embodiment of this utility model; Figure 9 This is a structural diagram of an output protection circuit for a plasma device provided in an embodiment of the present invention.

[0020] Illustration: 100 - Protection circuit; 10 - Isolated H-bridge high-frequency inverter circuit; 20 - Current sampling circuit; 30 - Overcurrent comparator circuit; 40 - Zero-crossing detection circuit; 50 - Short-circuit AND gate control circuit; 60 - Dynamic reactance adjustment circuit; +Vdc - Positive power supply; -Vdc - Negative power supply; Q1 - First NMOS transistor; Q2 - Second NMOS transistor; Q3 - Third NMOS transistor; Q4 - Fourth NMOS transistor; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; T1 - High-frequency transformer; C1 - First capacitor; C2 - Second capacitor; L1 - First inductor; L2 - Second inductor; D1 - First diode; D2 - Second diode; D3 - Third diode; D4 - Fourth diode; R5 - Fifth resistor; R6 - Sixth resistor; C3 - Third capacitor; CT1 - Current transformer; AC1 - First AC output side; R7 - Seventh resistor; R8 - Eighth resistor Resistors; R9 - Ninth resistor; C4 - Fourth capacitor; 31 - First driver module; U1 - First comparator; U2 - Second comparator; R10 - Tenth resistor; R11 - Eleventh resistor; R12 - Twelfth resistor; R13 - Thirteenth resistor; R14 - Fourteenth resistor; D5 - Fifth diode; D6 - Sixth diode; D7 - Seventh diode; D8 - Eighth diode; C5 - Fifth capacitor; AC2 - Second AC output side; C6 - Sixth capacitor; U3 - AND gate chip; 51 - Second driver module; 52 - Third driver module; 53 - Fourth driver module; Q5 - Fifth NMOS transistor; Q6 - Sixth NMOS transistor; Q7 - Seventh NMOS transistor; Q8 - Eighth NMOS transistor; R15 - Fifteenth resistor; R16 - Sixteenth resistor; R17 - Seventeenth resistor; R18 - Eighteenth resistor; 1000 - Output protection circuit of plasma equipment; 200 - Plasma equipment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0022] Some devices require the generation of plasma arc light using radio frequency energy to achieve their function, therefore their core circuits must have both high energy output and short-circuit protection.

[0023] In related technologies, output short-circuit protection technology is mainly based on H-bridge inverter architecture and LC impedance matching network, triggering protection action through current threshold. However, with the increasing demands for equipment reliability, significant deficiencies have been exposed in terms of plasma arc excitation success rate, energy efficiency, and impedance adaptability. Not only are misjudgments occurring during the plasma arc excitation stage, but also issues arise such as power device switching stress accumulation and the need to suppress short-circuit current stress through dynamic impedance matching. This greatly reduces equipment reliability and indirectly affects the operating efficiency of the equipment.

[0024] Specifically, the current output protection circuit technology mainly adopts the following design: (1) Short circuit detection mechanism based on single current threshold or multi-level current detection.

[0025] Solution: Use a current transformer to detect the load current in real time. When the current exceeds a fixed threshold (e.g., 15A), it is determined to be a short circuit, and the power device is forcibly turned off.

[0026] (2) The H-bridge inverter hard shutdown protection mode or voltage phase tracking scheme is proposed, but the zero-crossing synchronous shutdown mechanism is not integrated.

[0027] Solution: Directly cut off the MOS / IGBT drive signal during short-circuit protection.

[0028] (3) Fixed parameter LC impedance matching network.

[0029] Solution: Use a fixed inductor and capacitor series network to match the load impedance and suppress short-circuit current.

[0030] Based on this, the present invention provides a protection circuit and an output protection circuit for plasma equipment, which avoids misjudgment during the plasma arc excitation stage, the accumulation of switching stress in power devices, and the problem of suppressing short-circuit current stress through impedance dynamic matching, thereby improving equipment reliability and working efficiency when using the equipment.

[0031] To facilitate understanding of this embodiment, a protection circuit disclosed in this utility model embodiment will first be described in detail.

[0032] Example 1 This utility model embodiment provides a protection circuit. Figure 1 This is a structural diagram of a protection circuit provided in an embodiment of the present utility model. (See diagram below.) Figure 1 As shown, the protection circuit 100 may include: an isolated H-bridge high-frequency inverter circuit 10, a current sampling circuit 20, an overcurrent comparison circuit 30, a zero-crossing detection circuit 40, a short-circuit AND gate control circuit 50, and a dynamic reactance adjustment circuit 60.

[0033] The isolated H-bridge high-frequency inverter circuit 10 is connected to the following circuits: current sampling circuit 20, short-circuit AND gate control circuit 50, and dynamic reactance adjustment circuit 60; the current sampling circuit 20 is also connected to the following circuits: overcurrent comparator circuit 30 and zero-crossing detection circuit 40; the overcurrent comparator circuit 30 is also connected to the following circuits: zero-crossing detection circuit 40, short-circuit AND gate control circuit 50, and dynamic reactance adjustment circuit 60; the zero-crossing detection circuit 40 is also connected to the following circuits: short-circuit AND gate control circuit 50 and dynamic reactance adjustment circuit 60; the short-circuit AND gate control circuit 50 is also connected to the following circuit: dynamic reactance adjustment circuit 60.

[0034] Among them, the isolated H-bridge high-frequency inverter circuit 10 receives external DC input and is used to convert the DC input into a high-frequency AC signal.

[0035] Among them, the current sampling circuit 20 receives high-frequency AC signals: it is used to couple the high-frequency AC signals and convert them into DC signals through full-bridge rectification, and then perform voltage division and filtering on the DC signals to obtain smooth DC voltage signals.

[0036] Among them, the overcurrent comparison circuit 30 is used to receive a smoothed DC voltage signal and compare it with a predetermined voltage threshold, and output a comparison result signal and an overcurrent signal.

[0037] Among them, the zero-crossing detection circuit 40 receives high-frequency AC signals, divides the high-frequency AC signals to generate pulsating DC signals, and converts the pulsating DC signals into square wave zero-crossing signals.

[0038] Among them, the short-circuit AND gate control circuit 50 is used to receive the overcurrent signal and the square wave zero-crossing signal, and outputs a control signal to perform enable control when the overcurrent signal and the square wave zero-crossing signal are both valid.

[0039] The dynamic reactance adjustment circuit 60 is used to receive control signals, comparison result signals, and overcurrent signals, and to obtain the adjusted system reactance based on the control signals, comparison result signals, and overcurrent signals.

[0040] The protection circuit 100 provided in this embodiment of the present invention avoids misjudgment during the plasma arc excitation stage, the accumulation of switching stress in power devices, and the problem of suppressing short-circuit current stress through impedance dynamic matching, thereby improving equipment reliability and working efficiency when using the equipment.

[0041] Example 2 This utility model embodiment also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; this protection circuit focuses on describing the specific structure of the isolated H-bridge high-frequency inverter circuit 10.

[0042] Figure 2A circuit diagram of an isolated H-bridge high-frequency inverter circuit provided for an embodiment of this utility model is shown below. Figure 2 As shown, the isolated H-bridge high-frequency inverter circuit 10 may include: a positive power supply +Vdc, a negative power supply -Vdc, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a high-frequency transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2.

[0043] Specifically, the positive terminal of the power supply +Vdc is connected to the drain of the first NMOS transistor Q1, the first terminal of the first capacitor C1, and the drain of the third NMOS transistor Q3; the gate of the first NMOS transistor Q1 is connected to the short-circuit AND gate control circuit 50 and the first terminal of the fourth resistor R4; the source of the first NMOS transistor Q1 is connected to the second terminal of the fourth resistor R4, pin 2 of the high-frequency transformer T1, and the drain of the second NMOS transistor Q2; the second terminal of the first capacitor C1 is connected to the negative terminal of the power supply -Vdc; the gate of the third NMOS transistor Q3 is connected to the first terminal of the first resistor R1 and the short-circuit AND gate control circuit 50; the source of the third NMOS transistor Q3 is connected to the second terminal of the first resistor R1 and the drain of the fourth NMOS transistor Q4; the gate of the second NMOS transistor Q2 is connected to the first terminal of the second resistor R2 and the short-circuit AND gate control circuit 50. The gate control circuit 50 is connected; the source of the second NMOS transistor Q2 is connected to the second terminal of the second resistor R2 and the negative power supply -Vdc; the source of the fourth NMOS transistor Q4 is connected to pin 3 of the high-frequency transformer T1; the gate of the fourth NMOS transistor Q4 is connected to the first terminal of the third resistor R3; the drain of the fourth NMOS transistor Q4 is connected to the second terminal of the third resistor R3; the second terminal of the third resistor R3 is connected to the negative power supply -Vdc; pin 1 of the high-frequency transformer T1 is connected to the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 is connected to the first terminal of the first inductor L1 and the first terminal of the second inductor L2; pin 4 of the high-frequency transformer T1 is connected to the current sampling circuit 20; the second terminals of the first inductor L1 and the second terminals of the second inductor L2 are both connected to the dynamic reactance adjustment circuit 60.

[0044] Based on the full-bridge topology, the DC input is converted into a high-frequency square wave by controlling the switching of the H-bridge through complementary drive signals; electrical isolation and voltage transformation are completed by the high-frequency transformer T1, and the waveform quality is optimized by the LC network.

[0045] The full-bridge topology consists of a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, and a fourth NMOS transistor Q4. The LC network consists of a second capacitor C2, a first inductor L1, and a second inductor L2, specifically C2 + L1 / L2. The complementary drive signals are determined by drive signals HG1, LG1, HG2, and LG2, specifically HG1 / LG1 and HG2 / LG2. The H-bridge corresponds to the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor. The full-bridge rectifier corresponds to the first diode, the second diode, the third diode, and the fourth diode.

[0046] It should be noted that the first diode, second diode, third diode, fourth diode, drive signal HG1, drive signal LG1, drive signal HG2, and drive signal LG2 are not included in the isolated H-bridge high-frequency inverter circuit 10. Figure 2 There are no corresponding labels or connection methods in the text.

[0047] The isolated H-bridge high-frequency inverter circuit provided in this embodiment of the invention connects to a short-circuit AND gate control circuit and receives external DC input. It can convert the DC input into a high-frequency AC signal, realizing the DC to high-frequency AC conversion, providing safety isolation and voltage regulation, and outputting the high-frequency power required by the plasma load.

[0048] Example 3 This utility model embodiment also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; the specific structure of the current sampling circuit 20 is described in detail in this protection circuit.

[0049] Figure 3 A circuit diagram of a current sampling circuit provided for an embodiment of this utility model is shown below. Figure 3 As shown, the current sampling circuit 20 may include: a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth resistor R5, a sixth resistor R6, a third capacitor C3, a current transformer CT1, and a first AC output side AC1.

[0050] Specifically, the output of pin 4 of the high-frequency transformer passes through the current transformer CT1 and is connected to the first AC output side AC1. The first end of the secondary coil of the current transformer CT1 is connected to the negative terminal of the first diode D1 and the positive terminal of the second diode D2. The second end of the secondary coil of the current transformer CT1 is connected to the positive terminal of the third diode D3 and the negative terminal of the fourth diode D4. The positive terminal of the first diode D1 is connected to the second terminal of the fifth resistor R5 and the second terminal of the third capacitor C3. The second terminals of the fifth resistor R5 and the third capacitor C3 are both grounded. The negative terminal of the second diode D2 is connected to the negative terminal of the third diode D3, the first terminal of the fifth resistor R5, and the first terminal of the sixth resistor R6. The positive terminal of the fourth diode D4 is grounded. The second terminal of the sixth resistor R6 is connected to the first terminal of the third capacitor C3 and the overcurrent comparator circuit 30.

[0051] Among them, the current transformer CT1 couples the AC current signal, and the secondary side is converted into a DC signal through full-bridge rectification. After being divided by the fifth resistor R5 and the sixth resistor R6 and filtered by the third capacitor C3, a smooth DC voltage signal is formed.

[0052] The full-bridge rectifier corresponds to the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4.

[0053] It should be noted that the high-frequency transformer is not included in the current sampling circuit 20, therefore Figure 3 There are no corresponding labels or connection methods in the text.

[0054] The current sampling circuit provided in this embodiment of the utility model is connected to an isolated H-bridge high-frequency inverter circuit and receives high-frequency AC signals. It can couple the high-frequency AC signals and convert them into DC signals through full-bridge rectification. After voltage division and filtering of the DC signals, a smooth DC voltage signal is obtained, realizing non-intrusive monitoring of load current. It outputs a DC voltage signal that is proportional to the current amplitude, providing a quantitative basis for overcurrent protection.

[0055] Example 4 This utility model embodiment also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; the specific structure of the overcurrent comparison circuit 30 is described in detail in this protection circuit.

[0056] Figure 4 A circuit diagram of an overcurrent comparator circuit provided for an embodiment of this utility model is shown below. Figure 4 As shown, the overcurrent comparator circuit 30 may include: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth capacitor C4, a first drive module 31, and a first comparator U1.

[0057] Specifically, the non-inverting input of the first comparator U1 is connected to the second terminal of the sixth resistor; the inverting input of the first comparator U1 is connected to the first terminal of the fourth capacitor C4, the second terminal of the eighth resistor R8, and the first terminal of the ninth resistor R9; the second terminals of the fourth capacitor C4 and the ninth resistor R9 are both connected to the zero-crossing detection circuit 40; the output of the first comparator U1 is connected to the first terminal of the seventh resistor R7, the enable pin of the first drive module 31, and the short-circuit AND gate control circuit 50; the second terminal of the seventh resistor R7 is connected to the first terminal of the eighth resistor R8 and the zero-crossing detection circuit 40; the drive signal of the first drive module 31 is connected to the dynamic reactance adjustment circuit 60.

[0058] The driving signals of the first driving module 31 include: driving signal HG1 and driving signal LG1; driving signal HG1 is connected to the gate of the seventh NMOS transistor Q7; driving signal LG1 is connected to the gate of the eighth NMOS transistor Q8. The first comparator U1 compares the sampled voltage with a predetermined voltage threshold. When the threshold is exceeded, it outputs a high level to trigger the first driving module 31, which controls the seventh NMOS transistor / eighth NMOS transistor to turn off.

[0059] The sampling voltage corresponds to the non-inverting input of the first comparator U1, and the voltage threshold is set by the voltage divider of the eighth resistor R8 and the ninth resistor R9.

[0060] It should be noted that the sixth resistor, the seventh NMOS transistor, and the eighth NMOS transistor are not included in the overcurrent comparator circuit 30, therefore Figure 4 There are no corresponding labels or connection methods in the text.

[0061] The overcurrent comparison circuit provided in this embodiment can receive a smoothed DC voltage signal and compare it with a predetermined voltage threshold, outputting a comparison result signal and an overcurrent signal, thereby realizing real-time determination of the overcurrent state and triggering single-channel reactor adjustment or short-circuit protection.

[0062] Example 5 This embodiment of the invention also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; the specific structure of the zero-crossing detection circuit 40 is described in detail in this protection circuit.

[0063] Figure 5 A circuit diagram of a zero-crossing detection circuit provided for an embodiment of this utility model is shown below. Figure 5As shown, the zero-crossing detection circuit 40 may include: a second comparator U2, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a fifth capacitor C5, a first AC output side AC1, and a second AC output side AC2.

[0064] Specifically, the first AC output side AC1 is connected to the negative terminal of the fifth diode D5 and the positive terminal of the sixth diode D6; the negative terminal of the sixth diode D6 is connected to the negative terminal of the seventh diode D7 and the first terminal of the tenth resistor R10; the positive terminal of the seventh diode D7 is connected to the negative terminal of the eighth diode D8 and the second AC output side AC2; the positive terminal of the eighth diode D8 is grounded; the positive terminal of the fifth diode D5 and the second terminal of the eleventh resistor R11 are both grounded; the first terminal of the eleventh resistor R11 and the second terminal of the tenth resistor R10 are both connected to the second comparator U. The inverting input terminal of the second comparator is connected; the first terminal of the fifth capacitor C5 is connected to the second terminal of the fourth capacitor and the first terminal of the twelfth resistor R12 and grounded; the second terminal of the fifth capacitor C5 is connected to the first terminal of the thirteenth resistor R13 and connected to +5V; the second terminals of the thirteenth resistor R13 and the second terminals of the twelfth resistor R12 are both connected to the non-inverting input terminal of the second comparator U2; the output terminal of the second comparator U2 is connected to the first terminal of the fourteenth resistor R14 and the short-circuit AND gate control circuit; the second terminal of the fourteenth resistor R14 is connected to the second terminal of the seventh resistor.

[0065] In this circuit, the first AC output side AC1 in the current sampling circuit 20 is connected to the AC output side in the zero-crossing detection circuit 40.

[0066] Specifically, the AC output envelope is extracted through full-bridge rectification, a pulsating DC signal is generated through a voltage divider network, and then converted into a square wave zero-crossing signal by the second comparator U2.

[0067] Among them, the full-bridge rectifier corresponds to the fifth diode D5, the sixth diode D6, the seventh diode D7, and the eighth diode D8, and the voltage divider network corresponds to the tenth resistor R10 and the eleventh resistor R11.

[0068] It should be noted that the short-circuit AND gate control circuit, the fourth capacitor, and the seventh resistor are not included in the zero-crossing detection circuit 40, therefore Figure 5 There are no corresponding labels or connection methods in the text.

[0069] The zero-crossing detection circuit provided in this embodiment of the utility model is connected to an isolated H-bridge high-frequency inverter circuit and receives high-frequency AC signals. It can divide the high-frequency AC signals to generate pulsating DC signals, and convert the pulsating DC signals into square wave zero-crossing signals, thereby achieving accurate positioning of the AC phase zero point, providing synchronous triggering opportunities for protection actions, and reducing switching losses.

[0070] Example 6 This utility model embodiment also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; the specific structure of the short-circuit AND gate control circuit 50 is described in detail in this protection circuit.

[0071] Figure 6 A circuit diagram of a short-circuit AND gate control circuit provided for an embodiment of this utility model, as shown below. Figure 6 As shown, the short-circuit AND gate control circuit 50 may include: a sixth capacitor C6, an AND gate chip U3, a second driving module 51, a third driving module 52, and a fourth driving module 53.

[0072] Specifically, pin 1 of AND gate chip U3 is connected to the output of the first comparator; pin 2 of AND gate chip U3 is connected to the output of the second comparator; pin 3 of AND gate chip U3 is connected to the second terminal of the sixth capacitor C6 and grounded; pin 5 of AND gate chip U3 is connected to the first terminal of the sixth capacitor C6 and connected to +5V; pin 4 of AND gate chip U3 is connected to the enable pin of the second drive module 51, the enable pin of the third drive module 52, and the enable pin of the fourth drive module 53; the drive signal of the second drive module 51 is connected to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor; the drive signal of the third drive module 52 is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor; and the drive signal of the fourth drive module 53 is connected to the dynamic reactance adjustment circuit 60.

[0073] Among them, pin 1 of gate chip U3 corresponds to Figure 6 The A in the diagram corresponds to pin 2 of gate chip U3. Figure 6 The B in the diagram corresponds to pin 3 of gate chip U3. Figure 6 The GND inside the AND gate chip U3 corresponds to pin 4 of the AND gate chip U3. Figure 6 The Y in the diagram corresponds to pin 5 of gate chip U3. Figure 6 VCC in the middle.

[0074] The driving signals of the second driving module 51 include: driving signal HG2 and driving signal LG2; driving signal HG2 is connected to the gate of the third NMOS transistor, and driving signal LG2 is connected to the gate of the fourth NMOS transistor.

[0075] The driving signals of the third driving module 52 include: driving signal HG3 and driving signal LG3; driving signal HG3 is connected to the gate of the first NMOS transistor, and driving signal LG3 is connected to the gate of the second NMOS transistor.

[0076] The driving signals of the fourth driving module 53 include: driving signal HG4 and driving signal LG4; driving signal HG4 is connected to the gate of the fifth NMOS transistor, and driving signal LG4 is connected to the gate of the sixth NMOS transistor.

[0077] Among them, the AND gate chip U3 receives the output of the first comparator corresponding to the overcurrent signal and the zero-crossing signal, and outputs a high level only when both are valid at the same time, enabling the drive circuit to shut down the H-bridge and the reactance adjustment module.

[0078] Among them, the overcurrent signal corresponds to the output terminal of the first comparator, the zero-crossing signal corresponds to pin 1 of the AND gate chip U3; the driving circuit corresponds to the second driving module 51, the third driving module 52, and the third driving module 53; the H-bridge corresponds to the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor; and the reactance adjustment module corresponds to the fifth NMOS transistor and the sixth NMOS transistor.

[0079] It should be noted that the first comparator, the second comparator, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are not included in the short-circuit AND gate control circuit 50. Figure 6 There are no corresponding labels or connection methods in the text.

[0080] In practical applications, this is only used when the AC phase is at a zero-crossing point and the real-time current value exceeds the dynamic threshold I. max When triggered, the system short-circuit protection is activated, reducing false short-circuit detections and improving the plasma excitation success rate. Furthermore, during dual-condition triggering, the drive signal is synchronously disabled via gate circuits. Back-to-back NMOS / IGBTs ensure that power devices are turned off at zero voltage, reducing switching losses.

[0081] The short-circuit AND gate control circuit 50 provided in this embodiment of the utility model can receive overcurrent signals and square wave zero-crossing signals. When both overcurrent signals and square wave zero-crossing signals are valid, it outputs control signals for enable control, realizing dual-condition trigger protection, avoiding triggering short-circuit malfunctions and improving the plasma ignition success rate. At the same time, it turns off the power devices in the zero-crossing state, optimizing the power device turn-off timing.

[0082] Example 7 This utility model embodiment also provides another protection circuit; this protection circuit is implemented based on the protection circuit of the above embodiment; the specific structure of the dynamic reactance adjustment circuit 60 is described in detail in this protection circuit.

[0083] Figure 7 A circuit diagram of a dynamic reactance adjustment circuit provided for an embodiment of this utility model is shown below. Figure 7As shown, the dynamic reactance adjustment circuit 60 may include: a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a seventh NMOS transistor Q7, an eighth NMOS transistor Q8, a second AC output side AC2, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, and an eighteenth resistor R18.

[0084] Specifically, the drain of the fifth NMOS transistor Q5 is connected to the second terminal of the second inductor; the source of the fifth NMOS transistor Q5 is connected to the source of the sixth NMOS transistor Q6, the second terminal of the eighteenth resistor, and the first terminal of the fifteenth resistor R15; the gate of the fifth NMOS transistor Q5 is connected to the first terminal of the eighteenth resistor R18 and the drive signal of the fourth drive module; the gate of the sixth NMOS transistor Q6 is connected to the second terminal of the fifteenth resistor R15 and the drive signal of the fourth drive module; the drain of the sixth NMOS transistor Q6 is connected to the second AC output side AC2 and the drain of the eighth NMOS transistor Q8; the gate of the eighth NMOS transistor Q8 is connected to the drive signal of the fourth drive module and the first terminal of the seventeenth resistor R17; the source of the eighth NMOS transistor Q8 is connected to the second terminal of the seventeenth resistor R17, the first terminal of the sixteenth resistor R16, and the source of the seventh NMOS transistor Q7; the drain of the seventh NMOS transistor Q7 is connected to the second terminal of the first inductor; and the gate of the seventh NMOS transistor Q7 is connected to the second terminal of the sixteenth resistor R16 and the drive signal of the first drive module.

[0085] The second AC output side AC2 in the zero-crossing detection circuit 40 and the second AC output side AC2 in the dynamic reactance adjustment circuit 60 are connected.

[0086] Under normal operating conditions: the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the seventh NMOS transistor Q7, and the eighth NMOS transistor Q8 are all turned on, the equivalent value of the first inductor / second inductor in parallel is minimized, and the load is maintained to operate normally.

[0087] In the overcurrent state: turn off the seventh NMOS transistor Q7 and the eighth NMOS transistor Q8, and increase the equivalent inductance value to suppress the current rise; In the short-circuit state: the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the seventh NMOS transistor Q7, and the eighth NMOS transistor Q8 are turned off under the dual triggering of zero crossing and overcurrent, completely disconnecting the load circuit.

[0088] It should be noted that the first drive module, the fourth drive module, the first inductor, and the second inductor are not included in the dynamic reactance adjustment circuit 60, therefore Figure 7 There are no corresponding labels or connection methods in the text.

[0089] The dynamic reactance adjustment circuit 60 provided in this embodiment of the utility model is connected to the short-circuit AND gate control circuit 50 and the overcurrent comparison circuit 30. It can receive control signals, comparison result signals and overcurrent signals, and obtain the adjusted system reactance based on the control signals, comparison result signals and overcurrent signals. It realizes the adaptive adjustment of the circuit equivalent impedance, suppresses short-circuit inrush current in stages, and takes into account both system reliability and response speed.

[0090] Furthermore, for ease of understanding, Figure 8 An overall circuit diagram of a protection circuit 100 provided for an embodiment of the present utility model is shown, including the specific connections of all the components mentioned in the above embodiments.

[0091] Example 8 In practical applications, plasma devices can generate plasma arcs using radio frequency energy to cut tissue. Their core circuitry needs to combine high energy output with short-circuit protection. Existing output short-circuit protection technologies are mainly based on H-bridge inverter architectures and LC impedance matching networks, triggering protection actions through current thresholds. However, with increasing clinical demands for surgical efficiency and equipment reliability, existing technologies have revealed significant shortcomings in plasma arc excitation success rate, energy efficiency, and impedance adaptability. They fail to address the issues of misjudgment during plasma arc excitation and the problems of power device switching stress accumulation and impedance dynamic matching to suppress short-circuit current stress, directly impacting surgical efficiency and equipment reliability.

[0092] Specifically, the output protection circuits of current plasma equipment have three main technical problems: (1) Single or multi-level current detection mechanisms cannot distinguish between normal ignition current and metal contact short circuit current in the early stage of plasma arc formation, and false triggering of short circuit protection leads to low plasma excitation success rate (<90%).

[0093] (2) When the power devices MOS / IGBT of the H-bridge inverter are turned off by short-circuit protection, switching losses will occur, resulting in abnormal increase in junction temperature.

[0094] (3) The fixed LC matching network of the H-bridge inverter cannot adapt to the dynamic changes in impedance during the operation (10-1000Ω), resulting in excessive short-circuit current stress.

[0095] Therefore, this utility model embodiment also provides an output protection circuit for a plasma device. Figure 9 This is a structural diagram of an output protection circuit for a plasma device provided in an embodiment of the present invention.

[0096] like Figure 9 As shown, the output protection circuit of the plasma device includes: plasma device 200 and protection circuit 100 mentioned in the above embodiment.

[0097] The specific structure and effects of the protection circuit 100 have been described in detail in the above embodiments, and will not be repeated here.

[0098] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0099] Finally, it should be noted that the above-described embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model. These modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A protection circuit, characterized in that, The protection circuit includes: An isolated H-bridge high-frequency inverter circuit is connected to a short-circuit AND gate control circuit and receives an external DC input, which is used to convert the DC input into a high-frequency AC signal. A current sampling circuit is connected to the isolated H-bridge high-frequency inverter circuit and receives the high-frequency AC signal. It is used to couple the high-frequency AC signal and convert it into a DC signal through full-bridge rectification. The DC signal is then divided and filtered to obtain a smooth DC voltage signal. An overcurrent comparison circuit, connected to the current sampling circuit, is used to receive the smoothed DC voltage signal and compare it with a predetermined voltage threshold, and output a comparison result signal and an overcurrent signal. The zero-crossing detection circuit is connected to the isolated H-bridge high-frequency inverter circuit and receives the high-frequency AC signal. It is used to divide the high-frequency AC signal to generate a pulsating DC signal and convert the pulsating DC signal into a square wave zero-crossing signal. The short-circuit AND gate control circuit is used to receive the overcurrent signal and the square wave zero-crossing signal, and outputs a control signal to perform enable control when the overcurrent signal and the square wave zero-crossing signal are both valid. A dynamic reactance adjustment circuit, connected to the short-circuit AND gate control circuit and the overcurrent comparison circuit, is used to receive the control signal, the comparison result signal and the overcurrent signal, and to obtain the adjusted system reactance based on the control signal, the comparison result signal and the overcurrent signal.

2. The protection circuit according to claim 1, characterized in that, The isolated H-bridge high-frequency inverter circuit includes: a positive power supply terminal, a negative power supply terminal, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a high-frequency transformer, a first capacitor, a second capacitor, a first inductor, and a second inductor. The positive terminal of the power supply is connected to the drain of the first NMOS transistor, the first terminal of the first capacitor, and the drain of the third NMOS transistor; the gate of the first NMOS transistor is connected to the short-circuit AND gate control circuit and the first terminal of the fourth resistor; the source of the first NMOS transistor is connected to the second terminal of the fourth resistor, pin 2 of the high-frequency transformer, and the drain of the second NMOS transistor; the second terminal of the first capacitor is connected to the negative terminal of the power supply; the gate of the third NMOS transistor is connected to the first terminal of the first resistor and the short-circuit AND gate control circuit; the source of the third NMOS transistor is connected to the second terminal of the first resistor and the drain of the fourth NMOS transistor; the gate of the second NMOS transistor is connected to the first terminal of the second resistor and the first terminal of the fourth resistor. A short circuit is connected to the gate control circuit; the source of the second NMOS transistor is connected to the second terminal of the second resistor and the negative terminal of the power supply; the source of the fourth NMOS transistor is connected to pin 3 of the high-frequency transformer; the gate of the fourth NMOS transistor is connected to the first terminal of the third resistor; the drain of the fourth NMOS transistor is connected to the second terminal of the third resistor; the second terminal of the third resistor is connected to the negative terminal of the power supply; pin 1 of the high-frequency transformer is connected to the first terminal of the second capacitor; the second terminal of the second capacitor is connected to the first terminal of the first inductor and the first terminal of the second inductor; pin 4 of the high-frequency transformer is connected to the current sampling circuit; the second terminals of the first inductor and the second inductor are both connected to the dynamic reactance adjustment circuit.

3. The protection circuit according to claim 2, characterized in that, The current sampling circuit includes: a first diode, a second diode, a third diode, a fourth diode, a fifth resistor, a sixth resistor, a third capacitor, a current transformer, and a first AC output side; The output of pin 4 of the high-frequency transformer passes through the current transformer and is connected to the first AC output side. The first end of the secondary coil of the current transformer is connected to the negative terminal of the first diode and the positive terminal of the second diode. The second end of the secondary coil of the current transformer is connected to the positive terminal of the third diode and the negative terminal of the fourth diode. The positive terminal of the first diode is connected to the second end of the fifth resistor and the second end of the third capacitor. The second end of the fifth resistor and the second end of the third capacitor are both grounded. The negative terminal of the second diode is connected to the negative terminal of the third diode, the first end of the fifth resistor, and the first end of the sixth resistor. The positive terminal of the fourth diode is grounded. The second end of the sixth resistor is connected to the first end of the third capacitor and the overcurrent comparator circuit.

4. The protection circuit according to claim 3, characterized in that, The overcurrent comparator circuit includes: a seventh resistor, an eighth resistor, a ninth resistor, a fourth capacitor, a first driving module, and a first comparator; The non-inverting input of the first comparator is connected to the second terminal of the sixth resistor; the inverting input of the first comparator is connected to the first terminal of the fourth capacitor, the second terminal of the eighth resistor, and the first terminal of the ninth resistor; the second terminals of the fourth capacitor and the ninth resistor are both connected to the zero-crossing detection circuit; the output of the first comparator is connected to the first terminal of the seventh resistor, the enable pin of the first drive module, and the short-circuit AND gate control circuit; the second terminal of the seventh resistor is connected to the first terminal of the eighth resistor and the zero-crossing detection circuit; the drive signal of the first drive module is connected to the dynamic reactance adjustment circuit.

5. The protection circuit according to claim 4, characterized in that, The zero-crossing detection circuit includes: a second comparator, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifth diode, a sixth diode, a seventh diode, an eighth diode, a fifth capacitor, a first AC output side, and a second AC output side. The first AC output side is connected to the negative terminal of the fifth diode and the positive terminal of the sixth diode; the negative terminal of the sixth diode is connected to the negative terminal of the seventh diode and the first end of the tenth resistor; the positive terminal of the seventh diode is connected to the negative terminal of the eighth diode and the second AC output side; the positive terminal of the eighth diode is grounded; the positive terminal of the fifth diode and the second end of the eleventh resistor are both grounded; the first end of the eleventh resistor and the second end of the tenth resistor are both connected to the inverting input terminal of the second comparator; the first end of the fifth capacitor is connected to the second end of the fourth capacitor and the first end of the twelfth resistor and grounded; the second end of the fifth capacitor is connected to the first end of the thirteenth resistor and connected to +5V; the second end of the thirteenth resistor and the second end of the twelfth resistor are both connected to the non-inverting input terminal of the second comparator; the output terminal of the second comparator is connected to the first end of the fourteenth resistor and the short-circuit AND gate control circuit; the second end of the fourteenth resistor is connected to the second end of the seventh resistor.

6. The protection circuit according to claim 5, characterized in that, The short-circuit AND gate control circuit includes: a sixth capacitor, an AND gate chip, a second driving module, a third driving module, and a fourth driving module; Pin 1 of the AND gate chip is connected to the output of the first comparator; pin 2 of the AND gate chip is connected to the output of the second comparator; pin 3 of the AND gate chip is connected to the second terminal of the sixth capacitor and grounded; pin 5 of the AND gate chip is connected to the first terminal of the sixth capacitor and connected to +5V; pin 4 of the AND gate chip is connected to the enable pins of the second driving module, the third driving module, and the fourth driving module; the driving signal of the second driving module is connected to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor; the driving signal of the third driving module is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor; the driving signal of the fourth driving module is connected to the dynamic reactance adjustment circuit.

7. The protection circuit according to claim 6, characterized in that, The dynamic reactance adjustment circuit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a second AC output side, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and an eighteenth resistor; The drain of the fifth NMOS transistor is connected to the second terminal of the second inductor; the source of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor, the second terminal of the eighteenth resistor, and the first terminal of the fifteenth resistor; the gate of the fifth NMOS transistor is connected to the first terminal of the eighteenth resistor and the drive signal of the fourth drive module; the gate of the sixth NMOS transistor is connected to the second terminal of the fifteenth resistor and the drive signal of the fourth drive module; the drain of the sixth NMOS transistor is connected to the second AC output side and the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor is connected to the drive signal of the fourth drive module and the first terminal of the seventeenth resistor; the source of the eighth NMOS transistor is connected to the second terminal of the seventeenth resistor, the first terminal of the sixteenth resistor, and the source of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected to the second terminal of the first inductor; the gate of the seventh NMOS transistor is connected to the second terminal of the sixteenth resistor and the drive signal of the first drive module.

8. The protection circuit according to claim 7, characterized in that, The driving signals of the first driving module include: driving signal HG1 and driving signal LG1; driving signal HG1 is connected to the gate of the seventh NMOS transistor; driving signal LG1 is connected to the gate of the eighth NMOS transistor. The driving signals of the second driving module include: driving signal HG2 and driving signal LG2; driving signal HG2 is connected to the gate of the third NMOS transistor, and driving signal LG2 is connected to the gate of the fourth NMOS transistor. The driving signals of the third driving module include: driving signal HG3 and driving signal LG3; driving signal HG3 is connected to the gate of the first NMOS transistor, and driving signal LG3 is connected to the gate of the second NMOS transistor. The driving signals of the fourth driving module include: driving signal HG4 and driving signal LG4; driving signal HG4 is connected to the gate of the fifth NMOS transistor, and driving signal LG4 is connected to the gate of the sixth NMOS transistor.

9. The protection circuit according to claim 8, characterized in that, The full-bridge rectifier corresponds to the first diode, the second diode, the third diode, and the fourth diode.

10. An output protection circuit for a plasma device, characterized in that, include: The plasma device and the protection circuit according to any one of claims 1 to 9.

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