A grid-connected intelligent controller

Abstract

The utility model relates to a kind of grid-connected intelligent controller, it includes: shell, sampling input end is arranged on shell, for accessing grid voltage signal;Judgment unit, judgment unit is used to judge grid synchronization condition, and grid synchronization condition includes at least one in phase sequence, phase and frequency, and export corresponding judgment result;Logic control unit, logic control unit is connected with judgment unit, is configured to generate grid-connected permission signal when grid synchronization condition all satisfies, generates grid-connected prohibition signal when detecting that any grid synchronization condition does not satisfy;Isolation type switch output end, isolation type switch output end is connected with logic control unit, is configured to be turned on when receiving grid-connected permission signal, to provide isolated grid-connected permission switch quantity to external control loop.

Description

Technical Field

[0001] This utility model relates to the field of power equipment technology, and in particular to a grid-connected intelligent controller. Background Technology

[0002] With the rapid development of new energy power generation, distributed power sources, and microgrid technologies, a large number of power electronic devices need to be connected to the public power grid through grid-connected controllers. The basic function of the grid-connected controller is to detect and judge the grid status before the power source is connected to the grid, ensuring that parameters such as grid voltage, frequency, and phase meet the synchronization conditions, thereby avoiding impacts on the grid and power source equipment during the grid connection process.

[0003] Existing grid-connected controllers typically acquire grid signals through voltage sampling circuits and judge parameters such as grid voltage amplitude and frequency, issuing a grid connection permission signal when set conditions are met. However, these devices generally have the following shortcomings: First, they only detect voltage amplitude and frequency, without comprehensively judging grid phase sequence and phase difference, posing a risk of misjudgment; second, the voltage sampling stage has insufficient anti-interference capability, and surge impacts and electromagnetic interference can easily cause sampling signal distortion, affecting the accuracy of judgment; third, some control logics lack anti-jitter delay mechanisms, leading to frequent grid connection and disconnection when grid conditions fluctuate, reducing system stability; fourth, some devices lack fail-safe design in the event of power failure or internal faults, and may still maintain grid connection, posing a safety hazard.

[0004] Therefore, there is an urgent need for an improved grid-connected intelligent controller that can effectively overcome the problems of incomplete judgment of grid synchronization conditions, susceptibility to interference in the sampling process, frequent grid-connected control jitter, and insufficient safety in device failure in the existing technology, so as to fundamentally improve the reliability and safety of the grid connection process. Utility Model Content

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, one objective of this invention is to provide a grid-connected intelligent controller in one possible embodiment, comprising: a housing with a sampling input terminal for receiving a grid voltage signal; a judgment unit for judging grid synchronization conditions, the grid synchronization conditions including at least one of phase sequence, phase, and frequency, and outputting a corresponding judgment result; a logic control unit connected to the judgment unit, configured to generate a grid-connected permission signal when all grid synchronization conditions are met, and to generate a grid-connected prohibition signal when any grid synchronization condition is detected as not met; and an isolated switch output terminal connected to the logic control unit, configured to be turned on when receiving the grid-connected permission signal to provide an isolated grid-connected permission switching quantity to an external control loop.

[0006] In one possible implementation, the sampling input terminals are three-phase voltage input terminals L1, L2, and L3, and a voltage sampling circuit is provided inside. The voltage sampling circuit is a resistor voltage divider circuit used to convert the three-phase grid voltage into a sampling signal suitable for detection.

[0007] In one possible implementation, a surge suppression device and an electromagnetic interference filter are connected in series between the sampling input terminal and the voltage sampling circuit.

[0008] In one possible implementation, the judgment unit includes a phase sequence judgment module, which detects the phase sequence of the power grid based on the voltage sampling signal and outputs a phase sequence satisfaction signal when the detected phase sequence is positive.

[0009] In one possible implementation, the judgment unit includes a phase judgment module, which obtains phase information based on a zero-crossing detection circuit and outputs a phase satisfaction signal when the phase difference is within a preset tolerance band, wherein the preset tolerance band is ±10°.

[0010] In one possible implementation, the judgment unit includes a frequency judgment module, which calculates the power grid frequency based on the zero crossover time interval and outputs a frequency satisfaction signal when the power grid frequency is in the range of 49.8Hz to 50.2Hz.

[0011] In one possible implementation, a threshold setting unit is also included for locally adjustable setting of the phase tolerance.

[0012] In one possible implementation, the logic control unit includes a timing circuit, which is configured to output a grid connection permission signal after a delay of 0.5 seconds upon receiving all judgment results indicating that the grid synchronization conditions are met, and to output a grid connection prohibition signal after a delay of 1 second upon detecting that any grid synchronization condition is not met.

[0013] In one possible implementation, the output terminal of the isolation switch is a normally open dry contact output of a relay, including a common terminal (COM) and a normally open terminal (NO), where COM represents the common terminal and NO represents the normally open terminal.

[0014] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Based on the above technical solution, the grid-connected intelligent controller provided by this utility model constructs an intelligent closed-loop system for grid-connected control by setting up a sampling input terminal, a judgment unit, a logic control unit, and an isolated switch output terminal. After the grid voltage signal is connected to the sampling input terminal, the judgment unit performs real-time analysis and judgment on synchronization conditions such as phase sequence, phase, and frequency. When all synchronization conditions are met, the logic control unit generates a grid-connection permission signal; conversely, if any synchronization condition is not met, a grid-connection prohibition signal is generated. The isolated switch output terminal receives the control signal from the logic control unit, realizing isolated switching output to the external control loop. This structure realizes automatic judgment and control output of grid-connection conditions, improving the safety and reliability of grid-connected operation, and is especially suitable for occasions with high requirements for grid stability, effectively avoiding equipment failures or grid disturbances caused by abnormal grid-connection conditions. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the structure of the grid-connected intelligent controller provided in the embodiment of this utility model; Figure 2 for Figure 1 A schematic diagram of the internal structure of the device shown.

[0017] Explanation of reference numerals in the attached figures: 1. Housing; 2. Sampling input terminal; 3. Judgment unit; 4. Logic control unit; 5. Isolated switch output terminal; 6. Voltage sampling circuit; 7. Surge suppression device; 8. Electromagnetic interference filter; 9. Phase sequence judgment module; 10. Phase judgment module; 11. Frequency judgment module; 12. Threshold setting unit. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0019] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0021] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0022] Figure 1 A schematic diagram of the structure of the grid-connected intelligent controller provided in the embodiment of this utility model; Figure 2 for Figure 1 A schematic diagram of the internal structure of the device shown.

[0023] Please see Figure 1 , Figure 2In one possible implementation, the grid-connected intelligent controller includes a housing 1, on which a sampling input terminal 2 is provided for receiving the grid voltage signal; a judgment unit 3 is provided for judging grid synchronization conditions, the grid synchronization conditions including at least one of phase sequence, phase and frequency, and outputting the corresponding judgment result; a logic control unit 4 is connected to the judgment unit 3 and is configured to generate a grid-connected permission signal when all grid synchronization conditions are met, and to generate a grid-connected prohibition signal when any grid synchronization condition is detected to be unmet; an isolated switch output terminal 5 is connected to the logic control unit 4 and is turned on when receiving the grid-connected permission signal to provide an isolated grid-connected permission switching quantity to the external control loop.

[0024] Specifically, sampling input 2 continuously acquires the grid voltage signal and sends it to judgment unit 3; judgment unit 3 performs phase sequence discrimination, phase comparison, and frequency detection based on mature industry solutions (one or more of these can be enabled as needed), forming Boolean criteria and outputting them to logic control unit 4; logic control unit 4 executes AND logic on the enabled criteria, and outputs a grid connection enable signal to drive the isolated switch output 5 to conduct when all criteria are met, or when sampling abnormalities or invalid criteria occur, it outputs a grid connection prohibition signal and keeps the circuit disconnected, achieving fail-safe operation. Through the "measurement-criteria-logic-isolation output" link, a safe drive is provided for the external control loop; the isolated switch output 5 can be directly connected in series with existing grid connection protection and interlocking loops without modifying the original control strategy, thereby reducing the amount of on-site customization work and ensuring project reliability.

[0025] Among them, the judgment unit 3 can enable only phase and frequency judgment, or omit phase sequence judgment in scenarios with clear phase sequence guarantee; the logic control unit 4 can be implemented by hardware logic, microcontroller or programmable logic device, and the summary strategy and fault response can be configured by software / firmware; the isolated switch output terminal 5 can be a relay, solid-state relay or optocoupler driven switch interface to adapt to different voltage, current and life requirements; the sampling input terminal 2 can be adapted to single-phase or three-phase access, and the range and protection measures can be configured according to the field conditions to improve applicability and versatility.

[0026] Please see Figure 1 , Figure 2In one possible implementation, sampling input terminal 2 is configured as three-phase voltage input terminals L1, L2, and L3, and a voltage sampling circuit 6 with resistor divider is configured for each phase inside the housing 1: high resistance R1 and low resistance R2 are connected in series, L1 / L2 / L3 are respectively connected to the upper end of their respective R1, and the lower end of R2 is connected to the sampling reference ground, with a voltage division ratio k = R2 / (R1+R2). The three-phase low-voltage sampling signal after voltage division is output to the judgment unit 3 as the input for phase sequence, phase, and frequency criteria. R1 and R2 are selected to meet the withstand voltage and power rating requirements of the rated grid maximum voltage and overvoltage category, and the voltage division ratio is configured according to the target sampling range so that the sampling signal amplitude is adapted to the range of the subsequent ADC / comparator.

[0027] This implementation utilizes resistor voltage divider sampling technology to linearly attenuate the high voltage of the three-phase power grid into a low-level signal, maintaining the linearity and consistency of the amplitude-frequency characteristics within the power frequency range. This allows the judgment unit 3 to directly perform phase sequence discrimination, phase comparison, and frequency detection without additional compensation. By selecting resistors with higher matching accuracy for the three-phase channels, measurement deviations caused by amplitude and phase inconsistencies between channels can be reduced. By rationally determining the sum of the resistance values ​​of R1 and R2, the input equivalent impedance is increased, reducing the impact on the primary side circuit while controlling heat dissipation within a safe range. This structure is simple, low-cost, and highly reliable, and it is easy to coordinate with the aforementioned logic control and isolation output links, directly serving the determination of grid connection permission / prohibition and external output.

[0028] It is worth noting that equivalent transformations can be made according to different power grid levels and subsequent measurement ranges: R1 can be composed of multiple high-voltage resistors connected in series to meet the requirements of withstand voltage and creepage distance; R2 can be selected with low-temperature drift and tight tolerance components to improve measurement consistency; the three-phase voltage divider network can use resistor arrays from the same batch to optimize matching; the voltage division ratio k can be calibrated by replacing R1 and R2 or by setting the proportional coefficient in the subsequent software; the sampling reference ground can be shared with the controller's analog ground or connected through a single point to balance anti-interference and measurement stability.

[0029] Please see Figure 1 , Figure 2 In one possible implementation, surge suppression devices 7 and electromagnetic interference filters 8 are sequentially arranged between the three-phase input terminals L1, L2, and L3 and the resistor divider sampling circuit. L1, L2, and L3 first enter the surge suppression stage, then the EMI filtering stage, and finally connect to the voltage divider resistor network of each phase. The surge suppression stage can use a metal oxide varistor connected in parallel to the phase-to-ground path of PE, and / or form a delta network between phases; when higher withstand capability is required, a gas discharge tube can be connected in parallel or a combined SPD can be used. The EMI filtering stage uses a common-mode inductor in conjunction with differential-mode suppression components: X capacitors are connected between phases, Y capacitors are connected to PE, and the filter assembly is fixed as a whole and ensures a low-impedance connection at the ground terminal.

[0030] Specifically, in the event of a lightning strike or operational overvoltage, the surge suppression stage clamps and shunts the energy, limiting the port clamping voltage and protecting the subsequent voltage divider resistors and the judgment / logic unit. In the interference frequency band from 150 kHz to tens of MHz, the EMI filtering stage provides a high-impedance / low-pass path for common-mode and differential-mode noise, ensuring that the power frequency components entering the voltage divider and criterion link maintain essentially unchanged amplitude and phase, thus not affecting the accuracy of phase sequence, phase, and frequency determination. Filter component selection and parameter settings ensure that the insertion phase error at 50 / 60 Hz is negligible and meet the requirements for creepage distance, clearance distance, and grounding reliability, functionally decoupling the front-end protection / filtering from subsequent detection.

[0031] It is worth noting that surge suppression can be achieved using single devices or combinations of varistors, TVS diodes, and gas discharge tubes, with the current carrying capacity and continuous operating voltage selected according to the power grid level and the expected surge level. EMI filtering can employ a two-stage π-type or single-stage LC structure, with X / Y capacitors selected as safety-compliant devices and the configuration of the Y capacitor determined by the availability of a PE (protective earth). To enhance high-energy surge resistance, a fuse / thermometer can be connected in series before the surge stage as an energy matching device. In a three-phase system, the X capacitor can be placed in L1-L2, L2-L3, and L3-L1, while the Y capacitors are symmetrically arranged with respect to ground to balance leakage current. When there is no PE or strict limitations on leakage current, the Y capacitor can be reduced or eliminated, and suppression can be achieved through common-mode inductors and differential-mode RC circuits.

[0032] Please see Figure 2 In one possible implementation, the judgment unit 3 is equipped with a phase sequence judgment module 9, and the three-phase voltage sampling signals are respectively sent to channels A, B, and C of this module. The module adopts a commonly used phase sequence detection scheme in engineering: it identifies the zero-crossing / zero-crossing direction of the three-phase samples and records the order, or it calls the software library of the MCU / DSP to directly determine the phase sequence based on the phase sequence relationship within an integer cycle; when the detection result is consistent with the ABC positive phase sequence, it outputs a phase sequence satisfaction signal seq_ok=1 at the module output terminal; otherwise, it outputs seq_ok=0. The module output is a digital signal (such as 3.3V or 5V) compatible with the logic control unit 4 level, and reserves an abnormal state as a default 0 to meet fail-safe conditions.

[0033] This module works in conjunction with the front-end's anti-interference and amplitude limiting measures within the sampling frequency band. It sets a judgment window and a jitter counter to suppress misjudgments caused by noise, transient drops, or short-term phase imbalances. For example, it requires consistent judgments for N consecutive grid cycles (e.g., N=2~5) before updating seq_ok. When any phase sampling is missing, the amplitude is below the effective threshold, or the frequency exceeds the limit, the module immediately outputs seq_ok=0 and reports an alarm status bit to the logic control unit 4. To ensure compatibility with 50 / 60 Hz systems, the detection period and threshold are configured via a parameter table. In cases of reverse phase sequence or uncertain phase sequence, the logic control unit 4 maintains grid connection prohibition accordingly.

[0034] It is worth noting that the phase sequence detection can be hardware-based (phase comparison + direction discrimination circuit) or software-based (zero-crossing timestamp / phase measurement, space vector / Clarke transform direction discrimination, positive sequence PLL direction determination); the threshold and debouncing cycle can be configured locally or via communication; in cases where the upstream equipment has already ensured the correct phase sequence at the access site, the module can be bypassed but the monitoring and alarm functions can be retained; in particular, to adapt to different voltage levels and noise environments, the input range and front-end filtering parameters can be adjusted to maintain the stability of the judgment without changing the output interface and decision logic.

[0035] Please see Figure 2 In one possible implementation, the judgment unit 3 includes a phase judgment module 10. The module acquires grid phase information based on zero-crossing detection and compares it with a reference phase. When the phase difference is within a preset tolerance band, it outputs a phase satisfaction signal. The tolerance band is fixed at ±10°. When satisfied, it outputs phase_ok = 1; when not satisfied or abnormal, it outputs 0. The module is fail-safe by default: it outputs 0 during power-on self-test, when the reference is missing, or when the measurement is invalid.

[0036] Specifically, the grid voltage sampling signal and the reference phase signal, after being limited and bandwidth-constrained, enter a Schmitt comparator with hysteresis, outputting a shaped zero-crossing pulse. A hardware timer adds a timestamp to the zero-crossing signals of the same name to obtain Δt, and calculates the phase difference according to Δθ = 2πf·Δt, where f is the effective measured value of the current fundamental frequency (provided by this module or other functional units within the system). To suppress noise and jitter, the comparator threshold is set proportionally to the rated amplitude. The pulse enters the de-jittering and consistency counting process, and phase_ok is updated from 0 to 1 only when |Δθ|≤10° for N consecutive cycles (e.g., N=3~5). Once pulse loss, amplitude below the effective threshold, frequency out of bounds, or timestamp anomaly occurs, it immediately falls back to 0 and the alarm flag is set. Considering engineering resolution requirements, the timer can be configured to the order of 1 μs; the next cycle at 50 Hz is 20 ms, corresponding to a ±10° time window of approximately ±0.5556 ms. This resolution can control the quantization error within the thousandths of the tolerance band. To avoid upstream and downstream glitches, the module and logic control unit 4 agree on a minimum hold time: the transition from 0 to 1 must satisfy continuous cycle consistency, and the exit condition is to immediately set it to 0 and hold it for at least 1 cycle.

[0037] It is worth noting that the phase error can be directly output using a Synchronous Reference Coordinate System Phase-Locked Loop (SRF-PLL) and compared with a ±10° threshold; the instantaneous phase can be calculated using Clarke / Park transform combined with atan2 and then categorized after median / low-pass filtering; or jitter-free timestamp acquisition can be completed using MCU / DSP input capture + DMA. All of the above schemes adhere to the conventions of default failure prohibition, 4-level compatibility with the logic control unit, and support for parameterized thresholds and consistency counting, thus ensuring compatibility with grid-connected allowed / prohibited link stability.

[0038] Please see Figure 2 In one possible implementation, the judgment unit 3 includes a frequency judgment module 11. The module calculates the grid frequency based on the zero-crossing time interval and outputs a frequency that satisfies the signal freq_ok = 1 when the measured grid frequency is within the range of 49.8 Hz to 50.2 Hz. If the frequency exceeds this range or an abnormality is detected, the module outputs 0. The module output is a digital quantity compatible with the logic control unit 4 level and is fail-safe by default: it outputs 0 in case of power-on self-test, invalid input, or missing reference.

[0039] Specifically, the grid voltage sampling signal, after being limited and bandwidth-constrained, enters a zero-crossing comparator with hysteresis, outputting a shaped zero-crossing pulse. A hardware timer timestamps adjacent zero-crossings in the same direction, obtaining single-cycle periods T1, T2, etc. To suppress jitter and harmonic effects, a sliding window is used to average M consecutive periods (e.g., M = 5–10), calculating f = M / ∑Ti. freq_ok is set from 0 to 1 only when N consecutive update periods (e.g., N = 2–3) all satisfy 49.8 Hz ≤ f ≤ 50.2 Hz; if zero-crossing is lost, period times out, comparator saturation occurs, or frequency exceeds the limit, it is immediately set to 0 and an alarm flag is set. The timer resolution can be configured to the order of 1 μs; taking 50 Hz as an example, T ≈ 20 ms, the contribution of resolution error to frequency calculation is far less than the ±0.2 Hz criterion bandwidth. To avoid output jitter, the module sets a minimum hold time for freq_ok (e.g., ≥1 cycle). The exit condition takes effect immediately and is held for at least 1 cycle, which facilitates coordination with the relay's pull-in / release time and upstream interlocking.

[0040] It is worth noting that the number of zero-crossing pulses can be accumulated and the frequency converted within a fixed gate time using a hardware frequency counting method; the fundamental frequency can be estimated using a digital phase-locked loop (PLL / SRF-PLL) and compared with a threshold; jitter-free timestamp acquisition can be achieved on the MCU / DSP through input capture + DMA; and the interface logic can be changed when switching the reference in a 60 Hz power grid without altering the 49.8–50.2 Hz criterion (applicable to 50 Hz systems). To ensure long-term stability, the time reference can be calibrated with a standard source at the factory and the correction coefficients can be stored; during operation, the validity of the input amplitude and the quality of zero crossovers can be monitored, and freq_ok = 0 can be maintained and a fault code can be reported when an anomaly occurs. All the above modifications keep the interface and decision path unchanged, ensuring stable cooperation with grid-connected allowed / disallowed links.

[0041] Please see Figure 2 In one possible implementation, the judgment unit 3 is supplemented with a threshold setting unit 12 for locally adjustable setting of the phase tolerance. The threshold setting unit 12 is connected to the data interface of the phase judgment module 10. The factory default tolerance is ±10°, and it supports setting in 0.5° steps within the range of ±2° to ±20°. Parameter changes only take effect in the off-grid state. After taking effect, the phase judgment module 10 writes the new tolerance band into the operating parameter area and outputs phase_ok accordingly. To ensure intuitive operation and field versatility, the panel provides buttons / knobs and a small-size display screen (such as OLED / segment display) to display the current tolerance value and status prompts. Parameter storage uses non-volatile memory with CRC check and power-off protection. After setting, a readback comparison ensures consistency.

[0042] Specifically, the threshold setting unit 12 comprises three parts: a human-machine interface, power supply and isolation, and storage and security. The human-machine interface supports two local input modes: one is an incremental encoder knob + confirmation button, where rotation changes the setting, a short press confirms, and a long press cancels; the other is up / down adjustment buttons + confirmation / return button. Both modes change in minimum steps of 0.5°, with limits to ±2° or ±20° when exceeding the limit. To avoid accidental operation, a dual confirmation mechanism (e.g., "confirm → confirm again") is provided, and a four-digit maintenance password or physical key switch can be optionally enabled. When the key is in the "locked" position, changes are prohibited and "LOCK" is displayed. During the setting process, the threshold setting unit 12 requests a "configuration window" from the logic control unit 4. The logic control unit 4 returns permission when it detects that the current state is grid connection prohibited or de-connected, preventing modification of the threshold at the moment grid connection is allowed; if the state is grid connection allowed, the user is prompted to de-connect first. In terms of storage and security, a pre-write backup and power failure recovery strategy is adopted: new parameters are first written to the temporary storage area and verified before overwriting the main area. If the write fails, the parameters are rolled back to the last valid parameter. At the same time, the timestamp and event code are recorded for traceability.

[0043] Please see Figure 2 In one possible implementation, the logic control unit 4 is equipped with a timing circuit to initiate an allowable delay timer T_on = 0.5 s after receiving a criterion that all grid synchronization conditions are "fully satisfied". When T_on timer ends and the criterion remains "fully satisfied" throughout the period, a grid connection allow signal is output. During operation, if any synchronization condition is detected as "not satisfied", an prohibition delay timer T_off = 1.0 s is immediately initiated. If the criterion has recovered to "fully satisfied" before T_off timer ends, the prohibition action is canceled and the process returns to the allowable judgment flow. If T_off reaches 1.0 s and is still "not satisfied", a grid connection prohibition signal is output and the prohibition state is maintained until the allowable logic is satisfied again. Grid connection is prohibited by default after the system is powered on or reset, and is only allowed after a continuous 0.5 s satisfaction judgment is completed.

[0044] Specifically, to avoid malfunctions caused by jitter and glitches, the logic control unit 4 is implemented using a finite state machine, containing four operating states: S0 (disable), S1 (allow wait, timer 0.5 s), S2 (allow), and S3 (disable wait, timer 1.0 s). In state S0, upon receiving a rising edge indicating "all conditions met," it transitions to S1 and starts T_on. If any condition changes to "not met" during S1, it immediately returns to S0 and clears T_on. After S1 has counted for 0.5 s, it transitions to S2 and sets the enabled output to be valid. In state S2, if any condition changes to "not met," it transitions to S3 and starts T_off. If the conditions return to "all conditions met" during S3, it immediately returns to S2 and clears T_off. After S3 has counted for 1.0 s, it transitions to S0 and sets the enabled output to be invalid. To match the relay's pull-in / release characteristics, the minimum hold time for the enabled output is set to be no less than one power frequency cycle. Simultaneously, the timestamp and trigger reason for each state transition are recorded for event tracing. The timing circuit can be implemented by a high-precision timer inside the microcontroller. The time reference is provided by a crystal oscillator, and the combined error of 0.5 s and 1.0 s is guaranteed to be no more than ±5% after factory calibration. When an abnormal time reference, power supply drop, or invalid upstream criterion is detected, the state machine is forced to return to S0 and remain disabled.

[0045] Please see Figure 1 In one possible implementation, the output terminal 5 of the isolated switch adopts a normally open dry contact form of a relay, providing two terminals: a common terminal COM and a normally open terminal NO. The relay coil is driven by the enable signal of the logic control unit 4. The drive stage adopts an optocoupler + NPN / NMOS low-side switch structure with a parallel reverse freewheeling diode. The rated voltage of the coil can be 24VDC (or 12VDC depending on the model), and the coil power consumption is no more than 1W. The contact material is AgSnO2 or an equivalent long-life material, with a rated contact capacity such as 250 VAC / 3 A or 30 VDC / 3 A (depending on the model). The terminals are screw or pluggable terminal blocks and marked "COM / NO". Sufficient creepage / electrical clearance is maintained between the relay and the low-voltage control circuit. The wiring on the contact side and the measurement and control side are arranged separately to ensure that the output is a "voltage-passive" dry contact, and the external circuit is self-powered.

[0046] Specifically, after the grid connection allow signal is maintained for 0.5 seconds (see timing strategy), the drive coil is energized, closing NO-COM and providing a closing signal to the external protection / interlocking circuit. If any synchronization condition is not met for 1.0 seconds consecutively, the drive is revoked, the coil is released, NO-COM is disconnected, and the external circuit returns to an open circuit. Output default fail-safe: the coil is not energized during power-on, self-test, fault, or when the allowable condition is not met, and the contacts remain open. To accommodate inductive loads or long cable applications, RC resistors / capacitors can be connected in parallel on the contact side to reduce arcing and electromagnetic interference; diodes or RC+TVS are configured on the drive side to suppress coil reverse induction, and on-board synchronization indicator LEDs display the contact status. To improve engineering adaptability, the contact bounce time and release time are determined by the relay body characteristics (e.g., 5-15 ms for each of engagement and release). The logic layer avoids glitches to external links through minimum holding time and debouncing strategies, and the interface is clearly marked as "dry contact, no power supply provided."

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0048] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A grid-connected intelligent controller, characterized in that, include The housing is provided with a sampling input terminal for connecting to the power grid voltage signal; The judgment unit is used to judge the power grid synchronization conditions, which include at least one of phase sequence, phase and frequency, and output the corresponding judgment result. A logic control unit, connected to the judgment unit, is configured to generate a grid connection permission signal when all grid synchronization conditions are met, and to generate a grid connection prohibition signal when any grid synchronization condition is not met. An isolated switch output terminal, which is connected to the logic control unit, is configured to turn on when a grid connection permission signal is received, so as to provide an isolated grid connection permission switching quantity to the external control loop.

2. The grid-connected intelligent controller according to claim 1, characterized in that, The sampling input terminals are three-phase voltage input terminals L1, L2, and L3, and a voltage sampling circuit is set inside. The voltage sampling circuit is a resistor voltage divider circuit, which is used to convert the three-phase grid voltage into a sampling signal suitable for detection.

3. The grid-connected intelligent controller according to claim 2, characterized in that, A surge suppression device and an electromagnetic interference filter are connected in series between the sampling input terminal and the voltage sampling circuit.

4. The grid-connected intelligent controller according to claim 1, characterized in that, The judgment unit includes a phase sequence judgment module, which detects the phase sequence of the power grid based on the voltage sampling signal and outputs a phase sequence satisfaction signal when the detected phase sequence is positive.

5. The grid-connected intelligent controller according to claim 1, characterized in that, The judgment unit includes a phase judgment module, which obtains phase information based on a zero-crossing detection circuit and outputs a phase satisfaction signal when the phase difference is within a preset tolerance band, wherein the preset tolerance band is ±10°.

6. The grid-connected intelligent controller according to claim 1, characterized in that, The judgment unit includes a frequency judgment module, which calculates the power grid frequency based on the zero crossover time interval and outputs a frequency satisfaction signal when the power grid frequency is in the range of 49.8Hz to 50.2Hz.

7. The grid-connected intelligent controller according to claim 5, characterized in that, It also includes a threshold setting unit for locally adjustable setting of the phase tolerance.

8. The grid-connected intelligent controller according to claim 1, characterized in that, The logic control unit includes a timing circuit, which is used to output a grid connection permission signal after a delay of 0.5 seconds after receiving all the judgment results of the grid synchronization conditions being met, and to output a grid connection prohibition signal after a delay of 1 second after detecting that any grid synchronization condition is not met.

9. The grid-connected intelligent controller according to claim 1, characterized in that, The output terminal of the isolation switch is a normally open dry contact output of a relay, including a common terminal (COM) and a normally open terminal (NO), where COM represents the common terminal and NO represents the normally open terminal.

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