Semiconductor package structure and electronic device

Abstract

The present disclosure relates to a semiconductor packaging structure and an electronic device, the semiconductor packaging structure comprising a substrate, a chip, a blocking structure and a heat-conducting structure, wherein a heat dissipation cover of the blocking structure is connected to the chip through a second structure layer, so that the heat dissipation cover, the second structure layer and the chip enclose a cooling cavity for accommodating a cooling medium; the heat-conducting structure comprises a plurality of heat-conducting protrusions arranged at intervals, the heat-conducting protrusions are arranged in the cooling cavity and are heat-conducting connected to the chip, and the gap between two adjacent heat-conducting protrusions forms a first heat exchange flow channel communicated with the cooling cavity. Through the above technical solution, the semiconductor packaging structure provided by the present disclosure can transfer the heat generated at the chip to the heat-conducting structure, and directly act on the heat-conducting structure through the cooling medium in the cooling cavity, so as to realize heat removal, thereby achieving the purpose of cooling the chip, helping to improve the performance and reliability of the chip, and having the advantages of simple overall structure and easy processing and preparation.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and an electronic device. Background Technology

[0002] In related technologies, in order to meet the application needs of complex chip scenarios and improve user experience, the demand for high-performance chips is becoming increasingly widespread. However, with the increase in the computing power and memory bandwidth requirements of chips, the power consumption of chips is also rising sharply. Therefore, chip heat dissipation has become a key factor restricting performance release and ensuring reliability. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor packaging structure and electronic device that can improve the heat dissipation of the chip, help improve chip performance and reliability, and has the advantages of simple overall structure and easy processing and fabrication.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a semiconductor packaging structure, comprising: substrate; The chip is disposed on the substrate; A sealing structure includes a heat sink and a second structural layer. The heat sink is connected to the chip via the second structural layer, such that the heat sink, the second structural layer, and the chip together form a cooling cavity for containing a cooling medium. The heat sink has an inlet and an outlet communicating with the cooling cavity. The thermally conductive structure includes a plurality of thermally conductive protrusions arranged at intervals. The thermally conductive protrusions are disposed in the cooling cavity and are thermally connected to the chip. The gap between two adjacent thermally conductive protrusions forms a first heat exchange channel communicating with the cooling cavity.

[0005] In some possible implementations, the thermally conductive bump is connected to the top wall of the chip away from the substrate and extends toward the side away from the top wall. Wherein, the end of the thermally conductive protrusion facing away from the top wall of the chip has a gap with the inner wall of the sealing structure; and / or, The heat-conducting protrusion has a notch.

[0006] In some possible implementations, the plurality of the thermally conductive protrusions are arranged in a row along a first direction, and / or arranged in a column along a second direction perpendicular to the first direction.

[0007] In some possible implementations, the structural dimensions of each of the thermally conductive protrusions along the first direction are 10 μm-20 μm; and / or, The structural dimensions of each of the aforementioned thermally conductive protrusions along the second direction are 10mm-30mm; and / or, The structural dimensions of each of the thermally conductive protrusions along a third direction perpendicular to the plane containing the first and second directions are 100μm-200μm.

[0008] In some possible implementations, the thermally conductive protrusion is constructed in a cylindrical or rectangular shape.

[0009] In some possible implementations, the thermally conductive protrusion is made of copper.

[0010] In some possible implementations, a first structural layer is provided on the top wall of the chip facing the thermally conductive structure, and the thermally conductive structure is connected to the chip through the first structural layer.

[0011] In some possible implementations, the first structural layer is made of titanium or a titanium alloy.

[0012] In some possible implementations, the second structural layer is disposed between the heat sink and the chip, and the second structural layer is arranged in a ring around the outer periphery of the chip. The heat sink is provided with an inlet channel and an outlet channel. The inlet is connected to the cooling cavity through the inlet channel, and the outlet is connected to the cooling cavity through the outlet channel.

[0013] In some possible implementations, the second structural layer is formed of sealant.

[0014] In some possible implementations, the sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

[0015] In some possible implementations, the heat sink includes a manifold and a cover plate stacked in a third direction. The cover plate is connected to the chip through the second structural layer, and the cover plate is provided with a first fluid channel and a second fluid channel. The manifold is provided with an inlet, an outlet, a third fluid channel, and a fourth fluid channel. The first fluid channel and the third fluid channel are connected to form the liquid inlet channel, and the second fluid channel and the fourth fluid channel are connected to form the liquid outlet channel.

[0016] In some possible implementations, the sealing structure further includes a connecting structure through which the manifold plate and the cover plate are connected.

[0017] In some possible implementations, the connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

[0018] In some possible implementations, the substrate is provided with an annular protrusion arranged around the chip, and a second adhesive layer is provided between the sealing structure and the annular protrusion, the sealing structure being connected to the annular protrusion through the second adhesive layer.

[0019] In some possible implementations, the number of chips is one or more, and each chip is selected from either memory chips or logic chips.

[0020] In some possible implementations, the semiconductor package structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

[0021] A second aspect of this disclosure provides an electronic device including the semiconductor package structure provided in the first aspect above.

[0022] Through the aforementioned technical solution, namely the semiconductor packaging structure provided in this disclosure, the heat sink is connected to the chip via a second structural layer, so that the heat sink, the second structural layer, and the chip together form a cooling cavity for accommodating the cooling medium. Simultaneously, multiple thermally conductive protrusions of the thermally conductive structure are disposed within the cooling cavity and thermally connected to the chip. This arrangement allows heat generated at the chip to be transferred to the thermally conductive structure, and then directly acted upon by the cooling medium within the cooling cavity, thus removing the heat and achieving the purpose of cooling the chip, which helps improve chip performance and reliability. Furthermore, since the cooling medium within the cooling cavity can directly act on the thermally conductive structure, that is, after flowing through the cooling cavity, the cooling medium can directly exchange heat with the thermally conductive structure located within the cooling cavity, effectively shortening the heat transfer path and improving the heat dissipation effect of the cooling medium on the chip. Furthermore, since cooling the chip can be achieved simply by adding a thermally conductive structure to it, without requiring design modifications or precision machining of the chip itself, the overall design complexity of the chip is reduced, the fabrication process is simpler, and production efficiency and manufacturing costs are improved. Therefore, the semiconductor packaging structure provided in this disclosure can improve the heat dissipation effect of the chip, which helps to improve chip performance and reliability, and has the advantages of simple overall structure and easy fabrication.

[0023] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 Cross-sectional view at position AA; Figure 3 yes Figure 1 A magnified view of a portion of position B in the middle section; Figure 4 This is a schematic diagram of the packaging structure provided in related technologies.

[0025] Explanation of reference numerals in the attached figures 1-Substrate; 2-Chip; 210-Memory chip; 220-Logic chip; 3-Sealing structure; 310-Inlet; 320-Outlet; 330-Heat sink; 331-Manifold plate; 3311-Third fluid channel; 3312-Fourth fluid channel; 332-Cover plate; 3321-First fluid channel; 3322-Second fluid channel; 340-Second structural layer; 350-Connecting structure; 351-First adhesive layer; 352-First channel; 353-Second channel; 354-Connecting bolt; 4-Cooling cavity; 5-Heat-conducting structure; 510-Heat-conducting protrusion; 6-First heat exchange channel; 7-Notch; 8-First structural layer; 9-Annular protrusion; 10-Second adhesive layer; 11-Intermediate layer; 12-Heat-conducting layer; 13-Liquid cooling plate; 14-Bottom filler adhesive; 15-Gap. Detailed Implementation

[0026] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0027] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to upper and lower within the space of the semiconductor package structure when it is in use. "Inner" and "outer" refer to inner and outer relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0028] In related technologies, refer to Figure 4As shown, chip 2 is thermally connected to liquid cooling plate 13 through thermal conductive layer 12, so that chip 2 can be indirectly cooled by the cooling medium in liquid cooling plate 13. However, in this configuration, the heat generated at chip 2 will be transferred to the cooling medium in liquid cooling plate 13 through, for example, the thermal interface material (TIM) at thermal conductive layer 12 and the plate body of liquid cooling plate 13. Thus, since multiple heat transfer paths are required to cool chip 2, the thermal interface resistance at thermal interface material and other interfaces (such as the plate body of liquid cooling plate 13) is significantly increased, resulting in poor heat dissipation effect of chip 2, affecting the performance release and reliability of chip 2, and is not conducive to chip 2 meeting the application requirements of complex scenarios.

[0029] Based on this, according to the first aspect of this disclosure, a semiconductor packaging structure is provided, with reference to... Figures 1 to 3 As shown, the semiconductor packaging structure includes a substrate 1, a chip 2, a sealing structure 3, and a thermally conductive structure 5. The chip 2 is disposed on the substrate 1. The sealing structure 3 includes a heat dissipation cap 330 and a second structural layer 340. The heat dissipation cap 330 is connected to the chip 2 through the second structural layer 340, so that the heat dissipation cap 330, the second structural layer 340, and the chip 2 together form a cooling cavity 4 for containing a cooling medium. The heat dissipation cap 330 has an inlet 310 and an outlet 320 communicating with the cooling cavity 4. The thermally conductive structure 5 includes a plurality of thermally conductive protrusions 510 arranged at intervals. The thermally conductive protrusions 510 are disposed in the cooling cavity 4 and thermally connected to the chip 2. The gap between two adjacent thermally conductive protrusions 510 forms a first heat exchange channel 6 communicating with the cooling cavity 4.

[0030] Through the above technical solution, namely the semiconductor packaging structure provided in this disclosure, the heat sink 330 is connected to the chip 2 through the second structural layer 340, so that the heat sink 330, the second structural layer 340 and the chip 2 together form a cooling cavity 4 for containing the cooling medium. At the same time, multiple heat-conducting protrusions 510 of the heat-conducting structure 5 are disposed in the cooling cavity 4 and thermally connected to the chip 2. With this arrangement, the heat generated at the chip 2 can be transferred to the heat-conducting structure 5, and the cooling medium located in the cooling cavity can directly act on the heat-conducting structure 5 to remove the heat, thereby achieving the purpose of cooling the chip 2 and helping to improve the performance and reliability of the chip 2.

[0031] Furthermore, since the cooling medium located in the cooling cavity 4 can directly act on the heat-conducting structure 5, that is, after the cooling medium flows through the cooling cavity 4, it can directly exchange heat with the heat-conducting structure 5 located in the cooling cavity 4, which can effectively shorten the heat transfer path and improve the heat dissipation effect of the cooling medium on the chip 2. In addition, since the purpose of cooling the chip 2 can be achieved by adding the heat-conducting structure 5 to the chip 2, for example, without designing modifications to the chip 2's own structure or precision machining, the design complexity of the overall structure of the chip 2 can be reduced, the manufacturing process is less difficult, and it is beneficial to improve production efficiency and reduce manufacturing costs. Therefore, the semiconductor packaging structure provided by this disclosure can improve the heat dissipation effect of the chip 2, help improve the performance and reliability of the chip 2, and has the advantages of simple overall structure and easy processing and manufacturing.

[0032] Furthermore, since the heat dissipation cover 330 has an inlet 310 and an outlet 320 connected to the cooling chamber 4, it facilitates the replenishment and discharge of cooling medium, for example, within the cooling chamber 4. For instance, the inlet 310 and outlet 320 of the heat dissipation cover 330 can be connected to a cooling medium supply device (not shown), thereby achieving the purpose of replenishing and discharging cooling medium within the cooling chamber 4. The cooling medium supply device (not shown) can be adaptively designed with reference to any suitable cooling medium supply device in the art, and will not be described in detail here.

[0033] It should be noted that the cooling medium mentioned above may include, but is not limited to, deionized water. Since deionized water has weak conductivity and weak corrosiveness, it can safely and efficiently cool down the chip 2. This disclosure is not limited to this. For example, the cooling medium mentioned above may also include coolants with weak conductivity and weak corrosiveness, such as electronic fluorinated liquid. The purpose is to achieve safe and efficient cooling down of the chip 2 through the cooling medium. Those skilled in the art can design it adaptively according to actual application requirements.

[0034] In addition, such as Figures 1 to 3 As shown, since the heat-conducting structure 5 includes multiple heat-conducting protrusions 510 arranged at intervals, the gap between two adjacent heat-conducting protrusions 510 forms a first heat exchange channel 6 that communicates with the cooling cavity 4. In this way, by setting multiple heat-conducting protrusions 510, the heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2 can be effectively increased, so as to quickly remove heat and achieve efficient cooling of the chip 2, which helps to improve the performance and reliability of the chip 2.

[0035] It should be noted that by thermally connecting the thermally conductive protrusion 510 to the top wall of the chip 2 away from the substrate 1, the heat exchange area between the cooling medium and the chip 2 in the cooling cavity 4 can be increased, thereby improving the overall heat exchange efficiency. For example, in some possible embodiments, the thermally conductive protrusion 510 is connected to the top wall of the chip 2 away from the substrate 1 and extends towards the side away from the top wall. Furthermore, the thermally conductive protrusion 510 can abut against the inner wall surface of the sealing structure 3 (e.g., the heat sink 330 facing the inner wall surface of the chip 2). This ensures a high heat exchange area between the cooling medium and the chip 2 in the cooling cavity 4, which is beneficial for improving the heat dissipation effect on the chip 2.

[0036] Additionally, in some implementations, references Figures 1 to 3 As shown, the thermally conductive protrusion 510 can be provided with a notch 7. For example, the thermally conductive protrusion 510 can be provided with a notch 7 on the top wall facing the sealing structure 3. In addition, the thermally conductive protrusion 510 can also be provided with a notch 7 on its side wall. In this way, by providing the notch 7, the cooling medium in the cooling cavity 4 can flow through the multiple thermally conductive protrusions 510 through the notch 7, which helps to improve the heat dissipation efficiency. Furthermore, the notch 7 can form a second heat exchange channel for the cooling medium, which can increase the heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2, thereby improving the heat dissipation effect on the chip 2.

[0037] It is understood that the specific embodiment in which the above-mentioned thermally conductive protrusion 510 is connected to the top wall of the chip 2 away from the substrate 1 and extends toward the side away from the top wall, and the thermally conductive protrusion 510 can abut against the inner wall surface of the sealing structure 3, is exemplary. For example, in some alternative embodiments, the end of the thermally conductive protrusion 510 away from the top wall of the chip 2 may also have a gap 15 between it and the inner wall of the sealing structure 3. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs, with the aim of improving the heat dissipation effect on the chip 2.

[0038] In addition, the aforementioned multiple heat-conducting protrusions 510 can be arranged in rows and spaced apart along the first direction, and / or arranged in columns and spaced apart along a second direction perpendicular to the first direction. In this way, by setting multiple heat-conducting protrusions 510, it can be ensured that there is a high heat exchange area between the cooling medium in the cooling cavity 4 and the chip 2, which is beneficial to improving the heat dissipation effect on the chip 2.

[0039] The spacing between any two adjacent thermally conductive bumps 510 is not specifically limited in this disclosure. Those skilled in the art can design it adaptively according to actual application requirements. For example, it can be designed according to the power consumption of chip 2. For instance, the spacing between two adjacent thermally conductive bumps 510 can be 1.5 times the thickness of the thermally conductive bump 510 along the first or second direction. In addition, the multiple thermally conductive bumps 510 can be arranged in an array, that is, the multiple thermally conductive bumps 510 can be arranged at equal intervals. Alternatively, the multiple thermally conductive bumps 510 can also be arranged at unequal intervals. For example, the thermally conductive bumps 510 in the high-heat areas of chip 2 can be arranged more densely (i.e., the spacing between two adjacent thermally conductive bumps 510 is smaller), while the thermally conductive bumps 510 in the remaining low-heat areas of chip 2 can be arranged more dispersedly (i.e., the spacing between two adjacent thermally conductive bumps 510 is larger). This disclosure does not specifically limit this.

[0040] It should be noted that the specific shape, number, location, and dimensions of the aforementioned thermally conductive protrusions 510 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application requirements. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium in the cooling cavity 4 and the thermally conductive structure 5, so as to achieve rapid cooling of the chip 2.

[0041] In addition, the specific shape and size of the multiple thermally conductive bumps 510 can be the same to facilitate on-site processing. It is understood that those skilled in the art can also adapt the specific shape and size of the multiple thermally conductive bumps 510 to be different according to actual application needs. For example, the shape and size of some thermally conductive bumps 510 in the high-heat area of ​​the chip 2 can be made larger than those of some thermally conductive bumps 510 in the remaining area of ​​the chip 2 to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0042] Exemplarily, in some implementations, reference is made to Figures 1 to 3 As shown, each thermally conductive protrusion 510 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, each thermally conductive protrusion 510 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0043] Additionally, in some implementations, references Figures 1 to 3 As shown, each thermally conductive protrusion 510 is along the second direction (which can be referenced as perpendicular to the direction of the second direction). Figure 1The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, each heat-conducting protrusion 510 is along the second direction (which can be referenced to be perpendicular to the direction shown in the drawing). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0044] Furthermore, in some implementations, references Figures 1 to 3 As shown, each thermally conductive protrusion 510 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm-200μm. For example, each thermally conductive protrusion 510 has a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. This disclosure is not limited thereto.

[0045] In some possible implementations, refer to Figures 1 to 3 As shown, the specific external shape of the thermally conductive protrusion 510 can be constructed as, for example, rectangular, so as to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 4 and the thermally conductive structure 5, thereby achieving the purpose of rapidly cooling the chip 2, and having the advantages of simple overall structure and easy processing and fabrication.

[0046] Alternatively, in other alternative embodiments, the specific shape of the thermally conductive protrusion 510 can also be constructed as, for example, a cylindrical shape or other shapes. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 4 and the thermally conductive structure 5, so as to achieve rapid cooling of the chip 2.

[0047] It should be noted that the notch 7 formed on the thermally conductive protrusion 510 can be fabricated on the thermally conductive protrusion 510 by any suitable fabrication process in the art, such as etching or laser processing, which will not be described in detail here.

[0048] Considering that in order to ensure that the thermally conductive bump 510 has high thermal conductivity so that the heat generated at the chip 2 can be quickly transferred to the thermally conductive bump 510 and then quickly removed by the cooling medium, in some possible embodiments, the material of the thermally conductive bump 510 can be copper. This arrangement can ensure that the thermally conductive bump 510 has high thermal conductivity, so as to achieve the goal of quickly transferring the heat generated at the chip 2 to the thermally conductive bump 510 and then quickly removing the heat by the cooling medium. This is beneficial to improving the cooling effect of the chip 2. Furthermore, using copper to prepare the thermally conductive bump 510 is also convenient for on-site processing, easy to process, and highly reliable.

[0049] It is understood that in other alternative embodiments, the material of the above-mentioned thermally conductive bump 510 may also be a material with thermal conductivity, such as aluminum or aluminum alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the heat generated at the chip 2 to be transferred to the thermally conductive bump 510, and to be directly acted on by the cooling medium located in the cooling cavity to remove the heat, thereby achieving the purpose of cooling the chip 2.

[0050] In some possible implementations, refer to Figure 1 As shown, a first structural layer 8 can be provided on the top wall of the chip 2 facing the heat conduction structure 5. The heat conduction structure 5 is connected to the chip 2 through the first structural layer 8. This arrangement can ensure that the heat conduction structure 5 (e.g., heat conduction protrusion 510) can be stably connected to the chip 2, which is easy to process and has high reliability. It is beneficial to ensure efficient and stable cooling of the chip 2, and helps to improve the performance and reliability of the chip 2.

[0051] For example, the first structural layer 8 can be a coating structure coated on the outer wall (top wall) of the chip 2, or alternatively, the first structural layer 8 can be a connecting thin film structure disposed on the outer wall (top wall) of the chip 2. This disclosure does not specifically limit this, and those skilled in the art can design it adaptively according to actual application needs.

[0052] It should be noted that, in this disclosure, the first structural layer 8 is described along a third direction (see reference). Figure 1 The thickness dimension (in the vertical direction of the middle drawing) is not specifically limited. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the heat-conducting structure 5 (e.g., heat-conducting protrusion 510) can be stably connected to the chip 2, and at the same time, the heat generated at the chip 2 can be quickly transferred to the heat-conducting protrusion 510 and the heat can be quickly removed by the cooling medium.

[0053] Furthermore, the specific fabrication process of the first structural layer 8, which is, for example, a coating structure coated on the outer wall (top wall) of the chip 2 or a connecting thin film structure disposed on the outer wall (top wall) of the chip 2, can be adapted by referring to existing processing and fabrication processes, and this disclosure will not elaborate further on this.

[0054] Furthermore, since the cooling medium can directly exchange heat with the heat-conducting structure 5 disposed in the cooling cavity 4 after flowing through the cooling cavity 4, and since the thickness of the first structural layer 8 is thinner than the thickness of the heat-conducting layer 12 and the liquid cooling plate 13 in the related art, this disclosure can effectively shorten the heat transfer path and improve the heat dissipation effect of the cooling medium on the chip 2 compared with the multi-layer heat transfer path cooling method in the related art.

[0055] In some possible implementations, the first structural layer 8 can be made of titanium. This arrangement allows the first structural layer 8, made of titanium, to be placed on the top wall of the chip 2, so that the aforementioned thermally conductive structure 5 (thermally conductive bump 510) can be electroplated on the chip 2. This ensures that the thermally conductive structure 5 (e.g., thermally conductive bump 510) can be stably connected to the chip 2. At the same time, it can also quickly transfer the heat generated at the chip 2 to the thermally conductive bump 510 and quickly remove the heat through the cooling medium, thereby achieving efficient and stable cooling of the chip 2.

[0056] It is understood that in other alternative embodiments, the material of the first structural layer 8 may also be, for example, titanium alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the thermally conductive structure 5 (e.g., thermally conductive protrusion 510) can be stably connected to the chip 2, and at the same time, the chip 2 can be cooled efficiently and stably.

[0057] In some possible implementations, refer to Figure 1 As shown, the second structural layer 340 can be disposed between the heat sink 330 and the chip 2, and the second structural layer 340 is arranged in a ring around the outer periphery of the chip 2. The heat sink 330 is provided with an inlet channel and an outlet channel. The inlet 310 is connected to the cooling cavity 4 through the inlet channel, and the outlet 320 is connected to the cooling cavity 4 through the outlet channel. In this way, the inlet channel and the outlet channel are provided to facilitate the replenishment and discharge of cooling medium, for example, in the cooling cavity 4. In addition, since the second structural layer 340 is constructed to be arranged in a ring around the outer periphery of the chip 2, the cooling cavity 4 formed between the heat sink 330, the second structural layer 340 and the chip 2 can be guaranteed to have high sealing performance and reliability, which is conducive to ensuring that the cooling medium in the cooling cavity 4 can efficiently and stably cool and reduce the temperature of the chip 2.

[0058] In addition, in some possible implementations, the second structural layer 340 can be formed of sealant. This arrangement, since the sealant is compressible and stretchable, can cover the effects of warping during the chip 2 packaging process. This not only improves the overall reliability of the packaging structure, but also ensures that, for example, the heat sink 330 is stably connected to the chip 2, and ensures that the cooling cavity 4 has high sealing performance, thereby achieving efficient and stable cooling of the chip 2.

[0059] The sealant can be adaptively designed according to actual application requirements. For example, in some possible embodiments, the sealant material can be polydimethylsiloxane (PDMS) or epoxy-based negative photoresist (SU-8). This arrangement can ensure that, for example, the heat sink 330 is stably connected to the chip 2, while also ensuring that the cooling cavity 4 has high sealing performance, thereby achieving the purpose of stable and efficient cooling of the chip 2. This disclosure is not limited thereto.

[0060] In addition, the thickness of the sealant along the first or second direction can be no less than 500 μm, and the height of the sealant along the third direction can be, for example, 250 μm-300 μm, so as to ensure that the sealant has high structural strength while improving the overall reliability of the encapsulation structure.

[0061] Furthermore, in some possible implementations, reference is made to Figures 1 to 3 As shown, the heat sink 330 may include a manifold plate 331 and a cover plate 332 stacked along a third direction. The cover plate 332 is connected to the chip 2 through a second structural layer 340, and the cover plate 332 is provided with a first fluid channel 3321 and a second fluid channel 3322. The manifold plate 331 is provided with an inlet 310, an outlet 320, a third fluid channel 3311, and a fourth fluid channel 3312. The first fluid channel 3321 and the third fluid channel 3311 are connected to form a liquid inlet channel, and the second fluid channel 3322 and the fourth fluid channel 3312 are connected to form a liquid outlet channel. That is, the inlet 310 is connected to the third fluid channel 3321. 11 and the first fluid channel 3321 are connected to the cooling chamber 4, and the outlet 320 is connected to the cooling chamber 4 through the connected fourth fluid channel 3312 and the second fluid channel 3322. This arrangement facilitates the replenishment and discharge of the cooling medium in the cooling chamber 4. Furthermore, by constructing the sealing structure 3 as including the stacked manifold plate 331 and the cover plate 332, and by processing and preparing the fluid channels that can be connected on the manifold plate 331 and the cover plate 332 respectively, the overall structure of the sealing structure 3 can be simplified, the complexity of the sealing structure 3 can be reduced, and the on-site processing and preparation of the sealing structure 3 (such as the manifold plate 331 and the cover plate 332) can be facilitated.

[0062] In this disclosure, the specific arrangement of the fluid channels (such as the third fluid channel 3311, the fourth fluid channel 3312, the first fluid channel 3321 and the second fluid channel 3322) on the manifold plate 331 and the cover plate 332 is not specifically limited. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to facilitate the replenishment and discharge of the cooling medium in the cooling chamber 4.

[0063] Furthermore, considering that in order to ensure a high degree of connection reliability between the manifold plate 331 and the cover plate 332, in some possible embodiments, reference is made to... Figure 1 As shown, the sealing structure 3 may also include a connecting structure 350, through which the manifold plate 331 and the cover plate 332 are connected. This arrangement enables a stable connection between the manifold plate 331 and the cover plate 332 via the connecting structure 350, which is highly reliable and also facilitates the assembly and connection of the manifold plate 331 and the cover plate 332 on site.

[0064] The connection structure 350 can be arranged in any suitable manner; for example, in some possible embodiments, refer to... Figure 1 As shown, the connection structure 350 may include a first adhesive layer 351 disposed between the manifold plate 331 and the cover plate 332. The first adhesive layer 351 is provided with a first cavity 352 connecting the third fluid cavity 3311 and the first fluid cavity 3321, and a second cavity 353 connecting the fourth fluid cavity 3312 and the second fluid cavity 3322. In this way, the first adhesive layer 351 can achieve a stable connection between the manifold plate 331 and the cover plate 332, while also ensuring a high degree of sealing between the third fluid cavity 3311 and the first fluid cavity 3321 connected by the first cavity 352, and between the fourth fluid cavity 3312 and the second fluid cavity 3322 connected by the second cavity 353. This reduces the risk of cooling medium leakage and facilitates the replenishment and discharge of cooling medium in the cooling chamber 4.

[0065] Alternatively, in some implementations, refer to Figure 1 As shown, the connection structure 350 may also include a connecting bolt 354. The manifold plate 331 and the cover plate 332 are connected by the connecting bolt 354. This arrangement allows for a stable connection between the manifold plate 331 and the cover plate 332, and the overall structure is simple and easy to assemble on site.

[0066] It should be noted that the connection structure 350 may be constructed to include only the first adhesive layer 351, or alternatively, the connection structure 350 may be constructed to include only the connecting bolt 354, or alternatively, the connection structure 350 may include both the first adhesive layer 351 and the connecting bolt 354. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to achieve a stable connection and fixation between the manifold plate 331 and the cover plate 332.

[0067] Furthermore, this disclosure does not specifically limit the specific structure of the first adhesive layer 351 and the connecting bolt 354. For example, the first adhesive layer 351 can be formed by any suitable sealant or structural adhesive in the art, the purpose of which is to ensure a stable connection between the manifold plate 331 and the cover plate 332 through the first adhesive layer 351. Similarly, the connecting bolt 354 can be adapted to any suitable bolt structure in the art, the purpose of which is to ensure a stable connection between the manifold plate 331 and the cover plate 332 through the connecting bolt 354. This disclosure is not limited thereto.

[0068] Furthermore, it should be noted that the specific embodiment of the aforementioned sealing structure 3, which may include a manifold plate 331 and a cover plate 332 stacked along a third direction, is exemplary. For example, in some alternative embodiments not shown, the aforementioned sealing structure 3 may also be constructed as a single cover plate structure, for example, not shown. The single cover plate structure may together with the aforementioned second structural layer 340 and the chip 2 to form the aforementioned cooling cavity 4. The single cover plate structure may also be provided with the aforementioned inlet 310, outlet 320, fluid channel (liquid inlet channel) that connects the inlet 310 to the cooling cavity 4, and fluid channel (liquid outlet channel) that connects the outlet 320 to the cooling cavity 4, so as to achieve efficient cooling of the chip 2. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0069] In some possible implementations, refer to Figure 1 As shown, an annular protrusion 9 can be provided on the substrate 1, surrounding the chip 2. A second adhesive layer 10 is provided between the sealing structure 3 and the annular protrusion 9. The sealing structure 3 is connected to the annular protrusion 9 through the second adhesive layer 10. By connecting the sealing structure 3 (e.g., heat sink 330) to the annular protrusion 9 connected to the substrate 1, the connection reliability of the sealing structure 3 can be improved, the structural strength of the substrate 1 can be enhanced, and the possibility of warping risk due to the difference in thermal expansion coefficients during the packaging process can be reduced. This helps to improve the packaging yield and the overall reliability of the packaging structure.

[0070] This disclosure does not specifically limit the specific shape, dimensions, and material of the substrate 1, the specific structure, dimensions, and material of the annular protrusion 9, or the connection and fixing method between the substrate 1 and the annular protrusion 9. Those skilled in the art can adapt the design according to actual application needs, and this disclosure will not elaborate further. For example, the substrate 1 and the annular protrusion 11 can be fixedly connected by a third adhesive layer. Furthermore, the second adhesive layer 10 can be formed from any suitable sealant or structural adhesive in the art, and this disclosure does not specifically limit its application.

[0071] In some possible implementations, refer to Figures 1 to 3 As shown, the number of chips 2 can be one or more, and each chip 2 is selected from either the memory chip 210 or the logic chip 220. This arrangement allows for the adaptive design of the number and type of chips 2 according to the usage requirements of, for example, the package structure, to meet the application layout requirements in scenarios with complex package structures, thereby improving the performance and applicability of the package structure. Furthermore, since the chip 2 can be safely and efficiently cooled by the cooling medium located within the cooling cavity 4, it can be ensured that the chip 2 can still operate stably and with high performance at a safe temperature even under high power consumption, resulting in high reliability.

[0072] Chip 2 may include a silicon chip, that is, it is understood that chip 2 may be made of, but is not limited to, silicon. Thus, by having a thermally conductive structure 5 connected to the chip 2 made of silicon, the chip 2 can be cooled by a cooling medium, which helps to ensure that the chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of chip 2.

[0073] Understandably, reference Figure 2 As shown, multiple chips 2 can be arranged in a row along the first direction, or alternatively, multiple chips 2 can be arranged in a column along the second direction, or alternatively, multiple chips 2 can be arranged in a row along the first direction and multiple chips in a column along the second direction at the same time. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0074] It should be noted that this disclosure does not specifically limit the specific structure, specific arrangement position on the substrate 1, or specific number of the aforementioned chips 2 (e.g., memory chip 210 and logic chip 220). Those skilled in the art can adapt the design according to actual application requirements. For example, the aforementioned memory chip 210 may include, but is not limited to, high-bandwidth memory chips (HBM), and the aforementioned logic chip 220 may include, but is not limited to, system-on-a-chip (SOC). This disclosure is not limited to these. Its purpose is to meet the application arrangement requirements in scenarios with complex packaging structures, and to improve the performance and applicability of the packaging structure.

[0075] Additionally, in some embodiments not shown, when the number of chips 2 is, for example, one, the heat sink 330 may be provided with one of the aforementioned inlet 310 and outlet 320. Furthermore, when the heat sink 330 is connected to the chip 2 via the second structural layer 340, forming the aforementioned cooling cavity 4 between the heat sink 330, the second structural layer 340, and the chip 2, the fluid channels (e.g., the third fluid channel 3311, the fourth fluid channel 3312, the first fluid channel 3321, and the second fluid channel 3322) provided on the heat sink 330 can be adaptively designed as one or more channels. That is, each inlet 310 can be connected to the cooling chamber 4 through a corresponding fluid channel, or each inlet 310 can be connected to the cooling chamber 4 simultaneously through multiple fluid channels. Similarly, each outlet 320 can be connected to the cooling chamber 4 through a corresponding fluid channel, or each outlet 320 can be connected to the cooling chamber 4 simultaneously through multiple fluid channels. This disclosure does not make specific limitations in this regard. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the replenishment and discharge of the cooling medium in the cooling chamber 4 so as to achieve the cooling and temperature reduction of the chip 2.

[0076] Furthermore, in some possible implementations, when the number of chips 2 is arranged in multiples, the heat sink 330 may also be provided with one of the aforementioned inlet 310 and outlet 320. Multiple second structural layers 340 may be adaptively arranged corresponding to the number of chips 2, and each second structural layer 340 may be arranged in a ring around the outer periphery of the corresponding chip 2 between the chip 2 and the heat sink 330, so that the aforementioned cooling cavity 4 can be formed between each chip 2, each second structural layer 340, and the heat sink 330. When multiple cooling cavities 4 are designed, the inlet 310 provided on the heat sink 330 corresponds to multiple... When one of the cooling chambers 4 is connected, the inlet 310 can be connected to one of the cooling chambers 4 through one or more fluid channels on the heat sink 330. Similarly, when the outlet 320 on the heat sink 330 is connected to one of the cooling chambers 4, the outlet 320 can be connected to one of the cooling chambers 4 through one or more fluid channels on the heat sink 330. This disclosure is not limited to this. Its purpose is to enable the simultaneous replenishment and discharge of cooling medium in multiple cooling chambers 4 so as to simultaneously cool and reduce the temperature of multiple chips 2.

[0077] In some possible implementations, refer to Figure 1 As shown, the semiconductor packaging structure may also include an interposer 11 disposed between the chip 2 and the substrate 1. The chip 2 is connected to the substrate 1 through the interposer 11. In this way, by integrating one or more chips 2 on the interposer 11, high bandwidth and low latency data interconnection can be achieved, achieving the purpose of high-density interconnection of the overall packaging structure, which is conducive to meeting the high performance design requirements of the packaging structure.

[0078] It should be noted that one or more chips 2 can be integrated onto the interposer layer 11, for example, via upright or flip-chip mounting. Furthermore, micro-bumps on the chip 2 can form signal connections with corresponding pads on the interposer layer 11. This disclosure does not impose specific limitations on this; those skilled in the art can adapt the design according to actual application requirements, with the aim of achieving signal connections between the chip 2 and the interposer layer 11. Additionally, the specific design of the chip 2 integrated onto the interposer layer 11 can be adapted by referring to existing technologies such as CoWoS (Chip-on-Wafer-on-Substrate) packaging structures, which will not be elaborated upon here.

[0079] In addition, the aforementioned interposer 11 may include, but is not limited to, a silicon interposer, so that when one or more chips 2 are integrated on the interposer 11, high bandwidth and low latency data interconnection can be achieved, thereby achieving the purpose of high-density interconnection of the overall package structure.

[0080] Furthermore, an underfill 14 can be provided between the aforementioned interposer 11 and the substrate 1 to fill the gap between the interposer 11 and the substrate 1. This arrangement can improve the connection reliability between the interposer 11 and the substrate 1, and also isolate air, reduce the risk of surface oxidation, and help extend the overall service life of the packaging structure. This disclosure is not limited thereto.

[0081] According to a second aspect of this disclosure, an electronic device is provided, comprising the semiconductor packaging structure provided in the first aspect. Furthermore, the electronic device also possesses all the beneficial effects of the aforementioned semiconductor packaging structure, which will not be elaborated further herein.

[0082] In some possible implementations, the aforementioned electronic devices may include, but are not limited to, general-purpose computing devices or professional computing devices, such as computers, mobile phones, tablets, workstations, smartwatches, AI servers, cloud computing servers, data center equipment, etc.

[0083] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0084] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0085] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; The chip is disposed on the substrate; The sealing structure includes a heat dissipation cover and a second structural layer. The heat dissipation cover is connected to the chip through the second structural layer, such that the heat dissipation cover, the second structural layer and the chip together form a cooling cavity for containing a cooling medium. The heat dissipation cover has an inlet and an outlet communicating with the cooling cavity. as well as The thermally conductive structure includes a plurality of thermally conductive protrusions arranged at intervals. The thermally conductive protrusions are disposed in the cooling cavity and are thermally connected to the chip. The gap between two adjacent thermally conductive protrusions forms a first heat exchange channel communicating with the cooling cavity.

2. The semiconductor packaging structure according to claim 1, characterized in that, The thermally conductive protrusion is connected to the top wall of the chip away from the substrate and extends toward the side away from the top wall. Wherein, the end of the thermally conductive protrusion facing away from the top wall of the chip has a gap with the inner wall of the sealing structure; and / or, The heat-conducting protrusion has a notch.

3. The semiconductor packaging structure according to claim 1, characterized in that, The plurality of the heat-conducting protrusions are arranged in a row along a first direction, and / or arranged in a column along a second direction perpendicular to the first direction.

4. The semiconductor packaging structure according to claim 1, characterized in that, The structural dimensions of each of the aforementioned thermally conductive protrusions along the first direction are 10μm-20μm; and / or, The structural dimensions of each of the aforementioned thermally conductive protrusions along the second direction are 10mm-30mm; and / or, The structural dimensions of each of the thermally conductive protrusions along a third direction perpendicular to the plane containing the first and second directions are 100μm-200μm.

5. The semiconductor packaging structure according to claim 1, characterized in that, The thermally conductive protrusions are cylindrical or rectangular in shape.

6. The semiconductor packaging structure according to claim 1, characterized in that, The thermally conductive protrusion is made of copper.

7. The semiconductor packaging structure according to claim 1, characterized in that, A first structural layer is provided on the top wall of the chip facing the thermal conductive structure, and the thermal conductive structure is connected to the chip through the first structural layer.

8. The semiconductor packaging structure according to claim 7, characterized in that, The first structural layer is made of titanium or a titanium alloy.

9. The semiconductor packaging structure according to any one of claims 1-8, characterized in that, The second structural layer is disposed between the heat sink and the chip, and the second structural layer is arranged in a circle around the outer periphery of the chip. The heat sink is provided with an inlet channel and an outlet channel. The inlet is connected to the cooling cavity through the inlet channel, and the outlet is connected to the cooling cavity through the outlet channel.

10. The semiconductor packaging structure according to claim 9, characterized in that, The second structural layer is formed of sealant.

11. The semiconductor packaging structure according to claim 10, characterized in that, The sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

12. The semiconductor packaging structure according to claim 9, characterized in that, The heat dissipation cover includes a manifold plate and a cover plate stacked in a third direction. The cover plate is connected to the chip through the second structural layer, and the cover plate is provided with a first fluid channel and a second fluid channel. The manifold plate is provided with an inlet, an outlet, a third fluid channel and a fourth fluid channel. The first fluid channel and the third fluid channel are connected to form the liquid inlet channel, and the second fluid channel and the fourth fluid channel are connected to form the liquid outlet channel.

13. The semiconductor packaging structure according to claim 12, characterized in that, The sealing structure also includes a connecting structure, through which the manifold plate and the cover plate are connected.

14. The semiconductor packaging structure according to claim 13, characterized in that, The connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

15. The semiconductor packaging structure according to claim 1, characterized in that, The substrate has an annular protrusion arranged around the chip, and a second adhesive layer is disposed between the sealing structure and the annular protrusion. The sealing structure is connected to the annular protrusion through the second adhesive layer.

16. The semiconductor packaging structure according to claim 1, characterized in that, The number of chips is one or more, and each chip is selected from either memory chips or logic chips.

17. The semiconductor packaging structure according to claim 1 or 16, characterized in that, The semiconductor packaging structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

18. An electronic device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-17.

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