Semiconductor package structure and electronic device

Abstract

The present disclosure relates to a semiconductor packaging structure and an electronic device, the semiconductor packaging structure comprising a substrate, a chip, a blocking structure and a heat conduction structure, the chip being arranged on the substrate, and the chip being inwardly recessed downward from a top wall of the substrate to form a heat exchange flow channel; the blocking structure being connected to the chip, and a cooling cavity being formed between the blocking structure and the chip and being communicated with the heat exchange flow channel; the heat conduction structure being located in the cooling cavity and being heat-conductively connected to the top wall of the chip; wherein the blocking structure is configured to enable a cooling medium to flow through the cooling cavity, the heat exchange flow channel and the heat conduction structure, so that the cooling medium exchanges heat with the chip. Through the above technical solution, the semiconductor packaging structure provided by the present disclosure can solve the problem of poor heat dissipation effect of the chip in the related art due to the limitation of the arrangement form of the multi-layer heat transfer path of the existing packaging structure, and can meet the efficient cooling of the chip, which is beneficial to improving the performance and reliability of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and an electronic device. Background Technology

[0002] In related technologies, the demand for high-performance chips is becoming increasingly widespread. However, as chip performance improves, chip power consumption also increases dramatically. Existing packaging structures, due to limitations in the arrangement of multi-layer heat transfer paths, suffer from poor heat dissipation, affecting chip performance and reliability. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor packaging structure and electronic device that can improve the heat dissipation of the chip, thereby improving chip performance and reliability.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a semiconductor packaging structure, comprising: substrate; A chip is disposed on the substrate, and the chip is recessed downward from the top wall of the substrate to form a heat exchange channel. A sealing structure is connected to the chip, and a cooling cavity communicating with the heat exchange channel is formed between the sealing structure and the chip; and A thermally conductive structure is located within the cooling cavity and is thermally connected to the top wall of the chip; The sealing structure is configured to allow the cooling medium to flow through the cooling cavity, the heat exchange channel, and the heat conduction structure, so that the cooling medium can exchange heat with the chip.

[0005] In some possible implementations, the heat exchange channel includes a plurality of heat exchange channel segments arranged at intervals, and the heat conduction structure is provided between two adjacent heat exchange channel segments.

[0006] In some possible implementations, the thermally conductive structure includes a thermally conductive bump that is connected to the top wall of the chip and extends toward a side away from the top wall. Wherein, the end of the thermally conductive protrusion facing away from the top wall of the chip has a gap with the inner wall of the sealing structure; and / or, The heat-conducting protrusion has a notch.

[0007] In some possible implementations, the heat exchange channel includes a plurality of heat exchange channel segments spaced apart along a first direction, each of the heat exchange channel segments extending along a second direction perpendicular to the first direction; and / or, The heat-conducting structure includes a plurality of heat-conducting protrusions arranged at intervals, the plurality of heat-conducting protrusions being arranged in a row along a first direction and / or arranged in a column along a second direction perpendicular to the first direction.

[0008] In some possible implementations, the structural dimensions of the heat exchange channel section along the first direction are 10 μm-20 μm; and / or, The structural dimensions of the heat exchange channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the heat exchange channel section along a third direction perpendicular to the plane containing the first and second directions are 5μm-200μm.

[0009] In some possible implementations, the thermally conductive protrusion has a structural dimension of 10 μm-20 μm along the first direction; and / or, The thermally conductive protrusion has a structural dimension of 10mm-30mm along the second direction; and / or, The thermally conductive protrusion has a structural dimension of 100μm-200μm along a third direction perpendicular to the plane containing the first and second directions.

[0010] In some possible implementations, the thermally conductive protrusion is cylindrical or rectangular; and / or, The thermally conductive protrusion is made of copper.

[0011] In some possible implementations, a first structural layer is provided on the top wall of the chip facing the thermally conductive structure, and the thermally conductive structure is connected to the chip through the first structural layer.

[0012] In some possible implementations, the first structural layer is made of titanium or a titanium alloy.

[0013] In some possible implementations, the sealing structure includes a heat dissipation cap and a second structural layer. The heat dissipation cap is connected to the chip through the second structural layer, such that the heat dissipation cap, the second structural layer, the thermally conductive structure, and the chip together form the cooling cavity. The heat dissipation cap is provided with an inlet and an outlet communicating with the cooling cavity.

[0014] In some possible implementations, the second structural layer is disposed between the heat sink and the chip, and the second structural layer is arranged in a ring around the outer periphery of the chip. The heat sink is provided with an inlet channel and an outlet channel. The inlet is connected to the cooling cavity through the inlet channel, and the outlet is connected to the cooling cavity through the outlet channel.

[0015] In some possible implementations, the second structural layer is formed of sealant.

[0016] In some possible implementations, the sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

[0017] In some possible implementations, the heat sink includes a manifold and a cover plate stacked in a third direction, and the cover plate is connected to the chip through the second structural layer. The cover plate is provided with a first fluid channel and a second fluid channel. The manifold is provided with an inlet, an outlet, a third fluid channel, and a fourth fluid channel. The first fluid channel and the third fluid channel are connected to form the liquid inlet channel, and the second fluid channel and the fourth fluid channel are connected to form the liquid outlet channel.

[0018] In some possible implementations, the sealing structure further includes a connecting structure through which the manifold plate and the cover plate are connected.

[0019] In some possible implementations, the connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

[0020] In some possible implementations, the substrate is provided with an annular protrusion arranged around the chip, and a second adhesive layer is provided between the sealing structure and the annular protrusion, the sealing structure being connected to the annular protrusion through the second adhesive layer.

[0021] In some possible implementations, the number of chips is one or more, and each chip is selected from either memory chips or logic chips.

[0022] In some possible implementations, the semiconductor package structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

[0023] A second aspect of this disclosure provides an electronic device including the semiconductor package structure provided in the first aspect above.

[0024] The semiconductor packaging structure provided in this disclosure, through the aforementioned technical solution, incorporates a thermally conductive structure connected to the chip within a cooling cavity formed between the sealing structure and the chip. Furthermore, it directly forms a heat exchange channel on the top wall of the chip. This arrangement of the heat exchange channel and the thermally conductive structure effectively increases the heat exchange area between the cooling medium and the chip within the cooling cavity. As the cooling medium flows through the cooling cavity, the heat exchange channel, and the thermally conductive structure, it efficiently cools the chip, significantly improving the heat dissipation effect and ensuring stable and high-performance operation of the chip at a safe temperature. This enhances chip performance and reliability. Additionally, by directly applying the cooling medium to the chip and through the thermally conductive structure connected to the chip's top wall, the heat transfer path is effectively shortened, further improving the heat dissipation effect. Therefore, the semiconductor packaging structure provided in this disclosure solves the problem of poor heat dissipation in existing packaging structures due to limitations in the arrangement of multiple heat transfer paths, while simultaneously achieving efficient cooling of the chip, thus improving chip performance and reliability.

[0025] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 Cross-sectional view at position AA; Figure 3 yes Figure 1 A magnified view of a portion of position B in the middle section; Figure 4 This is a schematic diagram of the packaging structure provided in related technologies.

[0027] Explanation of reference numerals in the attached figures 1-Substrate; 2-Chip; 210-Memory chip; 220-Logic chip; 3-Heat exchange channel; 310-Heat exchange channel section; 4-Sealing structure; 410-Heat dissipation cover; 411-Inlet; 412-Outlet; 413-Manifold plate; 414-Cover plate; 420-Second structural layer; 430-First fluid cavity; 440-Second fluid cavity; 450-Third fluid cavity; 460-Fourth fluid cavity; 470-Connecting structure; 471-First adhesive layer; 472-First cavity; 473-Second cavity; 474-Connecting bolt; 5-Cooling cavity; 6-Heat-conducting structure; 610-Heat-conducting protrusion; 7-Gap; 8-Notch; 9-First structural layer; 10-Annular protrusion; 11-Second adhesive layer; 12-Intermediate layer; 13-Bottom filler adhesive; 14-Heat-conducting layer; 15-Liquid cooling plate. Detailed Implementation

[0028] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0029] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to upper and lower within the space of the semiconductor package structure when it is in use. "Inner" and "outer" refer to inner and outer relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0030] In related technologies, refer to Figure 4 As shown, chip 2 is thermally connected to liquid cooling plate 15 through thermal conductive layer 14, so that chip 2 can be indirectly cooled by the cooling medium in liquid cooling plate 15. However, this configuration requires the use of thermal interface material (TIM) at thermal conductive layer 14 to achieve heat exchange between chip 2 and liquid cooling plate 15. As a result, due to the arrangement of the multi-layer heat transfer path of the overall packaging structure, the thermal interface resistance at thermal interface material and other interfaces is significantly increased, resulting in poor heat dissipation effect on chip 2. This leads to an unprecedented increase in heat flux density inside chip 2, which is not conducive to the stable and high-performance operation of chip 2 at a safe temperature, thus affecting the performance and reliability of chip 2.

[0031] Based on this, according to the first aspect of this disclosure, a semiconductor packaging structure is provided, with reference to... Figures 1 to 3As shown, the semiconductor packaging structure includes a substrate 1, a chip 2, a sealing structure 4, and a thermally conductive structure 6. The chip 2 is disposed on the substrate 1, and a heat exchange channel 3 is formed by the chip 2 recessed downward from the top wall of the substrate 1. The sealing structure 4 is connected to the chip 2, and a cooling cavity 5 communicating with the heat exchange channel 3 is formed between the sealing structure 4 and the chip 2. The thermally conductive structure 6 is located in the cooling cavity 5 and is thermally connected to the top wall of the chip 2. The sealing structure 4 is configured to allow the cooling medium to flow through the cooling cavity 5, the heat exchange channel 3, and the thermally conductive structure 6, so that the cooling medium and the chip 2 can exchange heat.

[0032] Through the above-described technical solution, namely the semiconductor packaging structure provided in this disclosure, the semiconductor packaging structure, by providing a thermally conductive structure 6 connected to the chip 2 within the cooling cavity 5 formed between the sealing structure 4 and the chip 2, and by directly forming a heat exchange channel 3 on the top wall of the chip 2, can effectively increase the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 through the arrangement of the heat exchange channel 3 and the thermally conductive structure 6. Thus, when the cooling medium flows through the cooling cavity 5, the heat exchange channel 3, and the thermally conductive structure 6, it can efficiently cool and reduce the temperature of the chip 2, effectively improving the heat dissipation effect of the cooling medium on the chip 2, ensuring that the chip 2 can operate stably and with high performance at a safe temperature, which is beneficial to improving the performance and reliability of the chip 2.

[0033] Furthermore, by directly applying the cooling medium to chip 2 and the heat-conducting structure 6 thermally connected to the top wall of chip 2, the heat transfer path can be effectively shortened, thereby improving the heat dissipation effect of the cooling medium on chip 2. Therefore, the semiconductor packaging structure provided by this disclosure can solve the problem in related technologies where existing packaging structures are limited by the arrangement of multiple heat transfer paths, resulting in poor heat dissipation of the chip. It can also efficiently cool the chip, which is beneficial for improving chip performance and reliability.

[0034] It should be noted that the cooling medium mentioned above may include, but is not limited to, deionized water. Since deionized water has weak conductivity and weak corrosiveness, it can safely and efficiently cool down the chip 2. This disclosure is not limited to this. For example, the cooling medium mentioned above may also include coolants with weak conductivity and weak corrosiveness, such as electronic fluorinated liquid. The purpose is to achieve safe and efficient cooling down of the chip 2 through the cooling medium. Those skilled in the art can design it adaptively according to actual application requirements.

[0035] In some possible implementations, refer to Figures 1 to 3As shown, the heat exchange channel 3 may include multiple heat exchange channel sections 310 arranged at intervals, and a heat conduction structure 6 is provided between two adjacent heat exchange channel sections 310. This arrangement can effectively increase the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2. In this way, when the cooling medium flows through the cooling cavity 5, the heat exchange channel 3 and the heat conduction structure 6, the chip 2 can be cooled and cooled efficiently through the cooling medium, which effectively improves the heat dissipation effect of the cooling medium on the chip 2.

[0036] Exemplarily, in some possible implementations, references Figures 1 to 3 As shown, the thermally conductive structure 6 may include a thermally conductive protrusion 610. The thermally conductive protrusion 610 is connected to the top wall of the chip 2 and extends towards the side away from the top wall. In this way, the heat generated at the chip 2 can be transferred to the thermally conductive protrusion 610 through the setting of the thermally conductive protrusion 610, and the heat can be carried away by the cooling medium located in the cooling cavity 5. This achieves the purpose of cooling the chip 2. In addition, the heat exchange channel 3 is formed directly on the top wall of the chip 2, which can achieve efficient cooling of the chip 2 through the cooling medium. This helps to ensure that the chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of the chip 2.

[0037] It should be noted that by thermally connecting the thermally conductive protrusion 610 to the top wall of the chip 2 away from the substrate 1, the heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2 can be increased, thereby improving the overall heat exchange efficiency. For example, in some possible embodiments, the thermally conductive protrusion 610 can extend towards the side away from the top wall of the chip 2 and abut against the inner wall surface of the sealing structure 4 (e.g., the heat sink 410 facing the inner wall surface of the chip 2). This ensures a high heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2, which is beneficial for improving the heat dissipation effect on the chip 2.

[0038] Additionally, in some implementations, references Figures 1 to 3 As shown, a notch 8 can be provided on the heat-conducting protrusion 610. For example, a notch 8 can be provided on the top wall of the heat-conducting protrusion 610 facing the sealing structure 4. In addition, a notch 8 can also be provided on the side wall of the heat-conducting protrusion 610. In this way, by providing the notch 8, the cooling medium in the cooling cavity 5 can flow through the multiple heat-conducting protrusions 610 through the notch 8, which is beneficial to improving the heat dissipation efficiency.

[0039] It is understood that the specific embodiment in which the heat-conducting protrusion 610 extends toward the side opposite to the top wall of the chip 2 and abuts against the inner wall surface of the sealing structure 4 (e.g., the heat sink 410 toward the inner wall surface of the chip 2) is exemplary. For example, in some alternative embodiments, the end of the heat-conducting protrusion 610 away from the top wall of the chip 2 may also have a gap 7 between it and the inner wall of the sealing structure 4. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs, with the aim of improving the heat dissipation effect on the chip 2.

[0040] Furthermore, the aforementioned multiple thermally conductive bumps 610 can be arranged in rows and spaced apart along the first direction, and / or arranged in columns and spaced apart along a second direction perpendicular to the first direction. In this way, the arrangement of multiple thermally conductive bumps 610 ensures a high heat exchange area between the cooling medium within the cooling cavity 5 and the chip 2, which is beneficial for improving the heat dissipation effect on the chip 2. Moreover, when multiple thermally conductive bumps 610 are arranged, the gaps between adjacent thermally conductive bumps 610 also allow the cooling medium to flow through multiple thermally conductive bumps 610, achieving the purpose of efficient cooling of the chip 2.

[0041] The spacing between any two adjacent thermally conductive bumps 610 is not specifically limited in this disclosure. Those skilled in the art can design it adaptively according to actual application requirements. For example, it can be designed according to the power consumption of chip 2. For instance, the spacing between two adjacent thermally conductive bumps 610 can be 1.5 times the thickness of the thermally conductive bump 610 along the first or second direction. In addition, the multiple thermally conductive bumps 610 can be arranged in an array, that is, the multiple thermally conductive bumps 610 can be arranged at equal intervals. Alternatively, the multiple thermally conductive bumps 610 can also be arranged at unequal intervals. For example, the thermally conductive bumps 610 in the high-heat areas of chip 2 can be arranged more densely (i.e., the spacing between two adjacent thermally conductive bumps 610 is smaller), while the thermally conductive bumps 610 in the remaining low-heat areas of chip 2 can be arranged more dispersedly (i.e., the spacing between two adjacent thermally conductive bumps 610 is larger). This disclosure does not specifically limit this.

[0042] Furthermore, the specific shape, number, location, and dimensions of the aforementioned thermally conductive protrusions 610 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application requirements. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 5 and the thermally conductive protrusions 610, so as to achieve rapid cooling of the chip 2.

[0043] In addition, the specific shape and size of the multiple thermally conductive bumps 610 can be the same to facilitate on-site processing. It is understood that those skilled in the art can also adapt the specific shape and size of the multiple thermally conductive bumps 610 to be different according to actual application needs. For example, the shape and size of some thermally conductive bumps 610 in the high-heat area of ​​the chip 2 can be made larger than those of some thermally conductive bumps 610 in the remaining area of ​​the chip 2 to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0044] Exemplarily, in some implementations, reference is made to Figures 1 to 3 As shown, the thermally conductive protrusion 610 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the thermally conductive protrusion 610 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0045] Additionally, in some implementations, references Figures 1 to 3 As shown, the thermally conductive protrusion 610 is along the second direction (which can be referenced as perpendicular to) Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, the thermally conductive protrusion 610 along the second direction (refer to the direction perpendicular to the drawing) can be 10mm-30mm. Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0046] Furthermore, in some implementations, references Figures 1 to 3 As shown, the thermally conductive protrusion 610 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm-200μm. For example, the thermally conductive protrusion 610 can be located in a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, 200μm, etc. This disclosure is not limited thereto.

[0047] In some possible implementations, refer to Figures 1 to 3As shown, the specific external structure of the thermally conductive protrusion 610 can be constructed as, for example, rectangular, so as to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 5 and the thermally conductive protrusion 610, thereby achieving the purpose of rapid cooling of the chip 2, and having the advantages of simple overall structure and easy processing and fabrication.

[0048] Alternatively, in other alternative embodiments, the specific external shape of the thermally conductive protrusion 610 can also be constructed as, for example, a cylindrical shape or other external shapes. This disclosure does not specifically limit this, and those skilled in the art can design it adaptively according to actual application requirements. The purpose is to ensure that there is a high heat exchange contact area between the cooling medium located in the cooling cavity 5 and the thermally conductive protrusion 610, so as to achieve rapid cooling of the chip 2.

[0049] Considering that in order to ensure that the thermally conductive bump 610 has high thermal conductivity so that the heat generated at the chip 2 can be quickly transferred to the thermally conductive bump 610 and then quickly removed by the cooling medium, in some possible embodiments, the thermally conductive bump 610 can be made of copper. This arrangement can ensure that the thermally conductive bump 610 has high thermal conductivity, so as to achieve the goal of quickly transferring the heat generated at the chip 2 to the thermally conductive bump 610 and then quickly removing the heat by the cooling medium. This is beneficial to improving the cooling effect of the chip 2. Furthermore, using copper to prepare the thermally conductive bump 610 is also convenient for on-site processing, easy to process, and highly reliable.

[0050] It is understood that in other alternative embodiments, the material of the above-mentioned thermally conductive protrusion 610 may also be a material with thermal conductivity, such as aluminum or aluminum alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the heat generated at the chip 2 to be transferred to the thermally conductive protrusion 610, and to be directly acted on by the cooling medium located in the cooling cavity 5 to remove the heat, thereby achieving the purpose of cooling the chip 2.

[0051] In some possible implementations, refer to Figure 1 As shown, a first structural layer 9 can be provided on the top wall of the chip 2 facing the heat conduction structure 6. The heat conduction structure 6 is connected to the chip 2 through the first structural layer 9. This arrangement can ensure that the heat conduction protrusion 610 can be stably connected to the chip 2, which is easy to process and has high reliability. It is beneficial to ensure efficient and stable cooling of the chip 2, and helps to improve the performance and reliability of the chip 2.

[0052] For example, the first structural layer 9 can be a coating structure coated on the top wall of the chip 2, or alternatively, the first structural layer 9 can be a connecting thin film structure disposed on the top wall of the chip 2. This disclosure does not specifically limit it, and those skilled in the art can design it adaptively according to actual application needs.

[0053] It should be noted that this disclosure refers to the first structural layer 9 along a third direction (see reference). Figure 1 The thickness dimension (in the vertical direction of the middle part of the image) is not specifically limited. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the thermally conductive protrusion 610 can be stably connected to the chip 2, and at the same time, to enable the heat generated at the chip 2 to be quickly transferred to the thermally conductive protrusion 610 and then quickly removed by the cooling medium.

[0054] Furthermore, the specific fabrication process of the first structural layer 9, which is, for example, a coating structure coated on the top wall of the chip 2 or a connecting thin film structure disposed on the top wall of the chip 2, can be adapted by referring to existing processing and fabrication processes, and this disclosure will not elaborate further on this.

[0055] Furthermore, since the cooling medium can directly exchange heat with the heat-conducting protrusions 610 disposed in the cooling cavity 5 after flowing through the cooling cavity 5, and since the thickness of the first structural layer 9 is thinner than the thickness of the heat-conducting layer 14 and the liquid cooling plate 15 in the related art, this disclosure can effectively shorten the heat transfer path and improve the heat dissipation effect of the cooling medium on the chip 2 compared with the multi-layer heat transfer path cooling method in the related art.

[0056] In some possible implementations, the first structural layer 9 can be made of titanium. This arrangement allows the first structural layer 9, made of titanium, to be placed on the chip 2, so that the aforementioned thermally conductive bump 610 can be electroplated on the chip 2. This ensures that the thermally conductive bump 610 can be stably connected to the chip 2, and also enables the heat generated at the chip 2 to be quickly transferred to the thermally conductive bump 610 and carried away by the cooling medium, thereby achieving efficient and stable cooling of the chip 2.

[0057] It is understood that in other alternative embodiments, the material of the first structural layer 9 may also be, for example, titanium alloy. This disclosure does not specifically limit this. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to ensure that the thermally conductive protrusion 610 can be stably connected to the chip 2, and at the same time, the chip 2 can be cooled efficiently and stably.

[0058] It should be noted that, for example, when both heat exchange channels 3 and thermally conductive bumps 610 are provided on chip 2, the aforementioned first structural layer 9 can be provided on chip 2 in advance, and then the aforementioned heat exchange channels 3 and thermally conductive bumps 610 can be provided on chip 2 to facilitate on-site processing and fabrication.

[0059] The heat exchange channel section 310 can be adaptively designed according to actual application requirements. For example, in some possible implementations, refer to... Figures 1 to 3 As shown, the number of heat exchange channel sections 310 can be multiple, and they are along the first direction (refer to...). Figure 1 The heat exchanger channels 310 are arranged at intervals along the left and right directions of the central image, and each heat exchanger channel section 310 is along a second direction perpendicular to the first direction (refer to the direction perpendicular to the first direction). Figure 1 The arrangement extends in the direction shown in the figure. This arrangement helps to ensure a high heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2, while the overall structure is also relatively simple and easy to process and prepare the heat exchange channel section 310 on site.

[0060] It should be noted that the specific shape, structure and dimensions of each heat exchange channel section 310 are not specifically limited in this disclosure. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to ensure that there is a high heat exchange area between the cooling medium in the cooling cavity 5 and the chip 2.

[0061] In addition, the specific shape and size of each heat exchange channel section 310 can be the same to facilitate on-site processing and fabrication. It is understood that those skilled in the art can also adapt the specific shape and size of each heat exchange channel section 310 to be different according to actual application needs. For example, the shape and size of some heat exchange channel sections 310 in the high heat area of ​​the chip 2 can be made larger than those of some heat exchange channel sections 310 in the remaining area of ​​the chip 2, so as to ensure a higher heat dissipation effect on the chip 2. This disclosure does not make specific limitations in this regard.

[0062] Exemplarily, in some implementations, reference is made to Figures 1 to 3 As shown, the heat exchange channel section 310 is along the first direction (refer to...). Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm-20μm. For example, the heat exchange channel section 310 along the first direction (refer to...) Figure 1 The structural dimensions (in the left-right direction of the middle image) can be 10μm, 13μm, 15μm, 18μm, 20μm, etc. This disclosure is not limited thereto.

[0063] Additionally, in some implementations, references Figures 1 to 3 As shown, the heat exchange channel section 310 is along the second direction (which can be referenced as perpendicular to the direction of the second direction). Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm-30mm. For example, the heat exchanger flow channel section 310 along the second direction (which can be referenced to the direction perpendicular to the drawing) can be 10mm-30mm. Figure 1 The structural dimensions (in the direction shown in the drawing) can be 10mm, 15mm, 20mm, 25mm, 30mm, etc. This disclosure is not limited thereto.

[0064] Furthermore, in some implementations, references Figures 1 to 3 As shown, the heat exchange channel section 310 is along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle drawing) can range from 5μm to 200μm. For example, the heat exchange channel section 310 can be located along a third direction perpendicular to the plane containing the first and second directions (refer to...). Figure 1 The structural dimensions (in the vertical direction of the middle image) can be 5μm, 20μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm, 200μm, etc. This disclosure is not limited thereto.

[0065] It should be noted that the specific structural dimensions of the heat exchange channel section 310 formed on the chip 2 can also be adaptively designed according to different types of chips 2. For example, when there are multiple chips 2 and they include memory chips 210 and logic chips 220, the specific structural dimensions of the corresponding heat exchange channel sections 310 on the memory chips 210 and logic chips 220 can be adaptively designed according to the actual application requirements of different chips 2. This disclosure will not elaborate further here.

[0066] Additionally, in some implementations, references Figures 1 to 3 As shown, the specific external structure of each heat exchange channel section 310 can be constructed as, for example, a rectangular groove, which is simple in structure and easy to process and manufacture. It is understood that the specific external structure of each heat exchange channel section 310 can also be constructed as, for example, a "V" shaped groove or a semi-circular groove, etc. This disclosure does not make specific limitations in this regard, and those skilled in the art can design it adaptively according to actual application needs.

[0067] Furthermore, each heat exchange channel section 310 can be fabricated using any suitable fabrication process in the art, such as etching or laser micromachining, which will not be elaborated upon here.

[0068] Optionally, in some embodiments, the plurality of heat exchange channel segments 310 arranged at intervals along the first direction can be arranged at equal intervals. Such an arrangement can improve the uniformity of heat dissipation of the cooling medium to the chip 2 within the cooling cavity 5, ensuring a higher heat dissipation effect. Alternatively, the plurality of heat exchange channel segments 310 arranged at intervals along the first direction can also be arranged at unequal intervals. For example, some heat exchange channel segments 310 in the areas with higher heat on the chip 2 can be arranged more densely (i.e., the distance between two adjacent heat exchange channel segments 310 is smaller), while some heat exchange channel segments 310 in the remaining areas with lower heat on the chip 2 can be arranged more dispersedly (i.e., the distance between two adjacent heat exchange channel segments 310 is larger). This disclosure does not specifically limit this arrangement.

[0069] Additionally, it should be noted that the specific embodiment in which the heat exchange channel 3 includes a plurality of heat exchange channel segments 310 arranged at intervals along the first direction, and each heat exchange channel segment 310 extends along the second direction, is exemplary. In other alternative embodiments not shown, the heat exchange channel 3 may also be constructed as, for example, multiple branch channel segments formed on the top wall of the chip 2 and arranged in a "well" shape. This disclosure is not limited to this. The purpose is to ensure that the cooling medium located in the cooling cavity 5 and the chip 2 have a high heat exchange area through the arrangement of the heat exchange channel 3. Those skilled in the art can design it adaptively according to actual application requirements.

[0070] In some possible implementations, refer to Figure 1 As shown, the sealing structure 4 may include a heat dissipation cover 410 and a second structural layer 420. The heat dissipation cover 410 is connected to the chip 2 through the second structural layer 420, so that the heat dissipation cover 410, the second structural layer 420, the heat-conducting structure 6, and the chip 2 together form a cooling cavity 5. The heat dissipation cover 410 is provided with an inlet 411 and an outlet 412 communicating with the cooling cavity 5. This arrangement facilitates the replenishment and discharge of cooling medium, for example, within the cooling cavity 5. For example, the inlet 411 and outlet 412 of the heat dissipation cover 410 may be connected to a cooling medium supply device (not shown), thereby achieving the purpose of replenishing and discharging cooling medium within the cooling cavity 5. The cooling medium supply device (not shown) can be adaptively designed with reference to any suitable cooling medium supply device in the art, and will not be described in detail here.

[0071] Additionally, in some possible implementations, refer to Figure 1As shown, the second structural layer 420 is disposed between the heat sink 410 and the chip 2, and the second structural layer 420 is arranged in a ring around the outer periphery of the chip 2. The heat sink 410 is provided with an inlet channel and an outlet channel. The inlet 411 is connected to the cooling cavity 5 through the inlet channel, and the outlet 412 is connected to the cooling cavity 5 through the outlet channel. In this way, the inlet channel and the outlet channel are provided to facilitate the replenishment and discharge of cooling medium, for example, in the cooling cavity 5. Since the second structural layer 420 is constructed to be arranged in a ring around the outer periphery of the chip 2, the cooling cavity 5 formed between the heat sink 410, the second structural layer 420, the thermally conductive protrusion 610 and the chip 2 can be guaranteed to have high sealing performance and reliability, which is conducive to ensuring that the cooling medium in the cooling cavity 5 can efficiently and stably cool and reduce the temperature of the chip 2.

[0072] In addition, in some possible implementations, the second structural layer 420 can be formed of sealant. This arrangement, since the sealant is compressible and stretchable, can cover the effects of warping during the packaging of chip 2. This not only improves the overall reliability of the packaging structure, but also ensures that, for example, the heat sink 410 is stably connected to chip 2, and ensures that the cooling cavity 5 has high sealing performance, thereby achieving efficient and stable cooling of chip 2.

[0073] The sealant can be adaptively designed according to actual application requirements. For example, in some possible embodiments, the sealant material can be polydimethylsiloxane (PDMS) or epoxy-based negative photoresist (SU-8). This arrangement can ensure that, for example, the heat sink 410 is stably connected to the chip 2, while also ensuring that the cooling cavity 5 has high sealing performance, thereby achieving stable and efficient cooling of the chip 2. This disclosure is not limited thereto.

[0074] In addition, the thickness of the sealant along the first or second direction can be no less than 500 μm, and the height of the sealant along the third direction can be, for example, 250 μm-300 μm, so as to ensure that the sealant has high structural strength while improving the overall reliability of the encapsulation structure.

[0075] The heat sink 410 can be adaptively designed according to actual application requirements; for example, in some possible implementations, refer to... Figure 1 As shown, the heat sink 410 may include components along a third direction (see reference). Figure 1In the diagram (top to bottom), a manifold plate 413 and a cover plate 414 are stacked, with the cover plate 414 connected to the chip 2 via a second structural layer 420. The cover plate 414 is provided with a first fluid channel 430 and a second fluid channel 440. The manifold plate 413 is provided with an inlet 411, an outlet 412, a third fluid channel 450, and a fourth fluid channel 460. The first fluid channel 430 and the third fluid channel 450 are connected to form an inlet flow channel, and the second fluid channel 440 and the fourth fluid channel 460 are connected to form an outlet flow channel. That is, the inlet 411 is connected to the first fluid channel 430 and the third fluid channel 460. 50 is connected to the cooling chamber 5, and the outlet 412 is connected to the cooling chamber 5 through the second fluid channel 440 and the fourth fluid channel 460 arranged in a connected manner. This arrangement facilitates the replenishment and discharge of the cooling medium in the cooling chamber 5. Furthermore, by constructing the heat dissipation cover 410 as including the stacked manifold plate 413 and the cover plate 414, and by processing and preparing the fluid channels that can be arranged in a connected manner on the manifold plate 413 and the cover plate 414 respectively, the overall structure of the heat dissipation cover 410 can be simplified, the complexity of the heat dissipation cover 410 can be reduced, and the heat dissipation cover 410 (e.g., the manifold plate 413 and the cover plate 414) can be easily processed and prepared on site.

[0076] In this disclosure, the specific arrangement of the fluid channels (such as the first fluid channel 430, the second fluid channel 440, the third fluid channel 450 and the fourth fluid channel 460) on the manifold plate 413 and the cover plate 414 is not specifically limited. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to facilitate the replenishment and discharge of the cooling medium in the cooling chamber 5.

[0077] In addition, considering that in order to ensure a high degree of connection reliability between the manifold plate 413 and the cover plate 414, in some possible embodiments, reference is made to... Figure 1 As shown, the sealing structure 4 may also include a connecting structure 470, through which the manifold plate 413 and the cover plate 414 are connected. This arrangement enables a stable connection between the manifold plate 413 and the cover plate 414 via the connecting structure 470, which is highly reliable and also facilitates the assembly and connection of the manifold plate 413 and the cover plate 414 on site.

[0078] The connection structure 470 can be arranged in any suitable manner; for example, in some possible embodiments, refer to Figure 1As shown, the connection structure 470 may include a first adhesive layer 471 disposed between the manifold plate 413 and the cover plate 414. The first adhesive layer 471 is provided with a first cavity 472 connecting the first fluid cavity 430 and the third fluid cavity 450, and a second cavity 473 connecting the second fluid cavity 440 and the fourth fluid cavity 460. In this way, the first adhesive layer 471 can achieve a stable connection between the manifold plate 413 and the cover plate 414, while also ensuring a high degree of sealing between the first fluid cavity 430 and the third fluid cavity 450 connected by the first cavity 472, and between the second fluid cavity 440 and the fourth fluid cavity 460 connected by the second cavity 473. This reduces the risk of cooling medium leakage and facilitates the replenishment and discharge of cooling medium in the cooling chamber 5.

[0079] Alternatively, in some implementations, refer to Figure 1 As shown, the connection structure 470 may also include a connecting bolt 474. The manifold plate 413 and the cover plate 414 are connected by the connecting bolt 474. This arrangement allows for a stable connection between the manifold plate 413 and the cover plate 414, and the overall structure is simple and easy to assemble on site.

[0080] It should be noted that the connection structure 470 may be constructed to include only the first adhesive layer 471, or alternatively, the connection structure 470 may be constructed to include only the connecting bolt 474, or alternatively, the connection structure 470 may include both the first adhesive layer 471 and the connecting bolt 474. This disclosure does not specifically limit such variations. Those skilled in the art can design them adaptively according to actual application needs. The purpose is to achieve a stable connection and fixation between the manifold plate 413 and the cover plate 414.

[0081] Furthermore, this disclosure does not specifically limit the specific structure of the first adhesive layer 471 and the connecting bolt 474. For example, the first adhesive layer 471 can be formed by any suitable sealant or structural adhesive in the art, the purpose of which is to ensure a stable connection between the manifold plate 413 and the cover plate 414 through the first adhesive layer 471. Similarly, the connecting bolt 474 can be adapted to any suitable bolt structure in the art, the purpose of which is to ensure a stable connection between the manifold plate 413 and the cover plate 414 through the connecting bolt 474. This disclosure is not limited thereto.

[0082] Furthermore, it should be noted that the specific embodiment in which the heat dissipation cover 410 may include a manifold plate 413 and a cover plate 414 stacked along a third direction is exemplary. For example, in some alternative embodiments not shown, the heat dissipation cover 410 may also be constructed as a single cover plate structure, for example, not shown. The single cover plate structure may together with the second structural layer 420 and the chip 2 to form the cooling cavity 5. The single cover plate structure may also be provided with the inlet 411, the outlet 412, a fluid channel (liquid inlet channel) that connects the inlet 411 to the cooling cavity 5, and a fluid channel (liquid outlet channel) that connects the outlet 412 to the cooling cavity 5, so as to achieve efficient cooling of the chip 2. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0083] In some possible implementations, refer to Figure 1 As shown, an annular protrusion 10 can be provided on the substrate 1, surrounding the chip 2. A second adhesive layer 11 is provided between the sealing structure 4 and the annular protrusion 10. The sealing structure 4 is connected to the annular protrusion 10 through the second adhesive layer 11. With this arrangement, by connecting the heat sink 410 (e.g., cover plate 414) to the annular protrusion 10 connected to the substrate 1, not only can the connection reliability of the heat sink 410 be improved, but the structural strength of the substrate 1 can also be enhanced. This reduces the possibility of warping risk of the substrate 1 due to the difference in thermal expansion coefficient during, for example, the packaging process, which helps to improve the packaging yield and the overall reliability of the packaging structure.

[0084] In this disclosure, the specific shape, structural dimensions and structural materials of the substrate 1, the specific structure, structural dimensions and structural materials of the annular protrusion 10, and the connection and fixing method between the substrate 1 and the annular protrusion 10 are not specifically limited. Those skilled in the art can design them adaptively according to actual application needs. This disclosure will not elaborate on them in detail here. For example, the substrate 1 and the annular protrusion 10 can be fixedly connected by a third adhesive layer.

[0085] Additionally, in some possible implementations, refer to Figures 1 to 3 As shown, the number of chips 2 can be one or more, and each chip 2 is selected from either the memory chip 210 or the logic chip 220. This arrangement allows for the adaptive design of the number and type of chips 2 according to the usage requirements of, for example, the package structure, to meet the application layout requirements in scenarios with complex package structures, thereby improving the performance and applicability of the package structure. Furthermore, since the chip 2 can be safely and efficiently cooled by the cooling medium located within the cooling cavity 5, it can be ensured that the chip 2 can still operate stably and with high performance at a safe temperature even under high power consumption, resulting in high reliability.

[0086] Chip 2 may include a silicon chip, that is, it is understood that chip 2 may be made of, but is not limited to, silicon. In this way, by opening heat exchange channels 3 on chip 2 made of silicon, the chip 2 can be cooled by a cooling medium, which helps to ensure that chip 2 operates stably and with high performance at a safe temperature, thereby improving the performance and reliability of chip 2.

[0087] Understandably, reference Figure 2 As shown, multiple chips 2 can be arranged in a row along the first direction, or alternatively, multiple chips 2 can be arranged in a column along the second direction, or alternatively, multiple chips 2 can be arranged in a row along the first direction and multiple chips in a column along the second direction at the same time. This disclosure does not specifically limit such variations, and those skilled in the art can design them adaptively according to actual application needs.

[0088] It should be noted that this disclosure does not specifically limit the specific structure, specific arrangement position on the substrate 1, or specific number of the aforementioned chips 2 (e.g., memory chip 210 and logic chip 220). Those skilled in the art can adapt the design according to actual application requirements. For example, the aforementioned memory chip 210 may include, but is not limited to, high-bandwidth memory chips (HBM), and the aforementioned logic chip 220 may include, but is not limited to, system-on-a-chip (SOC). This disclosure is not limited to these. Its purpose is to meet the application arrangement requirements in scenarios with complex packaging structures, and to improve the performance and applicability of the packaging structure.

[0089] Furthermore, in some embodiments not shown, when the number of chips 2 is, for example, one, the heat sink 410 may be provided with one of the aforementioned inlet 411 and outlet 412. And when the heat sink 410 is connected to the chip 2 via the second structural layer 420, so that the aforementioned cooling cavity 5 is formed between the heat sink 410, the second structural layer 420, and the chip 2, the fluid channels provided on the heat sink 410 (e.g., the first fluid channel 430, the second fluid channel 440, the third fluid channel 450, and the fourth fluid channel 460, etc.) can be adaptively designed as one or more, i.e. Each inlet 411 can be connected to the cooling chamber 5 through a corresponding fluid channel, or each inlet 411 can be connected to the cooling chamber 5 simultaneously through multiple fluid channels. Similarly, each outlet 412 can be connected to the cooling chamber 5 through a corresponding fluid channel, or each outlet 412 can be connected to the cooling chamber 5 simultaneously through multiple fluid channels. This disclosure does not make specific limitations in this regard. Those skilled in the art can design it adaptively according to actual application needs. The purpose is to enable the replenishment and discharge of the cooling medium in the cooling chamber 5 so as to achieve cooling and temperature reduction of the chip 2.

[0090] Furthermore, in some possible implementations, when the number of chips 2 is arranged in multiples, the heat sink 410 may also be provided with one of the aforementioned inlet 411 and outlet 412. Multiple second structural layers 420 may be adaptively arranged corresponding to the number of chips 2, and each second structural layer 420 may be arranged in a ring around the outer periphery of the corresponding chip 2 between the chip 2 and the heat sink 410. This allows a cooling cavity 5 to be formed between each chip 2, each second structural layer 420, and the heat sink 410 for the cooling medium to flow through and exchange heat with the corresponding chip 2. When multiple cooling cavities 5 are designed, the heat sink 410 is provided with... When the inlet 411 is connected to one of the multiple cooling chambers 5, the inlet 411 can be connected to one of the multiple cooling chambers 5 through one or more fluid channels on the heat sink 410. Similarly, when the outlet 412 on the heat sink 410 is connected to one of the multiple cooling chambers 5, the outlet 412 can be connected to one of the multiple cooling chambers 5 through one or more fluid channels on the heat sink 410. This disclosure is not limited to this. Its purpose is to enable the simultaneous replenishment and discharge of cooling medium in multiple cooling chambers 5, so as to simultaneously cool and reduce the temperature of multiple chips 2.

[0091] In some possible implementations, refer to Figure 1As shown, the semiconductor packaging structure may also include an interposer 12 disposed between the chip 2 and the substrate 1. The chip 2 is connected to the substrate 1 through the interposer 12. In this way, by integrating one or more chips 2 on the interposer 12, high bandwidth and low latency data interconnection can be achieved, achieving the purpose of high-density interconnection of the overall packaging structure, which is conducive to meeting the high performance design requirements of the packaging structure.

[0092] It should be noted that one or more chips 2 can be integrated onto the interposer layer 12, for example, via upright or flip-chip mounting. Furthermore, micro-bumps on the chip 2 can form signal connections with corresponding pads on the interposer layer 12. This disclosure does not impose specific limitations on this; those skilled in the art can adapt the design according to actual application requirements, with the aim of achieving signal connections between the chip 2 and the interposer layer 12. Additionally, the specific design of the chip 2 integrated onto the interposer layer 12 can be adapted by referring to existing technologies such as CoWoS (Chip-on-Wafer-on-Substrate) packaging structures, which will not be elaborated upon here.

[0093] In addition, the aforementioned interposer 12 may include, but is not limited to, a silicon interposer, so that when one or more chips 2 are integrated on the interposer 12, high bandwidth and low latency data interconnection can be achieved, thereby achieving the purpose of high-density interconnection of the overall package structure.

[0094] Furthermore, an underfill 13 can be provided between the aforementioned interposer 12 and the substrate 1 to fill the gap between the interposer 12 and the substrate 1. This arrangement can improve the connection reliability between the interposer 12 and the substrate 1, and also isolate air, reduce the risk of surface oxidation, and help extend the overall service life of the packaging structure. This disclosure is not limited thereto.

[0095] According to a second aspect of this disclosure, an electronic device is provided, comprising the semiconductor packaging structure provided in the first aspect. Furthermore, the electronic device also possesses all the beneficial effects of the aforementioned semiconductor packaging structure, which will not be elaborated further herein.

[0096] In some possible implementations, the aforementioned electronic devices may include, but are not limited to, general-purpose computing devices or professional computing devices, such as computers, mobile phones, tablets, workstations, smartwatches, AI servers, cloud computing servers, data center equipment, etc.

[0097] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0098] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0099] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; A chip is disposed on the substrate, and the chip is recessed downward from the top wall of the substrate to form a heat exchange channel. A sealing structure is connected to the chip, and a cooling cavity communicating with the heat exchange channel is formed between the sealing structure and the chip; as well as A thermally conductive structure is located within the cooling cavity and is thermally connected to the top wall of the chip; The sealing structure is configured to allow the cooling medium to flow through the cooling cavity, the heat exchange channel, and the heat conduction structure, so that the cooling medium can exchange heat with the chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The heat exchange channel includes multiple heat exchange channel segments arranged at intervals, and the heat conduction structure is provided between two adjacent heat exchange channel segments.

3. The semiconductor packaging structure according to claim 1, characterized in that, The thermally conductive structure includes a thermally conductive protrusion, which is connected to the top wall of the chip and extends toward the side away from the top wall. Wherein, the end of the thermally conductive protrusion facing away from the top wall of the chip has a gap with the inner wall of the sealing structure; and / or, The heat-conducting protrusion has a notch.

4. The semiconductor packaging structure according to claim 1, characterized in that, The heat exchange channel includes a plurality of heat exchange channel segments arranged at intervals along a first direction, and each heat exchange channel segment extends along a second direction perpendicular to the first direction; and / or, The heat-conducting structure includes a plurality of heat-conducting protrusions arranged at intervals, the plurality of heat-conducting protrusions being arranged in a row along a first direction and / or arranged in a column along a second direction perpendicular to the first direction.

5. The semiconductor packaging structure according to claim 4, characterized in that, The structural dimensions of the heat exchange channel section along the first direction are 10μm-20μm; and / or, The structural dimensions of the heat exchange channel section along the second direction are 10mm-30mm; and / or, The structural dimensions of the heat exchange channel section along a third direction perpendicular to the plane containing the first and second directions are 5μm-200μm.

6. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusion has a structural dimension of 10μm-20μm along the first direction; and / or, The thermally conductive protrusion has a structural dimension of 10mm-30mm along the second direction; and / or, The thermally conductive protrusion has a structural dimension of 100μm-200μm along a third direction perpendicular to the plane containing the first and second directions.

7. The semiconductor packaging structure according to claim 4, characterized in that, The thermally conductive protrusions are cylindrical or rectangular; and / or, The thermally conductive protrusion is made of copper.

8. The semiconductor packaging structure according to claim 1, characterized in that, A first structural layer is provided on the top wall of the chip facing the thermal conductive structure, and the thermal conductive structure is connected to the chip through the first structural layer.

9. The semiconductor packaging structure according to claim 8, characterized in that, The first structural layer is made of titanium or a titanium alloy.

10. The semiconductor packaging structure according to any one of claims 1-9, characterized in that, The sealing structure includes a heat dissipation cover and a second structural layer. The heat dissipation cover is connected to the chip through the second structural layer, so that the heat dissipation cover, the second structural layer, the heat-conducting structure and the chip together form the cooling cavity. The heat dissipation cover is provided with an inlet and an outlet communicating with the cooling cavity.

11. The semiconductor packaging structure according to claim 10, characterized in that, The second structural layer is disposed between the heat sink and the chip, and the second structural layer is arranged in a circle around the outer periphery of the chip. The heat sink is provided with an inlet channel and an outlet channel. The inlet is connected to the cooling cavity through the inlet channel, and the outlet is connected to the cooling cavity through the outlet channel.

12. The semiconductor packaging structure according to claim 11, characterized in that, The second structural layer is formed of sealant.

13. The semiconductor packaging structure according to claim 12, characterized in that, The sealant is made of polydimethylsiloxane or epoxy-negative photoresist.

14. The semiconductor packaging structure according to claim 11, characterized in that, The heat dissipation cover includes a manifold plate and a cover plate stacked in a third direction, and the cover plate is connected to the chip through the second structural layer. The cover plate is provided with a first fluid channel and a second fluid channel. The manifold plate is provided with an inlet, an outlet, a third fluid channel and a fourth fluid channel. The first fluid channel and the third fluid channel are connected to form the liquid inlet channel, and the second fluid channel and the fourth fluid channel are connected to form the liquid outlet channel.

15. The semiconductor packaging structure according to claim 14, characterized in that, The sealing structure also includes a connecting structure, through which the manifold plate and the cover plate are connected.

16. The semiconductor packaging structure according to claim 15, characterized in that, The connection structure includes a first adhesive layer disposed between the manifold plate and the cover plate, the first adhesive layer having a first cavity communicating with the first fluid cavity and the third fluid cavity, and a second cavity communicating with the second fluid cavity and the fourth fluid cavity; and / or, The connection structure includes connecting bolts, and the manifold plate and the cover plate are threadedly connected by the connecting bolts.

17. The semiconductor packaging structure according to claim 1, characterized in that, The substrate has an annular protrusion arranged around the chip, and a second adhesive layer is disposed between the sealing structure and the annular protrusion. The sealing structure is connected to the annular protrusion through the second adhesive layer.

18. The semiconductor packaging structure according to claim 1, characterized in that, The number of chips is one or more, and each chip is selected from either memory chips or logic chips.

19. The semiconductor packaging structure according to claim 1 or 18, characterized in that, The semiconductor packaging structure further includes an intermediary layer disposed between the chip and the substrate, through which the chip is connected to the substrate.

20. An electronic device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-19.

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