Electronic component and method for manufacturing

Abstract

A method for producing a component, comprising: Providing an electrically insulating substrate (10); Applying a first electrically conductive layer (11) over the electrically insulating substrate (10); Placing a first semiconductor chip (12) on a pad of the first electrically conductive layer (11); Applying an electrically insulating layer (13) over the first electrically conductive layer (11) and the first semiconductor chip (12); Structuring the electrically insulating layer (13) in order to expose electrodes (20, 22) on a main surface (21) of the first semiconductor chip (12) facing away from the first electrically conductive layer, as well as a portion of the pad; Providing electrical through connections (23) to the exposed electrodes (20, 22) and the exposed portion of the pad; and Applying a second electrically conductive layer (14) to a surface of the electrically insulating layer (13) and the electrical through connections (23) facing away from the first semiconductor chip (12), wherein external contact elements (24, 25, 26) are formed from the second electrically conductive layer (14).

Description

[0001] The present invention relates to an electronic component and a method for assembling it.

[0002] Electronic components can contain two or more components that are electrically coupled to each other or electrically isolated from each other. The electronic components can therefore contain both electrically conductive means and electrically insulating means to achieve the desired arrangement within the component.

[0003] The publications DE 10 2004 019 445 A1, DE 199 54 941 A1, DE 10 2007 019 686 A1, WO 03 / 030247 A2 and US 6 306 680 B1 describe methods for producing electronic components. The Fig. 1A to 1E schematically show an embodiment of a method for manufacturing a component 100. Fig. 2A to 2I schematically show another embodiment of a method for producing a component 200. Fig. 3 schematically shows a component 300 according to a further embodiment. Fig. 4 schematically shows a component 400 according to a further embodiment. Fig. 5 shows a basic circuit of a half bridge 500.

[0004] Devices containing an electrically insulating substrate are described below. The substrate may be of any shape or size, or made of any material. The electrically insulating substrate need not be homogeneous or made of only one material; that is, different compositions and concentrations of the materials contained in the substrate are possible. During fabrication of the device, the substrate may be provided such that other substrates are arranged nearby and connected to the substrate by a connecting piece or connecting means for the purpose of separating the substrates. The substrate may be made entirely of electrically insulating materials. For example, the substrate may be made of a ceramic insulator such as Al 2 O 3or AlN. The substrate may, for example, be a DCB (Direct Copper Bonded) substrate, which is a ceramic substrate to which one or more copper foils are applied. In one embodiment, the substrate may be made of conductors or semiconductors, and at least one surface of the substrate may be electrically insulating. The insulating properties of this surface may be due to an electrically insulating layer coating this surface, which may, for example, be made of organic materials such as imide, epoxy, or thermoset, metal oxides, semiconductor oxides, ceramics, or diamond-like carbon. The electrically insulating layer may be formed using any suitable techniques, such as physical or chemical vapor deposition, solution deposition, or lamination.If the substrate is made of a semiconductor material such as silicon, the electrically insulating surface of the substrate can be created by doping the semiconductor material so that p-type and n-type semiconductors are in very close contact. A pn ​​junction is formed at the interface between the p-type and n-type semiconductors, which has the electrical properties of a diode. This diode allows electricity to flow in one direction but not in the opposite direction.

[0005] The substrate may contain a thermally conductive material. The thermal conductivity of this material may be greater than 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, or 150 W / (m·K) (units in watts / (meter·Kelvin)). For example, silicon has a thermal conductivity greater than 100 W / (m·K), and diamond-like carbon has a thermal conductivity greater than 1000 W / (m·K).

[0006] The devices described below may further include one or more semiconductor chips. The semiconductor chips may, for example, be placed above the electrically insulating substrate. If the substrate includes an electrically insulating surface and the rest of the substrate is electrically conductive, the semiconductor chips may be placed above the electrically insulating surface of the substrate. The semiconductor chips may be of extremely diverse types and may, for example, include integrated electrical or electro-optical circuits. The semiconductor chips may, for example, be configured as power transistors, power diodes, IGBTs (Insulated Gate Bipolar Transistors), control circuits, driver circuits, microprocessors, or microelectromechanical components.In one embodiment, semiconductor chips with a vertical structure may be involved, meaning that the semiconductor chips may be fabricated such that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip with a vertical structure may, in one embodiment, have contact pads on both of its main surfaces, meaning on its top and bottom surfaces. In one embodiment, power transistors, power diodes, and IGBTs may have a vertical structure. For example, the source electrode and gate electrode of a power transistor and the anode electrode of a power diode may be located on one main surface, while the drain electrode of the power transistor and the cathode electrode of the power diode are arranged on the other main surface. A power diode may, in one embodiment, be embodied as a Schottky diode.Furthermore, the components described below may contain integrated circuits for controlling and / or driving the integrated circuits of other semiconductor chips, for example, the integrated circuits of power transistors or power diodes. The semiconductor chips need not be made of a specific semiconductor material and may further contain inorganic and / or organic materials that are not semiconductors, such as insulators, plastics, or metals. Furthermore, the semiconductor chips may be encapsulated or unencapsulated.

[0007] One or more electrically conductive layers can be applied over the substrate, the semiconductor chips, and / or any other component. The electrically conductive layers can be used as wiring layers for establishing electrical contact with the semiconductor chips from outside the devices or for establishing electrical contact with other semiconductor chips and / or components contained in the devices. The electrically conductive layers can be manufactured with any desired geometric shape and any desired material composition. The electrically conductive layers can, for example, consist of conductive traces, but can also be in the form of a layer covering an area.Any desired electrically conductive material can be used as the material, such as metals, for example, aluminum, nickel, palladium, silver, tin, gold, or copper, metal alloys, metal stacks, or organic conductors. The electrically conductive layers do not need to be homogeneous or made of only one material; that is, different compositions and concentrations of the materials contained in the electrically conductive layers are possible. Furthermore, the electrically conductive layers can be arranged above, below, or between dielectric layers. The electrically conductive layers can also be thermally conductive, so that they can dissipate the heat generated by the semiconductor chips.

[0008] The devices contain one or more electrically insulating layers. The electrically insulating layers can cover any fraction of any number of surfaces of the device's components. The electrically insulating layers can serve different functions. For example, they can be used to electrically isolate components of the device from each other and / or from external components, but they can also be used as platforms for mounting other components, such as wiring layers. The electrically insulating layers can be fabricated using various techniques. For example, the electrically insulating layers can be deposited from a vapor phase or a solution, or laminated as films.The electrically insulating layers can be made, for example, of organic materials such as imide, epoxy or thermoset, metal oxides, semiconductor oxides, ceramics or diamond-like carbon.

[0009] The components may include a molding material covering at least portions of the components of the components. The molding material may be any suitable thermoplastic or thermosetting material. Various techniques may be used to cover the components with the molding material, such as compression molding or injection molding.

[0010] The Fig. 1A to 1E schematically show a method for manufacturing a component 100. A cross section through the component 100 obtained by the method is shown in Fig. 1E. First, an electrically insulating substrate 10 is provided (see Fig. 1A). A first electrically conductive layer 11 is applied over the electrically insulating substrate 10 (see Fig. 1B). A first semiconductor chip 12 is placed over the first electrically conductive layer 11 (see Fig. 1C). An electrically insulating layer 13 is applied over the first electrically conductive layer 11 (see Fig. 1D). The electrically insulating layer 13 may also cover the substrate 10 and the first semiconductor chip 12. A second electrically conductive layer 14 is applied over the electrically insulating layer 13 (see Fig. 1E).

[0011] The Fig. 2A to 2I schematically show a method for manufacturing a component 200, a cross section of which is shown in Fig. 2I. The Fig. The process shown in Figures 2A to 2I is a development of the Fig. 1A to 1E. The details of the manufacturing process described below can therefore equally be applied to the process of Fig. 1A to 1E can be applied.

[0012] In Fig. 2A, the electrically insulating substrate 10 is provided. The substrate 10 may be a plate made of a rigid material and may have a flat surface on which the components of the device 200 to be manufactured can be placed. The shape of the substrate 10 is not limited to any size or geometric shape; for example, the substrate 10 may be round or square. The substrate 10 may have a thickness in the range of 100 µm to 1 mm or even thicker. The electrically insulating substrate 10 may, for example, be made of a ceramic material such as Al 2 O 3or AlN. In one embodiment, the substrate 10 may consist of an electrically conductive or semiconductive body 15 and an electrically insulating layer 16 applied over the body 15, as in Fig. 2A. The body 15 may, for example, be a silicon substrate. The electrically insulating layer 16 may, for example, be made of organic materials such as imide, epoxy or thermoset, metal oxides, semiconductor oxides, ceramics, or diamond-like carbon. If the body 15 is made of a semiconductor material such as silicon, the electrically insulating layer 16 may be formed by doping the semiconductor material such that p-type and n-type semiconductors are in very close contact with each other. In the boundary region between the p-type and n-type semiconductors, a diode is formed that allows current to flow through the substrate 10 only in one direction, but not in the opposite direction. For example, the doping of the semiconductor body 15 may be performed such that no electricity can flow from the upper surface of the substrate 10 to its lower surface.

[0013] The thickness of the electrically insulating layer 16 may range from 1 to 20 µm and may depend on the voltages applied to the semiconductor chip 12. For example, if a maximum voltage of approximately 1000 V can be applied to the semiconductor chip 12 and the electrically insulating layer 16 has the capability of causing a voltage drop of 100 V per µm, the electrically insulating layer 16 should have a thickness of at least 10 µm to electrically isolate the lower surface of the substrate 10 from the voltage applied to the semiconductor chip 12.

[0014] The substrate 10 or the body 15 can be made of a material with a thermal conductivity of more than 10 W / (m K). Furthermore, the material of the substrate 10 or the body 15 can have a thermal conductivity of more than 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, or 150 W / (m K). Materials with a thermal conductivity of more than 10 W / (m K) include, for example, silicon and ceramic materials. The thermal conductivity of the substrate 10 can assist in dissipating the heat generated by the semiconductor chip 12. The material and thickness of the electrically insulating layer 16 can be selected such that the electrically insulating layer 16 allows adequate heat conduction from the semiconductor chip 12 to the body 15.

[0015] As in Fig. 2B, the first electrically conductive layer 11 is deposited on the substrate 10. If the substrate 10 consists of the body 15 and the electrically insulating layer 16, the first electrically conductive layer 11 can be deposited on the electrically insulating layer 16. The first electrically conductive layer 11 can have a thickness in the range of 10 to 400 µm, in one embodiment in the range of 80 to 120 µm and in particular approximately 100 µm. The first electrically conductive layer 11 can be structured such that only some areas of the substrate 10 are covered by the first electrically conductive layer 11. For example, after structuring, the first electrically conductive layer 11 can consist of an array of electrically conductive pads (contact areas) arranged on the substrate 10 (in Fig. 2B only two of the pads are shown.) Copper, iron, nickel, aluminum, or other metals or metal alloys can be used as materials for the first electrically conductive layer 11.

[0016] The first electrically conductive layer 11 can be fabricated using an electroplating process. For this purpose, a seed layer is first deposited on the upper surface of the substrate 10. The seed layer typically has a thickness of a few hundred nanometers. Materials such as palladium or titanium can be used for the seed layer.

[0017] The thickness of the seed layer can be increased by depositing another layer of an electrically conductive material on the seed layer. For example, a layer of copper can be electrolessly deposited on the seed layer. This copper layer can have a thickness of less than 1 µm. Subsequently, another layer of copper can be electroplated, which can have a thickness of more than 10 µm. The electroless copper deposition can also be omitted. The first electrically conductive layer 11 can be patterned after the deposition process of all its layers has been completed or after the deposition of the seed layer.

[0018] In one embodiment, the seed layer can be deposited using a vacuum deposition process, such as sputtering. For example, a layer of titanium with a thickness of, for example, approximately 50 nm is first sputtered, followed by a layer of copper with a thickness of, for example, approximately 200 nm. The copper layer can then be used as a seed layer for electroplating another copper layer with a thickness of over 10 µm.

[0019] In one or more embodiments, other deposition methods may also be used, such as physical vapor deposition, chemical vapor deposition, spin-on processes, spray deposition, or inkjet printing. Furthermore, the first electrically conductive layer 11 may be a metal film, such as a copper film, laminated to the top surface of the substrate 10. Vacuum, heat, and pressure may be applied for a time appropriate to adhere the first electrically conductive layer 11 to the substrate 10.

[0020] According to another embodiment, the substrate 10 and the first electrically conductive layer 11 can be prefabricated as a DCB (Direct Copper Bonded) substrate. A DCB substrate consists of a ceramic substrate to which a copper foil is attached.

[0021] As in Fig. 2C, the first semiconductor chip 12 and a second semiconductor chip 17, as well as possibly further semiconductor chips, are placed over the first electrically conductive layer 11. For example, a single semiconductor chip is mounted on each pad of the first electrically conductive layer 11. The semiconductor chips 12 and 17, as well as all other semiconductor chips described herein, may have been manufactured on a wafer made of semiconductor material. After sawing the wafer and thereby separating the individual semiconductor chips 12 and 17, the semiconductor chips 12 and 17 are transferred to the substrate 10 at greater distances than they were in the wafer interconnect. The semiconductor chips 12 and 17 may have been manufactured on the same wafer, but may also have been manufactured on different wafers. Furthermore, the semiconductor chips 12 and 17 may be physically identical, but may also contain different integrated circuits.

[0022] The semiconductor chips 12 and 17 may have a first electrode 18 on a first main surface 19 and a second electrode 20 on a second main surface 21 opposite the first main surface 19. The semiconductor chips 12 and 17 may, for example, be IGBTs (Insulated Gate Bipolar Transistors), vertical power diodes, or vertical power transistors, for example power MOSFETs. In the latter case, which is exemplified in Fig. 2C, the first and second electrodes 18 and 20 may be a drain and source electrode, respectively. Furthermore, the semiconductor chips 12 and 17 may have a third electrode 22 on the second main surface 21, which serves as a gate terminal in the case that the semiconductor chips 12 and 17 are power transistors. The semiconductor chips 12 and 17 are mounted on the first electrically conductive layer 11 such that their first main surfaces 19 face the first electrically conductive layer 11. The drain electrodes 18 may be electrically connected to the respective pads of the first electrically conductive layer 11.

[0023] The electrical connections between the drain electrodes 18 of the semiconductor chips 12 and 17 and the first electrically conductive layer 11 can be made, for example, by reflow soldering, vacuum soldering, diffusion soldering or adhesive bonding by using an electrically conductive adhesive.

[0024] When diffusion soldering is used as the joining technique, it is possible to use solder materials that, after the soldering operation, result in intermetallic phases at the interface between the first electrically conductive layer 11 and the respective semiconductor chips 12 and 17 due to interfacial diffusion processes. In this case, the use of Sn, AuSn, AgSn, CuSn, AgIn, AuIn, CuIn, AuSi, or Au solders is conceivable. If the semiconductor chips 12 and 17 are adhesively bonded to the first electrically conductive layer 11, it is possible to use electrically conductive adhesives based on epoxy resins and enriched with gold, silver, nickel, or copper to maintain electrical conductivity.

[0025] The electrically insulating layer 13 is deposited on the first electrically conductive layer 11 (see Fig. 2D). The electrically insulating layer 13 may also cover the exposed parts of the substrate 10 and the semiconductor chips 12 and 17. The electrically insulating layer 13 may be laminated as a film or sheet to the underlying structures by applying vacuum, heat, and pressure for a suitable time. It may also be provided that an electrically insulating material is deposited from a solution or a gas phase and can be built up layer by layer to a desired thickness. Techniques that can be used for this type of deposition include, for example, physical or chemical vapor deposition, spin coating, dispensing, dipping, injection molding, or compression molding.The electrically insulating layer 13 may be made of a polymer such as parylene, a photoresist material, a silicone, a molding material, or an inorganic ceramic-like material such as silicon-carbon compounds.

[0026] The electrically insulating layer 13 may cover the semiconductor chips 12 and 17, as shown in Fig. 2D. In one embodiment, at least the second main surfaces 21 of the semiconductor chips 12 and 17 may remain uncovered.

[0027] The electrically insulating layer 13 can be as in Fig. 2E. A plurality of cutouts or through-holes are formed in the electrically insulating layer 13 to expose at least portions of the source electrodes 20 and the gate electrodes 22 of the power transistors 12 and 17, as well as portions of the upper surfaces of the pads of the first electrically conductive layer 11, so that electrical connections can be made to those exposed regions. The electrically insulating layer 13 may be patterned, for example, by a stamping process, laser ablation, etching, photolithographic patterning, or any other suitable process known to one skilled in the art.

[0028] In a further embodiment, not shown in the figures, the electrically insulating layer 13 is supplied as a polymer film or sheet with multiple cutouts or through-holes before being laminated to the first electrically conductive layer 11. The cutouts or through-holes can be made by punching out regions of the polymer film or sheet. The size and arrangement of those regions correspond to the size and arrangement of the surfaces of the elements to be exposed.

[0029] The cutouts or through-holes created in the electrically insulating layer 13 can be filled with an electrically conductive material in order to form through connections 23 in the electrically insulating layer 13 (see Fig. 2F). The electrically conductive material may be a metal such as copper or aluminum, or a metal alloy such as SnAg or SnAu. The vias 23 may be formed using the same or similar methods as described above in connection with the production of the first electrically conductive layer 11.

[0030] The electrically insulating layer 13 acts as a platform for the deposition of the second electrically conductive layer 14 (see Fig. 2G). The second electrically conductive layer 14 may be deposited using the same or similar methods and materials as described above for the deposition of the first electrically conductive layer 11, for example, electrochemical deposition processes. The second electrically conductive layer 14 may have a thickness of more than 10 µm. The second electrically conductive layer 14 may be patterned to form external contact elements 24, 25, and 26, as shown in Fig. 2G. The external contact elements 24, 25, and 26 are electrically coupled via the through connections 23 to the source electrode 20, the gate electrode 22, and the drain electrode 18 of the semiconductor chips 12 and 17, respectively. It may be provided that the external contact element 24 is coupled to the source electrode 20 via two or more through connections 23, as shown by way of example in Fig. 2G. Analogously, the contact element 26 may be coupled to the drain electrode 18 via two or more vias 23. The external contact elements 24 to 26 may extend beyond the outline of the semiconductor chips 12 and 17. The external contact elements 24 to 26 allow the semiconductor chips 12 and 17 to be electrically contacted from outside the devices 200. It may also be provided that a redistribution layer is applied on the electrically insulating layer 13, including one or more wiring layers embedded in one or more dielectric layers.

[0031] As in Fig. 2H, the two semiconductor chips 12 and 17 are separated from each other by separating the substrate 10 and the electrically insulating layer 13, for example by sawing.

[0032] After the separation of the semiconductor chips 12 and 17, a mold transfer process can be carried out in order to encapsulate the components arranged on the substrate 10 with a molding material 27 (see Fig. 2I). The molding material 27 may encapsulate any portion of the device 200, but leaves at least portions of the external contact elements 24 to 26 uncovered. Furthermore, portions of the substrate 10 may also remain uncovered.

[0033] The mold material 27 may be made of any suitable thermoplastic or thermosetting material; in one embodiment, it may be made of a material commonly used in current semiconductor encapsulation technology. Various techniques may be used to cover the components of the device 200 with the mold material 27, for example, compression molding or injection molding.

[0034] The exposed surfaces of the external contact elements 24 to 26 can be used to electrically couple the device 200 to other components. This is exemplified in Fig. 2. There, a section of a component 300 is shown schematically, which includes the component 200 mounted on a printed circuit board 28, for example, a PCB (printed circuit board). The exposed surfaces of the external contact elements 24 to 26 may have been soldered to contact areas of the printed circuit board 28.

[0035] A heat sink or a cooling element may be mounted on the component 200 (not shown in Fig. 3). The heat sink or cooling element is electrically insulated from the first electrically conductive layer 11 by the electrically insulating substrate 10. However, if the thermal conductivity of the substrate 10 is high enough, the substrate 10 allows the transfer of heat generated by the semiconductor chip 12 to the heat sink or the exposed surface of the substrate 10, where the generated heat is dissipated. Furthermore, the heat generated by the semiconductor chip 12 can be transferred through the second electrically conductive layer 14 to the outer surface of the device 200, where it is dissipated.

[0036] For a specialist it is obvious that the Fig. 1E and Fig. 2I are intended only as exemplary embodiments and many variations are possible. For example, the components may include more than one semiconductor chip. One such embodiment is shown in Fig. 4. There, a component 400 is shown, which is a modification of the component 200 and contains the first semiconductor chip 12 and the second semiconductor chip 17. The two semiconductor chips 12 and 17 can be electrically coupled to one another using the second electrically conductive layer 14. In the Fig. In the device 400 shown in Figure 4, the drain electrode 18 of the first semiconductor chip 12 is electrically coupled to the source electrode 20 of the second semiconductor chip 17.

[0037] If the connection is as in Fig. 4, the component 400 can be used as a half-bridge. A basic circuit of a half-bridge 500 arranged between two nodes N1 and N2 is shown in Fig. 5. The half-bridge 500 consists of two series-connected switches S1 and S2. The semiconductor chips 17 and 12 can be implemented as the two switches S1 and S2, respectively. When compared with the Fig.In the component 400 shown in Figure 4, the node N1 is the drain terminal 18 of the second semiconductor chip 17, the node N3 arranged between the two switches S1 and S2 is the drain terminal 18 of the first semiconductor chip 12, and the node N2 is the source terminal 20 of the first semiconductor chip 12.

[0038] The half-bridge 500 can, for example, be implemented in electronic circuits for converting direct current voltages, so-called DC-DC converters. DC-DC converters can be used to convert a direct current input voltage supplied by a battery or accumulator into a direct current output voltage that is adapted to the demands of downstream electronic circuits. DC-DC converters can be embodied as step-down converters, where the output voltage is lower than the input voltage, or as step-up converters, where the output voltage is higher than the input voltage. Frequencies of several MHz or higher can be applied to DC-DC converters. Furthermore, currents of up to 50 A or even higher can flow through the DC-DC converters.

Claims

[1] A method for producing a component, comprising: Providing an electrically insulating substrate (10); Applying a first electrically conductive layer (11) over the electrically insulating substrate (10); Placing a first semiconductor chip (12) on a pad of the first electrically conductive layer (11); Applying an electrically insulating layer (13) over the first electrically conductive layer (11) and the first semiconductor chip (12); Structuring the electrically insulating layer (13) in order to expose electrodes (20, 22) on a main surface (21) of the first semiconductor chip (12) facing away from the first electrically conductive layer, as well as a portion of the pad; Providing electrical through connections (23) to the exposed electrodes (20, 22) and the exposed portion of the pad; and Applying a second electrically conductive layer (14) to a surface of the electrically insulating layer (13) and the electrical through connections (23) facing away from the first semiconductor chip (12), wherein external contact elements (24, 25, 26) are formed from the second electrically conductive layer (14). [2] The method according to claim 1, wherein the material of the electrically insulating substrate (10) has a thermal conductivity of more than 10 W / (m·K). [3] The method according to claim 1 or 2, wherein the first semiconductor chip (12) has a first electrode (18) on a first surface (19) and a second electrode (20) on a second surface (21) opposite the first surface (19). [4] Method according to one of the preceding claims, wherein the first semiconductor chip (12) is a power semiconductor chip. [5] A method according to any one of the preceding claims, comprising forming a via connection in the electrically insulating layer (13), whereby the first electrically conductive layer (11) is coupled to the second electrically conductive layer (14). [6] Method according to one of the preceding claims, wherein the electrically insulating substrate (10) comprises at least one semiconductor oxide, a ceramic material, an organic material, a metal oxide or a diamond-like carbon. [7] Method according to one of the preceding claims, comprising: Placing a second semiconductor chip (17) over the electrically insulating substrate (10); and Disassembling the electrically insulating substrate (10) after applying the second electrically conductive layer (14). [8] A method according to any one of the preceding claims, comprising performing a diffusion soldering process to connect the first semiconductor chip (12) to the first electrically conductive layer (11). [9] Method according to one of the preceding claims, comprising applying the first electrically conductive layer (11) by galvanic deposition. [10] Method according to one of claims 1 to 8, comprising applying the first electrically conductive layer (11) by laminating a film onto the electrically insulating substrate (10). [11] Component (100; 200; 400) comprising: an electrically insulating substrate (10); a first electrically conductive layer (11) applied over the electrically insulating substrate (10); a first semiconductor chip (12) placed on a pad of the first electrically conductive layer (11); an electrically insulating layer (13) applied over the first electrically conductive layer (11) and the first semiconductor chip (12); electrical through connections (23) arranged in the electrically insulating layer (13), which extend from a surface of the electrically insulating layer (13) facing away from the first semiconductor chip (12) to electrodes (20, 22) on a main surface (21) of the first semiconductor chip (12) facing away from the first electrically conductive layer and to a section of the pad; and a second electrically conductive layer (14) applied to the surface of the electrically insulating layer (13) facing away from the first semiconductor chip (12) and the electrical through connections (23), wherein external contact elements (24, 25, 26) are formed from the second electrically conductive layer (14). [12] Component (100; 200; 400) according to claim 11, wherein the substrate (10) is a semiconductor substrate (15) and has at least one electrically insulating surface (16). [13] The component (100; 200; 400) of claim 12, wherein the at least one electrically insulating surface (16) of the substrate (10) comprises at least one semiconductor oxide, an organic material, a metal oxide, a ceramic material, diamond-like carbon, or a pn junction. [14] Component (100; 200; 400) according to claim 11, wherein the substrate (10) is a ceramic substrate. [15] Component (100; 200; 400) according to one of claims 11 to 14, wherein the first electrically conductive layer (11) has a thickness of more than 10 µm. [16] Component (100; 200; 400) according to one of claims 11 to 15, wherein the second electrically conductive layer (14) is applied over the first semiconductor chip (12). [17] The component (400) of any one of claims 11 to 16, further comprising a second semiconductor chip (17) placed over the electrically insulating substrate (10), wherein the second electrically conductive layer (14) couples the first semiconductor chip (12) to the second semiconductor chip (17). [18] Component (100; 200; 400) according to one of claims 11 to 17, wherein the first semiconductor chip (12) is a power semiconductor chip. [19] Component (100; 200; 400) according to one of claims 11 to 18, wherein the material of the electrically insulating substrate (10) has a thermal conductivity of more than 10 W / (m·K). [20] Component (100; 200; 400) according to one of claims 11 to 19, wherein at least one of the external contact elements (26) is electrically coupled to the first electrically conductive layer (11).

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