I2C / SMBus ladders and ladder-activated ICs

Abstract

I2C / SMBus ladders and ladder-enabled ICs (devices) to enable daisy-chain I2C / SMBus communication. The devices are particularly useful in monitoring and / or maintaining high-voltage battery packs and other voltage stacks. The devices are powered from a respective voltage boost in the voltage stack and include level-shifting circuits, allowing them to operate with an input voltage up to the breakdown voltage of the level-shifting circuits. Various features are disclosed, including, but not limited to, unique data line drive, capacitive coupling between devices in a daisy-chain configuration with ladder clips for circuit protection, capacitive coupling charge cancellation, and clock stretching to accommodate chain latency.

Description

General state of the art1. Field of the invention

[0001] The present invention relates to the field of bus structures and methods. 2. State of the art

[0002] I 2 C is a serial multi-master computer bus developed by Philips that is used to connect low-speed peripherals to a motherboard, embedded system, or mobile phone. The name stands for Inter-Integrated Circuit.

[0003] The System Management Bus (abbreviated SMBus or SMB) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard, particularly power-related chips, such as a laptop's rechargeable battery subsystem. Other devices might include temperature sensors and flip switches. A device can provide manufacturer information, display its model / part number, save its state in the event of an interrupt, indicate various types of errors, receive control parameters, and return the state. The SMBus is generally neither configurable nor accessible by the user. The bus was defined by Intel in 1995. It carries the clock signal, data, and instructions and is based on the serial I / O architecture. 2 C-Bus protocol from Philips. Its clock frequency range is 10 kHz to 100 kHz. Its voltage levels differ from those of the I 2C, but devices belonging to the two systems are often successfully mixed on the same bus. The SMBus has a separate optional signal called ALERT#, which can be used by slaves to send an interrupt request to the control device.

[0004] These two buses are bidirectional buses, using a bidirectional clock line and a bidirectional data line, both of which are pulled high by pull-up resistors if they are not pulled low by one or more devices on the bus. Generally, the I2C bus and the SMBus are compatible, but there are some minor differences between the two. When the devices are stacked, as may be necessary in high-voltage battery stack monitors, for example, the required support circuitry is costly and extensive, requiring many optocouplers and microcontrollers to manage pack-to-pack communication.

[0005] For reference, the I2C bus specification, version 2.1, January 2000, and the System Management Bus (SMBus) specification, version 2.0, August 3, 2000, are incorporated herein by reference. Furthermore, the technical article "Digital Isolation Offers Compact, Low-Cost Solutions to Challenging Design Problems" (Analog Dialogue 40-12, Analog Devices Corporation, 2006) discloses an isolation technique that uses chip-scale microtransformers for digital isolation. The microtransformers are used, among other things, to transfer both data and power across the isolation barrier. In addition, an isolation solution for bidirectional I 2 C-Buses are described, which allows integration of the isolation device in a single housing. From the datasheet "ADuM1250 / ADuM1251" (Analog Devices Corporation, 2006) is a digital isolation device with bidirectional communication for I 2C interfaces are known. The device can be implemented in configurations with two bidirectional channels or with one bidirectional and one unidirectional channel. Hot-swap circuits are included to prevent data glitches when connecting a non-powered card to an active bus. US Patent 6,629,172 B1 discloses a system for automatically assigning unique addresses to multiple devices connected to an I 2 C-Bus and initially share the same address. The system uses a circuit enable input for each device and a cascading architecture in which the enable output of one device is connected to the enable input of the next device. A higher-level control unit communicates sequentially with each enabled device and assigns it a unique I 2C-bus address, after which the device only responds to this new address. From the technical application note "Microchip AN736 - An I2CTM Network Protocol for Environmental Monitoring" (Microchip Corporation, 2000, pages 1-5) an I 2 C network protocol for environmental monitoring systems. The protocol defines two message formats: data write messages and data request messages. Both contain a data length byte, an address offset byte, and an 8-bit checksum. For error handling, each slave node maintains a communication status, which is returned as the first data byte of each transmission. Brief description of the drawings Fig. Figure 1 illustrates the daisy-chain capability of devices according to the present invention as it may be used to monitor voltage stacks, such as batteries and battery cells connected in series. Fig.Figure 2 illustrates certain details unique to the devices according to a preferred embodiment of the present invention. Fig. 3A to Fig. 3C are diagrams illustrating the timing of various operations for a daisy-chained connection of multiple devices of the present invention. Detailed description of the preferred embodiments

[0006] The I2C / SMBus ladders of the present invention are communication systems for enabling daisy-chain I2C / SMBus communication. This eliminates the costly optocouplers in many applications, particularly in high-voltage battery packs commonly found in automotive or battery backup systems. A new stage of lithium battery development enables high-performance and high-energy packs, and the typical support circuitry for conventional I2C / SMBus communication devices is costly and bulky, requiring many optocouplers and microcontrollers to manage pack-to-pack communication. The present invention is also useful in other voltage stacks, such as those found in supercapacitors, fuel cells, and solar cells.

[0007] The I2C / SMBus standards and the common devices for communicating on these bus systems are very well known (see the specifications identified above and incorporated herein by reference), and accordingly, the present disclosure will focus on aspects of the present invention that differ from the common prior art devices and their communication protocols. The information transmitted will, of course, depend on the application and may be captured, formatted, etc., in the same manner as in the prior art. In the case of rechargeable batteries, the information would typically include the individual cell voltage and temperature.

[0008] Fig.Figure 1 illustrates a typical application of the I / 2C / SMBus ladder-enabled ICs of the present invention. As shown, the ICs may be chained together in a high-voltage battery stack. Each IC bridges a number of cells in a larger battery stack, the first of which is coupled to a host microcontroller. As will be seen below, the chains of the present invention differ somewhat from conventional chains in that each device recalculates values, such as the PEC (Packet Error Check) values and the data check bytes, performs level shifts, and forwards the received data and its data with the new PEC values and data check bytes to the next device in the chain. In particular, PEC is currently used in SMBus systems.However, in a standard system, for any given SMBus query, there is only one PEC, which is typically verified at each device but not recalculated. On the SMBus ladder of the present invention, however, the PEC is different at each device in the chain because the preceding bit stream is different for each stage. For example, in a 10-device Read All command, slave device #10 generates a PEC based on only 2 bytes of data. Slave device #09 verifies the PEC value it receives and generates a completely different PEC based on 4 bytes of data. Device #08 verifies the PEC value it receives and generates yet a third PEC based on 6 bytes of data, and so on, with the (total number - N)th device generating N-2 bytes and the corresponding PEC. The PEC verifies each connection, so there are 10 different PECs generated and 10 different verifications.A mechanism is provided to verify that each connection is happy with its result or that the data was not passed through.

[0009] Fig. Figure 2 is a diagram showing an embodiment of the I2C / SMBus conductor-enabled ICs of the present invention in an application example. The circuit is powered from each end of the corresponding battery stack element, which is designated GND here. M and GNDs. The IC itself consists of an upper portion and a lower portion separated by conventional level-shifting circuits 20. The lower portion is referred to as a slave and the upper portion as a master, in that the lower portion of each IC is the slave to the master portion of the IC below it or to the microcontroller if it is the first IC in the stack.

[0010] The master and slave components of each IC are powered separately. In a preferred embodiment, the ground connection for the slave component is the lower end of the battery stack element (GNDs), with the relatively low-voltage positive power (VDDs) for the slave component being derived from the voltage across the battery stack segment. For the master component, the ground connection is the lower end of the battery stack element (GNDs). M , where the positive power of relatively low voltage for the slave part is supplied from the slave power supply by a charge pump, which is generally marked with the number 22. In itself, the maximum input voltage (GND M - GNDs) is determined by the breakdown voltage of the transistors used in the level shift circuits.

[0011] In Fig. 2 are SDA s and SCL sthe data and clock lines. These lines are capacitively coupled between adjacent ICs in the stack. Furthermore, Fig. 2 only the interface circuits are shown, since the rest of the circuits and their function can be of a conventional type, except for the level shift between the two parts of the IC. For a signal that is applied to the SDA M -line is routed down the ladder to the IC shown, the signal passes through a Schmidt trigger and a glitch filter, through the level shift and the ladder on the SDA s -line. The delay between input and output for a bit traveling up or down the ladder is a small fraction of the bit time (see Fig. 30. For an outgoing signal running up the ladder when the SDA M-line is to be set low, transistor Q1 is turned on. If the line is to be set high, then the OR gate OR1 turns on transistor Q2 to couple a 50 kΩ pull-up resistor to the line. At the same time, the OR gate OR2 has triggered the ONE-SHOT circuit, which momentarily turns on transistor Q3 for 250 ns to couple a 3 kΩ pull-up resistor to the line for the same 250 ns. This results in a much faster (lower impedance) instantaneous pull-up, with the 50 kΩ resistor maintaining the high state on the line unless pulled down by another device on the bus. The same result is obtained in response to a write signal W applied to the SDA M -line for the data originating from this IC. The clamp circuit, which can be a Zener diode, only limits the upper voltage control on the SDA M-line, with the lower voltage output limited by the parasitic diodes in the IC. This provides protection against a charge or a charge deficiency on the coupling capacitors of Fig. 2 when a battery pack is replaced, and eliminates charge accumulation on the capacitors resulting from bus access contention during an acknowledgement. The output of the clock line SCL M In one embodiment, is simply latched using a push-pull output, although an open-drain design may also be used to advantage, as described below.

[0012] The interface circuits for the SDA s -Line are the same as the interface circuits for the SDA M -line, since both lines can send and receive information on the corresponding line. The clock line SCL sHowever, it has a protection clamp circuit to limit the voltage swing on the line to protect the input to the Schmitt trigger. It should be noted that the signals are effectively regenerated at each IC, maintaining signal and clock quality, relative timing, and duration regardless of signal direction.

[0013] A device ladder according to the present invention has a protocol definition and an analog definition as follows.

[0014] The main clock can be either a push / pull CMOS or an open-drain as in a conventional SMBus. If the clock is open-drain, then the clock stretching can be realized, which is Fig.3B for the ReadDevice instruction. With clock stretching, an addressed slave device can hold the clock line low after receiving a bit, indicating that it is not ready to process more data. The master communicating with the slave will attempt to raise the clock to send out the next bit, but it must verify that the clock line has actually been raised. If the slave stretches the clock, the clock line will still be low because the ICs can direct current to ground more efficiently than the pull-up resistors can provide. Without clock stretching, the ReadDevice instruction is not supported and is replaced by ReadAll instructions or those described below. Clock stretching allows "shrink-to-fit" timing during any Read instruction because the step delay is automatically handled by the stretched clock (see Fig.3B). This is equivalent to the clock-low extending of section 4.3.3, described starting on page 22 in the SMBus specification cited above, although in the SMBus specification it is used to enable communication between devices having different speed capabilities, while in the present invention it is used to account for ladder chain latency.

[0015] The present invention supports auto-addressing, which requires a change in the use of the address byte for a daisy-chained system. This change is still compatible with having conventional I2C / SMBus ICs on the bus, but it requires an inversion in the address bits for any daisy-chained device to allow a continuous increment of the address from IC to IC without having to wait for the full address to be received. The address byte is handled according to Table 1. Address byte Table 1 BIT NAME DESCRIPTION D7 1 This bit is always 1 to indicate communication with the IC. If this bit is 0, then the communication is intended for another device, and the IC will simply forward the message down the chain. This frees up addresses 0x00 to 0x7F. D6 ALL Setting ALL = 1 increments the address and forwards the command. This function also configures the slave addresses. Each device in the chain increments the address and forwards the command. Setting ALL = 0 only forwards the command to a specific address. D5 Addr1 Due to the requirements for auto-addressing the packs, the bits are encoded in reverse order to allow the address to be incremented without waiting for the full address to be received. D4 Addr2 D3 Addr3 D2 Addr4 D1 Addr5 D0 R / W 1 for Read command, 0 for Write command

[0016] Various aspects of the protocol are discussed below and illustrated in Figures 3A-3C as follows: Auto-addressing

[0017] The "HelloAll" command or any "WriteAll" or "ReadAll" command ( Fig. 3A) automatically assigns (or refreshes) sequential addresses to each device in the chain. (Note that in all three cases, D7 and D6 in Table 1 are set to 1.) These addresses can be used during a "WriteDevice" command to write to only one selected device in the chain.

[0018] However, for PEC management during ReadAll, each device needs to understand how many devices follow in the chain itself. The host also needs to understand how many total devices are in the chain. This allows the host (and each intermediate device) to correctly place the PEC byte at the end of the data stream. Each intermediate device must also recognize the received PEC byte, so it can verify data integrity. For this reason, the "RollCall" or "ReadAll Address" command (see Fig. 3A) specifically. Inserting and removing a pack

[0019] If a battery pack and its IC are removed or inserted, the alarm line (not shown) will stop pulsing to indicate an alarm. The host should execute a "RollCall" command to determine how many devices are now on the bus. At the same time, each device will automatically receive a new (the same or a different) address. Each device will display its address (in the same format normally used for addressing, with the LSB first). The last IC in the ladder, after communicating its address and finding no other IC in the ladder, will display OxFF. When OxFF is displayed, the last device has been found. This tells the host that there are no more devices.

[0020] After the host determines the device count, it should send a SetDeviceCount command (a type of WriteAll command). This informs each device how many devices are following, so each device knows when to generate or expect a PEC. Note that a failed PEC could also indicate a change in the device count. Communication timeout

[0021] If the SCL remains s If the input is high or low for more than 10 ms, any operation is aborted, and the device behaves as if it detects a stop condition. The host can ensure that all devices are in a "ready to communicate" state by remaining idle for more than 10 ms. Guided pull-ups

[0022] SDA M and SDA sare a guided open-drain system. In fact, the SDA line is only driven during certain bits, and the pullup is not driven when the pulldown is driven. This behaves almost the same as CMOS logic, since the pullup and pulldown devices do not normally conflict. During any write phase, the SDA uses M -line (unless the pulldown FET is on), and during a read phase the SDA uses s - line has its pullup. In addition, the host may have a normal pullup. During the ACK bit of any write phase, the master and the slave are in conflict because the master operates its pullup, but the slave can set low for ACK. This will cause a certain charge to accumulate on the IC to the IC coupling capacitors (see Fig.2). Since this can only happen for one bit per byte, only a very small charge will have accumulated on the coupling capacitors, provided that the RC time constant between the pull-up resistors and the coupling capacitors is several times larger than the maximum ACK bit length.

[0023] The only bit contention times occur during the acknowledgement bits. During an acknowledgement, the side receiving the acknowledgement must use its own pullup to listen because there is no guarantee that the other side is even present to talk. Active flank

[0024] If the SDA M is in a write mode (the W bit is set), or the SDA sIf the device is in read mode, the data line has an active pulldown and is driven with a fast 3 kΩ pullup for the first 250 ns. During the remainder of the write phase, the 50 kΩ pullup is used to maintain the DC state. This fast edge enables fast communication, while the slower 50 kΩ reduces contention across the coupling capacitor during the acknowledge bit (where one side is driven low and the other side uses its pullup to listen).

[0025] The present invention eliminates costly optocouplers in many applications, particularly in high-voltage battery packs commonly found in automotive or battery backup systems. A new stage of lithium battery development enables high-performance and high-energy packs, and the usual support circuitry is expensive and bulky, requiring multiple optocouplers and microcontrollers to manage pack-to-pack communication. Analog features of the invention include: suppression of DC voltage differences between packs. The size of the voltage tolerance is determined by the coupling capacitors.

[0026] Clock and data signals are regenerated at each node in the chain, maintaining signal integrity.

[0027] The level shifting is performed cleanly within a controlled integrated circuit environment.

[0028] GNDM and VDD M are "hard-wired" to the ground GNDS of the upper neighbor via a capacitor. This capacitor connection provides front-end power rejection for pack voltage fluctuations and pack-to-pack AC voltages.

[0029] GND M and VDD M are generated by a charge pump from the GNDs and VDDs. GND M is DC-connected to PCKP, so that the voltage at the GND M1 = GND S2 and VDD M1 = VDD S2 , although these voltages do not need to be exactly the same.

[0030] Capacitive coupling ensures DC blocking between the interfaces, which improves high voltage compatibility at the interface.

[0031] The system has a maximum frequency due to the SCL / SDA pullup resistors. The exemplary embodiment achieves a data rate of > 200 kbps including the 250 ns glitch filtering.

[0032] The pull-up resistors are configured to reduce the contention time, which is defined as the time it takes for one side of a coupling capacitor to be raised to a different state than the other side. Reducing the contention to just the ACK bit reduces the required value of the coupling capacitors.

[0033] The system exhibits a minimum frequency. Because of the integrated pull-up resistors, the only time any bit contention exists across the coupling capacitor is during an ACK / NACK read operation. The receiving side must use its pull-up, even if the sending side performs the pull-down (or doesn't). This bit contention ultimately creates a voltage across the coupling capacitor, which will reduce the noise margin on subsequent bits. This capacitor voltage is eliminated with the clamp circuits on the communication pins.

[0034] Packet error checking is included to tolerate communication errors.

[0035] The concatenated ladders of the present invention have several key features. In particular: Each stage is DC isolated by the capacitors.

[0036] The devices are “auto-addressed” according to their sequence in the chain.

[0037] The invention supports "shrink-to-fit" timing using a clock echo. "Shrink-to-fit" means that communication is precisely adapted to the chain latency.

[0038] The protocol supports broadcast read and write to maximize bus utilization.

[0039] Supply and common-mode rejection occur within the IC and are not dependent on external components.

[0040] The protocol is robust, noise-insensitive and fault-tolerant.

[0041] The present invention ICs can be implemented in conventional integrated circuits or, through the use of hardware controlled by on-device software, in any IC operating under stored program control. Although a preferred embodiment of the present invention has been disclosed and described herein for purposes of illustration and not limitation, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Likewise, the invention may be practiced without the use of the specific circuits or the entire protocol set forth herein.

Claims

[1] I2C / SMBus compatible device comprising: an integrated circuit with: first and second power input terminals, wherein the second power input terminal is provided for connection to a higher voltage than the first power input terminal; a first integrated circuit portion forming a slave section powered by a voltage from the first power input terminal and a voltage derived from the voltage at the second power input terminal, the slave section having an SDAs data line and an SCLs clock line for receiving and transmitting data and clock signals, respectively; a second integrated circuit portion forming a master section fed by a voltage from the second power input terminal and a voltage derived from the slave section by a charge pump (22), the master section comprising an SDA M-Data line and an SCL M -Clock line for receiving and transmitting data or clock signals; wherein the first integrated circuit portion and the second integrated circuit portion are coupled by level shift circuits (20) to pass the clock and data signals between the master and slave sections, whereby a plurality of such devices may be electrically stacked, with each successive device having its first power input terminal connected to the second power input terminal of the previous device in the stack. [2] The device of claim 1, wherein when multiple devices are electrically stacked, each device is arranged to check the packet error checking (PEC) values it receives and calculate new PEC values for the data it forwards to the next device in the stack. [3] The device of claim 1, wherein the first integrated circuit portion is powered by the first and second power input terminals, the first power input terminal being the circuit ground for the first integrated circuit portion, and the second integrated circuit portion is powered by a voltage charge-pumped from a voltage powering the first integrated circuit portion, the second power input terminal being the circuit ground for the second integrated circuit portion. [4] The device of claim 1, wherein each of the first and second integrated circuit portions maintains the signal and clock quality, relative timing, and duration independent of the signal direction propagating through the device. [5] The device of claim 1, further comprising voltage clamps on the SDA S-data line, the SCLs clock line and the SDAM data line, whereby when several electrically stacked devices are capacitively coupled, the SDA S -Data line, the SCLs clock line and the SDA M -Data line is protected against charge accumulation on the capacitive coupling. [6] The device of claim 5, further comprising a voltage clamp on the SCL M -Data line, whereby when several devices in a stack are capacitively coupled, the SCL M -Clock line are protected against charge accumulation on the capacitive coupling. [7] The device of claim 1, wherein the device is adapted to receive additional data inputs on other lines, and wherein the slave section is adapted to receive the additional data using the SDA S -data line and an SCLs clock line of its slave part. [8] A device according to claim 1, wherein the device has an auto-addressing capability whereby when a plurality of devices are electrically stacked and connected to a control device, each device, upon receiving a first command from the control device, will assign itself an address in an address sequence corresponding to its position in the stack and communicate this address to the control device, wherein the last device in the stack will also communicate that it is the last device in the stack. [9] The apparatus of claim 1, wherein the apparatus comprises packet error correction. [10] The device of claim 9, wherein the device is informed in response to a second command how many devices electrically stacked follow the device. [11] The device of claim 1, wherein the SDA M-Data line is in a write mode or the SDA5 line is in a read mode, the corresponding data line has an active pulldown and is initially controlled by a relatively low pullup resistor in the pullup and is controlled by a relatively high pullup resistor during the rest of the write phase. [12] The device of claim 1, wherein the device includes the capability of clock stretching during a read operation to account for ladder chain latency when multiple devices are electrically connected in a stacked manner.

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