Device and method for its production

Abstract

Device comprising: a vertical power semiconductor chip (10) with an epitaxial layer (15) and a bulk semiconductor layer (16), a first contact point (11) arranged on a first main surface of the power semiconductor chip (10), a second contact point (13) arranged on a second main surface of the power semiconductor chip (10), the second main surface being arranged opposite to the first main surface, and an electrically conductive carrier (20) which is fastened to the second contact point (13), wherein a distance between the electrically conductive carrier (20) and the epitaxial layer (15) is equal to or less than 50 µm and the bulk semiconductor layer (16) has a thickness of equal to or less than 15 µm, wherein the electrically conductive carrier (20) exerts a tensile stress on the epitaxial layer (15) in the unencapsulated state of the device which is greater than 50 MPa.

Description

The invention relates generally to semiconductor chip encapsulation and more particularly to encapsulation of a power semiconductor chip.Semiconductor device manufacturers are constantly striving to increase the performance of their products while wishing to reduce their manufacturing costs. A cost-intensive field in the production of semiconductor devices is the encapsulation of the semiconductor chips. As those skilled in the art will appreciate, integrated circuits are fabricated in wafers which are then singulated to produce semiconductor chips. One or more semiconductor chips are arranged in a package to protect them from environmental and physical influences and to ensure reliability and performance. Packaging semiconductor chips increases the cost and complexity of manufacturing semiconductor devices, as the packaging designs are not only intended to provide protection, they are also intended to allow the transmission of electrical signals to and from the semiconductor chips.The publication US 2007 / 0 166 877 A1 relates to electronic components, in particular electronic components which comprise at least one vertical semiconductor power switch and at least one further semiconductor component. US 2010 / 0 051 963 A1 relates to a power transistor having a carrier layer made of a first material and an active region made of a second material. US 2005 / 0 029 666 A1 relates to a semiconductor component in which the circuit elements (chip parts) installed on a wiring part are sealed with resin.An object on which the invention is based can be seen in the provision of a power semiconductor device which has good electrical performance. Furthermore, the invention aims to provide a method for manufacturing a power semiconductor device having a good electrical performance.The object underlying the invention is achieved by the features of the independent claims. Further developments and exemplary embodiments are specified in the dependent claims.The accompanying drawings are intended to provide a further understanding of the embodiments. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. FIG. 1 shows a cross-sectional view of an embodiment of a semiconductor device having a power semiconductor chip mounted on an electrically conductive carrier; FIG. 2 is a simplified illustration of the power semiconductor device of FIG. 1 showing the tension applied to the power semiconductor die by the carrier; FIG. 3 is a cross-sectional view of a detailed embodiment according to the embodiment shown in FIG. 1 ; FIG. 4 is a graph illustrating the probability distribution of on-resistance for a total of identical power semiconductor chips mounted on a carrier in a stress-loaded state as shown in FIG. 3 and for a total of identical power semiconductor chips operated in the absence of external tension; FIG. 5 shows a cross-sectional view of an embodiment with the semiconductor device of FIG. 1 encapsulated in an encapsulating body embedding the power semiconductor die; FIG. 6 shows a cross-sectional view of an embodiment with the semiconductor device of FIG. 1 encapsulated in an encapsulating body embedding the power semiconductor die and the carrier; FIG. 7 is a graph illustrating the stress in units of MPa as a function of chip area in units of mm 2 for power semiconductor chips having different thicknesses; FIG. 8 is a diagram of the semiconductor device of FIG. 2 encapsulated in an encapsulation body 50 showing tension weakening and downward pressure strengthening applied to the top major surface of the power semiconductor die due to an encapsulation process; and FIG. 9 is a graph depicting chip deflection in units of μm as a function of chip area in units of mm 2 for power semiconductor chips having different thicknesses.In the following description, reference is made to the accompanying drawings, in which there is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top," "bottom," "front," "back," "front," "back," etc. is used with reference to the orientation of the figure(s) described. Since components of embodiments may be arranged in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Of course, other embodiments may be utilized and structural or logical changes may be made without departing from the concept of the present invention. The following detailed description is therefore not to be taken in a limiting sense.It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically stated otherwise.As used in this specification, the terms "coupled" and / or "electrically coupled" are not intended to mean that the elements must be directly coupled to one another-intermediate elements may be provided between the "coupled" or "electrically coupled" elements.Devices including power semiconductor chips will be described below. The power semiconductor chips may be of different types, may be manufactured by different technologies and may include, for example, integrated electrical, electro-optical or electro-mechanical circuits or passive elements. The power semiconductor chips need not be made of a specific semiconductor material, for example Si, SiC, SiGe, GaAs, and may further include inorganic and / or organic materials other than semiconductors, such as discrete passive elements, antennas, insulators, plastics or metals. Furthermore, the devices described below may comprise further integrated circuits for controlling the power integrated circuits of the power semiconductor chips.The power semiconductor chips may include power MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction field effect transistors), power bipolar transistors or power diodes. In particular, power semiconductor chips having a vertical structure are involved, that is to say that the power semiconductor chips are produced in such a way that electrical currents can flow in a direction perpendicular to the main surfaces of the power semiconductor chips.A power semiconductor chip having a vertical structure may have pads on its two main surfaces, i.e. on its top and bottom. As an example, the source and gate of a power MOSFET may be on one major surface while the drain of the power MOSFET may be on the other major surface. The pads may be made of aluminum, copper, or any other suitable material. One or more metal layers may be applied to the contact pads of the power semiconductor chips. The metal layers may be, for example, titanium, nickel vanadium, gold, silver, copper, palladium, platinum, nickel, chromium, or any other suitable material. The metal layers need not be homogeneous or made of only one material, i.e. different compositions and concentrations of the materials contained in the metal layers are possible.The power semiconductor chip may be composed of a bulk semiconductor layer and an epitaxial layer formed on the bulk semiconductor layer. The epitaxial layer may have a thickness greater than the thickness of the bulk semiconductor layer. In particular, the epitaxial layer may have a thickness of equal to or greater than 20 μm, 30 μm, 40 μm, or 50 μm. Typically, the greater the thickness of the epitaxial layer, the higher the operating voltage of the power semiconductor chip. The bulk semiconductor layer may have a thickness of equal to or less than 30 μm, 20 μm, or 15 μm.An electrically conductive carrier can be applied to the power semiconductor chip. The electrically conductive carrier can significantly affect the electrical properties of the power semiconductor chip by mechanical interaction with the power semiconductor chip. The carrier may be a lead frame (lead frame), i.e. a structured metal sheet. The lead frame may have a thickness equal to or greater than 1.0 mm, 1.5 mm, or 2.0 mm to apply a mechanical stress to the power semiconductor chip.An encapsulation material may at least partially cover the power semiconductor chip to form an encapsulation body. The encapsulation material may be based on a polymer material, i.e. it may comprise a base material (hereinafter also referred to as matrix material) consisting of any suitable thermosetting, thermoplastic or thermosetting material or laminate (prepreg). In particular, a matrix material based on epoxy resin can be used. The matrix material may embed a filler material, for example SiO 2-, Al 2 O 3- or AlN particles, in order to adjust the physical properties of the encapsulation body, such as e.g. the modulus of elasticity or the CTE (coefficient of thermal expansion).After its deposition, the encapsulation material may be only partially cured and may then be cured and / or fully cured by the application of energy (e.g., heat, UV light, etc.) to form the solid encapsulation body. Various techniques may be used to form the encapsulation body from the encapsulation material, for example compression molding, transfer molding, injection molding, powder molding, liquid molding, dispensing or laminating. Heat and / or pressure may be used to apply the encapsulation material.The encapsulation body can be designed such that it significantly influences the electrical properties of the power semiconductor chip by mechanical interaction with the power semiconductor chip. The encapsulating body may have an elastic modulus of equal to or greater than 50000 MPa and / or a chip coverage thickness (i.e., thickness over an upper surface of the power semiconductor chip) that is large enough to satisfy the condition that the ratio of the chip coverage thickness and a sum of the thickness of the power semiconductor chip, the thickness of the connection layer, and the thickness of the electrically conductive carrier is equal to or greater than 3 to apply compression or downward pressure to the power semiconductor chip.FIG. 1 schematically illustrates a power device 100 in cross-section. The device 100 comprises a power semiconductor chip 10. the power semiconductor chip 10 has one or more first contact pads 11 arranged on a first main surface 12 of the power semiconductor chip 10 and has one or more second contact pads 13 arranged on a second main surface 14 of the power semiconductor chip 10 opposite to the first main surface 12. Furthermore, the power device 100 comprises a carrier 20 on which the power semiconductor chip 10 is mounted.The power semiconductor chip 10 is a vertical device, i.e. electric currents can flow in a direction perpendicular to the main surfaces 12, 14 of the power semiconductor chip 10. In an embodiment, the power semiconductor chip 10 is a power transistor and the first (n) pad(s) 11 may form a source terminal and the second (n) pad(s) 13 may form a drain terminal. In this embodiment, a gate terminal (not shown) is typically arranged on the first main surface 12 of the power semiconductor chip 10. In other embodiments, the power semiconductor chip 10 may be a power diode and the first pad(s) 11 may form, e.g., an anode terminal, while the second pad(s) 13 may form a cathode terminal of the power diode, or vice versa.In particular, the power semiconductor chip 10 may include an epitaxial layer 15 arranged on a bulk semiconductor layer 16, for example. One skilled in the art well knows several semiconductor processing techniques to fabricate such a structure. In short, the power semiconductor chips 10 may be made of a wafer made of semiconductor material. The upper surface of the wafer may correspond to the upper surface of the bulk semiconductor layer 16 in FIG. 1. The wafer, for example a silicon wafer, may be doped with suitable impurity atoms (dopants) to improve the electrical conductivity of the semiconductor material of the bulk semiconductor layer 16. As an example, the wafer may be doped to obtain an n+-doped bulk silicon layer 16 with high electrical conductivity.Still during front-end wafer processing, an epitaxial layer 15 may be formed on the upper surface of the wafer. Any epitaxy methods known to those skilled in the art may be used, e.g., MBE (molecular beam epitaxy), LPE (liquid phase epitaxy), etc. The epitaxial layer 15 is designed to include a sequence of p-n junctions to form the semiconductor active region of the vertical power device.The first pad(s) 11 is(are) formed on the upper surface 12 of the epitaxial layer 15. This step may still be performed during wafer processing, i.e., during front-end processing. In other embodiments, the first pad(s) 11 may be(can) formed on the individual power semiconductor chips 10 after dicing the wafer into a plurality of power semiconductor chips 10.Similar to the first pad(s) 11, the second pad(s) 13 is(are) formed either on the intact wafer during wafer processing or on the power semiconductor chips 10 singulated from the wafer.The power integrated circuits and possibly other integrated circuits may be electrically accessed via the pads 11, 13. The contact pads 11, 13 may be made of a metal, for example, aluminum or copper, and may have any desired shape and size.The power semiconductor chip 10 may be mounted on the upper surface of the carrier 20. A bonding layer 17 of solder material, e.g. a diffusion solder material comprising e.g. AuSn and / or other metal materials, may be used to electrically connect and mechanically attach the second contact pad(s) 13 to the carrier 20.The carrier 20 may be of various types. In an embodiment, the carrier 20 may be a patterned metal sheet or a patterned metal plate, e.g. a lead frame. The carrier 20 may include metal plate portions separated by spaces. In another embodiment, the carrier 20 may be a continuous, non-structured metal plate or a continuous, non-structured metal plate. The carrier 20 may be manufactured by a stamping and / or milling process. The metal constituting the support may comprise, for example, one or more metals selected from the group consisting of copper, aluminum, nickel, gold or any alloy based on one or more of these metals. The carrier (e.g. leadframe) may consist of a single bulk metal layer or a multi-layer metal structure. The carrier 20 may serve as a heat sink for dissipating the heat generated by the power semiconductor chip 10.D 1 is the distance between the carrier 20 and the epitaxial layer 15, that is, the distance between the upper surface of the carrier 20 and the beginning of the epitaxial layer 15 (in the example shown in FIG. 1, the beginning of the epitaxial layer 15 is the transition between the bulk silicon layer 16 and the epitaxial layer 15). The distance D 1 is a parameter having a strong influence on the degree of stress applied to the epitaxial layer 15 of the power semiconductor chip 10 through the carrier 20. Typically, the CTE of the carrier 20 and the CTE of the power semiconductor chip 10 are significantly different. Generally, the CTE of the carrier 20 may be larger than the CTE of the power semiconductor chip 10 by a factor of e.g. 5, 6, 7, 8, 9, 10 or even more. After soldering, therefore, since the contraction of the carrier 20 is considerably larger than the contraction of the power semiconductor chip 10, the carrier 20 (e.g., lead frame) applies a high tensile stress to the power semiconductor chip 10.This is illustrated in FIG. 2, which schematically shows the semiconductor device 100. The contraction of the carrier 20 is indicated by the arrows "contraction". The tensile stress applied to the power semiconductor chip 10 is indicated by the arrows "tensile stress". As can be seen in FIG. 2, the tensile stress in a vertical direction acts on the peripheral region of the power semiconductor chip 10, that is to say in a direction which is substantially perpendicular to the extent of the carrier 20 which runs in a horizontal direction. The tensile stress is accompanied by deflection (warping), i.e., the semiconductor device 100 is forced into an arc-shaped or convex shape. In FIG. 2, the curvature of the power semiconductor chip 10 and the carrier 20 is exaggerated for illustration. Furthermore, dashed lines correspond to the rectilinear extension of the power semiconductor chip 10 and the carrier 20 before soldering.The shorter the distance D 1, the greater the tensile stress acting on the power semiconductor chip 10. According to an embodiment, it has been found that a high tensile stress acting on the epitaxial layer 15 improves the electrical characteristics of the power semiconductor chip 10. Specifically, the on-state resistance (Ron) of the power semiconductor chip 10 is significantly reduced by enhancing the external tensile stress acting on the epitaxial layer 15 of the power semiconductor chip 10.In other words, the tensile stress is selectively introduced into the epitaxial layer 15 of the power semiconductor chip 10 by dimensioning D1=50 μm. Furthermore, smaller dimensions such as D1=40 μm or 30 μm or 20 μm or even 10 μm may be used. This is in contrast to the conventional method in which large dimensions of D1 are used to compensate for the various CTEs and thus reduce the tensile stress acting on the power semiconductor chip 10.The tensile stress acting on the epitaxial layer 15 can be strengthened by using a bonding layer 17 made of brittle brazing materials such as AuSn-based brazing materials. AuNb has a high modulus of elasticity of about 59000 MPa. Other lead-free solder materials may also be used. This is in contrast to the conventional method in which deformable or elastic bonding materials such as e.g. electrically conductive adhesives or Pb-based solder materials are used to compensate for the various CTEs and thus reduce the tensile stress acting on the power semiconductor chip 10.The tensile stress acting on the epitaxial layer 15 can be strengthened by using a thin joining layer 17 made of brazing material. The joint layer 17 of brazing material may be, for example, not thicker than or thinner than 10 μm, 5 μm, 2 μm, or even 1 μm. Further, the second contact pad 13 may have a thickness equal to or less than 2 μm or even 1 μm. This is in contrast to the conventional method in which interconnection layers of considerable thickness are used to compensate for the various CTEs and thus reduce the tensile stress acting on the power semiconductor chip 10.The tensile stress acting on the epitaxial layer 15 of the power semiconductor chip 10 may be strengthened using diffusion solder materials. Diffusion solder materials such as AuSn, CuSn, AgSn may have intermetallic phases formed from at least two solder components. The first of the brazing components has a melting point that is lower than the melting point of the intermetallic phases and the second of the brazing components has a melting point that is higher than the melting point of the intermetallic phases. Moreover, the diffusion solder may comprise, in its diffusion area, nanoparticles of a filler material, which may prevent the formation of microcracks originating from the intermetallic phases in the event of a thermomechanical stress. Compounds produced by diffusion solder materials are brittle, may have a high modulus of elasticity as mentioned above, and may not be thicker than mentioned above. Consequently, lead-free diffusion solder joints are very suitable for the bonding layer 17 to effectively apply the tension generated by the carrier 20 to the power semiconductor chip 10.The tensile stress acting on the epitaxial layer 15 can be strengthened using a thin bulk semiconductor layer 16. In one embodiment, the bulk semiconductor layer 16 may be, for example, no thicker than or thinner than 30 μm, in particular 20 μm, 15 μm or even 10 μm. This may be achieved by thinning the wafer at its bottom side to create a common planar wafer surface with the second main surface 14 of the power semiconductor chip 10. The thinning can be carried out, for example, by grinding or lapping. While abrasive tools use a grinding wheel, lapping tools use a fluid ("slurry") loaded with "rolling" abrasive particles that act between two surfaces. CMP (chemical mechanical polishing) may be employed, for example. Because the bulk semiconductor layer 16 has no effect on the performance of the semiconductor device 100 (it simply provides a highly conductive transition to the second pad 13), wafer thinning can be continued until a minimum grind thickness tolerance is reached. In an embodiment, the bulk semiconductor layer 16 may be no thicker than or thinner than 10 μm, 5 μm, or even 2 μm. This may be achieved by etching the wafer at its bottom side to create a common planar wafer surface with the second main surface 14 of the power semiconductor chip 10. Because the bulk semiconductor layer 16 has no operational effect on the performance of the semiconductor device 100 (except for providing a highly conductive transition to the second pad 13), the etching of the wafer may be continued until a minimum etch thickness tolerance is reached.Using one or more of these methods, the tensile stress acting on the epitaxial layer 15 may be set to about hundreds of MPa, e.g., more than 200 MPa, 500 MPa, or even 1000 MPa. Even a tensile stress not lower than one or more GPa can be obtained. Note that the tensile stress must not exceed the tensile stress at break, which is about 5 GPa for a typical silicon power chip with an operating voltage of about 500 V.It should be noted that other design parameters may be used to adjust the degree of tensile stress applied to the epitaxial layer 15. As an example, the thickness Dcarof the carrier 20 may have some effect on the tensile stress load. According to an aspect, a ratio of the thickness Dcar of the electrically conductive carrier 20 and a sum of the thickness Dchip of the power semiconductor chip 10, the thickness Dpad of the second contact pad 13 and the thickness Dcon of the connection layer 17 is equal to or greater than 3, i.e.This ratio may even be equal to or greater than 5, in particular 7, more particularly 10. The greater the thickness Dcar of the carrier 20, the more efficient the transport of heat from the semiconductor device 100.FIG. 3 is a cross-sectional view of a detailed exemplary embodiment according to the embodiment shown in FIG. 1. The semiconductor device 200 shown in FIG. 3 is a power MOSFET having an operating voltage of 600 V. The carrier 20 is a lead frame (lead frame) made of copper, for example, having a thickness Dcar=1.3 mm. In general, Dcar may be equal to or greater than 1.0 mm or even 2.0 mm. The bonding layer 17 is made of AuSn diffusion solder and has a thickness of 1.2 μm. The second pad 13 includes a pad lower layer 13 aconsisting of aluminum (Al), a pad upper layer 13 bsecuring the pad lower layer 13 aand made of titanium (Ti), and a plating layer 13 csecuring the pad upper layer 13 band made of nickel vanadium (NiV). These second pad layers 13 a, 13 b, 13 cmay have thicknesses of about 400 nm (Al layer), 400 nm (Ti layer), and 75 nm (NiV layer), for example. Consequently, the total thickness Dcon+Dpad of the connection layer 17 and the second pad 13 is about not greater than 2.075 μm. This thickness Dcon+Dpad could also be easily reduced to be equal to or less than 2.0 μm, if desired.Referring to FIG. 3, the bulk semiconductor layer 16 may be made of n+-doped silicon and may have a thickness Dbulk(see FIG. 1 ) of about 17.5 μm. This thickness can be obtained by wafer grinding. The doped bulk semiconductor layer 16 may substantially behave like a metal. The degenerate semiconductor-metal transition between the bulk semiconductor layer 16 and the lower contact point layer 13 aof the second contact point 13 also has a high electrical conductivity. The bulk semiconductor layer 16 and the second pad 13 constitute the drain terminal of the power MOSFET.The epitaxial layer 15 constitutes the active region of the power semiconductor chip 10. In this example, it has a thickness Depi (see FIG. 1 ) of 52.5 μm, which enables an operating voltage of approximately 600 V. The epitaxial layer 15 includes a series of p-n junctions that lie within a region of the epitaxial layer indicated by the arrow p-n in FIG. 3. In general, the epitaxial layer 15 may have a thickness of equal to or greater than 20 μm, in particular equal to or greater than 30 μm, further specifically equal to or greater than 40 μm, or in particular equal to or greater than 50 μm. As a rule of thumb, 100 V operating voltage may require about 9 μm epitaxial layer thickness. Consequently, the vertical power semiconductor chip 10 may have an operating voltage of equal to or greater than 200 V, in particular equal to or greater than 300 V, furthermore in particular equal to or greater than 400 V or in particular equal to or greater than 500 V.A highly conductive plug 41 is provided within the epitaxial layer 15. The highly conductive plug 41 is electrically connected to the p-n junctions of the epitaxial layer 15 to form a source contact thereof.The conductive plug 41 is covered with a first insulation layer 42 such as an oxide layer provided on the epitaxial layer 15. The insulation layer 42 is referred to as EOX in FIG. 3 and is configured to have openings through which the conductive plug 41 can be accessed.A first patterned metal layer 43 may be disposed over the isolation layer 42. The first patterned metal layer 43 may serve to provide electrical functionality such as electrostatic shielding of the power MOSFET. Further, additional patterned metal layers not shown in the cross-sectional view of FIG. 3 may be disposed near the top surface 12 of the epitaxial layer 15, e.g., patterned metal layers for providing additional connectivity and / or signal routing, such as a patterned metal layer, to form a gate contact of the p-n junctions of the epitaxial layer 15.A second patterned isolation layer 44, such as an oxide layer, may be disposed over the first patterned metal layer 43. The second insulation layer 44 is referred to as ZwOXin FIG. 3 and is configured to have openings through which the conductive plug 41 can be electrically contacted by a second metal layer 45. The second metal layer 45 may be made of AlSiCu, for example, and may be the source terminal of the power MOSFET. Further, a polymer layer 46 may be provided to cover the second metal layer 45. A polymeric material such as parylene, a photoresist material, imide, epoxy, thermoset, or silicone may be used.As an example, the layers 42, 43, 44, 45 and 46 may have the following dimensions in thickness. The first insulation layer 42 may have a thickness Dins 1 of 2.4 μm, the second insulation layer 44 may have a thickness Dins 2 of 1.5 μm, the first metal layer 43 may have a thickness Dmet of 5.0 μm, and the polymer layer 46 may have a thickness Dpoly of 6.0 μm. It should be noted that the dimensions, materials and the provision of these layers are exemplary and subject to changes according to the requirements of the semiconductor design.FIG. 4 is a diagram illustrating the probability distribution of Ron for a total of N identical power semiconductor chips 10 mounted on a carrier (lead frame) 20 as shown in FIG. 3 and for a total of N identical power semiconductor chips 10 operated in the absence of a tension stress. The x-axis shows Ron in units of mOhm, while the y-axis is the probability in the range of 0 to 1, drawn on a logarithmic scale. FIG. 4 illustrates that Ron is significantly different for voltage-loaded power semiconductor chips 10 (measurement results appearing along the line A) and power semiconductor chips 10 in an external voltage free state (measurement results appearing along the line B). While an average value of Ron=90 mOhm is obtained in an external voltage free state, the application of external voltage reduces the resistance in the on state Ron to an average value of Ron=65 mOhm. In this example, therefore, a mean reduction of Ron of 38% with respect to the target value of 65 mOhm can be achieved by applying an external tension. In other words, applying external stress to the p-n junctions in the epitaxial layer 15 significantly increases the charge carrier mobility in the epitaxial layer 15. Note that FIG. 4 further demonstrates that the standard deviation of Ron within each set is small compared to the difference between the respective average values of Ron. Both the formation of the external tensile stress by the mechanical measures and methods explained here and the effect of the external tensile stress on the electrical power of the power semiconductor chips 10 are consequently clearly systematic and very reproducible results.FIG. 5 schematically illustrates a cross-sectional view of a semiconductor device 300 of an embodiment including the semiconductor device 100 of FIG. 1 encapsulated in an encapsulating body 50 embedding the power semiconductor chip 10. The encapsulation body 50 may also partially or completely embed the carrier 20. As an example, in the semiconductor device 300 shown in FIG. 5, the carrier 20 protrudes from the encapsulating body 50 at one side surface 22, and is covered with the encapsulating body 50 at the other side surfaces 21, the upper surface 23, and the lower surface 24 opposite to the upper surface 23.FIG. 6 illustrates a cross-sectional view of a semiconductor device 400 according to an embodiment. The semiconductor device 400 is similar to the semiconductor device 300 of FIG. 5, except that the bottom surface 24 of the carrier 20 remains exposed (i.e., uncovered with the encapsulation body 50).The encapsulating body 50 may be made of any suitable thermosetting, thermoplastic or thermosetting (matrix) material or laminate, for example a prepreg (short for prepreg fibres). In particular, a (matrix) material based on epoxy resin can be used. The dielectric (matrix) material forming the encapsulation body 50 may include a filling material. As an example, the filling material may consist of small particles of glass (SiO 2) or other electrically insulating mineral filling materials such as Al 2 O 3 or organic filling materials. After its deposition, the dielectric material may be only partially cured and may be fully cured by the application of energy (e.g., heat, UV light, etc.) to form the encapsulation body 50.Various techniques may be used to form the encapsulation body 50 from the dielectric material, for example compression molding, transfer molding, injection molding, powder molding, liquid molding, dispensing, or laminating. Compression molding may be used, for example. In compression molding, a liquid molding material is dispensed into an open lower mold half in which the carrier 20 and the power semiconductor chip 10 mounted thereon are disposed. After dispensing the liquid molding material, an upper mold half is then moved downwardly and spreads the liquid molding material until a cavity formed between the lower mold half and the upper mold half is completely filled. This process may be accompanied by the application of heat and pressure.FIG. 7 is a graph depicting the tensile stress in units of MPa as a function of chip area in units of mm 2 for power semiconductor chips having different thicknesses of 50, 100, 150, 220, and 315 μm after soldering (solid lines) and after encapsulation (dashed lines). As a first result, it is found that the tensile stress depends only slightly on the chip area. Consequently, it is believed that semiconductor chips of all sizes benefit from the principles discussed above. As a second result, the tensile stress significantly increases as the chip thickness increases. Consequently, the thicker the power semiconductor chip, the more pronounced is the electrical effect (increase in charge carrier mobility) induced by the application of the external voltage. As a third result, FIG. 7 further indicates that the tensile stress can be significantly reduced by encapsulation. This aspect will be considered in more detail below.According to another aspect, the encapsulation body 50 may be used to apply a stress to the epitaxial layer 15 of the power semiconductor chip 10. To this end, the encapsulation material of the encapsulation body 50 may have an elastic modulus of equal to or greater than 50000 MPa.Using an encapsulating body 50 made of an encapsulating material having an elastic modulus equal to or greater than 50000 MPa, the stress acting on the power semiconductor chip 10 is significantly affected or even dominated by the encapsulating body 50 rather than by the carrier 20.FIG. 8 illustrates the forces acting in semiconductor devices such as device 300 of FIG. 5 when semiconductor chip 10 is encapsulated in an encapsulating body 50. FIG. 8 illustrates a decrease in the tensile stress and a strengthening of the downward pressure acting on the power semiconductor chip 10 due to the encapsulation process. In particular, as indicated in FIG. 8, the deflection of the power semiconductor chip 10 due to the contraction of the carrier 20 after soldering is counteracted and in this way reduced by the contraction of the encapsulation body 50 during curing. At the same time, contraction of the encapsulating body 50 during curing causes the encapsulating body 50 to generate a downward pressure on the upper main surface 12 of the power semiconductor chip 10. Both effects (reduction of deflection and tensile stress and reinforcement of downward pressure) are strongly dependent on the elastic modulus of the encapsulating material of the encapsulating body 50. The greater the elastic modulus of the encapsulation material of the encapsulation body 50, the greater the reduction in the deflection and the tensile stress and the reinforcement of the downward pressure applied by the (cured) encapsulation material to the upper main die surface 12 of the power semiconductor die 10. In general, the elastic modulus of the encapsulation material may even be equal to or greater than 60000 MPa, in particular equal to or greater than 70000 MPa or equal to or greater than 80000 MPa. This may be achieved by adding a filler material to the encapsulation material, the percentage of the filler material in the encapsulation material may be equal to or greater than 80 vol %, in particular equal to or greater than 85 vol %. The same principles as illustrated in FIG. 8 apply to the semiconductor device 400 shown in FIG. 6.In short, the encapsulating body 50 converts the tensile stress into a downward pressure, and the conversion efficiency increases with the elastic modulus of the encapsulating material. It has been found that applying external pressure to the top major surface 12 of the power semiconductor die 10 reduces the on-state resistance Ronto significantly lower values compared to the Ronvalues associated with the same deflection (which is a measure of the tensile stress for a given die thickness) but a lower external pressure on the top major surface 12 of the power semiconductor die 10. Consequently, the provision of an encapsulation material consisting of an elastic modulus equal to or greater than 50000 MPa enables to reduce the deflection (and hence the tensile stress) and at the same time can improve the electrical performance of the power semiconductor chip 10.FIG. 9 is a graph depicting chip deflection in units of μm as a function of chip area in units of mm 2 for power semiconductor chips having different thicknesses of 50 μm, 100 μm, 150 μm, 220 μm, and 315 μm. Solid lines correspond to die deflection after soldering, while dashed lines correspond to (reduced) die deflection after encapsulation. Note that die deflection is reduced by encapsulation for all die areas. The reduction in chip deflection after encapsulation increases with chip area. Further, die deflection decreases slightly with die thickness. It should be noted that the external tensile stress acting on the power semiconductor chip 10 depends only on the deflection for a given chip thickness.Table 1 relates to a semiconductor device designated as package P-SOT223-4 having a construction similar to the construction of the semiconductor device or package 200 shown in FIG. 3. Thus, in order to avoid repetition, reference is made to the semiconductor device 200. Table 1 - Mechanical properties of building block materials Table 1 - Mechanical properties of building block materialsPartMaterialE-moduleCTEEncapsulation BodyKMC 180-713000 MPa13 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmLead FramesC18070 / K75138000 MPa18 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmLeadframe PlatingAg Ag79000 MPa19,7 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmBonding LayerAuNb 80 / .2059000 MPa15,4 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmUpper Pad LayerTi110000 MPa9 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmLower pad layerAl71000 MPa23,8 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmCoating layerAu78000 MPa14,3 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmSemiconductor chipSilicon Silicon16800 MPa2,5 ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppm ppmAs indicated in Table 1, the encapsulation material of the encapsulation body 50 may have an elastic modulus of about 13000 MPa. This is a typical elastic modulus value of an encapsulating material commonly used in the art. Since this value is comparatively small with respect to the Young's modulus of the other parts of the package (see Table 1), the contribution of the package body to the forces acting on the power semiconductor chip can be small. Therefore, high deflection and high tensile stress can be obtained. On the other hand, according to the above-explained aspect, the elastic modulus of the sealing material of the sealing body 50 can be set to not lower than about 50000 MPa or more, for example, by adding a filler material or replacing the sealing material KMC 180-7 (see Table 1) with a sealing material having such a high elastic modulus. In this case, the deflection and the tensile stress are reduced (see FIG. 9 ). However, a low value of Ron is still assured or even reduced by the enhanced application of a downward pressure to the upper major surface 12 of the power semiconductor chip 10, as discussed above.The concept of using an encapsulating body 50 made of an encapsulating material having an elastic modulus equal to or greater than 50000 MPa may be combined with all methods and measures mentioned herein in connection with other embodiments. In particular, a bonding layer 17 made of a brittle brazing material such as an AuSn-based brazing material could be used. A diffusion solder material, e.g. based on AuSn, may be used and may have a high modulus of elasticity of about 59000 MPa (see Table 1).As an example, the package P-SOT223-4 illustrated in Table 1 uses an encapsulation body 50 having a thickness of 1 mm over the carrier 20, wherein the carrier 20 is a silver-plated copper leadframe (leadframe) having a thickness of 250 μm. The use of an encapsulating body 50 made of an encapsulating material having an elastic modulus equal to or greater than 50000 MPa substantially reduces the deflection of the device while at the same time allowing low values of Ron. Thus, the application of an encapsulating material having such a high modulus of elasticity could help limit deflection while at the same time improving (or at least not adversely affecting) the low Ron property.In some embodiments, see e.g. FIG. 5 or 6, a ratio of a distance Dentc between an upper surface 12 of the power semiconductor chip 10 and an upper surface 51 of the encapsulation body 50 and a sum of the thickness Dchip of the power semiconductor chip 10, the thickness Dpad of the second contact pad 13, the thickness Dcon of the connection layer 17 and the thickness Dcar of the electrically conductive carrier 20 is equal to or greater than 3, i.e.This ratio may even be equal to or greater than 5, in particular 6, more particularly 7.When the condition (2) is satisfied, typically, a considerable amount of tensile stress is converted into compression (i.e., downward pressure) acting on the power semiconductor chip 10. The advantageous effect of this conversion on Ron has already been explained in connection with the above-mentioned embodiment. In contrast to the aforementioned embodiment, in which the effect is mainly induced by the high modulus of elasticity of the encapsulation material, the effect here is mainly caused by geometric design constraints according to the condition (2), e.g. by a considerable thickness Dentc of the encapsulation body 50 above the top surface 12 of the power semiconductor chip 10. It should be noted that in the art, the ratio defined in condition (2) is still considerably smaller than 3 to the best knowledge of the inventor.Both of the above-mentioned methods for efficiently converting the external tensile stress into an external downward pressure may be naturally combined, that is, an encapsulating body 50 sized to satisfy the condition (2) and made of an encapsulating material having a high elastic modulus (e.g., elastic modulus= 50000 MPa or more) may be used in combination.In one embodiment of a method of manufacturing a semiconductor device, a vertical power semiconductor chip 10 is first provided with an epitaxial layer 15 and a bulk semiconductor layer 16. The power semiconductor chip 10 comprises a first contact pad 11 arranged on a first main surface 12 of the power semiconductor chip 10 and a second contact pad 13 arranged on a second main surface 14 of the power semiconductor chip 10 opposite to the first main surface 12.Then, the vertical power semiconductor chip 10 is mounted on the electrically conductive carrier 20, which is thereby fastened to the second contact pad 13. As mentioned above, the distance between the electrically conductive carrier 20 and the epitaxial layer 15 may be less than 50 μm and / or the condition (1) may be satisfied.Further, the power semiconductor chip 10 and optionally the carrier 20 may be embedded in an encapsulation material forming an encapsulation body 50. The encapsulation may be accomplished, for example, by a molding, dispensing or laminating technique.The encapsulation material may have a low elastic modulus or may not satisfy the condition (2). In these cases, the encapsulation material may not significantly affect or control the forces acting on the power semiconductor chip 10. On the other hand, as mentioned above, the sealing material may have an elastic modulus equal to or greater than 50000 MPa and / or the condition (2) may be satisfied. In this case, the chip deflection is reduced and the tensile stress is efficiently converted into a down-chip pressure that is applied to the epitaxial layer 15 of the power semiconductor chip 10 by the encapsulating body 50.Moreover, although a particular feature or aspect of an embodiment of the invention may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. To the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are further intended to be inclusive in a manner similar to the term "comprise". Further, it should be understood that the embodiments of the invention may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming means. The term "exemplary" is also meant merely as an example rather than the best or optimum. It should also be appreciated that features and / or elements illustrated herein are shown with particular dimensions relative to each other for purposes of simplicity and ease of understanding, and that actual dimensions may differ substantially from those illustrated herein.

Claims

A device comprising: a vertical power semiconductor chip (10) having an epitaxial layer (15) and a bulk semiconductor layer (16), a first pad (11) disposed on a first main surface of the power semiconductor chip (10), a second pad (13) disposed on a second main surface of the power semiconductor chip (10), the second main surface being disposed opposite the first main surface, and an electrically conductive carrier (20) attached to the second pad (13), wherein a distance between the electrically conductive carrier (20) and the epitaxial layer (15) is equal to or less than 50 μm and the bulk semiconductor layer (16) has a thickness equal to or less than 15 μm, wherein the electrically conductive carrier (20) applies a tensile stress to the epitaxial layer (15) in the unencapsulated state of the device that is greater than 50 MPa.The device according to claim 1, further comprising: a connection layer (17) arranged between the second contact pad (13) and the electrically conductive carrier (20), wherein the connection layer (17) has a thickness equal to or less than 10 μm.The apparatus of claim 2, wherein the bonding layer (17) comprises a diffusion solder material.The device according to any one of the preceding claims, wherein the epitaxial layer (15) has a thickness equal to or greater than 20 μm.The device according to any of the preceding claims, wherein the power semiconductor chip (10) is a vertical power transistor having an operating voltage equal to or greater than 200 V.A device comprising: a vertical power semiconductor chip (10) made of silicon having an epitaxial layer (15) and a bulk semiconductor layer (16), a first contact pad (11) arranged on a first main surface of the power semiconductor chip (10), a second contact pad (13) arranged on a second main surface of the power semiconductor chip (10) opposite to the first main surface, an electrically conductive carrier (20) formed as a lead frame, and a connection layer (17) arranged between the second contact pad (13) and the electrically conductive carrier (20), wherein a ratio of the thickness of the electrically conductive carrier (20) to a sum of the thickness of the power semiconductor chip (10), the thickness of the second contact pad (13) and the thickness of the connection layer (17) is equal to or greater than 3, wherein the electrically conductive carrier (20) exerts a tensile stress on the epitaxial layer (15) in the unencapsulated state of the device which is greater than 50 MPa.The device of claim 6, wherein the ratio is equal to or greater than 5.The device according to claim 6 or 7, wherein the bonding layer (17) has a thickness equal to or less than 10 μm.The device according to any one of claims 6 to 8, wherein the electrically conductive support (20) has a thickness equal to or greater than 1.0 mm.The device according to any one of claims 6 to 9, wherein the power semiconductor chip (10) is a vertical power transistor having an operating voltage equal to or greater than 200 V.A method of manufacturing a device, the method comprising: providing a vertical power semiconductor chip (10) having an epitaxial layer (15) and a bulk semiconductor layer (16) having a thickness equal to or less than 15 μm, providing a first pad (11) disposed on a first main surface of the power semiconductor chip (10), providing a second pad (13) disposed on a second main surface of the power semiconductor chip (10) opposite to the first main surface, and mounting the vertical power semiconductor chip (10) on an electrically conductive carrier (20) attached to the second pad (13), wherein a distance between the electrically conductive carrier (20) and the epitaxial layer (15) is less than 50 μm, wherein the electrically conductive carrier (20) applies a tensile stress to the epitaxial layer (15) in the unencapsulated state of the device, which is greater than 50 MPa.The method of claim 11, further comprising: applying a bonding layer (17) between the second contact pad (13) and the electrically conductive carrier (20), wherein the bonding layer (17) has a thickness equal to or less than 10 μm.The method according to claim 11 or 12, wherein the epitaxial layer (15) has a thickness equal to or greater than 20 μm.The method according to any one of claims 11 to 13, wherein a ratio of the thickness of the electrically conductive carrier (20) and a sum of the thickness of the power semiconductor chip (10), the thickness of the second pad (13), and the thickness of the connection layer (17) is equal to or greater than 3.

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