Semiconductor device

Abstract

Semiconductor component, including: first to seventh transistors and first to sixth wiring connections, where the first to seventh transistors have the same polarities, wherein one of a source and a drain of the first transistor (404) is electrically connected to the third wiring (407), the other is electrically connected to the first wiring (413) from the source and drain of the first transistor (404), wherein one of the source and drain of the second transistor (420) is electrically connected to the first wiring (413), wherein the other is electrically connected from the source and drain of the second transistor (420) to the fourth wiring (412), wherein one of a source and a drain of the third transistor (403) is electrically connected to the fifth wiring (406), wherein the other is electrically connected to the second wiring (414) from the source and drain of the third transistor (403), wherein a gate of the third transistor (403) is electrically connected to a gate of the first transistor (404), wherein one of a source and a drain of the fourth transistor (419) is electrically connected to the second wiring (414), where one clock signal is input into the other from the source and drain of the fourth transistor (419), wherein a gate of the fourth transistor (419) is electrically connected to a gate of the second transistor (420), wherein one of a source and a drain of the fifth transistor (402) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the fifth transistor (402) to the gate of the second transistor (420), wherein one of a source and a drain of the sixth transistor (415) is electrically connected to the gate of the second transistor (420), the other is electrically connected to the sixth wiring (405) from the source and drain of the sixth transistor (415), wherein one of a source and a drain of the seventh transistor (418) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the seventh transistor (418) to the gate of the first transistor (404), where the first wiring (413) is configured to output a first signal (GOUT), where the second wiring (414) is configured to output a second signal (SROUT), where a first low-level potential (VEE) is applied to the third wiring (407), where a second low-level potential (VSS) is applied to the fifth wire (406), where a high-level potential (VDD) is applied to the sixth wire (405), wherein a first conductive layer (115), which has a function as the gate of the first transistor (404), is electrically connected to a third conductive layer (110), which has a function as the gate of the fifth transistor (402), via a second conductive layer (119), wherein an area in which the first conductive layer (115) and a semiconductor thin film (116) of the first transistor (404) overlap is larger than an area in which the third conductive layer (110) and a semiconductor thin film (112) of the fifth transistor (402) overlap, and wherein the second conductive layer (119) has no area that overlaps with all semiconductor thin layers of the first to seventh transistors.

Description

Background of the invention 1. Field of the invention

[0001] The present invention relates to a semiconductor device using a field-effect transistor with an insulated gate electrode(s). 2. Description of the state of the art

[0002] In recent years, metal oxides with semiconductor properties, referred to as oxide semiconductors, have attracted attention as a novel semiconductor material exhibiting both high mobility, similar to that of polycrystalline or microcrystalline silicon, and homogeneous elemental properties, similar to those of amorphous silicon. Metal oxides have been used in a wide variety of applications; for example, indium oxide, a well-known metal oxide, has been used as a material for a transparent electrode in a liquid crystal display device, etc. Examples of such metal oxides with semiconductor properties include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Transistors in which a channel-forming region is formed using such a metal oxide with semiconductor properties are known (patent applications 1 and 2).US patent 2010 / 0117079 A discloses a flip-flop circuit that can be used, for example, in a shift register. [Source reference] Patent application 1: published Japanese patent application no. JP 2007-123 861 A Patent application 2: published Japanese patent application no. JP 2007-96055A Summary of the invention

[0003] The invention provides a semiconductor device according to claim 1 or claim 2. Transistors made of amorphous silicon or an oxide semiconductor enable the fabrication of a fifth-generation (1200 mm wide x 1300 mm long) or higher-generation semiconductor display device based on a glass substrate, thereby offering the advantages of higher productivity and lower costs. As screen size increases, the load on the wiring, called the bus line, which is connected to a large number of pixels, also increases; for example, a scanning line or signal line in a pixel portion of the semiconductor display device widens.Thus, the required current supply capability of a driver circuit to apply a potential to the scanning line or the signal line is increased, and accordingly, the size of a transistor included in the driver circuit, especially a transistor on the output side of the driver circuit, will tend to increase with an increase in screen size, although depending on the electrical properties of the transistor.

[0004] Such an increase in transistor size results in an enlargement of the wiring area, which, considering the layout in the driver circuit, serves as the transistor's gate electrode. Therefore, it is likely that a so-called antenna effect will occur—a phenomenon in which charge accumulates in the wiring during a manufacturing step using a plasma, such as dry etching—increasing the probability of electrostatic damage to the wiring due to discharge of the accumulated charge.

[0005] In particular, the forward current of a transistor using amorphous silicon or an oxide semiconductor tends to be lower than that of a transistor using polycrystalline or monocrystalline silicon. Consequently, although a transistor made of amorphous silicon or an oxide semiconductor allows for the fabrication of a larger screen in the process, such a larger screen requires a transistor designed with larger dimensions to meet the current delivery requirements of the driver circuit. Therefore, the probability of electrostatic damage to the wiring increases with an increase in the wiring area, so the yield tends to decrease.

[0006] In view of the technical background described above, one object of the present invention is to create a semiconductor device in which a reduction in yield due to electrostatic destruction can be prevented.

[0007] In one embodiment of the present invention, a conductive thin film, which serves as the gate electrode in a plurality of transistors, is subdivided into a plurality of conductive thin films to prevent charge accumulation in the conductive thin film due to an antenna effect. The subdivided conductive thin films are spaced apart from one another. Furthermore, the subdivided conductive thin films are electrically connected to one another by a conductive thin film that is different from the subdivided conductive thin films. The plurality of transistors includes a transistor on the output side of a driver circuit.

[0008] In one embodiment of the present invention, a scanning line driver circuit for supplying a signal for a selection of a plurality of pixels to a scanning line includes a shift register for generating the signal. A conductive thin film, which serves as the gate electrode for each of a plurality of transistors of the shift register, is divided into a plurality of conductive thin films. The divided conductive thin films are spaced apart from one another. Furthermore, the divided conductive thin films are electrically connected to one another by a conductive thin film that is different from the divided conductive thin films. The plurality of transistors includes a transistor on the output side of the shift register.

[0009] The conductive thin film, which is different from the partitioned conductive thin films, can be created in a layer that is different from the partitioned conductive thin films, such that the conductive thin film and respective source and drain electrodes of the plurality of transistors can be created in the same layer.

[0010] In one embodiment of the present invention, the plurality of transistors can contain amorphous silicon or an oxide semiconductor in the active layers.

[0011] According to one embodiment of the present invention, by electrically connecting the plurality of conductive thin films serving as gate electrodes by the conductive thin film created in the other layer, the area of ​​each conductive thin film serving as a gate electrode can be reduced so that it is smaller than that of a conductive thin film serving as a gate electrode for a plurality of transistors. Consequently, even if the size of the transistor on the output side of the driver circuit increases with an increase in screen size, the area of ​​the conductive thin film serving as the gate electrode of the transistor can be kept small, thereby avoiding damage to the conductive thin film by static electricity resulting from an antenna effect during a plasma-using manufacturing step, such as a step to form a gate electrode by etching.

[0012] In particular, a semiconductor device according to one embodiment of the present invention includes a driver circuit for supplying signals to a plurality of pixels. The driver circuit includes a plurality of transistors. In the plurality of transistors, a gate electrode of at least one transistor on the signal output side is electrically connected to a gate electrode of at least one other transistor by a conductive thin film that is distinct from the gate electrodes.

[0013] The structure described above enables the semiconductor device, according to one embodiment of the present invention, to avoid a reduction in yield due to electrostatic destruction. Brief description of the drawing

[0014] They show: Fig. 1 a circuit diagram showing a circuit arrangement of a semiconductor device of the present invention; Fig. 2A and Fig. 2C Top views of transistors, and Fig. 2B a cross-sectional view of the transistor; Fig. 3A and Fig. 3C Top views of transistors, and Fig. 3B a cross-sectional view of the transistor; Fig. 4 a circuit diagram showing a circuit arrangement of a semiconductor device of the present invention; Fig. 5 a circuit diagram showing the construction of a shift register; Fig. 6 a flowchart showing the operation of a pulse output circuit; Fig. 7 a representation that schematically shows a j-th impulse generator; Fig. 8A and Fig. 8B Circuit diagrams, each showing a circuit arrangement of a pulse generator; Fig. 9A and Fig. 9B Circuit diagrams, each showing a circuit arrangement of a pulse generator; Fig. 10 a circuit diagram showing a circuit arrangement of a pulse generator; Fig. 11 a cross-sectional view of a driver circuit and a pixel; Fig. 12 a representation showing the structure of a screen; and Fig. Figures 13A to 13E show an electronic device. Detailed description of the invention

[0015] The following describes in detail embodiments of the invention; reference is made to the accompanying drawing. However, the present invention is not limited to the following description, and a person skilled in the art will readily understand that the nature and details can be modified in various ways without departing from the inventive concept and the scope of protection of the present invention. Accordingly, the present invention is not to be considered as limited by the following description of embodiments.

[0016] The present invention includes any semiconductor device that uses a transistor, such as an integrated circuit, an RF transponder, and a semiconductor device. The category of integrated circuits includes highly integrated circuits (LSIs), such as a microprocessor, an image processing circuit, a digital signal processor (DSP), a microcontroller, and the like, and programmable logic devices (PLDs), such as a field-programmable gate array (FPGA) and a complex programmable logic device (CPLD).Furthermore, the category of semiconductor display devices includes: liquid crystal display devices, light-emitting devices in which a light-emitting element embodied by an organic light-emitting element (OLED) is provided for each pixel, electronic paper displays, digital micromirror devices (DMDs), plasma displays (PDPs), field emission displays (FEDs) and other semiconductor display devices in which the driver circuit contains a circuit element using a semiconductor thin film.

[0017] Within the scope of this application, the category of semiconductor display devices includes: screens in which a display element, such as a liquid crystal element or a light-emitting element, is provided for each pixel, and modules in which an integrated circuit or similar component, including a control unit, is mounted on the screen. (Emphasis 1)

[0018] Fig. Figure 1 shows an example of a circuit arrangement of a semiconductor device according to an embodiment of the present invention. A semiconductor device 100, as shown in Fig. Figure 1 shows a variety of transistors, including at least one transistor 101 and one transistor 102.

[0019] A high-level potential VH and a low-level potential VL are applied to the semiconductor device 100 via a wiring connection 105 and a wiring connection 106. Fig. 1. The potential VH is applied to the semiconductor device 100 via wiring 105, and the potential VL is applied to the semiconductor device 100 via wiring 106. Additionally, a potential Vin of an input signal is applied to the semiconductor device 100 via wiring 103. Within the semiconductor device 100, the numerous transistors, including transistor 101 and transistor 102, are switched on or off according to the potential Vin. Consequently, by the switching process described above, one of the potentials VH and VL is selected, so that the selected potential is output as the potential Vout of an output signal from the semiconductor device 100 via wiring 104.

[0020] One of the source and drain terminals of transistor 102 is connected to the wiring 104. This means that transistor 102 is located on the output side of the semiconductor device 100 and is responsible for controlling the output of the potential Vout to the wiring 104. In one embodiment, a gate electrode (G) of transistor 101 is electrically connected to a gate electrode (G) of transistor 102 by means of wiring 107, which is separate from the other gate electrodes.

[0021] In this description, the term "connection" has the meaning of both an electrical connection and a direct connection, unless otherwise specified, and corresponds to a state in which current, voltage, or a potential can be supplied or transmitted. Accordingly, the "connected" state does not necessarily mean a direct connection, but rather includes, by its very definition, an indirect connection via an element such as wiring, a conductive thin film, a resistor, a diode, or a transistor, such that current, voltage, or a potential can be supplied or transmitted.

[0022] Furthermore, the "source terminal" of the transistor refers to a source region that is part of an active layer or a source electrode connected to an active layer. Similarly, the "drain terminal" of the transistor refers to a drain region that is part of an active layer or a drain electrode connected to an active layer.

[0023] The terms "source terminal" and "drain terminal" of a transistor are interchangeable depending on the transistor's polarity and which of the potentials at the terminals is high or low. In an n-channel transistor, an electrode with a low potential is generally called the source terminal, while an electrode with a high potential is called the drain terminal. Conversely, in a p-channel transistor, an electrode with a low potential is called the drain terminal, while an electrode with a high potential is called the source terminal.In the present description, the connection relationship of a transistor is in some cases described, for the sake of simplicity, based on the assumption that the source connection and the drain connection are fixed; however, in and of themselves, the source connection and the drain connection are used interchangeably according to the potential relationship described above.

[0024] In the case where the potential Vout output by semiconductor device 100 is applied to a heavily loaded wiring, referred to as a bus line, such as a scanning line or a signal line connected to a large number of pixels, transistor 102 must have a high current delivery capability to control the output of the potential Vout. Consequently, it is preferable to design transistors 102 and 102 such that the channel width W of transistor 102 is larger than the channel width W of transistor 101.

[0025] Fig. 2A is an example of a top view of the in Fig. Transistors 101 and 102 are shown in the top view. Fig. However, in 2A, to better illustrate the structure of transistors 101 and 102, a thin film 111 insulating the gate has been omitted. Furthermore, Fig. 2B is an example of a cross-sectional view along the dash-dot line A1-A2 of transistor 102. Fig. 2A.

[0026] In Fig. 2A, transistor 101 has a conductive thin film 110, which serves as a gate electrode, above the conductive thin film 110 a gate-insulating thin film 111, a semiconductor thin film 112, which is designed to overlap with the conductive thin film 110 above the gate-insulating thin film 111, and a conductive thin film 113 as well as a conductive thin film 114, which serves as a source electrode and drain electrode respectively above the semiconductor thin film 112.

[0027] Furthermore, it indicates Fig. 2A and Fig. 2B of transistor 102 a conductive thin film 115, which serves as gate electrode, above the conductive thin film 115 a gate-insulating thin film 111, a semiconductor thin film 116, which is designed to overlap with the conductive thin film 115 above the gate-insulating thin film 111, and a conductive thin film 117 and a conductive thin film 118, which serve as source electrode and drain electrode respectively above the semiconductor thin film 116.

[0028] Furthermore, in one embodiment of the present invention, the current delivery capability of transistor 102 arranged on the output side is better than that of transistor 101. Therefore, in one embodiment of the present invention, as described in Fig. 2A shown, it is preferable to design transistors 101 and 102 such that the ratio of the channel width W 102 for the channel length L 102of transistor 102 greater than the ratio of the channel width W 101 for the channel length L 101 of transistor 101. In particular, the ratio of the channel width W 102 for the channel length L 102 at least twice as large as the ratio of the channel width W 102 for the channel length L 101 , furthermore preferably at least three times as large as the ratio of the channel width W 101 for the channel length L 101 .

[0029] Furthermore, the conductive thin film 110 is spaced apart from the conductive thin film 115. In this description, "spaced apart" means arranged with an intermediate gap. Furthermore, in Fig. 2A and Fig. 2B The conductive thin film 110 is electrically connected to the conductive thin film 115 by a conductive thin film 119, which serves as wiring. In particular, the conductive thin film 110 is connected to the conductive thin film 119 in an opening 120 formed in the gate-insulating thin film 111, and the conductive thin film 115 is connected to the conductive thin film 119 in an opening 121 formed in the gate-insulating thin film 111.

[0030] Furthermore, the in Fig. 2A and Fig. The conductive thin films 110 and 115 shown in Figure 2B are formed by machining a conductive thin film formed over an insulating surface to obtain a suitable shape, for example by etching or similar processes. The conductive thin films 113 and 114, the conductive thin films 117 and 118, and the conductive thin film 119 can be formed by machining a thin film to obtain a suitable shape, for example by etching or similar processes, the latter being formed over the thin film 111 insulating the gate in order to cover the openings 120 and 121. That is to say, the conductive thin film 119 is formed in a layer that is different from the conductive thin films 110 and 115.

[0031] As in Fig. 2A and Fig. As shown in Figure 2B, in one embodiment of the present invention the conductive thin films 110 and 115, which serve as gate electrodes, are electrically connected to each other by the electrical thin film 119, which is formed in a layer that is different from the layer of the conductive thin films 110 and 115.

[0032] As a comparative example, Fig. 2C is another example of the top view of the in Fig. Transistors 101 and 102 are shown in the top view. Fig. However, in 2C, a thin film insulating the gate has been omitted to better illustrate the structure of transistors 101 and 102.

[0033] In Fig. 2C, transistor 101 has a conductive thin film 122, which serves as a gate electrode, above the conductive thin film 122 a gate-insulating thin film, a semiconductor thin film 123 which is designed to overlap the conductive thin film 122 above the gate-insulating thin film, and a conductive thin film 124 and a conductive thin film 125, which serve as source electrode and drain electrode respectively above the semiconductor thin film 123.

[0034] Furthermore, it indicates Fig. 2C of transistor 102 a conductive thin film 122, which serves as a gate electrode, above the conductive thin film 122 a gate-insulating thin film, a semiconductor thin film 126, which is designed to overlap the conductive thin film 122 above the gate-insulating thin film, and a conductive thin film 127 and a conductive thin film 128, which serve as source electrode and drain electrode respectively above the semiconductor thin film 126.

[0035] This means that in Fig. 2C the conductive thin film 122 is common to transistors 101 and 102; the conductive thin film 122 serves as both the gate electrode of transistor 101 and the gate electrode of transistor 102. Consequently, the region of the conductive thin film 122 that is in Fig. 2C serves as a gate electrode, larger than one of the respective areas of the conductive thin films 110 and 115, which are in Fig. 2A and Fig. 2B serve as gate electrodes.

[0036] Thus, in one embodiment of the present invention, by making each of the regions of the conductive thin films 110 and 115, which serve as gate electrodes, smaller than that of the conductive thin film 122 in the comparative example, the amount of charge accumulated in each of the conductive thin films 110 and 115 during etching to form them can be kept small; i.e., an antenna effect can be reduced. Accordingly, in one embodiment of the present invention, during the formation of the conductive thin films 110 and 115 by etching, the probability of electrostatic destruction of the conductive thin films 110 and 115 by discharge of the charge described above will be lower than in the comparative example.

[0037] Furthermore, in one embodiment of the present invention, when forming the semiconductor thin film 112 over the conductive thin film 110 and the semiconductor thin film 116 over the conductive thin film 115 by etching, the probability of electrostatic destruction of the conductive thin films 110 and 115 by an antenna effect will be lower than in the comparative example.

[0038] Next, we will show Fig. 3A an example of the top view of the in Fig. 1 shown transistors 101 and 102, which is from the one in Fig. The example shown in 2A is different. In the top view of Fig. However, in 3A, the gate-insulating thin film 211 has been omitted to better illustrate the structure of transistors 101 and 102. Furthermore, Fig. 3B is an example of a cross-sectional view along the dash-dot line B1-B2 of transistor 102. Fig. 3A.

[0039] In Fig. 3A, transistor 101 has a conductive thin film 213 and a conductive thin film 214, which serve as source electrode and drain electrode respectively, a semiconductor thin film 212 over the conductive thin films 213 and 214, the gate-insulating thin film 211 over the semiconductor thin film 212, and a conductive thin film 210, which serves as a gate electrode and is designed to overlap with the semiconductor thin film 212 over the gate-insulating thin film 211.

[0040] In Fig. 3A and Fig. 3B, transistor 102 has a conductive thin film 217 and a conductive thin film 218, which serve as source electrode and drain electrode, a semiconductor thin film 216 over the conductive thin films 217 and 218, the gate-insulating thin film 211 over the semiconductor thin film 216, and a conductive thin film 215, which serves as a gate electrode and is designed to overlap with the semiconductor thin film 216 over the gate-insulating thin film 211.

[0041] Furthermore, in one embodiment of the present invention, the current delivery capability of transistor 102 arranged on the output side is better than that of transistor 101. Therefore, in one embodiment of the present invention, as described in Fig. As shown in 3A, it is preferable to design transistors 101 and 102 such that the ratio of the channel width W 102 for the channel length L 102of transistor 102 greater than the ratio of the channel width W 101 for the channel length L 101 of transistor 101. In particular, the ratio of the channel width W 102 for the channel length L 102 preferably at least twice as large as the ratio of the channel width W 101 for the channel length L 101 , furthermore preferably at least three times as large as the ratio of the channel width W 101 for the channel length L 101 .

[0042] Furthermore, the conductive thin film 210 is spaced apart from the conductive thin film 215. Furthermore, in Fig. 3A and Fig. 3B The conductive thin film 210 is electrically connected to the conductive thin film 215 by a conductive thin film 219, which serves as wiring. In particular, the conductive thin film 210 is connected to the conductive thin film 219 in an opening 220 formed in the gate-insulating thin film 211, and the conductive thin film 215 is connected to the conductive thin film 219 in an opening 221 formed in the gate-insulating thin film 211.

[0043] Furthermore, the in Fig. 3A and Fig. The conductive thin films 210 and 215 shown in Figure 3B are formed by machining a thin film to obtain a suitable shape, for example by etching or similar processes, the latter being formed over the thin film 211 insulating the gate for the purpose of covering the openings 220 and 221. The conductive thin films 213 and 214, the conductive thin films 217 and 218, and the conductive thin film 219 can be formed by machining a conductive thin film formed over an insulating surface to obtain a suitable shape, for example by etching or similar processes. That is, the conductive thin film 219 is formed in a layer that is different from the conductive thin films 210 and 215.

[0044] As in Fig. 3A and Fig. As shown in Figure 3B, in one embodiment of the present invention the conductive thin films 210 and 215, which serve as gate electrodes, are electrically connected to each other by the electrical thin film 219, which is formed in a layer that is different from the layer of the conductive thin films 210 and 215.

[0045] As a comparative example, Fig. 3C is another example of the top view of the in Fig. Transistors 101 and 102 are shown in the top view. Fig. However, in 3C, a thin film insulating the gate has been omitted to better illustrate the structure of transistors 101 and 102.

[0046] In Fig. 3C, transistor 101 has a conductive thin film 224 and a conductive thin film 225, which serve as source electrode and drain electrode, a semiconductor thin film 223 over the conductive thin films 224 and 225, a gate-insulating thin film over the semiconductor thin film 223, and a conductive thin film 222, which serves as a gate electrode and is designed to overlap with the semiconductor thin film 223 over the gate-insulating thin film.

[0047] Furthermore, it points out that Fig. 3C of transistor 102 a conductive thin film 227 and a conductive thin film 228, which serve as source electrode and drain electrode respectively, over the conductive thin films 227 and 228 a semiconductor thin film 226, over the semiconductor thin film 226 a gate-insulating thin film and the conductive thin film 222, which serves as gate electrode and is designed such that it overlaps with the semiconductor thin film 226 over the gate-insulating thin film.

[0048] This means that in Fig. 3C the conductive thin film 222 is common to transistors 101 and 102; the conductive thin film 222 serves as both the gate electrode of transistor 101 and the gate electrode of transistor 102. Consequently, the region of the conductive thin film 222 that is in Fig. 3C serves as a gate electrode, larger than one of the respective areas of the conductive thin films 210 and 215, which are in Fig. 3A and Fig. 3B serve as gate electrodes.

[0049] Thus, in one embodiment of the present invention, by making each of the regions of the conductive thin films 210 and 215, which serve as gate electrodes, smaller than that of the conductive thin film 222 in the comparative example, the amount of charge accumulated in each of the conductive thin films 210 and 215 during etching to form them can be kept small, i.e., an antenna effect can be reduced. Accordingly, in one embodiment of the present invention, the probability of electrostatic destruction of the conductive thin films 210 and 215 by discharge of the charge described above will be lower during etching than in the comparative example.

[0050] Furthermore, in an embodiment of the present invention, when processing a conductive thin film over the conductive thin films 210 and 215 by etching in order to obtain a suitable shape, the probability of electrostatic destruction of the conductive thin films 210 and 215 due to an antenna effect will also be lower.

[0051] Next, a pulse generator is described which is a semiconductor device according to an embodiment of the present invention. Fig. Figure 4 shows, as an example of a semiconductor device according to an embodiment of the present invention, a pulse generator.

[0052] An impulse generator 300, as in Fig. Figure 4 shows transistors 301 to 315 and a capacitor 316. Transistor 302 corresponds to the one in Fig. Transistor 101 is shown in Figure 1. Each of transistors 309, 312, and 315 corresponds to the one shown in Figure 1. Fig. 1 transistor 102 shown. The pulse generator 300 is supplied with various potentials from the wirings 317 to 326 and outputs potentials to the wirings 327 to 329.

[0053] A shift register can be formed by connecting several pulse generators 300 in series.

[0054] Specifically, in the case where transistors 301 to 315 are n-channel transistors, a high-level potential VDD, a low-level potential VSS, and a low-level potential VEE are present at wiring points 317, 318, and 326, respectively. The potential VEE is preferably equal to or higher than the potential VSS. Furthermore, a potential LIN is present at wiring point 319, a potential INRES is present at wiring point 320, a potential CLK2 is present at wiring point 321, a potential RIN is present at wiring point 322, a potential CLK1 is present at wiring point 323, a potential PWC2 is present at wiring point 324, and a potential PWC1 is present at wiring point 325.

[0055] Furthermore, a potential GOUT1, output by pulse generator 300, is present at wiring 327. A potential GOUT2, output by pulse generator 300, is present at wiring 328. A potential SROUT, output by pulse generator 300, is present at wiring 329.

[0056] The potentials LIN, RIN, CLK2 and INRES each correspond to the potential Vin of the in Fig. 1 of the semiconductor device shown 100. The potentials GOUT1, GOUT2 and SROUT each correspond to the potential Vout of the in Fig. 1 of the semiconductor device shown 100. The potentials VSS, VEE, PWC1, PWC2 and CLK1 correspond either to the potential VH or the potential VL of the in Fig. 1 of the semiconductor device shown 100.

[0057] Specifically, the gate electrode of transistor 301 is connected to wiring 319; one of the source and drain terminals of transistor 301 is connected to wiring 317; and the other of the source and drain terminals of transistor 301 is connected to one of the source and drain terminals of transistor 302. One gate electrode of transistor 302 is connected to a gate electrode of transistor 315; and the other of the source and drain terminals of transistor 302 is connected to wiring 318. One gate electrode of transistor 303 is connected to wiring 320; one of the source and drain terminals of transistor 303 is connected to wiring 317; and the other of the source and drain terminals of transistor 303 is connected to the gate electrode of transistor 302.One gate electrode of transistor 304 is connected to wiring 321; one of the source and drain terminals of transistor 304 is connected to wiring 317; and the other of the source and drain terminals of transistor 304 is connected to the gate electrode of transistor 302. One gate electrode of transistor 305 is connected to wiring 322; one of the source and drain terminals of transistor 305 is connected to wiring 317; and the other of the source and drain terminals of transistor 305 is connected to the gate electrode of transistor 302. One gate electrode of transistor 306 is connected to wiring 319; one of the source and drain terminals of transistor 306 is connected to the gate electrode of transistor 302. and the other of the source and drain terminals of transistor 306 is connected to the wiring 318.One gate electrode of transistor 307 is connected to wiring 317; one of the source and drain terminals of transistor 307 is connected to the other source and drain terminal of transistor 301; and the other source and drain terminal of transistor 307 is connected to a gate electrode of transistor 308. One source and drain terminal of transistor 308 is connected to wiring 323, and the other source and drain terminal of transistor 308 is connected to wiring 329. One gate electrode of transistor 309 is connected to the gate electrode of transistor 302; one source and drain terminal of transistor 309 is connected to wiring 329; and the other source and drain terminal of transistor 309 is connected to wiring 318.One gate electrode of transistor 310 is connected to wiring 317; one source and drain terminal of transistor 310 is connected to the other source and drain terminal of transistor 301; and the other source and drain terminal of transistor 310 is connected to a gate electrode of transistor 311. One source and drain terminal of transistor 311 is connected to wiring 324, and the other source and drain terminal of transistor 311 is connected to wiring 328. One gate electrode of transistor 312 is connected to the gate electrode of transistor 302; one source and drain terminal of transistor 312 is connected to wiring 328; and the other source and drain terminal of transistor 312 is connected to wiring 318.One gate electrode of transistor 313 is connected to wiring 317; one of the source and drain terminals of transistor 313 is connected to the other of the source and drain terminals of transistor 301; and the other of the source and drain terminals of transistor 313 is connected to a gate electrode of transistor 314. One of the source and drain terminals of transistor 314 is connected to wiring 325; and the other of the source and drain terminals of transistor 314 is connected to wiring 327. One of the source and drain terminals of transistor 315 is connected to wiring 327; and the other of the source and drain terminals of transistor 315 is connected to wiring 326. One electrode of capacitor 316 is connected to the gate electrode of transistor 302. and the other electrode of capacitor 316 is connected to the wiring 318.

[0058] In Fig. 4. The other source and drain terminal of transistor 315 on the output side is connected to the wiring 326; however, embodiments of the present invention are not limited in this respect. The other source and drain terminal of transistor 315 on the output side can be connected to the wiring 318. The dimensions of transistor 315 on the output side are larger, which is why, if the transistor is a self-conducting transistor, the drain current of the transistor is greater than that in the off-state of any other transistor.Therefore, if transistor 315 is a self-conducting transistor, then when the other of the source and drain terminals of transistor 315 is connected to wiring 318, the potential of wiring 318 will likely be increased by the drain current described above, resulting in a reduction in the amplitude of the potential GOUT1, which is an output potential. On the other hand, if, as in . Fig. Figure 4 shows that the other of the source and drain terminals of transistor 315 on the output side is not connected to wiring 318, but to wiring 326. Even if transistor 315 is a self-conducting transistor and the potential of wiring 326 increases accordingly, the potential of wiring 318 for applying the potential to the gate electrode of transistor 315 is unrelated to the increase in the potential of wiring 326. Similarly, if the potential of wiring 326 increases due to the drain current of transistor 315, the gate voltage of transistor 315 decreases relative to the threshold voltage, which is a negative voltage, so that transistor 315 can be switched off even if it is a self-conducting transistor.

[0059] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 309, 312, and 315, corresponding to the output-side transistors, is electrically connected to the gate electrode of transistor 302 by a conductive thin film that is distinct from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than if the respective gate electrodes of transistors 309, 312, 315, and 302 were all formed from a single conductive thin film. Consequently, the probability of electrostatic damage resulting from the antenna effect of the conductive thin film serving as a gate electrode will be reduced.

[0060] One embodiment of the present invention is not limited to a structure in which two conductive thin films, each serving as a gate electrode, are electrically connected to each other by a conductive thin film that is different from the two conductive thin films. For example, two conductive thin films, each serving as a gate electrode, can be electrically connected to each other by a plurality of conductive thin films that are different from the two conductive thin films. In this case, at least one of the plurality of conductive thin films is formed in a layer that is different from the two conductive thin films that each serve as a gate electrode.

[0061] Furthermore, one embodiment of the present invention is not limited to a structure in which an insulating thin film is provided between a plurality of conductive thin films, each serving as a gate electrode, and a conductive thin film for electrically connecting the plurality of conductive thin films to one another. In one embodiment of the present invention, a plurality of conductive thin films, each serving as a gate electrode, are formed in a process step that differs from that of a conductive thin film for electrically connecting the plurality of conductive thin films to one another. Therefore, an insulating thin film is not necessarily provided between the plurality of conductive thin films, each serving as a gate electrode, and the conductive thin film for electrically connecting the plurality of conductive thin films to one another. (Version 2)

[0062] In this embodiment, a shift register is described which is formed by a series connection of several Fig. The pulse generator 300 shown in section 4 is formed.

[0063] A shift register, as in Fig. Figure 5 shows a system containing pulse generators 300_1 to 300_y (where y is a natural number) and an empty pulse generator 300_d. Each pulse generator 300_1 to 300_y has a configuration that is identical to that of the one shown in Figure 5. Fig. The pulse generator shown in section 4 is similar. On the other hand, the configuration of the pulse generator 300_d differs from that of the one shown in section 4. Fig. 4 pulse generator 300 shown insofar as the pulse generator 300_d is not connected to the wiring 322, to which the potential RIN is applied, and does not contain the transistor 305.

[0064] At the in Fig. The 5 shift registers shown are the positions of the wiring connections 319 to 325 and 327 to 329, which are connected to the pulse generator 300_j. Fig. 7 are connected (j is a natural number less than or equal to y), shown schematically. As from Fig. 5 and Fig. As can be seen in Figure 7, a potential SROUTj-1, output from wiring 329 of the preceding pulse generator 300_j, is applied to wiring 319 of pulse generator 300_j as a potential LIN. The potential of a start pulse signal GSP is applied to wiring 319 of the first pulse generator 300_1.

[0065] A potential SROUTj+1, output by wiring 329 of the subsequent pulse generator 300j+1, is applied as potential RIN to wiring 322 of pulse generator 300_j. A potential SROUTd, output by wiring 329 of pulse generator 300_d, is applied as potential RIN to wiring 322 of pulse generator 300_y.

[0066] The potentials of two clock signals GCK1 to GCK4 are present at wires 321 and 323. Specifically, for pulse generator 300_4m+1, the potential of clock signal GCK1 is present at wire 323 as potential CLK1, and the potential of clock signal GCK2 is present at wire 321 as potential CLK2. For pulse generator 300_4m+2, the potential of clock signal GCK2 is present at wire 323 as potential CLK1, and the potential of clock signal GCK3 is present at wire 321 as potential CLK2. For pulse generator 300_4m+3, the potential of clock signal GCK3 is present at wire 323 as potential CLK1, and the potential of clock signal GCK4 is present at wire 321 as potential CLK2. In the case of the pulse generator 300_4m+4, the potential of the clock signal GCK4 is present at the wiring 323 as potential CLK1, and the potential of the clock signal GCK1 is present at the wiring 321 as potential CLK2.For pulse generator 300_d, the potential of the clock signal GCK1 is present at wiring 323 as potential CLK1, and the potential of the clock signal GCK2 is present at wiring 321 as potential CLK2. Note that m is an integer, and the condition is that the total number of pulse generators is 300y.

[0067] The potential of one of the pulse width control signals PWCA to PWCD and the potential of one of the pulse width control signals PWCa to PWCd is applied to wiring 324 and wiring 325, respectively. Specifically, for pulse generator 300_4m+1, the potential of pulse width control signal PWCa is present at wiring 325 as potential PWC1, and the potential of pulse width control signal PWCA is present at wiring 324 as potential PWC2. For pulse generator 300_4m+2, the potential of pulse width control signal PWCb is present at wiring 325 as potential PWC1, and the potential of pulse width control signal PWCB is present at wiring 324 as potential PWC2. For the pulse generator 300_4m+3, the potential of the pulse width control signal PWCc is present at wiring 325 as potential PWC1, and the potential of the pulse width control signal PWCC is present at wiring 324 as potential PWC2.For the 300_4m+4 pulse generator, the potential of the pulse width control signal PWCd is present at wire 325 as potential PWC1, and the potential of the pulse width control signal PWCD is present at wire 324 as potential PWC2. For the 300_d pulse generator, the potential of the pulse width control signal PWCa is present at wire 325 as potential PWC1, and the potential of the pulse width control signal PWCA is present at wire 324 as potential PWC2.

[0068] The potential GOUT1 of the wiring 327, which is connected to the pulse generator 300_j, is present at the scanning line GLaj.

[0069] The potential SROUT_j of wiring 329, which is connected to the pulse generator 300_j, is applied to the sampling line GLbj with reversed polarity via inverter 351_j. Specifically, the clock signal GCK2 is input to inverter 351_4m+1, and when the potential of the clock signal GCK2 is at a low level, the polarity of the potential SROUT_4m+1 is reversed, and then the potential is applied to the sampling line GLb4m+1. The clock signal GCK3 is input to inverter 351_4m+2, and when the potential of the clock signal GCK3 is at a low level, the polarity of the potential SROUT_4m+2 is reversed, and then the potential is applied to the sampling line GLb4m+2. The clock signal GCK4 is input into inverter 351_4m+3, and when the potential of the clock signal GCK4 is at a low level, the polarity of the potential SROUT_4m+3 is reversed, and then the potential is applied to the sample line GLb4m+3.The clock signal GCK1 is input into inverter 351_4m+4, and when the potential of the clock signal GCK1 is at a low level, the polarity of the potential SROUT_4m+4 is reversed, and then the potential is applied to the sample line GLb4m+4. The clock signal GCK2 is input into inverter 351_d, and when the potential of the clock signal GCK2 is at a low level, the polarity of the potential SROUT_d is reversed, and then the potential is applied to the sample line GLbd.

[0070] The potential GOUT2 of wiring 328, which is connected to the pulse generator 300_j, is applied to the scanning line GLcj with reversed polarity due to inverter 350_j. Specifically, the clock signal GCK2 is input to inverter 350_4m+2, and when the potential of the clock signal GCK2 is at a low level, the polarity of the potential GOUT2 is reversed, and then the potential is applied to the scanning line GLc4m+1. The clock signal GCK3 is input to inverter 350_4m+2, and when the potential of the clock signal GCK3 is at a low level, the polarity of the potential GOUT2 is reversed, and then the potential is applied to the scanning line GLc4m+2. The clock signal GCK4 is input into the inverter 350_4m+3, and when the potential of the clock signal GCK4 is at a low level, the polarity of the potential GOUT2 is reversed, and then the potential is applied to the sampling line GLc4m+3.The clock signal GCK1 is input into inverter 350_4m+4, and when the potential of the clock signal GCK1 is at a low level, the polarity of the potential GOUT2 reverses, and then the potential is applied to the sampling line GLc4m+4. The clock signal GCK2 is input into inverter 350_d, and when the potential of the clock signal GCK2 is at a low level, the polarity of the potential GOUT2 reverses, and then the potential is applied to the sampling line GLcd.

[0071] Next, a description of how the [system] works will be given. Fig. The pulse generator 300 shown in section 4 is described with reference to a flowchart that is in Fig. Figure 6 is shown. In this embodiment, the INRES potential is at the low level during all periods.

[0072] How Fig. Figure 6 shows that in one period t1, the potential CLK1 at wiring 323 is at the low level, the potential CLK2 at wiring 321 is at the low level, the potential of the pulse width control signal PWC1 at wiring 325 is at the low level, the potential of the pulse width control signal PWC2 at wiring 324 is at the low level, the potential LIN at wiring 319 is at the high level, and the potential RIN at wiring 322 is at the low level.

[0073] Thus, at pulse generator 300, during period t1, the potential (low level) of the pulse width control signal PWC1, which is present at wiring 325, is applied as potential GOUT1 to wiring 327. The potential (low level) of the pulse width control signal PWC2, which is present at wiring 324, is applied as potential GOUT2 to wiring 328. The potential CLK1 (low level), which is present at wiring 323, is applied as potential SROUT to wiring 329.

[0074] Next, as in Fig. Figure 6 shows that in one period t2, the potential CLK1 at wiring 323 is at the high level, the potential CLK2 at wiring 321 is at the low level, the level of the potential of the pulse width control signal PWC1 at wiring 325 changes from low to high, the potential of the pulse width control signal PWC2 at wiring 324 is at the low level, the potential LIN at wiring 319 is at the high level, and the potential RIN at wiring 322 is at the low level.

[0075] Thus, with pulse generator 300, during period t2, the potential (alternating from low to high level) of the pulse width control signal PWC1, which is present at terminal 325, is applied as potential GOUT1 to terminal 327. The potential (low level) of the pulse width control signal PWC2, which is present at terminal 324, is applied as potential GOUT2 to terminal 328. The potential CLK1 (high level), which is present at terminal 323, is applied as potential SROUT to terminal 329.

[0076] Next, as in Fig. Figure 6 shows that in one period t3, the potential CLK1 at wiring 323 is at the high level, the potential CLK2 at wiring 321 is at the low level, the potential of the pulse width control signal PWC1 at wiring 325 is at the high level, the potential of the pulse width control signal PWC2 at wiring 324 is at the high level, the level of the potential LIN at wiring 319 changes from high to low, and the potential RIN at wiring 322 is at the low level.

[0077] Thus, with pulse generator 300, during period t3, the potential (high level) of the pulse width control signal PWC1, which is present at wiring 325, is applied as potential GOUT1 to wiring 327. The potential (high level) of the pulse width control signal PWC2, which is present at wiring 324, is applied as potential GOUT2 to wiring 328. The potential CLK1 (high level), which is present at wiring 323, is applied as potential SROUT to wiring 329.

[0078] Next, as in Fig. Figure 6 shows that in one period t4, the potential CLK1 at wiring 323 is at the high level, the potential CLK2 at wiring 321 is at the low level, the level of the potential of the pulse width control signal PWC1 at wiring 325 changes from high to low, the potential of the pulse width control signal PWC2 at wiring 324 is at the high level, the potential LIN at wiring 319 is at the low level, and the potential RIN at wiring 322 is at the low level.

[0079] Thus, with pulse generator 300, during period t4, the potential (changing from high to low level) of the pulse width control signal PWC1, which is present at terminal 325, is applied as potential GOUT1 to terminal 327. The potential (high level) of the pulse width control signal PWC2, which is present at terminal 324, is applied as potential GOUT2 to terminal 328. The potential CLK1 (high level), which is present at terminal 323, is applied as potential SROUT to terminal 329.

[0080] Next, as in Fig. Figure 6 shows that in one period t5, the potential CLK1 at wiring 323 is at the low level, the potential CLK2 at wiring 321 is at the high level, the potential of the pulse width control signal PWC1 at wiring 325 is at the low level, the potential of the pulse width control signal PWC2 at wiring 324 is at the low level, the potential LIN at wiring 319 is at the low level, and the potential RIN at wiring 322 is at the high level.

[0081] Thus, in pulse generator 300, during period t5, the potential VEE (low level) present at terminal 326 is applied as potential GOUT1 to terminal 327. The potential VSS (low level) present at terminal 318 is applied as potential GOUT2 to terminal 328. The potential VSS (low level) present at terminal 318 is applied as potential SROUT to terminal 329.

[0082] In one embodiment of the present invention, as described in section "Embodiment 1", at least one of the respective gate electrodes of transistors 309, 312, and 315, corresponding to the output-side transistors, is electrically connected to the gate electrode of transistor 302 by a conductive thin film that is distinct from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 309, 312, 315, and 302 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the shift register described above according to an embodiment of the present invention.

[0083] This embodiment can optionally be implemented in combination with another embodiment. (Version 3)

[0084] Examples of the design of a pulse generator for a semiconductor device according to an embodiment of the present invention are described.

[0085] A pulse generator 400, as in Fig. Figure 8A, as shown according to the invention, contains transistors 402 to 404 and transistors 415 to 420. A shift register can be formed by connecting several pulse generators 400 in series.

[0086] One gate electrode of transistor 402 is connected to the respective gate electrodes of transistors 403 and 404; one of the source and drain terminals of transistor 402 is connected to a wire 406; and the other of the source and drain terminals of transistor 402 is connected to a gate electrode of transistor 420. One of the source and drain terminals of transistor 403 is connected to wire 406; and the other of the source and drain terminals of transistor 403 is connected to wire 414. One of the source and drain terminals of transistor 404 is connected to wire 407; and the other of the source and drain terminals of transistor 404 is connected to wire 413.

[0087] One gate electrode of transistor 415 is connected to a wire 408; one of the source and drain terminals of transistor 415 is connected to the gate electrode of transistor 420; and the other of the source and drain terminals of transistor 415 is connected to a wire 405. One gate electrode of transistor 416 is connected to a wire 409; one of the source and drain terminals of transistor 416 is connected to the respective gate electrodes of transistors 402, 403, and 404, respectively; and the other of the source and drain terminals of transistor 416 is connected to wire 405. One gate electrode of transistor 417 is connected to a wire 410; One of the source and drain terminals of transistor 417 is connected to the respective gate electrodes of transistors 402, 403 and 404; and the other of the source and drain terminals of transistor 417 is connected to the wiring 405.One gate electrode of transistor 418 is connected to wiring 408; one of the source and drain terminals of transistor 418 is connected to wiring 406; and the other source and drain terminal of transistor 418 is connected to the respective gate electrodes of transistors 402, 403, and 404. One gate electrode of transistor 419 is connected to the gate electrode of transistor 420; one source and drain terminal of transistor 419 is connected to wiring 414; and the other source and drain terminal of transistor 419 is connected to wiring 411. One source and drain terminal of transistor 420 is connected to wiring 413; and the other source and drain terminal of transistor 420 is connected to wiring 412.

[0088] If, in particular, transistors 402 to 404 and transistors 415 to 420 are n-channel transistors, the potential VDD is present at terminal 405, the potential VSS is present at terminal 406, and the potential VEE is present at terminal 407. The respective potentials of corresponding signals, such as clock signals, are present at terminals 408 to 412. The potentials GOUT and SROUT are output by terminals 413 and 414, respectively.

[0089] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 403 and 404, corresponding to transistors on the output side, is electrically connected to the gate electrode of transistor 402 by a conductive thin film provided in a layer different from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 403, 404, and 402 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the pulse generator 400 described above for a shift register or similar device according to an embodiment of the present invention.

[0090] In one embodiment of the present invention, the gate electrode of transistor 420, corresponding to a transistor on the output side, can be electrically connected to the gate electrode of transistor 419, which also corresponds to a transistor on the output side, by a conductive thin film provided in a layer separate from these gate electrodes. This structure makes a reduction in yield due to electrostatic destruction less likely in a semiconductor device using the pulse generator 400 described above for a shift register or the like, according to one embodiment of the present invention.

[0091] Although in Fig. 8A In embodiments of the present invention, one of the source and drain terminals of transistor 404 on the output side is connected to the wiring 407. The one of the source and drain terminals of transistor 404 on the output side can be connected to the wiring 406. The connection of one of the source and drain terminals of transistor 404 on the output side not to the wiring 406, but to the wiring 407, as shown in Fig. As shown in 8A, it is possible to safely block transistor 404 even in the case where it is a self-conducting transistor.

[0092] A pulse generator 430, as in Fig. Figure 8B shows transistors 432 to 434 and transistors 446 to 452. A shift register can be formed by connecting several pulse generators 430 in series.

[0093] One gate electrode of transistor 432 is connected to the respective gate electrodes of transistors 433 and 434; one of the source and drain terminals of transistor 432 is connected to a wire 436; and the other of the source and drain terminals of transistor 432 is connected to the respective gate electrodes of transistors 451 and 452. One of the source and drain terminals of transistor 433 is connected to wire 436; and the other of the source and drain terminals of transistor 433 is connected to wire 445. One of the source and drain terminals of transistor 434 is connected to wire 437; and the other of the source and drain terminals of transistor 434 is connected to wire 444.

[0094] One gate electrode of transistor 446 is connected to a wiring 438; one of the source and drain terminals of transistor 446 is connected to the respective gate electrodes of transistors 451 and 452; and the other of the source and drain terminals of transistor 446 is connected to a wiring 435. One gate electrode of transistor 447 is connected to a wiring 439; one of the source and drain terminals of transistor 447 is connected to the respective gate electrodes of transistors 432, 433, and 434; and the other of the source and drain terminals of transistor 447 is connected to wiring 435.One gate electrode of transistor 448 is connected to wiring 440; one of the source and drain terminals of transistor 448 is connected to the respective gate electrodes of transistors 432, 433, and 434; and the other of the source and drain terminals of transistor 448 is connected to wiring 435. One gate electrode of transistor 449 is connected to wiring 438; one of the source and drain terminals of transistor 449 is connected to wiring 436; and the other of the source and drain terminals of transistor 449 is connected to the respective gate electrodes of transistors 432, 433, and 434.One gate electrode of transistor 450 is connected to wiring 441; one of the source and drain terminals of transistor 450 is connected to the respective gate electrodes of transistors 432, 433, and 434; and the other of the source and drain terminals of transistor 450 is connected to wiring 435. One of the source and drain terminals of transistor 451 is connected to wiring 445; and the other of the source and drain terminals of transistor 451 is connected to wiring 442. One of the source and drain terminals of transistor 452 is connected to wiring 444; and the other of the source and drain terminals of transistor 452 is connected to wiring 443.

[0095] If, in particular, transistors 432 to 434 and transistors 446 to 452 are n-channel transistors, the potential VDD is present at terminal 435, the potential VSS is present at terminal 436, and the potential VEE is present at terminal 437. The respective potentials of corresponding signals, such as clock signals, are present at terminals 438 to 443. The potentials GOUT and SROUT are output by terminals 444 and 445, respectively.

[0096] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 433 and 434, corresponding to transistors on the output side, is electrically connected to the gate electrode of transistor 432 by a conductive thin film provided in a layer different from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 433, 434, and 432 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the pulse generator 430 described above for a shift register or similar device according to an embodiment of the present invention.

[0097] In one embodiment of the present invention, the gate electrode of transistor 452, corresponding to a transistor on the output side, can be electrically connected to the gate electrode of transistor 451, corresponding to a transistor on the output side, by a conductive thin film provided in a layer separate from these gate electrodes. This structure makes a reduction in yield due to electrostatic destruction less likely in a semiconductor device using the pulse generator 430 described above for a shift register or the like, according to one embodiment of the present invention.

[0098] Although in Fig. 8B, where one of the source and drain terminals of transistor 434 on the output side is connected to the wiring 437, embodiments of the present invention are not limited in this respect. One of the source and drain terminals of transistor 434 on the output side can be connected to the wiring 436. The connection of one of the terminals, the source terminal or the drain terminal of transistor 434 on the output side, not to the wiring 436, but to the wiring 437, as shown in Fig. As shown in Figure 8B, it is possible to safely block transistor 434 even in the case where it is a self-conducting transistor.

[0099] A pulse generator 460, as in Fig. Figure 9A contains transistors 462 to 464 and transistors 476 to 482. A shift register can be formed by connecting several pulse generators 460 in series.

[0100] One gate electrode of transistor 462 is connected to the respective gate electrodes of transistors 463 and 464; one of the source and drain terminals of transistor 462 is connected to a wire 466; and the other of the source and drain terminals of transistor 462 is connected to one of the source and drain terminals of transistor 477. One of the source and drain terminals of transistor 463 is connected to wire 466; and the other of the source and drain terminals of transistor 463 is connected to wire 475. One of the source and drain terminals of transistor 464 is connected to wire 467; and the other of the source and drain terminals of transistor 464 is connected to wire 474.

[0101] One gate electrode of transistor 476 is connected to a wire 468; one of the source and drain terminals of transistor 476 is connected to one of the source and drain terminals of transistor 477, and the other of the source and drain terminals of transistor 476 is connected to a wire 465. One gate electrode of transistor 477 is connected to wire 465; and the other of the source and drain terminals of transistor 477 is connected to the respective gate electrodes of transistors 481 and 482. One gate electrode of transistor 478 is connected to a wire 469; one of the source and drain terminals of transistor 478 is connected to the respective gate electrodes of transistors 462, 463, and 464. and the other of the source and drain terminals of transistor 478 is connected to the wiring 465.One gate electrode of transistor 479 is connected to wiring 468; one of the source and drain terminals of transistor 479 is connected to wiring 466; and the other of the source and drain terminals of transistor 479 is connected to the respective gate electrodes of transistors 462, 463, and 464. One gate electrode of transistor 480 is connected to wiring 470; one of the source and drain terminals of transistor 480 is connected to the respective gate electrodes of transistors 462, 463, and 464; and the other of the source and drain terminals of transistor 480 is connected to wiring 465. One of the source and drain terminals of transistor 481 is connected to wiring 475. and the other of the source and drain terminals of transistor 481 is connected to a wiring 471.One of the source and drain terminals of transistor 482 is connected to wiring 474; and the other of the source and drain terminals of transistor 482 is connected to wiring 472.

[0102] Specifically, if transistors 462 to 464 and transistors 476 to 482 are n-channel transistors, the potential VDD is present at terminal 465, the potential VSS is present at terminal 466, and the potential VEE is present at terminal 467. The respective potentials of corresponding signals, such as clock signals, are present at terminals 468 to 472. The potentials GOUT and SROUT are output by terminals 474 and 475, respectively.

[0103] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 463 and 464, corresponding to transistors on the output side, is electrically connected to the gate electrode of transistor 462 by a conductive thin film provided in a layer different from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 463, 464, and 462 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the pulse generator 460 described above for a shift register or similar device according to an embodiment of the present invention.

[0104] In one embodiment of the present invention, the gate electrode of transistor 482, corresponding to a transistor on the output side, can be electrically connected to the gate electrode of transistor 481, corresponding to a transistor on the output side, by a conductive thin film provided in a layer separate from these gate electrodes. This structure makes a reduction in yield due to electrostatic destruction less likely in a semiconductor device using the pulse generator 460 described above for a shift register or the like, according to one embodiment of the present invention.

[0105] Although in Fig. 9A In embodiments of the present invention, one of the source and drain terminals of transistor 464 on the output side is connected to the wiring 467. The one of the source and drain terminals of transistor 464 on the output side can be connected to the wiring 466. The connection of one of the source and drain terminals of transistor 464 on the output side not to the wiring 466, but to the wiring 467, as shown in Fig. As shown in 9A, it is possible to safely block transistor 464 even in the case where it is a self-conducting transistor.

[0106] A pulse generator 500, as in Fig. Figure 9B shows transistors 502 to 504 and transistors 516 to 523. A shift register can be formed by connecting several pulse generators 500 in series.

[0107] One gate electrode of transistor 502 is connected to the respective gate electrodes of transistors 503 and 504; one of the source and drain terminals of transistor 502 is connected to a wire 506; and the other of the source and drain terminals of transistor 502 is connected to one of the source and drain terminals of transistor 517. One of the source and drain terminals of transistor 503 is connected to wire 506; and the other of the source and drain terminals of transistor 503 is connected to wire 515. One of the source and drain terminals of transistor 504 is connected to wire 507; and the other of the source and drain terminals of transistor 504 is connected to wire 514.

[0108] One gate electrode of transistor 516 is connected to a wire 508; one of the source and drain terminals of transistor 516 is connected to one of the source and drain terminals of transistor 517; and the other of the source and drain terminals of transistor 516 is connected to a wire 505. One gate electrode of transistor 517 is connected to wire 505; the other of the source and drain terminals of transistor 517 is connected to a gate electrode of transistor 521. One gate electrode of transistor 518 is connected to a wire 509; one of the source and drain terminals of transistor 518 is connected to the respective gate electrodes of transistors 502, 503, and 504; and the other of the source and drain terminals of transistor 518 is connected to wire 505.One gate electrode of transistor 519 is connected to wiring 508; one of the source and drain terminals of transistor 519 is connected to wiring 506; and the other source and drain terminal of transistor 519 is connected to the respective gate electrodes of transistors 502, 503, and 504. One gate electrode of transistor 520 is connected to wiring 510; one of the source and drain terminals of transistor 520 is connected to the respective gate electrodes of transistors 502, 503, and 504; and the other source and drain terminal of transistor 520 is connected to wiring 505. One of the source and drain terminals of transistor 521 is connected to wiring 515. and the other of the source and drain terminals of transistor 521 is connected to a wiring 511.One gate electrode of transistor 522 is connected to wiring 505; one of the source and drain terminals of transistor 522 is connected to the gate electrode of transistor 521; and the other source and drain terminal of transistor 522 is connected to a gate electrode of transistor 523. One source and drain terminal of transistor 523 is connected to wiring 514; and the other source and drain terminal of transistor 523 is connected to wiring 512.

[0109] If, in particular, transistors 502 to 504 and transistors 516 to 523 are n-channel transistors, the potential VDD is present at terminal 505, the potential VSS is present at terminal 506, and the potential VEE is present at terminal 507. The respective potentials of corresponding signals, such as clock signals, are present at terminals 508 to 512. The potentials GOUT and SROUT are output by terminals 514 and 515, respectively.

[0110] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 503 and 504, corresponding to transistors on the output side, is electrically connected to the gate electrode of transistor 502 by a conductive thin film provided in a layer different from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 503, 504, and 502 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the pulse generator 500 described above for a shift register or similar device according to an embodiment of the present invention.

[0111] Although in Fig. 9B, where one of the source and drain terminals of transistor 504 on the output side is connected to the wiring 507, embodiments of the present invention are not limited in this respect. One of the source and drain terminals of transistor 504 on the output side can be connected to the wiring 506. The connection of one of the source and drain terminals of transistor 504 on the output side not to the wiring 506, but to the wiring 507, as shown in Fig. As shown in Figure 9B, it is possible to safely block transistor 504 even in the case where it is a self-conducting transistor.

[0112] A pulse generator 530, as in Fig. Figure 10 shows transistors 532 to 534 and transistors 546 to 553. A shift register can be formed by connecting several pulse generators 530 in series.

[0113] One gate electrode of transistor 532 is connected to the respective gate electrodes of transistors 533 and 534; one of the source and drain terminals of transistor 532 is connected to a wiring connection 536; and the other of the source and drain terminals of transistor 532 is connected to one of the source and drain terminals of transistor 552. One of the source and drain terminals of transistor 533 is connected to wiring connection 536; and the other of the source and drain terminals of transistor 533 is connected to wiring connection 545. One of the source and drain terminals of transistor 534 is connected to wiring connection 537; and the other of the source and drain terminals of transistor 534 is connected to wiring connection 544.

[0114] One gate electrode of transistor 546 is connected to a wiring 538; one of the source and drain terminals of transistor 546 is connected to one of the source and drain terminals of transistor 532; and the other of the source and drain terminals of transistor 546 is connected to a wiring 535. One gate electrode of transistor 547 is connected to a wiring 539; one of the source and drain terminals of transistor 547 is connected to the respective gate electrodes of transistors 532, 533, and 534; and the other of the source and drain terminals of transistor 547 is connected to wiring 535.One gate electrode of transistor 548 is connected to wiring 540; one of the source and drain terminals of transistor 548 is connected to the respective gate electrodes of transistors 532, 533, and 534; and the other of the source and drain terminals of transistor 548 is connected to wiring 535. One gate electrode of transistor 549 is connected to wiring 538; one of the source and drain terminals of transistor 549 is connected to wiring 536; and the other of the source and drain terminals of transistor 549 is connected to the respective gate electrodes of transistors 532, 533, and 534.One gate electrode of transistor 550 is connected to wiring 535; one of the source and drain terminals of transistor 550 is connected to one of the source and drain terminals of transistor 552; and the other of the source and drain terminals of transistor 550 is connected to a gate electrode of transistor 551. One of the source and drain terminals of transistor 551 is connected to wiring 545; and the other of the source and drain terminals of transistor 551 is connected to wiring 541. One gate electrode of transistor 552 is connected to wiring 535; and the other of the source and drain terminals of transistor 552 is connected to a gate electrode of transistor 553. One of the source and drain terminals of transistor 553 is connected to wiring 544. and the other of the source and drain terminals of transistor 553 is connected to a wiring 542.

[0115] If, in particular, transistors 532 to 534 and transistors 546 to 553 are n-channel transistors, the potential VDD is present at terminal 535, the potential VSS is present at terminal 536, and the potential VEE is present at terminal 537. The respective potentials of corresponding signals, such as clock signals, are present at terminals 538 to 542. The potentials GOUT and SROUT are output by terminals 544 and 545, respectively.

[0116] In one embodiment of the present invention, at least one of the respective gate electrodes of transistors 533 and 534, corresponding to transistors on the output side, is electrically connected to the gate electrode of transistor 532 by a conductive thin film provided in a layer different from these gate electrodes. This structure allows the area of ​​each conductive thin film serving as a gate electrode to be smaller than in the case where the respective gate electrodes of transistors 533, 534, and 532 are all formed from a single conductive thin film. Accordingly, the probability of electrostatic damage resulting from an antenna effect of the conductive thin film serving as a gate electrode will be reduced.Accordingly, a reduction in yield due to electrostatic destruction will be less likely in a semiconductor device using the pulse generator 530 described above for a shift register or similar device according to an embodiment of the present invention.

[0117] Although in Fig. 10. The embodiments of the present invention are not limited to the fact that one of the source and drain terminals of transistor 534 on the output side is connected to the wiring 537. One of the source and drain terminals of transistor 534 on the output side can be connected to the wiring 536. The connection of one of the source and drain terminals of transistor 534 on the output side not to the wiring 536, but to the wiring 537, as shown in Figure 10. Fig. As shown in Figure 10, it is possible to safely block the transistor 534 even in the case where it is a self-conducting transistor.

[0118] This embodiment can optionally be implemented in combination with another embodiment. (Version 4)

[0119] With reference to Fig. Section 11 describes cross-sectional structures of a pixel and a driver circuit in a semiconductor display device according to an embodiment of the present invention, using an OLED – an organic light-emitting device – as an example. As an example, in Fig. 11 cross-sectional views of a Pixel 840 and a driver circuit 841 are shown.

[0120] In Fig. 11. The Pixel 840 contains a light-emitting element 832 and a transistor 831 for controlling the power supply of the light-emitting element 832. In addition to the light-emitting element 832 and the transistor 831, the Pixel 840 can include various semiconductor elements, such as a transistor for controlling the application of an image signal to the Pixel 840 and a capacitor for holding the potential of an image signal.

[0121] Furthermore, it contains Fig. 11. The driver circuit 841 uses a transistor 830. Specifically, the transistor 830 corresponds to a transistor on the output side of a shift register that is part of the driver circuit 841. Besides the transistor 830, the driver circuit 841 can include various semiconductor elements, such as a transistor and a capacitor.

[0122] The transistor 831 has a conductive thin film 816, which serves as the gate electrode, on a substrate 800 with an insulating surface; a gate-insulating thin film 802; a semiconductor thin film 817, which is positioned over the gate-insulating thin film 802 so that it overlaps the conductive thin film 816; and conductive thin films 815 and 818, which are positioned over the semiconductor thin film 817 and serve as the source terminal and drain terminal, respectively. The conductive thin film 816 also serves as the scanning line.

[0123] The transistor 830 has a conductive thin film 812, which serves as a gate electrode, over the substrate 800 having an insulating surface; a gate-insulating thin film 802; a semiconductor thin film 813, which is provided over the gate-insulating thin film 802 such that it overlaps with the conductive thin film 812; and conductive thin films 814 and 819, which are provided over the semiconductor thin film 813 and serve as the source terminal and drain terminal, respectively.

[0125] Furthermore, a conductive thin film 850, which is provided over the substrate 800 having an insulating surface, serves as the gate electrode of a transistor that is different from the transistor 830.The conductive thin films 812 and 850 are connected to a conductive thin film 851, which is formed above the gate-insulating thin film 802, in corresponding openings formed in the gate-insulating thin film 802.

[0124] Additionally, conductive thin films 820 and 821 are stacked successively over conductive thin films 814, 815, 818, 819, and 851. Conductive thin films 852 and 853 are provided over insulating thin film 821. In corresponding openings formed in insulating thin films 820 and 821, conductive thin film 852 is connected to conductive thin film 851, and conductive thin film 853 is connected to conductive thin film 818.

[0125] Furthermore, an insulating thin film 854 is provided above the conductive thin films 852 and 853. A conductive thin film 822, serving as an anode, is provided above the insulating thin film 854. The conductive thin film 822 is connected to the conductive thin film 853 in an opening formed in the insulating thin film 854.

[0126] An insulating thin film 824 is provided above the insulating thin film 854, the insulating thin film having an opening through which a portion of the conductive thin film 822 is exposed. An EL layer 825 and a conductive thin film 826, serving as a cathode, are successively layered over the portion of the conductive thin film 822 and the insulating thin film 854. The area where the conductive thin film 822, the EL layer 825, and the conductive thin film 826 overlap corresponds to the light-emitting element 832.

[0127] In one embodiment of the present invention, a semiconductor thin film can be used for the transistor 830, 831, for which an amorphous, microcrystalline, polycrystalline or monocrystalline semiconductor made of silicon, germanium or the like is used, or a semiconductor thin film for which a semiconductor with a large band gap, such as an oxide semiconductor, is used.

[0128] In cases where an amorphous, microcrystalline, polycrystalline, or monocrystalline semiconductor such as silicon, germanium, or similar material is used for the semiconductor thin film of transistors 830 and 831, an impurity is added to the semiconductor thin film. This imparts a specific conductivity type, creating defect regions that serve as source and drain regions, respectively. For example, adding phosphorus or arsenic to the semiconductor thin film can create a defect region with n-type conductivity. Similarly, adding boron to the semiconductor thin film can create a defect region with p-type conductivity.

[0129] In the case where an oxide semiconductor is used for the semiconductor thin film of transistors 830 and 831, a dopant can be added to the semiconductor thin film, thereby forming impurity regions that serve as the source and drain regions, respectively. The dopant can be added by an ion implantation process. Examples of dopants include noble gases, such as helium, argon, and xenon, and elements of group 15, such as nitrogen, phosphorus, arsenic, and antimony. For example, in the case where nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is preferably greater than or equal to 5 × 10⁻⁶. 19 / cm 3 and less than or equal to 1 × 10 22 / cm 3 .

[0130] Any of the following can be used as a silicon semiconductor, for example: amorphous silicon, which is formed by a sputtering process or a gas-phase epitaxy process, such as a plasma-assisted CVD process; polycrystalline silicon, which is obtained by subjecting amorphous silicon to a process such as laser annealing; and monocrystalline silicon, which is obtained by separating a surface section of a monocrystalline silicon wafer by implanting hydrogen ions or similar substances into the wafer.

[0131] Regarding the oxide semiconductor, it is preferred that it contains at least indium (In) or zinc (Zn). Preferably, it contains both In and Zn. In addition to In and Zn, the oxide semiconductor preferably contains gallium (Ga) as a stabilizer, which, in transistors using the oxides described above, mitigates fluctuations in the electrical properties. Preferably, tin (Sn) is included as a stabilizer. Preferably, hafnium (Hf) is included as a stabilizer. Preferably, aluminum (Al) is included as a stabilizer.

[0132] As a further stabilizer, one or more lanthanides may be included, selected from: Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb) and Lutetium (Lu).

[0133] Examples of oxide semiconductors that can be used include: indium oxide, tin oxide, zinc oxide, an oxide containing two main metal components, such as an In-Zn-based oxide, an Sn-Zn-based oxide, an Al-Zn-based oxide, a Zn-Mg-based oxide, an Sn-Mg-based oxide, an In-Mg-based oxide, or an In-Ga-based oxide, an oxide containing three main metal components, such as an In-Ga-Zn-based oxide (also known as IGZO), an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, an Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, an Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, an oxide based on In-La-Zn-based, an In-Ce-Zn-based oxide, an In-Pr-Zn-based oxide, an In-Nd-Zn-based oxide, an In-Sm-Zn-based oxide, an In-Eu-Zn-based oxide, an In-Gd-Zn-based oxide, an In-Tb-Zn-based oxide, an In-Dy-Zn-based oxide, an In-Ho-Zn-based oxide, an In-Er-Zn-based oxide, an In-Tm-Zn-based oxide,An oxide based on In-Yb-Zn or an oxide based on In-Lu-Zn, or an oxide containing four main metal components, such as an oxide based on In-Sn-Ga-Zn, an oxide based on In-Hf-Ga-Zn, an oxide based on In-Al-Ga-Zn, an oxide based on In-Sn-Al-Zn, an oxide based on In-Sn-Hf-Zn, or an oxide based on In-Hf-Al-Zn. The oxide semiconductor may contain silicon.

[0134] For example, "In-Ga-Zn-based oxide" means an oxide containing In, Ga, and Zn, without any specific restriction on the ratio of In, Ga, and Zn. Furthermore, the In-Ga-Zn-based oxide may additionally contain an elemental metal other than In, Ga, and Zn. Moreover, the In-Ga-Zn-based oxide is suitable as a semiconductor material for a semiconductor device because its resistance in the absence of an electric field is sufficiently high, thus allowing for a sufficiently weak reverse current, and its mobility is high.

[0135] For example, an In-Ga-Zn-based oxide with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5), or an oxide with an atomic ratio close to one of the aforementioned ratios, can be used. Alternatively, an In-Sn-Zn-based oxide with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2), In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8), or an oxide with an atomic ratio close to one of the aforementioned ratios, can be used.

[0136] For example, high mobility can be achieved relatively easily when using an In-Sn-Zn-based oxide. However, mobility can also be increased when using an In-Ga-Zn-based oxide by reducing the impurity density.

[0137] Furthermore, a high-purity oxide semiconductor obtained by reducing impurities such as moisture and hydrogen, which act as electron donors, and by reducing oxygen vacancies, is intrinsically conductive (i-conducting) or substantially i-conducting. Consequently, a transistor using an oxide semiconductor is characterized by a very low reverse current. In addition, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and particularly 3 eV or more. Therefore, an oxide semiconductor thin film that is highly pure due to a sufficient reduction in the concentration of impurities such as moisture and water and a reduction in oxygen vacancies enables the reverse current of a transistor to be low.

[0138] In particular, a lower reverse current of a transistor using a high-purity oxide semiconductor for a thin semiconductor film can be demonstrated through various experiments. For example, even with an element size of 1 × 10⁻⁶ 6 With a channel length of 10 µm, a reverse current is achieved which is less than or equal to the measurement limit of the semiconductor parameter analyzer, i.e., which, at a voltage (drain voltage) between a source terminal and a drain terminal in the range of 1 V to 10 V, is less than or equal to 1 × 10 -13A is. In this case, it can be observed that the reverse current, corresponding to a value obtained by dividing the reverse current by the channel width of the transistor, is 100 zA / µm or less. Furthermore, the reverse current was measured using a circuit in which a capacitor and a transistor are connected, and the charge flowing to or from the capacitor is controlled by the transistor. In the measurement, a high-purity oxide semiconductor thin film was used for the channel formation area of ​​the transistor, and the transistor's reverse current was determined by measuring the change in the amount of charge on the capacitor per unit time. As a result, it was found that at a drain voltage of 3 V, a weaker reverse current of several tens of yoktoamperes per micrometer (yA / µm) is obtained.Consequently, a transistor whose channel formation area is formed in a high-purity oxide semiconductor thin film has a much weaker reverse current than a transistor using crystalline silicon.

[0139] In this description, unless otherwise specified, the "reverse current" of an n-channel transistor is a current that flows between the source and drain terminals when the gate electrode potential is 0 or less than the source terminal potential, provided the drain terminal potential is higher than either the source or gate electrode potential. Furthermore, unless otherwise specified, in this description, the "reverse current" of a p-channel transistor is a current that flows between the source and drain terminals when the gate electrode potential is 0 or greater than the source terminal potential, provided the drain terminal potential is lower than either the source or gate electrode potential.

[0140] For example, the oxide semiconductor thin film can be formed by a sputtering process using a target containing indium (In), gallium (Ga), and zinc (Zn). When forming an In-Ga-Zn-based oxide thin film by sputtering, the use of a target consisting of an In-Ga-Zn-based oxide with an atomic ratio of In:Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 is preferable. Forming an oxide semiconductor thin film using a target consisting of an In-Ga-Zn-based oxide with such an atomic ratio increases the likelihood of forming a polycrystal or a c-axis aligned crystal (CAAC). Furthermore, the relative density of the target containing In, Ga and Zn is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than 100%.The target with such a high relative density enables the formation of a dense oxide-semiconductor thin film.

[0141] When using an In-Zn-based oxide as the oxide semiconductor, the target has an atomic ratio of In:Zn = 50:1 to 1:2 (In₂O₃:ZnO = 25:1 to 1:4 molar ratio), preferably In:Zn = 20:1 to 1:1 (In₂O₃ZnO = 10:1 to 1:2 molar ratio), and particularly In:Zn = 15:1 to 1.5:1 (In₂O₃ZnO = 15:2 to 3:4 molar ratio). For example, in a target used for forming an oxide-semiconductor thin film containing an In-Zn-based oxide, the relation Z > 1.5X + Y is satisfied, where the atomic ratio In:Zn:O = X:Y:Z applies. Mobility can be improved by keeping the Zn content within the range mentioned above.

[0142] The oxide semiconductor thin film is monocrystalline, polycrystalline (also called polycrystal), amorphous, or similar.

[0143] The oxide semiconductor thin film is preferably a CAAC-OS thin film (a crystalline oxide semiconductor oriented with respect to the c-axis).

[0144] The CAAC-OS thin film is neither completely monocrystalline nor completely amorphous. It is an oxide-semiconductor thin film with a crystalline / amorphous mixed-phase structure, in which crystalline regions are embedded within an amorphous phase. In most cases, the size of the crystalline region fits within a cube with an edge length of less than 100 nm. Furthermore, as observed using a transmission electron microscope image, the boundary between the amorphous and crystalline regions is not clearly defined in the CAAC-OS thin film. Additionally, no grain boundary was detected in the CAAC-OS thin film using TEM. Consequently, the reduction in electron mobility typically attributed to grain boundaries is suppressed in the CAAC-OS thin film.

[0145] In each of the crystal regions enclosed in the CAAC-OS thin film, the c-axis is oriented in a direction parallel to a normal vector of the surface on which the CAAC-OS thin film is formed, or to a normal vector of a surface of the CAAC-OS thin film, in the case of a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab-plane, with metal atoms arranged in a layered manner, or with metal and oxygen atoms arranged in a layered manner when viewed from the direction perpendicular to the c-axis. For the crystal regions, both or one of the directions corresponding to the a-axis and the b-axis may differ. In this description, "exactly perpendicular" means within a range of 85° to 95°. Furthermore, "exactly parallel" means within a range of -5° to 5°.

[0146] In CAAC-OS thin films, the distribution of crystal regions is not necessarily uniform. For example, during the formation process of CAAC-OS thin films, if crystal growth originates from one surface side of the oxide-semiconductor thin film, the proportion of crystal regions near the surface of the oxide-semiconductor thin film is sometimes higher than near the surface where the oxide-semiconductor thin film forms. Furthermore, if a foreign atom is added to the CAAC-OS thin film, the crystal region in the area where the foreign atom is added may become amorphous in some cases.

[0147] Since the c-axes of the crystal regions enclosed in the CAAC-OS thin film are oriented parallel to a normal vector of the surface on which the CAAC-OS thin film forms, or to a normal vector of a surface of the CAAC-OS thin film, the directions of the c-axes can differ depending on the shape of the CAAC-OS thin film (the cross-sectional shape of the surface on which the CAAC-OS thin film forms, or the cross-sectional shape of the surface of the CAAC-OS thin film). It is important to note that the direction of the c-axis of the crystal region is that which is parallel to a normal vector of the surface on which the CAAC-OS thin film forms, or parallel to a normal vector of the surface of the CAAC-OS thin film. The crystal region forms during thin-film formation or through a crystal-forming treatment, such as heat treatment after thin-film formation.

[0148] By using the CAAC-OS thin film in a transistor, changes in the transistor's electrical properties caused by irradiation with visible or UV light can be reduced. Consequently, the transistor exhibits high reliability.

[0149] For example, the CAAC-OS thin film is formed by a sputtering process using a polycrystalline oxide semiconductor target. When ions collide with the sputtering target, a crystal region contained within the target can be cleaved along the ab plane, allowing a plate- or bead-like sputtered particle with a plane parallel to the ab plane to be separated from the target. In this case, the plate-like sputtered particle, retaining its crystalline state, reaches a substrate, thus forming the CAAC-OS thin film.

[0150] The following conditions are preferably applied during the formation of the CAAC-OS thin film.

[0151] By reducing the amount of foreign substances that penetrate the CAAC-OS thin film during its formation, it is possible to prevent the crystal structure from being ruined by these substances. For example, the concentration of foreign substances present in the coating chamber (e.g., hydrogen, water, carbon dioxide, or nitrogen) can be reduced. Furthermore, the concentration of foreign substances in the deposition gas can be reduced. In particular, a deposition gas with a dew point of -80 °C or lower, preferably -100 °C or lower, is used.

[0152] Furthermore, increasing the heating temperature of the substrate during thin-film formation causes a migration of a atomized particle after it reaches the substrate. Specifically, the heating temperature of the substrate during thin-film formation is higher than or equal to 100°C and lower than or equal to 740°C, preferably higher than or equal to 200°C and lower than or equal to 500°C. Upon increasing the heating temperature of the substrate during thin-film formation, migration occurs when a plate-like atomized particle reaches the substrate, such that a flat surface of the plate-like atomized particle adheres to the substrate.

[0153] Furthermore, it is preferable that the oxygen content of the deposition gas is high and the energy flow is optimized to minimize plasma damage during thin-film formation. The oxygen content of the deposition gas is 30 vol% or more, preferably 100 vol%.

[0154] As an example of the atomization target, a target made of an In-Ga-Zn-O compound is described below.

[0155] The target, consisting of an In-Ga-Zn-O compound and being polycrystalline, is formed by mixing InO x -powder, GaO y -powder and ZnO z Powder in a specified molar ratio is produced by applying pressure to the mixture and performing a heat treatment at a temperature above or equal to 1000 °C and below or equal to 1500 °C. Note that X, Y, and Z are specified positive numbers. Here, the specified molar ratio is InO. x -Powder: GaO y -Powder: ZnOz -Powders, for example, in ratios of 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The types of powder and the molar ratio in which the powders are mixed can be tailored to the atomization target.

[0156] This embodiment can optionally be implemented in combination with another embodiment. (Version 5)

[0157] Within the scope of this embodiment, an example of a screen is described that corresponds to an embodiment of a semiconductor display device. A screen, as in Fig. Figure 12 shows a substrate 700, and above the substrate 700 a pixel part 701, a signal line driver circuit 702a, a signal line driver circuit 702b, a scanning line driver circuit 703a and a scanning line driver circuit 703b.

[0158] The pixel section 701 contains a plurality of pixels. Each pixel contains a display element and one or more transistors for controlling the operation of the display element. The scan line driver circuits 703a and 703b provide potentials for scanning lines connected to the pixels in order to select pixels in the pixel section 701. The signal line driver circuits 702a and 702b control the delivery of image signals to the pixels selected by the scan line driver circuits 703a and 703b.

[0159] In Fig. Figure 12 shows a case in which the scanning line driver circuits 703a and 703b supply a potential to the scanning line from both sides of the pixel part 701. This structure makes it possible to prevent a potential drop caused by a line resistance of the scanning line in the pixel part 701, even if the scanning line is lengthened as a result of an increase in the size of the pixel part 701.

[0160] The 702a and 702b signal line driver circuits deliver image signals to the pixels via signal lines. Fig. 12 The signal line driver circuit 702a delivers image signals to the pixels via odd-numbered signal lines, and the signal line driver circuit 702b delivers image signals to the pixels via even-numbered signal lines.

[0161] In Fig. Figure 12 shows a case in which the scanning line driver circuits 703a and 703b are formed together with the pixel part 701 on the substrate 700, and the signal line driver circuits 702a and 702b are each formed on a chip and then mounted onto the substrate 700 by a film bonding (TAB) process. Alternatively, the scanning line driver circuits 703a and 703b can each be formed on a chip and then mounted onto the substrate 700, and the signal line driver circuits 702a and 702b can be formed together with the pixel part 701 on the substrate 700. Furthermore, the method for bonding the chip is not limited to the TAB process. The chip can be mounted on the substrate 700 using a flexible printed circuit (FPC) or similar, or it can instead be mounted on the substrate 700 using a chip-on-film (COF) process.

[0162] Since the scanning lines are connected to a large number of pixels, the required current delivery capability of each of the scanning line driver circuits 703a and 703b is high. Therefore, each transistor located on the output side of a pulse output circuit contained in the scanning line driver circuits 703a and 703b must be large. The line resistance of the scanning lines, or the load connected to the scanning lines, increases, in particular, if the number of pixels in the pixel section 701 is increased or the area of ​​the pixel section 701 is enlarged; this necessitates further increasing the dimensions of the transistor described above to provide a higher current delivery capability.Such an increase in the size of the transistor described above is accompanied by an increase in the area of ​​a conductive thin film, which serves as the gate electrode for a large number of transistors in the scanning line driver circuit 703a, 703b, resulting in an increase in the probability of electrostatic destruction of the wiring described above due to an antenna effect.However, in one embodiment of the present invention, the plurality of gate electrodes are electrically connected to each other by a conductive thin film provided in a layer different from the gate electrodes; consequently, the area of ​​each conductive thin film serving as a gate electrode can be kept small, so that the probability of electrostatic destruction due to an antenna effect can be lower even if the number of pixels in the pixel part 701 is increased or the area of ​​the pixel part 701 is enlarged.

[0163] Although a case has been described in this embodiment in which the structure according to one embodiment of the present invention was applied to the scanning line driver circuit 703a, 703b, the structure according to one embodiment of the present invention can also be applied to the signal line driver circuit 702a, 702b.

[0164] This embodiment can optionally be implemented in combination with another embodiment. (Version 6)

[0165] A semiconductor device according to one embodiment of the present invention can be used for display devices, personal computers, or image reproduction devices in which recording media are provided (typically devices that reproduce the contents of recording media such as DVDs (Digital Versatile Discs) and have screens for displaying the reproduced images). In addition to the examples given above, electronic devices that can utilize the display device according to one embodiment of the present invention include mobile phones, gaming machines (including portable gaming devices), portable information devices, e-book readers, cameras such as video cameras and digital cameras, eyeglass screens (head-mounted screens), navigation systems, and audio playback devices (e.g.,...).Car audio components and digital audio players), copiers, fax machines, printers, multifunction printers, ATMs, vending machines and the like. Fig. Sections 13A to 13E show specific examples of these electronic devices.

[0166] Fig. Figure 13A shows a portable gaming device comprising a housing 5001, a housing 5002, a screen part 5003, a screen part 5004, a microphone 5005, a loudspeaker 5006, an operating switch 5007, a stylus 5008, and the like. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit or the screen part(s) 5003 and / or 5004 of the portable gaming device, making it possible to manufacture the portable gaming device with a high yield. While the Fig. Figure 13A shows a portable gaming device with two screen parts 5003 and 5004, but the number of screen parts included in the portable gaming device is not limited to two.

[0167] Fig. Figure 13B shows a display device comprising a housing 5201, a screen part 5202, a stand 5203, and the like. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit or the screen part 5202 of the display device, making it possible to manufacture the display device with high yield. The category of display device includes any display device for showing information, such as displays for personal computers, television reception, and advertising.

[0168] Fig. Figure 13C shows a laptop comprising a screen frame 5401, a screen part 5402, a keyboard 5403, a pointing device 5404, and the like. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit or the screen part 5402 of the laptop, making it possible to manufacture the laptop with high yield.

[0169] Fig. Figure 13D shows a portable information device comprising a first housing 5601, a second housing 5602, a first screen section 5603, a second screen section 5604, a joint 5605, an operating switch 5606, and the like. The first screen section 5603 is intended for the first housing 5601, and the second screen section 5604 is intended for the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other by means of the joint 5605 such that the angle between the first housing 5601 and the second housing 5602 can be changed by means of the joint. Depending on the angle between the first housing 5601 and the second housing 5602, an image on the first screen section 5603 can be changed or switched at the joint 5605. A semiconductor display device with a position input function can be used for at least one part, the first screen part 5603 or / and the second screen part 5604.Such a position input function can be provided by including an interactive control panel for the semiconductor display device. The position input function can also be provided by including a photoelectric transducer element, called a photodetector, in a pixel portion of the semiconductor display device. The semiconductor component according to one embodiment of the present invention can be used for a driver circuit or for the first screen portion 5603 and / or the second screen portion 5604 of the portable information device, making it possible to manufacture the portable information device with high yield.

[0170] Fig.Figure 13E shows a mobile phone comprising a housing 5801, a screen section 5802, an audio input section 5803, an audio output section 5804, control buttons 5805, a light reception section 5806, and the like. Light received in the light reception section 5806 is converted into electrical signals, enabling the acquisition of external images. The semiconductor device according to one embodiment of the present invention can be used for a driver circuit or the screen section 5802 of the mobile phone, making it possible to manufacture the mobile phone with high yield.

[0171] This embodiment can optionally be implemented in combination with another embodiment.

Claims

[1] Semiconductor device, comprising: first to seventh transistors and first to sixth wiring connections, where the first to seventh transistors have the same polarities, wherein one of a source and a drain of the first transistor (404) is electrically connected to the third wiring (407), the other is electrically connected to the first wiring (413) from the source and drain of the first transistor (404), wherein one of the source and drain of the second transistor (420) is electrically connected to the first wiring (413), wherein the other is electrically connected from the source and drain of the second transistor (420) to the fourth wiring (412), wherein one of a source and a drain of the third transistor (403) is electrically connected to the fifth wiring (406), wherein the other is electrically connected to the second wiring (414) from the source and drain of the third transistor (403), wherein a gate of the third transistor (403) is electrically connected to a gate of the first transistor (404), wherein one of a source and a drain of the fourth transistor (419) is electrically connected to the second wiring (414), where one clock signal is input into the other from the source and drain of the fourth transistor (419), wherein a gate of the fourth transistor (419) is electrically connected to a gate of the second transistor (420), wherein one of a source and a drain of the fifth transistor (402) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the fifth transistor (402) to the gate of the second transistor (420), wherein one of a source and a drain of the sixth transistor (415) is electrically connected to the gate of the second transistor (420), the other is electrically connected to the sixth wiring (405) from the source and drain of the sixth transistor (415), wherein one of a source and a drain of the seventh transistor (418) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the seventh transistor (418) to the gate of the first transistor (404), where the first wiring (413) is configured to output a first signal (GOUT), where the second wiring (414) is configured to output a second signal (SROUT), where a first low-level potential (VEE) is applied to the third wiring (407), where a second low-level potential (VSS) is applied to the fifth wire (406), where a high-level potential (VDD) is applied to the sixth wire (405), wherein a first conductive layer (115), which has a function as the gate of the first transistor (404), is electrically connected to a third conductive layer (110), which has a function as the gate of the fifth transistor (402), via a second conductive layer (119), wherein an area in which the first conductive layer (115) and a semiconductor thin film (116) of the first transistor (404) overlap is larger than an area in which the third conductive layer (110) and a semiconductor thin film (112) of the fifth transistor (402) overlap, and wherein the second conductive layer (119) has no area that overlaps with all semiconductor thin layers of the first to seventh transistors. [2] Semiconductor device, comprising: first to seventh transistors and first to sixth wiring connections, where the first to seventh transistors have the same polarities, wherein one of a source and a drain of the first transistor (404) is electrically connected to the third wiring (407), the other is electrically connected to the first wiring (413) from the source and drain of the first transistor (404), wherein one of the source and drain of the second transistor (420) is electrically connected to the first wiring (413), wherein the other is electrically connected from the source and drain of the second transistor (420) to the fourth wiring (412), wherein one of a source and a drain of the third transistor (403) is electrically connected to the fifth wiring (408), wherein the other is electrically connected to the second wiring (414) from the source and drain of the third transistor (403), wherein a gate of the third transistor (403) is electrically connected to a gate of the first transistor (404), wherein one of a source and a drain of the fourth transistor (419) is electrically connected to the second wiring (414), where one clock signal is input into the other from the source and drain of the fourth transistor (419), wherein a gate of the fourth transistor (419) is electrically connected to a gate of the second transistor (414), wherein one of a source and a drain of the fifth transistor (402) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the fifth transistor (402) to the gate of the second transistor (420), wherein one of a source and a drain of the sixth transistor (415) is electrically connected to the gate of the second transistor (420), the other is electrically connected to the sixth wiring (405) from the source and drain of the sixth transistor (415), wherein one of a source and a drain of the seventh transistor (418) is electrically connected to the fifth wiring (406), wherein the other is electrically connected from the source and drain of the seventh transistor (418) to the gate of the first transistor (404), where the first wiring (413) is configured to output a first signal (GOUT), where the second wiring (414) is configured to output a second signal (SROUT), where a first low-level potential (VEE) is applied to the third wiring (407), wherein a second low-level potential (VSS) is applied to the fifth wire (406), wherein the first low-level potential (VEE) is equal to or higher than the second low-level potential (VSS), where a high-level potential (VDD) is applied to the sixth wire (405), wherein a first conductive layer (115), which has a function as the gate of the first transistor (404), is electrically connected to a third conductive layer (110), which has a function as the gate of the fifth transistor (402), via a second conductive layer (119), wherein an area in which the first conductive layer (115) and a semiconductor thin film (116) of the first transistor (404) overlap is larger than an area in which the third conductive layer (110) and a semiconductor thin film (112) of the fifth transistor (402) overlap, wherein the second conductive layer (119) has no area that overlaps with all semiconductor thin layers of the first to seventh transistors, and wherein the second conductive layer (119) is arranged above the first conductive layer (115) or the third conductive layer (110).

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