Ceramic multilayer capacitor

Abstract

Ceramic multilayer capacitor (1) comprising: - a base body (2) comprising ceramic layers (3) arranged in a stack along a layer stacking direction (S), and first and second electrode layers (41, 42) arranged between the ceramic layers (3), wherein the base body (2) has a cuboid shape, - a first external contact (51) arranged on a first side face (61) of the base body (2) and electrically connected to the first electrode layers (41), and - a second external contact (52) arranged on a second side face (62) of the base body (2) opposite the first side face (61) and electrically connected to the second electrode layers (42), wherein - the base body (2) has a width B along the layer stacking direction (S), - the base body (2) has a height H perpendicular to the first side face (61),- the base body (2) has a length L perpendicular to the height H and perpendicular to the layer stacking direction (S), - where B / H ≥ 0.2, where the ceramic layers (3) have a ceramic material for which the following formula applies: Pb(1-1.5a-0.5b+1.5d+e+0.5f) AaBb(Zr1-xTix)1-cde-fLidCeFefSicO3+ y·PbO(I) where A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb; B is selected from the group consisting of Na, K and Ag; C is selected from the group consisting of Ni, Cu, Co and Mn; and 0 <a<0,120,05<x<0,30≤b<0,120≤c<0,120≤d<0,120≤e<0,12,0≤f<0,12,0≤y<1,wobeib+d+e+f> 0.,

Description

A multilayer ceramic capacitor, which is preferably suitable for high-power applications, is specified. The multilayer capacitor can be used, for example, as a filter element in an AC / DC or DC / DC converter.The publication WO 2011 / 085932 A1 describes a capacitor which comprises a heating element and a capacitor region with dielectric layers and inner electrodes arranged between the layers, wherein the heating element and the capacitor region are connected to one another in a thermally conductive manner.Ceramic multilayer components are described in the publications U.S. Pat. No. 7,808,770 B2, JP 2000-106 320 A and DE 103 45 500 A1.It is an object to be achieved of at least some embodiments to specify a ceramic multilayer capacitor which has improved properties, such as, for example, a particularly low ESR value (equivalent series resistance), in comparison with known multilayer capacitors.This object is achieved by an object according to the independent claim. Advantageous embodiments and developments of the subject matter are furthermore evident from the dependent patent claims, the following description and from the drawings.A ceramic multilayer capacitor according to at least one embodiment has a main body. The base body has a rectangular parallelepiped shape. The base body comprises dielectric layers which are arranged along a layer stacking direction to form a stack. The dielectric layers are preferably formed as ceramic layers. Furthermore, the base body comprises first and second electrode layers which are arranged between the ceramic layers. For example, a first and a second electrode layer can be arranged spaced apart from one another in the same layer plane. Furthermore, the first and second electrode layers can each be arranged in different layer planes of the stack.According to a further embodiment, the base body comprises a first external contact. The external contact is preferably arranged on a first side surface of the base body and is electrically conductively connected to the first electrode layers. The first electrode layers are preferably directly electrically conductively connected to the first external contact, that is to say the first electrode layers directly adjoin the first external contact and are directly connected to the first external contact. The first electrode layers preferably extend as far as the first side surface.Furthermore, the base body has a second external contact which is arranged on a second side surface of the base body opposite the first side surface and is electrically conductively connected to the second electrode layers. The second electrode layers are preferably directly electrically conductively connected to the second external contact, that is to say the second electrode layers directly adjoin the second external contact and are directly connected to the second external contact. The second electrode layers preferably extend as far as the second side surface.According to a further embodiment, the base body has a width B along the layer stacking direction. In this case, B denotes the spatial extent of the main body of the multilayer capacitor along the layer stacking direction. Furthermore, the base body has a height H perpendicular to the first side face. The height H can thus be understood as a spatial extent of the base body perpendicular to the first side surface of the base body. Preferably, the height H also extends perpendicular to the second side surface of the base body. Furthermore, the base body has a length L perpendicular to the height H and perpendicular to the layer stacking direction. The length L consequently denotes the spatial extent of the base body in a direction perpendicular to the width B and to the height H.According to a further embodiment, the relationship B / H≥0.2 applies to the ratio of the width B to the height H. According to a preferred embodiment, B / H≥0.3. According to a particularly preferred embodiment, B / H≈0.35.According to a further embodiment, L / B≥1 applies to the ratio of the length L to the width B. Furthermore, L / B≤5, and particularly preferably L / B≤3.5, applies.According to a further embodiment, L / H≥0.8 applies to the ratio of the length L to the height H. L / H≥1.1.The ratios specified here between the width B and the height H of the base body can significantly increase the ratio of the supply cross section of the electrode layers to the useful cross section, that is to say to the area determining the capacitance, in the case of a ceramic multilayer capacitor described here. This makes it possible to achieve that the ceramic multilayer capacitor described here has a particularly low ESR value (equivalent series resistance). For example, a ceramic multilayer capacitor described here, e.g. having a capacitance between 4 μF and 10 μF, can have an ESR between 3 mΩ and 5 mΩ when operating at a frequency between 100 kHz and 1 MHz.According to a further embodiment, the base body has third electrode layers which are not electrically conductively connected either to the first or to the second external contact. Preferably, the third electrode layers are not electrically conductively connected to any external contacting. The third electrode layers can also be referred to here and in the following as free electrodes (floating electrodes).According to a further embodiment, the third electrode layers overlap with the first electrode layers. In other words, the third electrode layers each have at least one subregion which could be brought into congruence with at least one subregion of the first electrode layers in the case of a conceptual projection in the layer stack direction of the stack. Further, the third electrode layers may overlap with the second electrode layers. For example, a first and a second electrode layer can be arranged spaced apart from one another in the same layer plane of the base body and can each overlap with at least one third electrode arranged in a further layer plane.The use of first, second and free third electrode layers, i.e. the use of serial internal electrodes, advantageously brings about an increase in the breakdown field strength, which has a favourable effect on the robustness and the reliability of the multilayer capacitor. Furthermore, this enables a lowering of the dielectric layer thickness, i.e. of the layer thickness of the ceramic layers, which results in an increase of the cross section of an electrode layer per volume of ceramic and thus an improvement of the ESR value (equivalent series resistance) and an improvement of the current-carrying capacity of the component for application currents.According to a further embodiment, the ceramic layers have a layer thickness between 3 μm and 200 μm. According to a further preferred embodiment, the ceramic layers have a layer thickness between 10 μm and 100 μm. The ceramic layers particularly preferably have a layer thickness of approximately 25 μm.According to a further embodiment, the electrode layers have a layer thickness between 0.1 μm and 10 μm. According to a preferred embodiment, the electrode layers have a layer thickness between 1 μm and 4 μm. Particularly preferably, the electrode layers have a layer thickness of approximately 3.5 μm.According to a further embodiment, the base body has at least ten ceramic layers. According to a further embodiment, the base body has at least ten first electrode layers. According to a further embodiment, the base body has at least ten second electrode layers.According to a further embodiment, the following relationship applies for the number of first electrode layers provided in the base body and the width B of the base body: ratio of the number of first electrode layers to the width B≥10 / mm. In other words, the base body has at least ten first electrode layers per mm width. Furthermore, the base body preferably has at least ten second electrode layers per mm width.According to a further embodiment, the electrode layers comprise a base metal. Preferably, the electrode layers comprise copper. According to a preferred embodiment, the electrode layers consist of copper. In particular after sintering of the multilayer capacitor, the electrode layers can consist of pure copper. Due to the high thermal and electrical conductivity of copper, a particularly low ESR value (equivalent series resistance) can be achieved in the multilayer capacitor described here. Furthermore, the use of base metals advantageously makes it possible to reduce the production process of the multilayer capacitor.According to a further embodiment, the first and second side surfaces are surface-treated. For example, the first and second side surfaces may be lapped. Furthermore, it is possible for the first and second side surfaces to be ground, buffed or plasma-etched. By means of the surface-treated side surfaces, particularly good contact between the external contacts and the first or second electrode layers can advantageously be achieved. In particular, by means of the surface treatment of the first and second side surfaces, ceramic material present between individual first electrode layers or between individual second electrode layers can be removed, so that the first and second electrode layers can be securely brought to the surface of the base body by process technology. For example, the external contacts can then be applied without burning in a gas flow, for example using a standard sputtering process.According to a further embodiment, the first and the second external contacting each have at least one first sputtering layer, wherein the first sputtering layers are in direct contact with the first or second electrode layers. Preferably, a first sputtering layer is applied to the first side surface of the base body, which sputtering layer is in direct contact with exit surfaces of the first electrode layers from the base body. Likewise, a first sputtering layer can be applied to the second side surface of the base body, which sputtering layer is in direct contact with exit surfaces of the second electrode layers from the base body. The sputter layers can have a layer thickness between 0.1 μm and 1.5 μm, for example. Preferably, the first sputter layers comprise or consist of chromium. According to a further embodiment, the first and the second external contacting each have a second sputtering layer, wherein the second sputtering layers are preferably applied directly to the first sputtering layers. The second sputtering layers preferably comprise copper or consist of copper.According to a further embodiment, the first and the second external contacting each have a third sputtering layer, wherein the third sputtering layers are preferably applied directly on the second sputtering layers. The third sputter layers preferably comprise gold or consist of gold. Alternatively, the third sputtering layers can also comprise silver or consist of silver.According to the invention, the ceramic layers comprise a ceramic material, for which the following formula applies: Pb (1-1,5a-0,5b+1,5d+e+0,5f) A a B b( Zr 1-x Ti x)1-c-d-e-f Li d C e Fe f Si c O 3+ y·PbO (I) wherein A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb; wherein B is selected from the group consisting of Na, K and Ag; and wherein C is selected from the group consisting of Ni, Cu, Co and Mn; where 0<a<0.12; 0.05≤x≤0.3; 0≤b<0.12; 0≤c<0.12; 0≤d<0.12; 0≤e<0.12; 0≤f<0.12; 0≤y<1, wherein b+d+e+f>0.Preferably, a particularly Zr-rich PZT mixed crystal phase is selected from the phase diagram. In addition, the condition b+d+e+f>0 specifies that in addition to a dopant from the defined group A (rare earth element), at least one element from the group consisting of Li, Na, K, Ag, Fe, Ni, Cu, Co and Mn (lithium, iron and groups B and C) must be present in the ceramic material. As a result, a ceramic material sinterable at temperatures of 1000° C. to 110° C. can be provided, which enables a combination with other materials / materials not resistant at higher temperatures already during the production process of the ceramic material. For example, sintering of the ceramic material ("co-firing") with electrode layers of base metals, such as silver or copper, becomes possible. In addition, the ceramic material has a higher switching field strength and / or higher relative permittivity (dielectric constant) compared with the PZT material doped only by group A.In addition, low sintering temperatures promote the formation of small grain sizes of the ceramic material, which has a favourable influence on the dielectric properties. More specifically, the dielectric properties of PZT ceramics are generally also determined by the domain size. Domains are understood to mean regions in the ceramic with the same polarization. The domain size is dependent on the grain size. The number of domains per grain increases with increasing grain size. The altered domain size has consequences for the material properties of the ceramic. It is thus desirable to be able to control the grain size or the grain growth.The doped lead zirconate titanate ceramic preferably has a perovskite lattice, which can be described by the general formula ABO 3 wherein A stands for the A sites and B stands for the B sites of the perovskite lattice.The perovskite lattice is distinguished by a high tolerance with respect to dopings and vacancies.The perovskite structure of the lead zirconate titanate (PZT) can be described by the general formula ABO 3. An elementary cell of the PZT crystal lattice can be described by a cube. The A-sites are occupied by Pb 2+- ions which sit on the corners of the cube. In the middle of each cube surface there is an O 2- ion in each case. At the center of the cube there is a Ti 4+- ion and a Zr 4+- ion (B sites). This structure has a high tolerance to substitution of the metal ions by other metal ions and defects, and therefore it can be well doped.Depending on the difference in size between the ion introduced by doping and the ion replaced, the highly symmetrical coordination polyhedron can be distorted. This distortion can alter the center of symmetry of the crystal and thus affect polarizability.The different possibilities of doping can be classified on the basis of the valence of the doping ion. The isovalent doping, i.e. the replacement of one ion by another ion with the same valence, does not affect possible vacancies in the ceramic material. If lower-valent cations (acceptors) replace cations with a higher valence, vacancies are produced in the anion lattice. Higher valent cations (donors), when they replace lower valent cations, cause vacancies in the cation lattice. The doping with acceptors and donors in each case leads to characteristic changes in the material properties. Acceptor-doped ceramics are also referred to as "hard", donor-doped ceramics as "soft" ceramics.Doping, for example with Nd 3+( or another rare earth element from group A), in the A sites represents donor doping. Due to the ionic radius of neodymium, it is incorporated in the Pb 2+- sites. Charge balancing is accomplished by the corresponding formation of Pb vacancies. The effect of the doping is metric changes of the lattice and the influence of longer-acting interactions between the unit cells.Doping, for example with K + or Fe 3+, on the A or. B sites represent acceptor doping. Owing to the ionic radius of potassium, it is incorporated in the Pb 2+- sites, while Fe 3+ is incorporated in the Zr 4+ or in the Zr. Ti 4+- sites. Charge equalization is effected by reducing Pb 2+- vacancies (A-vacancies) and / or the corresponding formation of oxygen vacancies. The effect of the doping is grain growth and sinter compaction promoting oxygen void formation induced by K acceptors at the sintering temperature. In the process of cooling, recombination with the Nd donors can take place with formation of quasi-neutral {Nd / K} defect pairs, so that no lead or only a very low concentration of vacancies is present in the finished ceramic.This doping has an effect on the grain growth of the material, which depends on the concentration of the doping introduced. Small amounts of doping contribute to grain growth, whereas excessively large amounts of doping ions can inhibit grain growth.The properties of donor-doped PZT materials, as are present in the case where Nd occupies Pb sites, are essentially based on increased domain mobility caused by the Pb vacancies. The voids result in the domains already being influenceable by small electric fields. Compared with undoped PZT ceramics, this leads to easier displaceability of the domain boundaries and thus to higher dielectric constants.Acceptor and donor dopants are present simultaneously in the ceramic material. This results in compensating for the negative properties which occur when the ceramic has been doped with only one of the two doping types. If, for example, only one acceptor doping were present, this often leads to decreasing dielectric constants, i.e. the constants are below those of the undoped ceramic. If only donor doping is present, grain growth is inhibited and the bodies of the ceramic do not reach the desired size. The combination of dopings present, however, is positively offset from the undoped ceramic at these points. It has higher dielectric constants, which are also present at lower sintering temperatures.According to a preferred embodiment, 0.1≤x≤0.2, since the polarization curves can be set better in this range.According to a further embodiment, 0≤y<0.05 applies.According to a further embodiment, 0.001<b<0.12, wherein more preferably d=e=f=0 applies.According to a further embodiment, 0.001<e<0.12, wherein more preferably b=d=f=0 applies.According to a further preferred embodiment, B is sodium (Na). This particularly advantageously influences the material properties, in particular lowers the sintering temperature compared to PZT material containing only one rare earth element, and at the same time increases the switching field strength.According to a further preferred embodiment, the relative permittivity at an electrical field strength of 1 kV / mm, preferably 2 kV / mm, is at least 60% of the relative permittivity at an electrical field strength of 0 kV / mm. More preferably, the relative permittivity (dielectric constant) of the ceramic material at a field strength of 2 to 5 kV / mm, preferably 1 kV / mm to 10 kV / mm, is at least 60% of the relative permittivity at an electric field strength of 0 kV / mm. The measurements are preferably carried out at a ceramic material temperature of 125° C.According to a further preferred embodiment, the ceramic material has a relative permittivity of at least 500, preferably at least 1500, at an electric field strength of 1 kV / mm, preferably 2 kV / mm. More preferably, the ceramic material has a relative permittivity of at least 500, preferably at least 1500, at an electrical field strength of 2 to 5 kV / mm, preferably 1 kV / mm to 10 kV / mm. The measurements are preferably carried out at a ceramic material temperature of 125° C.Polarization hysteresis measurement is a standard method for determining relative permittivity (dielectric constant). For frequency-independent measurement, quasistatic methods are known in which the hysteresis loop is measured point by point. For example, polarization measurements can be carried out with the aid of the TF Analyser 2000 from aixTBT Systems GmbH.According to a further preferred embodiment, the ceramic material is an antiferromagnetic dielectric. For this purpose, the base material PZT is preferably used from the antiferromagnetic-orthorhombic phase region (O phase). The antiferromagnetic order is characterized by a superposition of a plurality of polar sublattices whose dipole electric moments cancel each other out. An antiferromagnetic crystal thus does not have spontaneous polarization but has particular dielectric properties. If an electric field is applied to the antiferromagnetic material, it initially behaves as a linear dielectric. Starting from a certain critical field strength, a sudden transition is induced into the ferroelectric phase and the previously antiparallel dipoles switch into the then more favourable, parallel, orientation in terms of energy. The reverse transition takes place at a lower field strength. This results in a so-called double hysteresis loop.Antiferromagnetic ceramic materials have less pronounced polarization-field strength hysteresis compared to ferroelectric ceramic materials. This leads to lower energy losses when used in capacitors. For this reason, the use of antiferromagnetic ceramic materials is preferred.For the production of pure and differently doped lead carbonate titanate (PZT) powders, the classic mixed oxide method or else solvent-based methods, which are also called "sol-gel" methods, can be used. Starting points are, for example, solutions of the acetates or alcoholates of the constituent metals, which are converted via various drying methods into granulated xerogels, the ceramic precursor substances (precursors). For drying, for example, spray drying and spray freeze granulation with subsequent freeze drying are available. The precursors are subsequently pyrolyzed to the oxides. Powders produced in this way can be deagglomerated with little effort and conditioned for further processing.A ceramic multilayer capacitor described here is distinguished in particular by a particularly low ESR value (equivalent series resistance) and a particularly low ESL value (equivalent series inductance).At the same time, the arrangement of the electrode layers described here is favorable for the process management during the production of a multilayer capacitor described here. Both in the case of binder removal and in the case of sintering, a gas exchange / equilibrium of binder removal products and process gases is required, which is favored in the multilayer capacitor described here. The construction promotes an improved possibility of process control via the electrode layers which are relatively short in the lateral direction, as a result of which large ceramic parts are also possible in terms of volume, as measured on conventional multilayer capacitors. Furthermore, in the case of a multilayer capacitor described here, synergy effects arise from the described arrangement of the electrode layers and the selected ceramic material of the ceramic layers, which have a positive effect on the ESR value, the ESL value and the mechanical and thermal robustness. In particular, the combination of the ceramic together with the aspect ratios between B, H and L specified above and with the geometry of the electrode layers can improve the electrical and thermal properties of the component. For example, the short paths through which the current can pass through the electrodes (geometry effect) have an extremely positive effect on the current-carrying capacity behavior of the component together with the thermal stability of the insulation resistance (ceramic property).Further advantages and advantageous embodiments of the ceramic multilayer capacitor result from the embodiments described below in connection with FIGS. 1 and 2.The following are shown: FIG. 1 shows a perspective schematic view of a ceramic multilayer capacitor according to one embodiment, FIG. 2 shows a cross section of the ceramic multilayer capacitor from FIG. 1.In the exemplary embodiments and figures, identical or identically acting components can each be provided with the same reference numerals. The elements shown and their relative sizes with respect to one another are fundamentally not to be regarded as being to scale. Rather, individual elements, such as layers, components and regions, may be shown with exaggerated thickness or large dimensions for better illustration and / or for better understanding.FIGS. 1 and 2 show different schematic views of a ceramic multilayer capacitor 1 according to an exemplary embodiment. The multilayer capacitor 1 comprises a main body 2 which has a rectangular parallelepiped shape with six side faces. The base body 2 has ceramic layers 3 and first and second electrode layers 41, 42 arranged between the ceramic layers 3, wherein the ceramic layers 3 and the electrode layers 41, 42 are arranged along a layer stacking direction S to form a stack. In particular, the base body 2 has at least 10 first and at least 10 second electrode layers 41, 42. In the exemplary embodiment shown, the ceramic layers 3 have a layer thickness of approximately 25 μm. The electrode layers 41, 42 have a layer thickness of approximately 3.5 μm. Alternatively, the ceramic layers 3 and the electrode layers 41, 42 can also have different layer thicknesses.In the exemplary embodiment shown, the electrode layers comprise copper. On the one hand, this makes it possible to achieve that the multilayer capacitor 1 has an ESR value that is as small as possible, and on the other hand, the production process of the multilayer capacitor 1 can be made less expensive.The multilayer capacitor 1 furthermore has a first external contact 51 which is arranged on a first side surface 61 of the base body 2, and a second external contact 52 which is arranged on a second side surface 62 of the base body 2. The first electrode layers 41 are electrically conductively connected to the first external contact 51 and the second electrode layers 42 are electrically conductively connected to the second external contact 52. The first and second side surfaces 61, 62 are surface-treated, wherein the surface treatment is preferably carried out before the application of the external contacts 51, 52. In particular, the first and second side surfaces 61, 62 may be lapped, buffed, ground or plasma etched. By means of the surface-treated side surfaces 61, 62, particularly good contact between the external contacts 51, 52 and the first or second electrode layers 41, 42 can advantageously be achieved.In the exemplary embodiment shown, a first and a second electrode layer 41, 42 are arranged spaced apart from one another in a same plane. This plane is formed by a layer plane which is formed perpendicular to the layer stacking direction S of the stack. Between the first electrode layers 41 and the second electrode layers 42, a gap is present. This gap constitutes a region between a first electrode layer 41 and a second electrode layer 42 in the layer plane in which no electrode layers are arranged. According to an alternative exemplary embodiment, it is also possible for the first and second electrode layers 41, 42 to be arranged in different layer planes in each case.The base body 2 furthermore has third electrode layers 43 which are not electrically conductively connected either to the first or to the second external contact 51, 52. The third electrode layers 43 overlap both with the first and with the second electrode layers 41, 42, that is to say the third electrode layers 43 each have at least one subregion which, in the case of a conceptual projection in the layer stack direction S of the stack, could be brought into coincidence with at least one subregion of both the first and the second electrode layers 41, 42. According to the alternative embodiment, in which the first and second electrode layers 41, 42 are respectively arranged in different layer planes, it is possible for the first and second electrode layers 41, 42 to overlap with one another.The first and second external contactings 51, 52 each have a first sputtering layer, wherein the first sputtering layers are each applied directly to the base body 2. The first sputtering layers are in direct contact with the first and second electrode layers 41, 42, respectively. In each case, second sputtering layers are applied to the first sputtering layers, the second sputtering layers preferably comprising copper. Furthermore, third sputtering layers, which preferably comprise gold, are applied to the second sputtering layers in each case. Alternatively, the third sputter layers can also comprise silver.The base body 2 has a width B along the layer stacking direction S. In other words, B denotes the extent of the base body 2 in the direction parallel to the layer stacking direction S. Preferably, at least 10 first electrode layers and at least 10 second electrode layers are provided in the base body 2 per mm width B of the base body. Furthermore, the base body 2 has a height H perpendicular to the first side surface 51. The base body 2 thus has an extension perpendicular to the first side surface 51 which corresponds to the height H. Furthermore, the base body 2 has a length L perpendicular to the height H and perpendicular to the layer stacking direction S, which length corresponds to the extent of the base body 2 perpendicular to the layer stacking direction and perpendicular to the height H. For the ratio of the width B to the height H of the base body 2, B / H≥0.2. furthermore, for the ratio of the length L to the width B of the base body, L / B≥1 applies, as well as for the ratio of the length L to the height H of the base body, L / H≥1.In the exemplary embodiment shown, the base body 2 has a width B of approximately 2.5 mm, a height H of approximately 7.0 mm and a length L of approximately 7.0 mm. Thus, in the embodiment shown, the ratio B / H is approximately equal to 0.36, and the ratio L / B is approximately 2.8, and the ratio L / H is approximately 1.0.The multilayer capacitor 1 according to the exemplary embodiment shown is distinguished in particular by a low ESR value, a low ESL value and high mechanical and thermal robustness. For example, the ceramic multilayer capacitor (380V / 10 μF) shown in the exemplary embodiment according to FIGS. 1 and 2 has the following frequency-dependent values: ESR(min)=3 mΩ, ESR(100 kHz)=5 mΩ and ESL<4 nH. Furthermore, the multilayer capacitor 1 can be produced at low cost.List of reference characters1 Multilayer capacitor 2 Base body 3 Ceramic layers 41 First electrode layers 42 Second electrode layers 43 Third electrode layers 51 First external contact 52 Second external contact 61 First side surface 62 Second side surface H Height of the base body B Width of the base body L Length of the base body S Layer stacking direction

Claims

Ceramic multilayer capacitor (1) having - a base body (2) which has ceramic layers (3) which are arranged in a stack along a layer stacking direction (S) and first and second electrode layers (41, 42) arranged between the ceramic layers (3), wherein the base body (2) has a cuboid shape, - a first external contact (51) which is arranged on a first side face (61) of the base body (2) and is electrically conductively connected to the first electrode layers (41), and - a second external contact (52) which is arranged on a second side face (62) of the base body (2) which is situated opposite the first side face (61) and is electrically conductively connected to the second electrode layers (42), wherein - the base body (2) has a width B along the layer stacking direction (S), - the base body (2) has a height H perpendicularly to the first side face (61), the base body (2) has a length L perpendicular to the height H and perpendicular to the layer stacking direction (S), - wherein B / H≥0.2, wherein the ceramic layers (3) have a ceramic material, for which the following formula applies: Pb (1-1,5a-0,5b+1,5d+e+0,5f) A a B b( Zr 1-x Ti x)1-c-d-e-f Li d C e Fe f Si c O 3+ y·PbO (I) wherein A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb; B is selected from the group consisting of Na, K and Ag; C is selected from the group consisting of Ni, Cu, Co and Mn; and 0<a<0.12 0.05<x<0.3 0≤b<0.12 0≤c<0.12 0≤d<0.12 0≤e<0.12, 0≤f<0.12, 0≤y<1, where b+d+e+f>0. The multilayer capacitor according to claim 1, wherein L / B ≥ 1.Multilayer capacitor according to either of Claims 1 and 2, wherein L / H ≥ 1.Multilayer capacitor according to one of the preceding claims, wherein the base body (2) has third electrode layers (43) which are electrically conductively connected neither to the first nor to the second external contact (51, 52).The multilayer capacitor according to claim 4, wherein the third electrode layers (43) overlap with the first and second electrode layers (41, 42).Multilayer capacitor according to one of the preceding claims, wherein the ceramic layers (3) have a layer thickness of between 3 μm and 200 μm.Multilayer capacitor according to one of the preceding claims, wherein the electrode layers (3) have a layer thickness of between 0.1 μm and 10 μm.Multilayer capacitor according to one of the preceding claims, wherein the base body (2) has at least 10 first electrode layers (41) and at least 10 second electrode layers (42).The multilayer capacitor according to any one of the preceding claims, wherein the following relationship applies: number of the first electrode layers / width B ≥ 10 / mm. The multilayer capacitor according to any of the preceding claims, wherein the electrode layers (41, 42, 43) comprise copper.The multilayer capacitor according to any one of the preceding claims, wherein the first and second side surfaces (61, 62) are surface-treated.The multilayer capacitor of claim 11, wherein the first and second side surfaces (61, 62) are lapped, ground or plasma etched.Multilayer capacitor according to one of the preceding claims, wherein the first and the second external contact (51, 52) each have at least one sputtering layer which is in direct contact with the first or second electrode layers (41, 42).

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