Voltage generators that are adaptable to small external supply voltages

Abstract

Reference voltage generator (100; 400; 500; 708) with: a clamp regulator (110; 410; 510) which is operated by a first external supply voltage (VEXT; VEXT1) supplied by an external source and which is configured to receive a first voltage (VREF) to generate a clamp voltage (VREF PRE ); and a level amplifier (120; 420; 520) that is powered by a second supply voltage (VPPE) that is higher than the first supply voltage (VEXT; VEXT1) and that is configured to measure the clamp voltage (VREF) PRE ) to receive for generating a reference voltage (VREFA).

Description

BACKGROUND

[0001] The present disclosure relates to a semiconductor storage device and, in particular, to a voltage generator which generates internal voltage at a specific level even at low external supply voltage, and to a semiconductor storage device and a storage system comprising the voltage generator.

[0002] The operating environment of a semiconductor memory device tends to reduce power consumption by using a low operating voltage. The semiconductor memory device may be designed to operate from an internal voltage that is voltage-stripped from a voltage supplied by an external source. With the development of low-power semiconductor memory devices, the level of the external supply voltage, which serves as the operating voltage, is further reduced. Due to the reduced level of the external supply voltage, the level of the internal voltage is also further reduced. If the level of the internal voltage is reduced below a target voltage, the operating characteristics of the semiconductor memory device may degrade.

[0003] From US patent publication 6,285,242 B1, a reference voltage generator for producing a reference voltage that is a preset amount below the supply voltage is known. A reference voltage source generates a first reference voltage, VREF, which is above ground potential. A first load device is coupled to the ground node and generates an internal reference signal, the magnitude of which is determined by the current flowing in the first load device. A differential amplifier generates a signal, the magnitude of which is determined by the difference between the signals at the first and second inputs. A current control switch with a control node is connected to the output of the differential amplifier and determines the current through the first load device.A second load device, connected in series with the first load device and connected to the power supply node, has an impedance chosen such that the second load device generates the second reference voltage. SUMMARY

[0004] The disclosed embodiments provide voltage generators that produce a reference voltage of a specific level, and an internal supply voltage of a specific level even at low external supply voltage, and a semiconductor storage device and a storage system that include the voltage generator.

[0005] According to one embodiment, a reference voltage generator is provided, comprising a clamp regulator which is operated with a first supply voltage provided by an external source and which receives a first voltage to generate a clamp voltage, and a level amplifier which is operated with a second supply voltage which is higher than the first supply voltage and which receives the clamp voltage to generate a reference voltage.

[0006] The reference voltage generator can be contained in a direct access memory (DRAM) and the clamp voltage can be set to a voltage level that results in a successful recovery workflow with respect to the memory cell data in the DRAM.

[0007] The clamp regulator may include a first comparator unit, powered by the first supply voltage and configured to compare the first voltage with a voltage of a first node in order to output the voltage of a second node; a first switching unit, powered by the first supply voltage and configured to output the clamp voltage in response to the voltage of the second node; and a first level control unit configured to output the voltage of the first node at the same level as the level of the first voltage and to control a level of the clamp voltage.

[0008] The first switching unit can be a p-channel metal oxide semiconductor (PMOS) transistor, in which the first supply voltage is connected to a source, the second node is connected to a gate, and the clamp voltage is connected to a drain.

[0009] The first level control unit can include a first resistor connected between the clamp voltage and the second node, and a second resistor connected between the second node and a ground voltage.

[0010] The level amplifier can include a second comparator unit, powered by the second supply voltage, which compares the clamp voltage with a voltage of a third node to output a voltage of a fourth node; a second switching unit, powered by the second supply voltage, which outputs a reference voltage in response to the voltage of the fourth node; and a second level control unit for outputting the voltage of the third node, which has the same level as a level of the clamp voltage, and for controlling a level of the reference voltage.

[0011] The second switching unit can be a p-channel metal oxide semiconductor (PMOS) transistor, in which the second supply voltage is connected to a source, the fourth node is connected to a gate, and the reference voltage is connected to a drain.

[0012] The second level control unit can include a third resistor connected between the reference voltage and the third node, and a fourth resistor connected between the third node and the ground voltage.

[0013] The reference voltage generator may further include a charge pump unit to receive the first supply voltage and output the second supply voltage through a charge pumping process.

[0014] The reference voltage generator may further include a voltage drop unit to receive a third supply voltage that is higher than the first supply voltage, and to reduce the third supply voltage to output the second supply voltage.

[0015] According to another aspect of the disclosed embodiments, a direct access memory (DRAM) is provided to which a first external supply voltage is supplied from an external source, the DRAM comprising a comparator unit powered by a second supply voltage higher than the first supply voltage and configured to compare a first voltage with a voltage of a first node in order to generate a voltage of a second node, and a switching unit powered by the second supply voltage and configured to output a reference voltage in response to the voltage of the second node;and a level control unit configured to output the voltage of the first node, which has the same level as a level of the first voltage, and to regulate a level of the reference voltage, the first voltage being set to have a voltage level that results in a successful recovery operation with respect to the memory cell data in the DRAM.

[0016] According to another embodiment, a direct access memory (DRAM) is provided to which a first external supply voltage is supplied from an external source, wherein the DRAM comprises a voltage divider configured to split a voltage between a first external supply voltage and a ground voltage to generate a clamp voltage, and a level amplifier driven by a second supply voltage higher than the first supply voltage and configured to receive the clamp voltage to generate the reference voltage, wherein the clamp voltage is set to have a minimum voltage level that results in a successful recovery operation with respect to the memory cell data in the DRAM.

[0017] According to another embodiment, a semiconductor storage device is provided comprising a first reference voltage generator configured to receive a first supply voltage supplied from an external source and to generate a first reference voltage, a second reference voltage generator driven by a second supply voltage higher than the first supply voltage and configured to receive the first reference voltage to generate a clamp voltage and a second reference voltage, and an internal voltage generator driven by the second supply voltage and configured to receive the second reference voltage to generate an internal supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following detailed description, in conjunction with the accompanying drawings, provides a clearer understanding of the example designs, in which: Fig. 1 a diagram for describing a reference voltage generator according to a first exemplary embodiment of the inventive concept; Fig. 2. A graph to describe an exemplary workflow of a reference voltage generator according to Fig. 1 according to one embodiment; Fig. 3 a diagram for describing a reference voltage generator according to a second exemplary embodiment; Fig. 4 a diagram for describing a reference voltage generator according to a third exemplary embodiment; Fig. 5 a diagram for describing a reference voltage generator according to a fourth exemplary embodiment; Fig. 6 a diagram for describing a reference voltage generator according to a fifth exemplary embodiment; Fig. 7 is a diagram to describe an example of a direct access memory (DRAM) comprising a reference voltage generator according to various exemplary embodiments; Fig. 8 An exemplary circuit diagram to describe a first reference voltage generator according to Fig. 7 according to one embodiment; Fig. 9 An exemplary circuit diagram to describe a first internal voltage-generating circuit according to Fig. 7 according to one embodiment; Fig. 10A an exemplary circuit diagram to describe a second internal voltage generator according to Fig. 7 and a read amplifier of a core block according to an embodiment; Fig. 10B an example diagram to describe a data write operation on a bit line to Fig. 10A according to one embodiment; Fig. 11 a diagram to describe another example of a DRAM comprising a reference voltage generator according to various exemplary embodiments; Fig. 12 is a diagram for describing a semiconductor storage device comprising a reference voltage generator according to various exemplary embodiments; Fig. 13 is a diagram showing an implementation example of a memory system to which a semiconductor memory device is applied. Fig. 12 is applied according to an embodiment; and Fig. 14 is a block diagram of a data processing system which has a storage system installed thereon according to an exemplary embodiment. DETAILED DESCRIPTION

[0019] The following are descriptions of embodiments with reference to the accompanying drawings. These embodiments are provided to describe the disclosure more fully for those with average knowledge in the field. Various modifications can be made to the disclosed embodiments, and the disclosed embodiments can have different forms, even though certain exemplary embodiments are shown and described in detail in the drawings. These embodiments are not intended to limit the inventive concept and should be understood as encompassing all modifications, equivalents, and substitutions within the sense and scope of the inventive concept. Throughout the drawings, the same reference symbols refer to the same components.In the accompanying drawings, structures may be enlarged or exaggerated for the sake of clarity.

[0020] The terminology used here is solely for the purpose of describing the disclosure and is not intended to be limiting. As used here, singular forms are meant to include plural forms unless the context clearly indicates otherwise. Furthermore, the terms "includes," "contains," and / or "exists," when used in this description, denote the presence of the designated feature, number, step, process, component, element, or combination thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, processes, components, elements, or combinations thereof.

[0021] Furthermore, it should be understood that when an element is referred to as "connected," "coupled with," or "located on" another element, it may be directly connected or coupled to, or located on, the other element, or intermediate elements may be present. Conversely, no intermediate elements are present when an element is referred to as "directly connected" or "directly coupled" to another element. As used here, the term "and / or" encompasses any and all combinations of one or more of the related listed items and can be abbreviated as " / ".

[0022] It should be understood that, although the terms first, second, etc. may be used here to describe different elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. For example, a first chip could be called a second chip, and similarly, a second chip could be called a first chip, without deviating from the teachings of Revelation.

[0023] The terms used here, including technical and scientific terms, have the same meanings as those commonly understood by those with expertise in the field, unless otherwise defined. It should be understood that terms defined in a commonly used dictionary have meanings consistent with those in the related technology. Unless explicitly defined, terms should not be ideally or excessively analyzed as having formal meanings.

[0024] A semiconductor memory device can include an internal voltage reducer that generates an internal supply voltage AIVC from an external supply voltage VEXT. If the semiconductor memory device is implemented as a direct-access memory (DRAM), the internal supply voltage AIVC can be used as a supply voltage for a core block comprising a DRAM cell array.

[0025] Among the operating characteristics of DRAM, the refresh time can be proportional to the amount of charge stored in a cell node. A cell node refers to a junction between a DRAM cell transistor and a cell capacitor. The amount of charge stored in the cell node, Q, is proportional to a cell capacitance C based on Q = CV, and it is proportional to an internal voltage IVC, which is a stored voltage V. If the size of a cell capacitor decreases due to the segmentation of a semiconductor manufacturing process, the cell capacitance also decreases. Under such circumstances, where the cell capacitance decreases, the level of an internal supply voltage AIVC must be high to ensure a sufficient refresh time.The refresh time can be maintained at a specific desired level if the internal supply voltage AIVC is kept constant at a target voltage level, regardless of the level of the external supply voltage VEXT.

[0026] The internal supply voltage AIVC is typically generated by underscoring the external supply voltage VEXT. With the development of low-power DRAM, the level of the external supply voltage VEXT is reduced. This reduced level can be lower than the target level of the internal supply voltage AIVC. In this case, due to the reduced level of the external supply voltage VEXT, the internal supply voltage AIVC may be generated at a lower level than the target voltage level. Because the internal supply voltage AIVC is lower than the target voltage level, ensuring the DRAM's refresh rate becomes challenging.Accordingly, there is a need for voltage generators that are able to keep the target voltage level of the internal supply voltage AIVC constant, even when the level of the external supply voltage VEXT is reduced.

[0027] Fig. Figure 1 is a diagram for describing a reference voltage generator 100 according to an exemplary embodiment.

[0028] With reference to Fig. The reference voltage generator 100 can comprise a clamp regulator 110 and a level amplifier 120. The clamp regulator 110 is driven by a first supply voltage VEXT and receives a first voltage VREF to generate a clamp voltage VREFA. PREto generate. The first external supply voltage VEXT can be an external supply voltage, for example, received from a voltage source outside a semiconductor storage device. The level amplifier 120 is driven by a second supply voltage VPPE and receives the clamp voltage VREFA. PRE to generate a reference voltage VREFA. The second supply voltage VPPE can be set to have a higher level than the first supply voltage VEXT. The second supply voltage VPPE can also be an external supply voltage.

[0029] The clamp regulator 110 can be a voltage control circuit comprising a first comparator 112, a first switching unit 114, and a first level control unit 115. The first comparator 112 is driven by the first supply voltage VEXT and compares the first voltage VREF with a voltage at a first node NA to output a voltage at a second node NB. The first supply voltage VEXT can be approximately 1.1 V, for example. The first voltage VREF can be approximately 0.75 V, for example. The first comparator 112 can output a logic-low level to the second node NB if the voltage at the first node NA is lower than the first voltage VREF. The first comparator 112 can output a logic-high level to the second node NB if the voltage at the first node NA is higher than the first voltage VREF.The first comparator unit 112 can comprise circuit elements that form a comparator, and therefore it can be referred to here as a comparator circuit. The second node NB can be connected to the first switching unit 114.

[0030] The first switching unit 114 can be a circuit comprising, for example, a p-channel metal oxide semiconductor (PMOS) transistor, which is driven by the first supply voltage VEXT and connected to the second node NB via its gate. In the PMOS transistor, the first supply voltage VEXT is connected to a source, the second node NB is connected to a gate, and a drain provides the clamp voltage VREFA. PRERegarding the first switching unit 114, the PMOS transistor can be switched on in response to the voltage of the second node NB, which corresponds to the logic-low level. The first supply voltage VEXT is provided by the switched-on PMOS transistor, thereby setting the level of the clamp voltage VREFA. PRE to increase. Regarding the first switching unit 114, the PMOS transistor can be switched off in response to the voltage of the second node NB, which corresponds to a logic-high level. The switched-off PMOS transistor raises the level of the clamp voltage VREFA. PRE not, because it interrupts the supply of the second supply voltage VEXT.

[0031] Between the clamp tension VREFA PREThe ground voltage VSS can be connected to the first level control unit 115, which is also referred to as the first level voltage control circuit 115, in which a first resistor 116 and a second resistor 118 can be connected in series. A connection node between the first resistor 116 and the second resistor 118 is the first node NA. Due to the operating procedures of the first comparator unit 112 and the first switching unit 114, which is included in the clamp regulator 110, the voltage of the first node NA becomes almost equal to the first voltage VREF (e.g., the voltage of the first node NA is configured to converge to the first voltage VREF). Therefore, the clamp voltage VREF can be PRE by a resistance R1 of the first resistor 116 and a resistance R2 of the second resistor 118 as below. VREFAPRE=VREF(R1+R2R2)

[0032] Accordingly, the level of the clamp voltage VREFA PRE The clamp voltage VREFA can be regulated by adjusting the resistance R1 of the first resistor 116 and the resistance R2 of the second resistor 118 so that it has a specific value with respect to VREF. PRE The clamp voltage (VREFA) can be set to a minimum voltage level that results in a successful cell recovery operation when data is written to a memory cell (MC) connected to a bit line (BL) of the DRAM. PRE It can, for example, be set to approximately 1.08 V.

[0033] The level amplifier 120 can be a voltage control circuit comprising a second comparator unit 122, a second switching unit 124, and a second level control unit 125. The second comparator unit 122 is driven by the second supply voltage VPPE and compares the clamp voltage VREFA. PREwith a voltage from the third node NC to output a voltage from a fourth node ND. The second supply voltage VPPE can be set to be at a higher level than the level of the first supply voltage VEXT. For example, the first supply voltage VEXT might be approximately 1.2 V, and the second supply voltage VPPE might be approximately 1.6 V. The second comparator unit 122 can include circuit elements forming a comparator and can therefore be referred to here as a comparator circuit.

[0034] The second comparator unit 122 can output a logic low level to the fourth node ND if the voltage of the third node NC is lower than the clamp voltage VREFA. PRE The second comparator unit 122 can output a logic-high level to the fourth node ND if the voltage of the third node NC is higher than the clamp voltage VREFA. PREThe fourth node ND can be connected to the second switching unit 124.

[0035] The second switching unit 124 can be a circuit comprising, for example, a PMOS transistor driven by the second supply voltage VPPE and connected via its gate to the fourth node ND. In the PMOS transistor, the second supply voltage is connected to a source, the fourth node ND is connected to a gate, and a drain outputs the reference voltage VREFA. With respect to the second switching unit 124, the PMOS transistor can be turned on in response to the voltage at the fourth node corresponding to a logic-low level. The second supply voltage VPPE is provided by the turned-on PMOS transistor, thus increasing the level of the reference voltage VREFA. With respect to the second switching unit 124, the PMOS transistor can be turned off in response to the voltage at the fourth node corresponding to a logic-high level.The switched-off PMOS transistor does not raise the level of the reference voltage VREFA, as it interrupts the supply of the second supply voltage VPPE.

[0036] A second level control unit 125, also referred to as the second level voltage control circuit 115, can be connected between the reference voltage VREFA and the ground voltage VSS. This circuit may contain a third resistor 126 and a fourth resistor 128 connected in series. The third node NC is a connecting node between the third resistor 126 and the fourth resistor 128. Due to the operation of the second comparator unit 122 and the second switching unit 124, which is included in the level amplifier 120, the voltage at the third node NC becomes almost equal to the clamp voltage VREFA. PRETherefore, the reference voltage VREFA can be determined by the resistance R3 of the third resistor 126 and the resistance R4 of the fourth resistor 128 as shown below. VREFA=VREFAPRE(R3+R4R4)

[0037] Accordingly, the level of the reference voltage VREFA can be adjusted by adjusting the level of the clamp voltage VREFA. PRE The resistances R3 of the third resistor 126 and R4 of the fourth resistor 128 are adjusted to have a specific value. The reference voltage VREFA can be generated to be, for example, 1.2 V when the clamp voltage VREFA PRE For example, 1.08 V. The level amplifier 120 receives a clamp voltage VREFA. PRETo generate a reference voltage VREFA, its gain can be calculated as approximately 1.2 / 1.08. In this example, the reference voltage VREFA can be set to be approximately equal to the reference voltage VREF, so that the reference voltage VREF is maintained even when the external voltages VEXT and / or VPPE are reduced.

[0038] Fig. Figure 2 is a graph describing a workflow of the reference voltage generator 100. Fig. 1.

[0039] With reference to Fig. 2. The level of the clamp voltage VREFA PRE and the level of the reference voltage VREFA, which is generated according to the level of the supply voltage VEXT, is shown. The clamp voltage VREFA PREThe reference voltage VREFA is generated almost simultaneously with the first supply voltage VEXT, along with the increase of the first supply voltage VEXT, and is then clamped at approximately 1.08 V. The reference voltage VREFA is generated such that it has a voltage level of 1.2 / 1.08, as shown below, which is a product of the clamp voltage VREFA. PRE and the amplification of the level amplifier 120, is. VREFA=VREFAPRE⋅1.21.08

[0040] Fig. Figure 3 is a diagram for describing a reference voltage generator 300 according to a second exemplary embodiment.

[0041] With reference to Fig. 3. The reference voltage generator 300 is powered by the second supply voltage VPPE and receives a second voltage VPERI to generate a reference voltage VREFA. The second supply voltage VPPE can be set to have a higher level than the first external supply voltage VEXT, which is an external supply voltage as described above. Fig. 1 described. For example, the second supply voltage VPPE can be set to approximately 1.6 V if the first external supply voltage VEXT is approximately 1.2 V.

[0042] The reference voltage generator 300 can be contained within a semiconductor memory device, for example, a DRAM. The DRAM can comprise, for instance, a core block and peripheral circuit blocks. The core block refers to a block containing a DRAM cell array, and the peripheral circuit blocks refer to the blocks remaining apart from the core block. The second voltage VPERI can be one of the voltages used in the peripheral circuit blocks of the DRAM. The second voltage VPERI can be set to be, for example, approximately 1.8 V. In one embodiment, the second voltage VPERI is set based on a first external supply voltage VEXT.

[0043] The reference voltage generator 300 can comprise a comparator unit 322, a switching unit 324, and a level control circuit or control unit 325. The comparator unit 322 is driven by the second supply voltage VPPE and comprises a circuit, for example, a comparator, configured to compare the second voltage VPERI with a voltage of a first node NE in order to output a voltage of a second node NF. The comparator unit 322 can output a logic-low level to the second node NF if the voltage of the first node is lower than the second voltage VPERI. The comparator unit 322 can output a logic-high level to the second node NF if the voltage of the first node NE is higher than the second voltage VPERI. The second node NF can be connected to the switching unit 324.

[0044] Switching unit 324 can be a circuit comprising, for example, a PMOS transistor driven by the second supply voltage VPPE and connected to the second node NF via its gate. In the PMOS transistor, the second supply voltage VPPE is connected to a source, the second node NF is connected to a gate, and a drain outputs a reference voltage VREFA. With respect to switching unit 324, the PMOS transistor can be turned on in response to the voltage at the second node NF, which corresponds to a logic-low level. The second supply voltage VPPE is provided by the turned-on PMOS transistor, thus increasing the level of the reference voltage VREFA. With respect to switching unit 324, the PMOS transistor can be turned off in response to the voltage at the second node NF, which corresponds to a logic-high level.The switched-off PMOS transistor does not increase the level of the reference voltage VREFA, as it interrupts the supply of the second supply voltage VPPE.

[0045] The level control circuit 325 can be connected between the reference voltage VREFA and the ground voltage VSS, in which a first resistor 326 and a second resistor 328 can be connected in series. The first node NE is a connection point between the first resistor 326 and the second resistor 328. Due to the operation of the comparator unit 322 and the switching unit 324, the voltage at the first node NE becomes almost equal to the second voltage VPERI. Therefore, the reference voltage VREFA can be determined by a resistor R3 of the first resistor 326 and a resistor R4 of the second resistor 328, as shown below. VREFA=VPERI(R3+R4R4)

[0046] Accordingly, the level of the reference voltage VREFA can be adjusted by modifying the level of the second voltage VPERI, the resistance R3 of the first resistor 326, and the resistance R2 of the second resistor 328. The reference voltage VREFA can be generated to be approximately 1.2 V, for example, if the second reference voltage VPERI is approximately 1.08 V.

[0047] Fig. Figure 4 is a diagram for describing a reference voltage generator 400 according to a third embodiment.

[0048] With reference to Fig. The reference voltage generator 400 can include a clamp regulator 410, a charge pump unit 415, and a level amplifier 420. The reference voltage generator 400 is driven by the first supply voltage VEXT, which is an external supply voltage, and receives the first voltage VREF to generate a clamp voltage VREFA. PREand to generate the reference voltage VREFA.

[0049] The Clamp control 410 can be structured essentially the same as the Clamp control 110, which, with reference to Fig. As described in section 1. To avoid repetitive descriptions, a detailed description of the clamp regulator 410 is not provided. The clamp regulator 410 is powered by the first supply voltage VEXT, for example, approximately 1.2 V, and receives the first voltage VREF of, for example, approximately 0.75 V to set the clamp voltage VREFA. PRE to generate, for example, 1.08 V.

[0050] The charge pump unit 415 receives the first supply voltage VEXT and outputs the second supply voltage VPPE at a higher level than the first supply voltage VEXT through a charge pumping operation. If the first supply voltage VEXT is approximately 1.2 V, the second supply voltage VPPE can be set to be, for example, approximately 1.6 V. The charge pump unit 415 can include an oscillator and a pump capacitor. The oscillator generates an oscillating signal, and the pump capacitor generates a pump voltage from the first supply voltage VEXT in response to the oscillating signal. The charge pump unit 415 can include a pump control unit that stops the charge pumping operation when the pump voltage reaches a predetermined voltage level. The pump voltage can be output as the second supply voltage VPPE.

[0051] The level amplifier 420 is operated by the second supply voltage VPPE and receives the clamp voltage VREFA. PRE , which is generated by the clamp regulator 410 to produce the reference voltage VREFA. The level amplifier 420 can be structured essentially the same way as the level amplifier 120, which with reference to Fig. 1 is described. To avoid repetitive descriptions, a detailed description of the level amplifier 420 is not provided. The level amplifier 420 is driven by the second supply voltage VPEE, which has a level of, for example, approximately 1.6 V, and in one embodiment generates the reference voltage VREFA of approximately 1.2 V when the clamp voltage VREFA PRE approximately 1.08 V. The level amplifier 420 receives the clamp voltage VREFA. PRE , to generate the reference voltage VREFA, and an amplification of this can be calculated as approximately 1.2 / 1.08.

[0052] Fig. Figure 5 is a diagram for describing a reference voltage generator 500 according to a fourth embodiment.

[0053] With reference to Fig. The reference voltage generator 500 comprises a clamp regulator 510, a voltage reduction unit 515, and a level amplifier 520. The reference voltage generator 500 is powered by a first external supply voltage VEXT1 and a second external supply voltage VEXT2 and receives the first voltage VREF to generate the clamp voltage VREFA. PRE and to generate the reference voltage VREFA. The level of the first external supply voltage VEXT1 and the level of the second external supply voltage VEXT2 can differ from each other. The second external supply voltage VEXT2 can be set to have a level higher than that of the first external supply voltage VEXT1.

[0054] The Clamp 510 control can be structured essentially the same as the Clamp 110 control, which, with reference to Fig. 1 is described. To avoid repetitive descriptions, no detailed description of the clamp regulator 510 is provided. The clamp regulator 510 is powered by a first external supply voltage VEXT1 of, for example, approximately 1.2 V and receives the first voltage VREF of, for example, approximately 0.75 V to set the clamp voltage VREFA. PRE to generate, for example, approximately 1.08 V.

[0055] The voltage reduction unit 515 receives the second external supply voltage VEXT2 and reduces the voltage to output a second supply voltage VPPE. For example, if the second external supply voltage VEXT2 is approximately 2.5 V, the second supply voltage VPPE can be set to be, for example, 1.6 V. The voltage reduction unit 515 can include a number of diode elements connected in series between the second external supply voltage VEXT2 and the second supply voltage VPPE. The diode element causes a voltage drop in the pass-through, which corresponds to a PN contact forward voltage drop Vf. For example, for n diode elements, the second supply voltage can be determined as VEXT2 - n · Vf.

[0056] The voltage reduction unit 515 can comprise a variety of MOS transistors connected in series between the second external supply voltage VEXT2 and the second supply voltage VPPE. In each of the MOS transistors, a gate and a drain can be connected together. Each of the MOS transistors operates in diode mode and causes a voltage drop across the input that corresponds to a threshold voltage VTN. For example, for MOS transistors, the second supply voltage VPPE can be defined as VEXT2 - n · VTN.

[0057] The level amplifier 520 is powered by the second supply voltage VPPE and receives the clamp voltage VREFA. PRE , which is generated in the clamp regulator 510 to produce the reference voltage VREFA. The level amplifier 520 can be structured essentially the same way as the level amplifier 120, which is described with reference to Fig. 1 is described. To avoid repetitive descriptions, a detailed description of the level amplifier 520 is not provided. In one embodiment, the level amplifier 520 is operated by the second supply voltage of approximately 1.6 V and can provide the reference voltage VREFA of approximately 1.2 V for the clamp voltage VREFA. PRE generates approximately 1.08 V. The 520 level amplifier receives the clamp voltage VREFA. PRE , to generate the reference voltage VREFA and an amplification of it can be calculated as approximately 1.2 / 1.08.

[0058] Fig. Figure 6 is a diagram for describing a reference voltage generator 600 according to a fifth embodiment.

[0059] With reference to Fig. The reference voltage generator 600 comprises a voltage divider 610 and a level amplifier 620. The voltage divider 610 divides a voltage between the first supply voltage VEXT and the third supply voltage VSS to generate the clamp voltage VREFA. PRE to generate. The voltage divider 610 can include a first resistor that is connected between the first supply voltage VEXT and the clamp voltage VREFA. PRE is switched, and a second resistor that is connected between the clamp voltage VREFA PRE and the third supply voltage VSS is switched on. By adjusting the resistances of the first resistor and the second resistor, the level of the clamp voltage VREFA can be adjusted. PREThe first supply voltage, VEXT, can be approximately 1.2 V, for example, and the third supply voltage, VSS, can be a ground voltage. The resistances of the first and second resistors can be adjusted to set the clamp voltage, VREFA. PRE to generate approximately 1.08 V.

[0060] The level amplifier 620 is powered by the second supply voltage VPPE and receives the clamp voltage VREFA. PRE , which is generated by the voltage divider 610 to produce the reference voltage VREFA. The level amplifier 620 can be structured essentially the same way as the level amplifier 120, which, with reference to Fig. 1 is described. To avoid repetitive descriptions, a detailed description of the level amplifier 420 is not provided. In one embodiment, the level amplifier 620 is operated by the second supply voltage VPPE of approximately 1.6 V and can provide the reference voltage VREFA of approximately 1.2 V for the clamp voltage VREFA. PRE generates approximately 1.08 V. The 620 level amplifier receives the clamp voltage VREFA. PRE , to generate the reference voltage VREFA, and an amplification of this can be calculated as approximately 1.2 / 1.08.

[0061] The reference voltage VREFA, which is generated by the reference voltage generators according to various embodiments, can serve as a voltage that acts as a criterion for generating internal supply voltages used in the DRAM.

[0062] Fig. Figure 7 is a diagram describing an example of a DRAM 700 comprising a reference voltage generator according to various embodiments.

[0063] With reference to Fig. The DRAM 700 can comprise a core block 701, which includes a memory cell array 702 and a read amplifier 703, a peripheral circuit unit 704, and an output buffer unit 705. The memory cell array 702 can comprise a plurality of word lines, a plurality of bit lines that intersect the plurality of word lines on the plurality of word lines, a plurality of memory cells arranged near intersections between the word lines and the bit lines, a row decoder capable of selecting a predetermined word line from the plurality of word lines, and a column decoder capable of selecting a predetermined bit line from the plurality of bit lines. The read amplifier 703 can amplify cell data read from the plurality of bit lines. The peripheral circuit unit 704 can include an address buffer, a data input buffer, and control circuits.The output buffer unit 705 is powered by the external supply voltage VEXT and reads the read amplifier-amplified memory cell data.

[0064] The DRAM 700 can include a first reference voltage generator 706, a first internal voltage generator 707, a second reference voltage generator 708, and a second internal voltage generator 709. The first reference voltage generator 706 receives the external supply voltage VEXT to generate the first reference voltage VREF. The first internal voltage generator 707 is driven by the external supply voltage VEXT and receives the first reference voltage VREF to generate a first internal supply voltage IVC. The first internal supply voltage IVC can be used as a current source to drive the peripheral circuit unit 704.

[0065] The second reference voltage generator 708 is powered by the external supply voltage VEXT and the second supply voltage VPPE and receives the first reference voltage VREF to generate the second reference voltage VREFA. Like the reference voltage generator 100, which is referenced to Fig. As described in Figure 1, the second reference voltage generator 708 can include the clamp regulator 110 and the level amplifier 120. The clamp regulator 110 is driven by the external supply voltage VEXT and receives the first reference voltage VREF to generate the clamp voltage VREFA. PRE to generate. The level amplifier 120 is operated by the second supply voltage VPPE, which is higher than an external supply voltage VEXT, and receives the clamp voltage VREFA. PRE , to generate the second reference voltage VREFA. The second reference voltage generator 708 can be configured according to one of the embodiments of the reference voltage generator, which refers to Fig. As described in sections 3 to 6, it must be implemented.

[0066] The second internal voltage generator 709 is driven by the second supply voltage VPPE and receives the second reference voltage VREFA to generate a second internal supply voltage AIVC. The second internal supply voltage AIVC can be used as a current source to drive the core block 701.

[0067] Fig. Figure 8 is a circuit diagram for describing the first reference voltage generator 706 from Fig. 7 according to an exemplary embodiment.

[0068] With reference to Fig. The first reference voltage generator 706 can generate the first reference voltage VREF by dividing the external supply voltage VEXT. The first reference voltage generator 706 can include a bias unit 810, a control unit 820, and an operating unit 830. The bias unit 810 can be a circuit comprising first and second resistors 801 and 802, connected in series between the external supply voltage VEXT and the ground voltage VSS, and first to third n-channel metal oxide semiconductor (NMOS) transistors 803 to 805. A first-node voltage VREF_F between the first resistor 801 and the second resistor 802 can be connected to the gates of the first and second NMOS transistors 803 and 804. The gate of the third NMOS transistor 805 can be connected to the external supply voltage VEXT.The external supply voltage VEXT is divided by the first resistor 801, the second resistor 802 and the first to third NMOS transistors 803 to 805, so that the divided voltage can be indicated by the first node voltage VREF_F.

[0069] The control unit 820 can control the first-node voltage VREF_F until the external supply voltage VEXT is stabilized. The control unit 820 can include a PMOS transistor 806 connected between the first-node voltage VREF_F and the ground voltage VSS. One gate of the PMOS transistor 806 can be connected to a second node ND_A, between the first resistor 802 and the first NMOS transistor 803. The PMOS transistor 806 is initially switched on when the external supply voltage VEXT is applied, thereby stabilizing the first-node voltage VREF_F relative to the ground voltage VSS. The PMOS transistor 806 can then be switched off when the external supply voltage VEXT is constant, for example, at approximately 1.2 V.

[0070] The operating unit 830 can generate the first reference voltage VREF in response to the first node voltage VREF_F. The operating unit 830 can include a third resistor 807 and fourth and fifth NMOS transistors 808 and 809, which are connected in series between the first node voltage VREF_F and the ground voltage VSS. One gate of the fourth NMOS transistor 808 is connected to the first node voltage VREF_F, and one gate of the fifth NMOS transistor 809 can be connected to the external supply voltage VEXT. A voltage at a junction between the third resistor 807 and the fourth NMOS transistor 808 can be generated as the first reference voltage VREF.

[0071] As the external supply voltage VEXT increases, the first node voltage VREF_F increases, and the first reference voltage VREF also increases. When the first node voltage VREF_F increases, the fourth NMOS transistor 808 can be switched on, thus preventing the first reference voltage VREF from increasing further.

[0072] As soon as the external supply voltage VEXT drops, the first node voltage VREF_F decreases, and the first reference voltage VREF also decreases. When the first node voltage VREF_F decreases, the fourth NMOS transistor 808 can be switched off, thus preventing the first reference voltage from dropping.

[0073] Therefore, the first reference voltage generator 706 can stably generate the first reference voltage VREF independently of changes in the external supply voltage VEXT. The first reference voltage generator 706 can generate the first reference voltage VREF of, for example, approximately 0.75 V for an external supply voltage VEXT of approximately 1.2 V. The first reference voltage VREF can be defined as the first voltage VREF of the reference voltage generator according to various embodiments, which are described with reference to Fig. 1 and 3 to 5 are described and will be provided.

[0074] Fig. Figure 9 is a circuit diagram for describing the first internal voltage generator 707 according to Fig. 7 according to an exemplary embodiment.

[0075] With reference to Fig. 9. The first internal voltage generator 707 is driven by the external supply voltage and receives the first reference voltage VREF to generate the first internal supply voltage IVC. The first internal voltage generator 707 can include circuitry forming a comparator unit 902, a switching unit 904, and a level control unit 905. The comparator unit 902 is driven by the external supply voltage VEXT, compares the first reference voltage VREF with a voltage at the first node ND_B, and outputs a comparison result to a second node ND_C. The external supply voltage VEXT can be approximately 1.2 V, for example, and the first reference voltage VREF can be approximately 0.75 V. The comparator unit 902 can output a logic-low level to the second node ND_C if the voltage at the first node ND_B is lower than the first reference voltage VREF.The comparator unit 902 can output a logic-high level to the second node ND_C if the voltage of the first node ND_B is higher than the first reference voltage VREF. The second node ND_C can be connected to the switching unit 904.

[0076] In one embodiment, the switching unit 904 can be a PMOS transistor driven by an external supply voltage and connected to the second node ND_C via its gate. In the PMOS transistor, the external supply voltage VEXT is connected to a source, the second node ND_C is connected to a gate, and a drain outputs the internal supply voltage IVC. The switching unit 904 can turn on the PMOS transistor in response to a voltage at the second node ND_C corresponding to a logic-low level. The external supply voltage VEXT is provided by the turned-on PMOS transistor, thereby raising the level of the internal supply voltage IVC. With respect to the switching unit 904, the PMOS transistor can be turned off in response to a voltage at the second node ND_C corresponding to a logic-high level.The switched-off PMOS transistor does not raise the level of the internal supply voltage IVC, as it interrupts the supply of the external supply voltage VEXT.

[0077] The level control unit 905, in which a first resistor 906 and a second resistor 908 can be connected in series, can be connected between the internal supply voltage IVC and the ground voltage VSS. The first node ND_B is a connection point between the first resistor 906 and the second resistor 908. Due to the operation of the comparator unit 902 and the switching unit 904, the voltage at the first node ND_B becomes almost equal to the first reference voltage VREF. Therefore, the internal supply voltage IVC can be determined by the resistance of the first resistor 906 and the resistance of the second resistor 908.

[0078] Fig. 10A is a circuit diagram for describing the second internal voltage generator 709 according to Fig. 7 and the reading amplifier 703 of the core block 701 according to an exemplary embodiment.

[0079] With reference to Fig. The second internal voltage generator 709 is driven by the second supply voltage VPPE and receives the second reference voltage VREFA, generated by the second reference voltage generator 708, to generate the second internal supply voltage AIVC. The second internal voltage generator 709 may include a comparator unit 1002 and an operating unit 1004.

[0080] The comparator unit 1002 compares the second reference voltage VREFA with the second internal supply voltage AIVC and outputs a comparison result. The comparator unit 1002 can output a logic-low level if the second internal supply voltage AIVC is lower than the second reference voltage VREFA. The comparator unit 1002 can output a logic-high level if the second internal supply voltage AIVC is higher than the second reference voltage VREFA. An output of the comparator unit 1002 can be connected to the operating unit 1004.

[0081] Operating unit 1004 is powered by the second supply voltage VPPE and generates the second internal supply voltage AIVC in response to an output from comparator unit 1002. Operating unit 1004 can, for example, be a PMOS transistor connected to the output of comparator unit 1002 via its gate. In the PMOS transistor, the second supply voltage VPPE is connected to a source, the output of comparator unit 1002 is connected to a gate, and a drain outputs the second internal supply voltage AIVC. With respect to operating unit 1004, the PMOS transistor can be turned on in response to the logic-low output from comparator unit 1002. The second supply voltage VPPE is provided by the turned-on PMOS transistor, thereby raising the level of the second internal supply voltage AIVC.For operating unit 1004, the PMOS transistor is switched off in response to the logic-high level output of comparator unit 1002. The switched-off PMOS transistor does not raise the level of the second internal supply voltage AIVC, as it interrupts the supply of the second supply voltage VPPE.

[0082] Therefore, the second internal voltage generator 709 can generate the second internal supply voltage AIVC at a level almost equal to that of the second reference voltage VREFA. In one embodiment, the second internal supply voltage AIVC can be generated at approximately 1.2 V when the second current voltage VPPE is approximately 1.6 V and the second reference voltage VREFA, generated by the second reference voltage generator 708, is approximately 1.2 V.

[0083] The read amplifier 703 can comprise a sampling unit 1030 and a balancing unit 1040. The sampling unit 1030 can amplify data on a bit line BL and a supplementary bit line BLB of the memory cell arrangement 702. The sampling unit 1030 can comprise a first sampling unit PSA and a second sampling unit NSA, which are connected between the bit line BL and the supplementary bit line BLB. The first sampling unit PSA can comprise PMOS transistors whose gates are connected between the bit line BL and the supplementary bit line BLB. The second sampling unit NSA can comprise NMOS transistors whose gates are connected between the bit line BL and the supplementary bit line BLB. The balancing unit 703 can comprise NMOS transistors connected between the bit line BL and the supplementary bit line BLB, which respond to a bit-line balancing signal PEQI.

[0084] The first scanning unit PSA is powered by the second internal supply voltage AIVC, which is generated by the second internal voltage generator 709, and the second scanning unit NSA is powered by the ground voltage VSS. The second internal supply voltage AIVC is provided to the first scanning unit PSA by a first switching unit 1010, which responds to a first activation signal LAPG, and the ground voltage VSS is provided to the second scanning unit NSA by a second switching unit 1020, which responds to a second activation signal LANG.

[0085] The second internal supply voltage AIVC, which drives the scanning unit 1030, can be an important element of a cell recovery operation when data is written to a memory cell MC connected to the bit line BL. In particular, as shown in Fig. As shown in Figure 10B, the second internal supply voltage AIVC must maintain a specific voltage level when a previous logic level of the bit line BL and the complementary bit line BLB is inverted, and the inverted logic level is written to the memory cell MC. Even if the level of the external supply voltage VEXT is reduced to lower the power consumption of the DRAM, the second internal supply voltage AIVC can be maintained at a constant target voltage level.

[0086] The second internal voltage generator 709 can generate the second internal supply voltage AIVC, which is almost equal to the second reference voltage VREFA. In one embodiment, the second reference voltage generator 708 can generate the clamp voltage VREFA. PREof approximately 1.08 V, which is higher than the first reference voltage VREF, even when the first reference voltage VREF is generated with approximately 0.75 V due to the reduction of the external supply voltage VEXT to approximately 1.2 V. The level of the clamp voltage VREFA PRE It can be set to a minimum voltage level that results in a successful cell recovery operation when data is written to the memory cell MC, which is connected to the DRAM's BL bit line. The second reference voltage generator 708 can generate the second reference voltage VREFA of approximately 1.2 V using the clamp voltage VREFA. PRETherefore, the second internal supply voltage AIVC can be generated at a voltage level of approximately 1.2 V, resulting in a successful cell recovery operation. Regardless of the level of the external supply voltage VEXT, the second internal supply voltage AIVC, with its target voltage (e.g., 1.2 V), can ensure a refresh time in a situation where the cell capacity of the memory cell MC decreases.

[0087] Fig. Figure 11 is a diagram to describe another example of a DRAM 1000 comprising a reference voltage generator according to various embodiments.

[0088] With reference to Fig. The DRAM 1100 can comprise the core block 701, which includes the memory cell assembly 702 and the read amplifier 703, the peripheral circuit unit 704, the output buffer unit 705, the first reference voltage generator 706, and the second reference voltage generator 708. The DRAM 1100 can also include a single internal voltage generator 709, which can be structured essentially the same way as the second internal voltage generator 709. Fig. 7. However, unlike the DRAM 700, the DRAM 1100 comprises... Fig. 7, not the first internal voltage generator 707, which drives the peripheral circuit unit 704.

[0089] To meet the low-power requirements of the DRAM 1100, the external supply voltage VEXT can be reduced to, for example, 1.2 V or less. In this case, the peripheral circuit unit 704 and the output buffer unit 705 can be configured to be connected to and operated at the reduced external supply voltage VEXT. The peripheral circuit unit 704 can, for example, include an address buffer, a data input buffer, and control circuitry. The output buffer unit 705 operates at the external supply voltage VEXT and reads the read-amplified memory cell data.

[0090] The first reference voltage generator 706 receives the external supply voltage VEXT and generates the first reference voltage VREF. The second reference voltage generator 708 is operated with the external supply voltage VEXT and the second supply voltage VPPE, and receives the first reference voltage VREF to generate the second reference voltage VREFA.

[0091] Like the reference voltage generator 100, which refers to Fig. As described in Figure 1, the second reference voltage generator 708 can include the clamp regulator 110 and the level amplifier 120. The clamp regulator 110 is operated with the external supply voltage VEXT and receives the first reference voltage VREF to generate the clamp voltage VREFA. PRE to generate. In one embodiment, the second reference voltage generator 708 can generate the clamp voltage VREFA. PREof approximately 1.08 V, which is higher than the first reference voltage VREF, even if the first reference voltage VREF is generated with 0.75 V or less due to the reduction of the external supply voltage VEXT to 1.2 V or less. The level of the clamp voltage VREFA PRE It can be set to a minimum voltage level that results in a successful cell recovery operation when data is written to the memory cell MC, which is connected to the DRAM's BL bit line. In one embodiment, the level amplifier 120 is operated with the second supply voltage VPPE, which is higher than the external supply voltage VEXT, and generates VREFA using the clamp voltage. PRE The second reference voltage VREFA is approximately 1.2 V, and the first reference voltage is approximately 1.08 V. The second reference voltage generator 708 can, for example, also be configured according to one of the embodiments of the reference voltage generator, which refers to Fig. As described in sections 3 to 6, it must be implemented.

[0092] The internal voltage generator 709 is driven by the second supply voltage VPPE and receives the second reference voltage VREFA to generate the second internal supply voltage AIVC. The internal voltage generator 709 can generate the second internal supply voltage AIVC, which is equal to the second reference voltage VREFA. In one embodiment, the second internal supply voltage can be generated at approximately 1.2 V, which is a target voltage level. The second internal supply voltage AIVC can be used as a current source to drive the core block 701. The second internal supply voltage AIVC has a target voltage level that results in a successful cell recovery operation when data is written to the memory cell MC, which is connected to the bit line BL.The second internal supply voltage AIVC of approximately 1.2 V can ensure a refresh time for the memory cell MC, independent of the level of the external supply voltage VEXT.

[0093] The reference voltage generator according to the embodiments disclosed herein can be powered by a semiconductor storage device located in Fig. As shown in 12, it includes, for example, a Double Date Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM).

[0094] With reference to Fig. 12. A DDR SDRAM 1200 can comprise a memory cell assembly 1201, which includes DRAM cells and various circuit blocks for operating the DRAM cells. For example, a timing register 1202 can be activated when a chip select signal CS transitions from an inactive level (e.g., logic high) to an active level boost (e.g., logic low). The timing register 1202 receives a command signal, such as a clock signal CLK, a clock activation signal CKE, a chip select signal CSB, a row address sample signal RASB, a column address sample signal CASB, a write activation signal WEB, a data input / output mask signal DQM, etc., processes the received command signal, and generates various internal command signals LRLS, LCBR, LWE, LCAS, LWCBR, and LDQM to control the circuit blocks.

[0095] Some of the internal command signals generated in the timing register 1202 are stored in a programming register 1204. For example, latency and burst length information related to data output can be stored in programming register 1204. The internal command signals stored in programming register 1204 can be provided to a latency / burst length control unit 1206, which then provides a control signal to control the latency or burst length of the data output for a column decoder 1210 or for an output buffer 1212.

[0096] An address register 1220 can receive an address signal ADD from an external source. A row address signal can be provided to the row decoder 1224 by a row address buffer 1222. The column address signal can be provided to the column decoder 1210 by a column address buffer 1208. Furthermore, the row address buffer 1222 can receive a refresh signal generated by a refresh counter in response to refresh commands LRAS and LCBR and provide the row decoder 1224 with a combination of the row address signal and the refresh address signal. The address register 1220 can provide a bank signal for selecting a bank for a bank selection unit 1226.

[0097] The row decoder 1224 decodes the row address signal or the refresh address signal input from the row address buffer 1222 and activates a word line of the memory cell array 1201. The column decoder 1210 decodes a column address signal and selects a bit line of the memory cell array 1201. For example, a column select line is applied to a semiconductor memory device 1200 so that a selection can be made by means of a column select line.

[0098] A read amplifier 1230 amplifies the data of a memory cell selected by the row decoder 1224 and the column decoder 1210 and makes the amplified data available to the output buffer 1212. Data for writing to a data cell is provided to the memory cell array 1201 by a data input register 1232, and an input / output controller 1234 can control a data transfer operation through the data register 1232.

[0099] The reference voltage generator, as in Fig. Figure 1 shows that the clamp regulator 110 and the level amplifier 120 can be included. The clamp regulator 110 is powered by the external supply voltage VEXT and receives the first reference voltage VREF to determine the clamp voltage VREFA. PRE to generate. In one embodiment, the second reference voltage generator 708 can generate the clamp voltage VREFA. PRE of approximately 1.08 V, which is higher than the first reference voltage VREF, even if the first reference voltage VREF is generated with 0.75 V or less due to the reduction of the external supply voltage VEXT to 1.2 V or less. The level of the clamp voltage VREFA PREIt can be set to a minimum voltage level that results in a successful recovery operation when data is written to the memory cell MC, which is connected to the bit line BL of the DRAM. In one embodiment, the level amplifier 120 is driven by the second supply voltage VPPE, which is higher than an external supply voltage VEXT, and generates the clamp voltage VREFA. PRE The second reference voltage VREFA is approximately 1.2 V, of approximately 1.08 V. The reference voltage generator 100 can also be configured according to one of the embodiments of the reference voltage generator described with reference to Fig. The second reference voltage, VREFA, can be implemented as described in sections 3 to 6. It can have a reference voltage level for generating an internal supply voltage that drives the read amplifier 1230 (e.g., by means of an internal voltage generator 700). The internal supply voltage AIVC has a target voltage level that results in a successful recovery operation when data is written to the memory cell MC connected to the bit line BL. In one embodiment, an internal supply voltage AIVC of approximately 1.2 V can ensure the refresh time of the memory cell MC, independent of the level of the external supply voltage VEXT.

[0100] Fig. 13 is a diagram showing an implementation example of a memory system 1300 according to an embodiment, to which the semiconductor memory device according to Fig. 12 was applied.

[0101] With reference to Fig. 13. The memory system 1300 can comprise a memory module 1310 and a memory controller 1320. The memory module 1310 can comprise at least one semiconductor memory device mounted on a module board.

[0102] The semiconductor memory device 1330 can, for example, be implemented as a DRAM chip and can comprise a variety of semiconductor layers. These semiconductor layers can include one or more master chips 1331 and one or more slave chips 1332. Signal transmission between the semiconductor layers can be achieved through a substrate via, such as a silicon via (TSV).

[0103] While a structure in which signal transmission between the semiconductor layers is carried out by a TSV has been described in the present embodiment, such signal transmission can also be applied to a structure in which the semiconductor layers are deposited by wire-bonding, interposing or a wire-formed tape.

[0104] Signal transmission between semiconductor layers can also be achieved through optical input / output (IO) connections. For example, semiconductor layers can be interconnected using a radiation-based connection employing radio waves (RF) or ultrasound waves, an inductively coupled connection employing magnetic induction, or a non-radiation-based connection employing magnetic resonance.

[0105] The radiation-based type transmits a signal wirelessly using an antenna, such as a monopole antenna or a planar inverted F-antenna (PIFA). The radiation manifests as an electric or magnetic field, which changes over time and influences each other. An antenna, if any, tuned to the same frequency can receive a signal in a manner suitable for the polarization characteristics of the incoming waves.

[0106] The inductively coupled type generates a strong magnetic field by repeatedly winding a coil, and a coil that resonates at a similar frequency is close to the strong magnetic field, thus generating the coupling.

[0107] The non-radiation-based type uses evanescent wave coupling, which moves electromagnetic waves through a close electromagnetic field between two media that resonate at the same frequency.

[0108] The master chip 1331 and the slave chip 1332 can include a reference voltage generator according to various disclosed embodiments. The reference voltage generator can include a clamp regulator and a level amplifier, as shown in Fig. The clamp regulator, shown in Figure 1, is driven by the external supply voltage and receives a first reference voltage to generate a clamp voltage. In one embodiment, the reference voltage generator can produce the clamp voltage of approximately 1.08 V, which is higher than the first reference voltage, even if the first reference voltage is generated at 0.75 V because the external supply voltage is reduced to 1.2 V or less. The clamp voltage level can be set to a minimum voltage level that results in a successful cell recovery operation when data is written to the memory cell MC, which is connected to the DRAM's BL bit line. The level amplifier is driven by the second supply voltage, which is higher than the external supply voltage, and uses the clamp voltage of, for example, approximately 1.08 V to generate the second reference voltage of, for example, approximately 1.2 V.The reference voltage generator can be, according to one of the embodiments of the reference voltage generator, which refers to . Fig. The second reference voltage, as described in sections 3 to 6, can be implemented. It can have a reference voltage level for generating the internal supply voltage that drives the read amplifier. The internal supply voltage has a target voltage level that results in a successful cell recovery operation when data is written to the memory cell connected to the bit line. The internal supply voltage can ensure the refresh time of the memory cell MC independently of the level of the external supply voltage.

[0109] The 1310 memory module can communicate with the 1320 memory controller via a bus system. Data (DQ), command (CMD) / address (ADD), a clock signal (CLK), etc., can be sent and received between the 1310 memory module and the 1320 memory controller via the system bus.

[0110] Fig. Figure 14 is a block diagram of a data processing system 1440, which has a storage system attached to it, according to an exemplary embodiment.

[0111] With reference to Fig. 14. A semiconductor storage device according to one embodiment, designated as a RAM 1420, can be mounted on the data processing system 1400, for example, a mobile device or a desktop computer. The semiconductor storage device, designated as the RAM 1420, can correspond to any of the aforementioned embodiments. For example, the RAM 1420 can be a semiconductor storage device according to the preceding embodiments, or it can be a memory module. The RAM 1420 can have a concept that includes the semiconductor storage device and the memory controller.

[0112] The data processing system 1440 according to an exemplary embodiment comprises a main processor (CPU) 1410, RAM 1420, a user interface 1430, and non-volatile memory 1440, which are electrically connected to a bus 1450. The non-volatile memory 1440 can be a high-capacity storage device, for example, a solid-state drive (SSD) or a hard disk drive (HDD).

[0113] In the 1400 data processing system, the RAM 1420 can include a reference voltage generator according to the embodiments disclosed herein. The reference voltage generator can include a clamp regulator and a level amplifier, as shown in Fig. As shown in Figure 1, the clamp regulator is powered by the external supply voltage and receives the initial reference voltage to generate the clamp voltage. Even if the initial reference voltage is generated at, for example, 0.75 V or less due to a drop in the external supply voltage to, for example, 1.2 V or less, the reference voltage generator can still produce a clamp voltage, for example, approximately 1.08 V, which is higher than the initial reference voltage. The clamp voltage level can be set to a minimum voltage level that results in a successful cell recovery operation when data is written to the memory cell MC, which is connected to the DRAM's BL bit line.The level amplifier is operated with the second supply voltage, which is higher than the external supply voltage, and generates the second reference voltage of, for example, approximately 1.2 V using the clamp voltage of, for example, approximately 1.08 V. The reference voltage generator can be configured according to one of the various embodiments described with reference to [reference to be added]. Fig. The second reference voltage, as described in sections 3 to 6, can be implemented. It can have a reference voltage level for generating the internal supply voltage that drives the read amplifier. The internal supply voltage has a target voltage level that results in a successful cell recovery operation when data is written to the memory cell connected to the bit line. The internal supply voltage can ensure a memory cell refresh time independent of the reduced external supply voltage level.

Claims

[1] Reference voltage generator (100; 400; 500; 708) with: a clamp regulator (110; 410; 510) which is operated by a first external supply voltage (VEXT; VEXT1) supplied by an external source and which is configured to receive a first voltage (VREF) to generate a clamp voltage (VREF PRE ); and a level amplifier (120; 420; 520) that is powered by a second supply voltage (VPPE) that is higher than the first supply voltage (VEXT; VEXT1) and that is configured to measure the clamp voltage (VREF) PRE ) to receive for generating a reference voltage (VREFA). [2] Reference voltage generator (708) according to claim 1, wherein the reference voltage generator (708) is contained in a Dynamic Random Access Memory (DRAM), and wherein the clamp voltage (VREF) PRE) is set so that it has a minimum voltage level which results in a successful recovery operation with respect to the memory cell data in the DRAM. [3] Reference voltage generator (100; 300) according to claim 1, wherein the clamp regulator (110) comprises: a first comparator unit (112; 322) powered by the first supply voltage (VEXT; VPPE) and configured to compare the first voltage (VREF) with a voltage of a first node (NA; NE) in order to output the voltage of a second node (NB; NF); a first switching unit (114; 324) which is operated by the first supply voltage (VEXT; VPPE) and which is configured to, in response to the voltage of the second node (NB; NF), the clamp voltage (VREF) PRE ; VREFA) to issue; and a first level control unit (115) configured to output the voltage of the first node (NA) which has the same level as the level of the first voltage, and a level of the clamp voltage (VREF) PRE ; VREFA) to regulate. [4] Reference voltage generator (100; 300) according to claim 3, wherein the first switching unit (114; 324) is a p-channel metal oxide semiconductor (PMOS) transistor in which the first supply voltage (VEXT; VPPE) is connected to a source, the second node (NB; NF) is connected to a gate, and the clamp voltage (VREF) PRE ) is connected to a drain. [5] Reference voltage generator (100; 300) according to claim 3, wherein the first level control unit (115; 325) comprises: a first resistor (116; 326) that is connected between the clamp voltage (VREF) PRE ; VREFA) and the second node (NB; NF); and a second resistor (118; 328) connected between the second node (NB; NF) and an earth voltage (VSS). [6] Reference voltage generator (100) according to claim 1, wherein the level amplifier (120) comprises: a second comparator unit (122) powered by the second supply voltage (VPPE) and configured to measure the clamp voltage (VREF) PRE ) to compare with a voltage of a third node (NC) in order to output a voltage of a fourth node (ND); a second switching unit (124) powered by the second supply voltage (VPPE) and configured to output a reference voltage (VREFA) in response to the voltage of the fourth node (ND); and a second level control unit (125) configured to output the voltage of the third node (NC) which has the same level as a level of the clamp voltage (VREF) PRE), and to regulate the level of the reference voltage (VREFA). [7] Reference voltage generator (100) according to claim 6, wherein the second switching unit (124) is a p-channel metal oxide semiconductor (PMOS) transistor, wherein the second supply voltage (VPPE) is connected to a source, the fourth node (ND) is connected to a gate, and the reference voltage (VREFA) is connected to a drain. [8] Reference voltage generator (100) according to claim 6, wherein the second level control unit (125) comprises: a third resistor (126) connected between the reference voltage (VREFA) and the third node (NC); and a fourth resistor (128) which is connected between the third node (NC) and the earth voltage (VSS). [9] Reference voltage generator (400) according to claim 1, further comprising a charge pump unit (415) to receive the first supply voltage (VEXT) and to output the second supply voltage (VPPE) by a charge pumping process. [10] Reference voltage generator (500) according to claim 1, wherein the reference voltage generator (500) further comprises a voltage drop unit (515) to receive a third supply voltage (VEXT2) which is higher than the first supply voltage (VEXT) and to reduce the third supply voltage (VEXT2) to output the second supply voltage (VPPE). [11] Direct access memory (DRAM) to which a first external supply voltage (VEXT) is supplied from an external source, wherein the DRAM comprises: a comparator circuit powered by a second supply voltage (VPPE) higher than the first supply voltage (VEXT) and configured to compare a first voltage with a voltage of a first node to generate a voltage of a second node; a switching circuit powered by the second supply voltage (VPPE) and configured to output a reference voltage (VREF) in response to the voltage of the second node; and a level control circuit configured to output the voltage of the first node as it approaches the level of the first voltage, and to regulate a level of the reference voltage, where the first voltage is set such that it has a voltage level that results in a successful recovery operation with respect to the memory cell data in the DRAM. [12] DRAM according to claim 11, wherein the first voltage is set such that it has a minimum voltage level that results in a successful recovery operation with respect to the memory cell data in the DRAM. [13] DRAM according to claim 11, wherein the switching circuit is a p-channel metal oxide semiconductor (PMOS) transistor, wherein the second supply voltage is connected to a source, the second node is connected to a gate, and the reference voltage is connected to a drain. [14] DRAM according to claim 11, wherein the level control circuit comprises: a first resistor (116; 326; 801; 906) connected between the reference voltage and the first node; and a second resistor (118; 328; 802; 808) that is connected between the first nodes and a ground voltage. [15] Dynamic Random Access Memory (DRAM) to which a first external supply voltage is supplied from an external source, the DRAM comprising: a voltage divider (610) for dividing a voltage between a first external supply voltage and an earth voltage to generate a clamp voltage; and a level amplifier (120; 420; 520; 620) that is powered by a second supply voltage which is higher than the first supply voltage and is configured to receive the clamp voltage in order to generate the reference voltage, where the clamp voltage is set to have a minimum voltage level that results in a successful recovery operation with respect to the memory cell data in the DRAM. [16] DRAM according to claim 15, wherein the voltage divider (610) comprises: a first resistor (116; 326; 801; 906) connected between a first supply voltage and the clamp voltage; and a second resistor (118; 328; 802; 808) connected between the clamp voltage and the ground voltage. [17] DRAM according to claim 15, wherein the level amplifier comprises (120; 420; 520; 620): a comparator circuit powered by the second supply voltage and configured to compare the clamp voltage with a voltage from a first node; a switching circuit powered by the second supply voltage and configured to output the reference voltage in response to the voltage of a second node; and a level control circuit configured to output the voltage of the first node, which has the same level as a level of the clamp voltage, and to regulate a level of the reference voltage. [18] DRAM according to claim 17, wherein the switching circuit is a p-channel metal oxide semiconductor (PMOS) transistor, wherein the second supply voltage is connected to a source, the second node is connected to a gate and the reference voltage is connected to a drain. [19] DRAM according to claim 17, wherein the level control circuit comprises: a first resistor (116; 326; 801; 906) connected between the reference voltage and the first node; and a second resistor (118; 328; 802; 808) that is connected between the first nodes and the ground voltage. [20] Reference voltage generator (100; 300; 400; 500; 600; 706; 708) comprising: a voltage regulator connected to an external voltage source and a reference voltage source, and configured to output a regulated voltage determined based on an external voltage input from the external voltage source and the reference voltage input from the reference voltage source; and an amplifier connected to the voltage regulator and a second voltage source, and configured to output an amplified, regulated reference voltage determined based on the regulated voltage output of the voltage regulator and a voltage input from the second voltage source. where the voltage input to the voltage regulator from the external voltage source has a lower level than the voltage input to the amplifier from the second voltage source. [21] Reference voltage generator (100; 300; 400; 500; 600; 706; 708) according to claim 20, wherein: the second voltage source is an external voltage source. [22] Reference voltage generator (100; 300; 400; 500; 600; 706; 708) according to claim 20, wherein: the reference voltage generator (100; 300; 400; 500; 600; 706; 708) is configured such that the amplified, regulated reference voltage is greater than the regulated voltage output of the voltage regulator, and approximately equal to the reference voltage. [23] Reference voltage generator (100; 300; 400; 500; 600; 706; 708) according to claim 20, wherein the voltage regulator comprises: a first comparator circuit, powered by the external voltage, configured to compare the reference voltage with a voltage of a first node in order to output a voltage of a second node; a first switching circuit that is operated by the external voltage, and which is configured to output the regulated voltage in response to the voltage of the second node; and a first level control circuit configured to output the voltage of the first node, which has a level approaching the level of the reference voltage.

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