Transistor device and method for manufacturing a transistor device

Abstract

A transistor device (100A, 100B, 1500) formed on a semiconductor substrate (102), comprising: a depression (114) arranged within a transistor region of the semiconductor substrate (102), wherein the transistor region is doped with foreign atoms of a first type of foreign atoms; encompassing a canal region: a delta-doped layer (108, 108A, 108B) comprising dopant foreign atoms of the first kind arranged within the well (114); a layer of carbon-containing material (110) directly resting on the delta-doped layer (108, 108A, 108B); and an undoped layer of a substrate material (112) that lies directly on the layer of the carbon-containing material (110); and a gate structure arranged on the canal region (1002, 1102).

Description

BACKGROUND

[0001] A modern integrated circuit (IC) fabricated on a semiconductor substrate contains millions or even billions of transistors. The IC's performance depends on matching the physical and electronic properties of the transistors. As the minimum gate length of transistors continues to scale, variations in substrate properties, transistor dimensions, or in the geometries or composition of the various components and constituents of each transistor can create an electronic mismatch between the transistors within the IC. These effects can degrade device performance and reduce IC yield.

[0002] High-performance transistors based on silicon carbide with delta-doped channel layers are known from US 2005 / 0 173 739 A1 and US 2003 / 0 075 719 A1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A-1B illustrate cross-sectional views of some embodiments of transistor channels. Fig. 2-15 illustrate cross-sectional views of some embodiments of transistor formation. Fig. 16 illustrates some embodiments of a method for transistor formation. DETAILED DESCRIPTION

[0003] The invention relates to a transistor device having the features of claim 1 and to methods for forming a transistor device having the features of claim 11 and 18, respectively. Exemplary embodiments are specified in the dependent claims.

[0004] This description is made with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth to aid understanding. It should be apparent to one skilled in the art that one or more of the aspects described herein may be practiced with a lesser degree of these specific details. In other instances, well-known structures and devices are shown in block diagrams to facilitate understanding.

[0005] As the minimum gate length of transistors within an IC continually scales according to Moore's Law, the relative contribution of manufacturing variability to IC performance increases. Manufacturing variability can result from impurities within the semiconductor substrate, non-uniform doping, overlap variability between two or more mask alignment steps, variable exposure conditions, etc. In some cases, manufacturing variability affects certain devices within the IC while others remain relatively unaffected, which can reduce the electronic matching between devices within the IC.

[0006] For example, transistors formed on semiconductor substrates can be subject to drain-induced barrier degradation (DIBL). DIBL results in loss between the source and drain of the transistors and arises from low channel doping or source / drain connections that are too deep. The channel doping and source / drain connection placement can vary between transistors within the IC due to variable processing conditions across an entire surface of the IC. The variable processing conditions can therefore lead to variable loss between transistors across an entire IC. This can result in poor gate control across the entire IC. To combat this global variation in loss, a localized halo implant is used to increase the channel dopant concentrations near the source / drain regions of the channel within the transistor.The increased doping in these regions reduces the interaction between the source and drain without the threshold voltage (V. th ) of the transistors. However, the halo implantation can cause local variations in the substrate structure, which can induce local variations in the transistor performance. The net result of these effects is a poor electronic match between the V th of the transistors across the entire IC.

[0007] Therefore, some embodiments of the present disclosure relate to a transistor device employing a channel configured to enhance global and local variations between a plurality of such transistor devices arranged within an IC. In some embodiments, the channel is formed in a transistor region of a semiconductor substrate including dopant impurities of a first type of impurity. The channel is constructed from a delta-doped layer also including dopant impurities of a first type of impurity and configured to maintain a retrograde peak dopant concentration within the channel. The channel is further constructed from a layer of carbon-containing material overlying the delta-doped layer and configured to prevent back-diffusion of dopants from the delta-doped layer and the semiconductor substrate.The channel is also constructed from a layer of substrate material overlying the layer of carbon-containing material, and configured to provide a low dopant concentration to achieve a steep retrograde dopant profile near a surface of the channel. In some embodiments, the channel is further constructed from a counterdoped layer underlying the delta-doped layer. The counterdoped layer is constructed from dopant impurities of a second impurity type, which is opposite to the first impurity type. The counterdoped layer is also configured to reduce loss within the semiconductor substrate.

[0008] Fig. 1A illustrates a cross-sectional view of some embodiments of a first transistor channel 100A formed in a recess 114 laterally disposed between first and second shallow trench isolations (STIs) 104A, 104B of a semiconductor substrate 102. The semiconductor substrate 102 has been doped with a dopant impurity of a first type of impurity (e.g., n-type or p-type). The first transistor channel 100A includes a delta-doped layer 108 comprising dopant impurities of the first type of impurity disposed within the recess 114. In some embodiments, the delta-doped layer 108 has a first thickness t1 in the range of about 2 nm to about 15 nm. In some embodiments, the delta-doped layer 108 is epitaxially deposited on a bottom surface of the recess 114 by a suitable epitaxial deposition technique.In other embodiments, the delta-doped layer 108 includes a doped region of the semiconductor substrate 102 underlying a bottom surface of the recess 104, wherein the doped region is formed by an implantation technique (e.g., ion implantation). In some embodiments, the delta-doped layer 108 has a peak dopant concentration of approximately 2e19 cm-1. -3 to provide a retrograde dopant concentration profile within the first transistor channel 100A.

[0009] The first transistor channel 100A further includes a layer of carbon-containing material 110 overlying the delta-doped layer 108. In some embodiments, the layer of carbon-containing material 110 is epitaxially deposited on a bottom surface of the delta-doped layer 108 by a suitable epitaxial deposition technique. In some embodiments, the layer of carbon-containing material 110 has a second thickness t2 in the range of approximately 2 nm to approximately 15 nm. The layer of carbon-containing material 110 is configured to prevent back-diffusion of dopants from the delta-doped layer 108 or the semiconductor substrate 102. In some embodiments, the layer of carbon-containing material 110 comprises silicon carbide (SiC).

[0010] The first transistor channel 100A further includes a layer of substrate material 112 overlying the layer of carbon-containing material 110. In some embodiments, the layer of substrate material 112 is epitaxially deposited on a bottom surface of the layer of carbon-containing material 110 by a suitable epitaxial technique. In some embodiments, the layer of substrate material 112 has a third thickness t3 in the range of approximately 5 nm to approximately 30 nm. In some embodiments, the layer of substrate material 112 has a dopant concentration less than 1e18 cm -3 at an interface between the layer of substrate material 112 and the gate structure disposed on a top surface of the layer of substrate material 112. In some embodiments, the substrate material comprises silicon.

[0011] Fig. 1B illustrates a cross-sectional view of some embodiments of a second transistor channel 100B formed in a recess 114. The second transistor channel 100B includes a delta-doped layer 108, a layer of carbon-containing material 110, and a layer of substrate material 112, which are identical to those used in the embodiments of Fig. 1A. In addition, the second transistor channel 100B includes a counterdoped layer 106 including dopant impurities of a second type of impurity (e.g., n-type or p-type, respectively), which is opposite to the first type of impurity (e.g., p-type or n-type, respectively). In some embodiments, the dopant impurities of the first or second type of impurity comprise boron, carbon, indium, or a combination thereof, respectively. In such embodiments, the dopant impurities of the second or first type of impurity comprise phosphorus, antimony, arsenic, or a combination thereof, respectively. The addition of the counterdoped layer 106 below the delta-doped layer 108 improves the current loss (1 boff ) within the channel.

[0012] In some embodiments, the counterdoped layer 106 overlies the bottom surface of the recess 114 and underlies the delta-doped layer 108. In such embodiments, the counterdoped layer 106 is epitaxially disposed within the recess 114. In some embodiments, the counterdoped layer 106 is formed by a doped region of the semiconductor substrate 102 that underlies the bottom surface of the recess 114 as well as the delta-doped layer 108. In such embodiments, the delta-doped layer 108 may be epitaxially disposed on the counterdoped layer (i.e., on a bottom surface of the recess). Alternatively, in such embodiments, the delta-doped layer 108 may also comprise a doped region of the semiconductor substrate 102 that overlies the counterdoped layer 106. In some embodiments, the counterdoped layer 106 has a fourth thickness t4 in the range of approximately 2 nm to approximately 25 nm.

[0013] Fig. 2 to 15 illustrate cross-sectional views of some embodiments of the formation of a transistor in accordance with embodiments of the present disclosure. Fig. 2 illustrates a cross-sectional view of a semiconductor substrate 102.

[0014] Fig. 3 illustrates a cross-sectional view of some embodiments of a transistor device 300 comprising the semiconductor substrate 102 where a well-and-Vt h -Implantation step can be used to introduce dopant impurities of a first type of impurities into a transistor region of the semiconductor substrate 102. The Vt h -Implantation introduces the impurities of the first type of impurities into the transistor region to generate the V thof a transistor formed in the subsequent processing steps. In some embodiments, the dopant impurities include p-type dopant impurities such as boron, carbon, indium, etc. In other embodiments, the dopant impurities include n-type dopant impurities such as phosphorus, antimony, or arsenic, etc. In various embodiments, the V th -Implantation an implantation energy in a range of approximately 5 keV to approximately 150 keV.

[0015] Fig. Figure 4 illustrates a cross-sectional view of some embodiments of a transistor device 400, including the transistor device 300, where an annealing process is used to activate the implanted dopants to eliminate crystalline defects that may have occurred during the well-and-V th-Implantation302, and to enhance the diffusion and redistribution of dopant impurities within the semiconductor substrate 102. Many conventional annealing processes can be used, and the annealing processes can drive the implanted dopant impurities deeper into the semiconductor substrate 102, as determined by the dark gradient of the semiconductor substrate 102 in Fig. 4 is displayed.

[0016] Fig. 5 illustrates a cross-sectional view of some embodiments of a transistor device 500 comprising the transistor device 400 recessed by a depth (d) in the transistor region. In some embodiments, the formation of the recess includes one or more etching processes, including, but not limited to, a drying process such as a plasma etching process, a wet etching process, or a combination thereof.

[0017] Fig. 6A to 6C illustrate various embodiments of forming a counter-doped layer on the semiconductor substrate 102. Fig. 6A illustrates a cross-sectional view of some embodiments of a transistor device 600A comprising the transistor device 500, upon which a first counterdoped layer 106 is epitaxially deposited. The second type of impurity is opposite to the first type of impurity. For the embodiments of the Fig. 6A, the first counter-doped layer 106A lies on the bottom surface of the recess, which in the embodiments of Fig. 5 was formed.

[0018] Fig. 6B illustrates a cross-sectional view of some embodiments of a transistor device 600B comprising the transistor device 500, where a second counterdoped layer 106B is formed by an implantation technique. The implantation technique introduces the dopant impurities of a second type of impurities directly into the semiconductor substrate 102, such that the second counterdoped layer 106B underlies the bottom surface of the recess, which in the embodiments of the Fig. 5 is formed. Fig. 6C illustrates a cross-sectional view of some embodiments of a transistor device 600C including the transistor device 500, where no counter-doped layer is formed. Therefore, Fig. 6A to 6C show three options for forming a counterdoped layer on the semiconductor substrate 102: an epitaxial layer, a doped region of the semiconductor substrate 102, or no counterdoped layer.

[0019] Fig. 7A to 7F illustrate various embodiments of forming delta-doped layers on transistor devices 600A to 600C of the Fig. 6A to 6C. Fig. 7A illustrates a cross-sectional view of some embodiments of a transistor device 700A comprising the transistor device 600A, where a first delta-doped layer 108A including dopant impurities of the first type of impurities has been epitaxially arranged on the first counter-doped layer 106A by means of a suitable epitaxial technique.

[0020] Fig. 7B illustrates a cross-sectional view of some embodiments of a transistor device 700B comprising the transistor device 600B, the first delta-doped layer 108A has been epitaxially deposited onto the second counter-doped layer 106B by a suitable epitaxial technique.

[0021] Fig. 7C illustrates a cross-sectional view of some embodiments of a transistor device 700C, including the transistor device 600C, where the first delta-doped layer 108A includes dopant impurities of a first type of impurities epitaxially deposited on a bottom surface of the recess by a suitable epitaxial technique. The first delta-doped layer 108A includes a peak dopant concentration of approximately 1e19cm -3 .

[0022] Fig. 7D illustrates a cross-sectional view of some embodiments of a transistor device 700D, including the transistor device 600A, where a second delta-doped layer 108B including dopant impurities of a first impurity type has been formed underlying an upper surface of the first counterdoped layer 106A by an implantation technique. As a result, the second delta-doped layer 108B is formed within an upper portion of the first counterdoped layer 106A.

[0023] Fig. 7E illustrates a cross-sectional view of some embodiments of a transistor device 700E, including the transistor device 600B, where the second delta-doped layer 108B has also been formed below a top surface of the recess by an implantation technique. As a result, the second counter-doped layer 106B and the second delta-doped layer 108B are formed within the semiconductor substrate 102. For the embodiments of the Fig. 7E, the second counter-doped layer 106B was formed with an implant that penetrates the semiconductor substrate 102 to a depth greater than a first thickness (t1) of the second delta-doped layer 108B and that forms the second counter-doped layer 106B with a second thickness (t2).

[0024] Fig. 7F illustrates a cross-sectional view of some embodiments of a transistor device 700F comprising the transistor device 600C, where the second delta-doped layer 108B including dopant impurities of a first type of impurities has been formed underlying the bottom surface of the recess by an appropriate implantation technique.

[0025] Therefore, illustrate Fig. 7A to 7F show six options for forming a delta-doped layer on the counter-doped layer or the semiconductor substrate 102, following the three options for forming the counter-doped layer of the Fig. 6A to 6C. These six options include: an epitaxial layer formed on an epitaxial layer (700A), an epitaxial layer formed on a doped region of the semiconductor substrate 102 (700B), an epitaxial layer formed directly on the semiconductor substrate 102 without a counterdoped layer (700C), a doped region formed within an epitaxial layer (700D), a first doped region of the semiconductor substrate 102 formed beneath a second doped region of the semiconductor substrate (700E), or a doped region of the semiconductor substrate 102 with no counterdoped layer (700F). Each of these six combinations is suitable for subsequent processing in Fig. 8 to 15. However, only the embodiments of the transistor device 700A for these subsequent processing steps are illustrated. The others follow analogously.

[0026] Fig. 8 illustrates a cross-sectional view of some embodiments of a transistor device 800, including the transistor device 700A, where a layer of carbon-containing material 110 is disposed on the first delta-doped layer 108A. In some embodiments, the layer of carbon-containing material 110 includes silicon carbide (SiC). The layer of carbon-containing material 110 mitigates back-diffusion of dopants from the well region of the semiconductor substrate 102 to subsequently formed epitaxial layers.

[0027] Fig. Figure 9 illustrates a cross-sectional view of some embodiments of a transistor device 900 comprising the transistor device 800, where a layer of substrate material 112 is disposed on the layer of carbon-containing material 110. In some embodiments, the layer of substrate material 112 comprises silicon (Si) and is disposed by a suitable epitaxial technique. The carbon-containing material 110 mitigates back-diffusion of the well-and-V th -dopants from the semiconductor substrate 102 into the layer of substrate material 112. This results in a steep retrograde doping profile within a channel of the transistor device including a relatively low surface dopant concentration (e.g., less than 1e18cm -3) at a surface of the layer of substrate material 112. The low surface dopant concentration and the retrograde dopant profile improve device performance by mitigating local and global dopant variations in a channel 902 formed by the first counterdoped layer 106A, the first delta-doped layer 108A, carbon-containing material 110, and the layer of substrate material 112.

[0028] Fig. 10 illustrates a cross-sectional view of some embodiments of a transistor device 1000 comprising the transistor device 900, where a gate dielectric 1002 is disposed on the layer of substrate material 112. In some embodiments, the gate dielectric 1002 includes an oxide layer, such as silicon dioxide (SiO2). The formation of such an oxide layer occurs using an oxidation process performed at an elevated temperature. It should be understood that the elevated temperature of the oxidation process may increase back-diffusion of dopants from the well region into the epitaxial layers overlying it. However, the carbon-containing material 110 mitigates this back-diffusion, resulting in a steep retrograde doping profile within the channel.

[0029] Fig. 11 illustrates a cross-sectional view of some embodiments of a transistor device 1100 comprising the transistor device 1000, where a gate electrode 1102 (e.g., polysilicon) is disposed on the gate dielectric 1002. The gate electrode 1102 and the gate dielectric 1002 are then patterned by a suitable lithographic process, including, but not limited to, optical lithography, multiple patterning (MP) optical lithography (e.g., double patterning), deep ultraviolet (UV) lithography, extreme UV (EUV) lithography, or other suitable patterning techniques.

[0030] Fig. 12 illustrates a cross-sectional view of some embodiments of a transistor device 1200 comprising the transistor device 1100, where first and second spacers 1202A, 1202B are formed on both sides of the patterned gate electrode 1102 and the gate dielectric 1002. In various embodiments, the first and second spacers 1202A, 1202B include combinations of oxide, silicon, and nitride.

[0031] Fig. 13 illustrates a cross-sectional view of some embodiments of a transistor device 1300, including the transistor device 1200, where a lightly doped drain (LDD) implant 1302 is performed after patterning the gate electrode 1102 and the gate dielectric 1002 to form first and second LDD regions 1304A, 1304B. The LDD implant 1302 uses dopants of a second type of impurity, which is opposite to the first type of impurity of the well-and-V th -Implantation as in Fig. 3. For the embodiment of the Fig. 2 to 15, the first and second LDD regions 1304A, 1304B are n-type (e.g. phosphorus, antimony, or arsenic, etc.) and the tub-and-V th -Implantation 304 use p-type (e.g. boron, carbon, indium, etc.).

[0032] Fig. 14 illustrates a cross-sectional view of some embodiments of a transistor device 1400, including the transistor device 1300, where a halo implant 1402 is performed after the LDD implant 1302. The halo implant 1402 introduces the dopant impurities of a first type of impurity (i.e., the same as the well-and-V th Implant 304) into first and second highly doped regions 1404A, 1404B on opposite ends of the channel. In one exemplary embodiment, halo implant 1402 is used to introduce a mixture of indium and carbon. In other exemplary embodiments, halo implant 1402 is used to introduce indium, boron, or BF2 into the first and second highly doped regions 1404A, 1404B.

[0033] Fig. 15 illustrates a cross-sectional view of some embodiments of a transistor device 1500 comprising the transistor device 1400, where a source / drain implantation 1502 is performed to form first and second source / drain regions 1504A, 1504B. The first and second source / drain regions 1504A, 1504B include the second type of impurities (i.e., the same as the first counterdoped layer 106A). In some embodiments, the first and second source / drain regions 1504A, 1504B may be formed by epitaxial growth.

[0034] The embodiments of the Fig. 2 to 15 can be used for a p-type MOSFET or an n-type MOSET by reversing the dopant types.

[0035] Fig.16 illustrates some embodiments of a method 1600 of transistor formation. Although the method 1600 is described as a series of acts or events, it should be understood that the illustrated sequence of such acts or events should not be interpreted in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those illustrated and / or described herein. In addition, not all of the illustrated acts may be necessary to implement one or more aspects or embodiments of this description. Further, one or more of the acts described herein may be performed in one or more separate acts or phases.

[0036] At 1602, dopant impurities of a first type are introduced into a transistor region from a semiconductor substrate, where the transistor region includes a channel region and source / drain regions. In some embodiments, annealing is performed after the introduction of the dopant impurities of a first type within the transistor region.

[0037] At 1604, the substrate is recessed over the transistor region.

[0038] At 1606, a counterdoped layer comprising dopant impurities of a second type of impurity opposite to the first type of impurity may optionally be formed. In some embodiments, the counterdoped layer is formed overlying a bottom surface of the recess by epitaxially depositing the counterdoped layer onto a bottom surface of the recess. In some embodiments, the counterdoped layer is alternatively formed by implanting dopant impurities of a second type of impurity within the bottom surface of the recess, such that the counterdoped layer comprises a doped region of the semiconductor substrate. In some embodiments, no counterdoped layer is formed.

[0039] At 1608, a delta-doped layer comprising dopant impurities of a first type of impurity is formed on the counterdoped layer within the recess, or simply within the recess if no counterdoped layer was formed at 1606. In some embodiments, forming the delta-doped layer comprises epitaxially disposing the delta-doped layer on a bottom surface of the recess. In some embodiments, forming the delta-doped layer comprises implanting dopant impurities of a first type of impurity into a bottom surface of the recess such that the delta-doped layer comprises a doped region of the semiconductor substrate.

[0040] In 1610, a layer of carbon-containing material (e.g., SiC) is formed on the delta-doped layer by an epitaxial deposition technique.

[0041] In 1612, an undoped layer of a substrate material (e.g., Si) is formed on the layer of carbon-containing material by an epitaxial deposition technique.

[0042] At 1614, a gate dielectric (e.g., SiO2) is formed on the layer of substrate material.

[0043] In 1616, a gate electrode (e.g., polysilicon) is formed on the gate dielectric and patterned to form a gate of the transistor.

[0044] In 1618, lightly doped drain (LDD) regions are formed on both sides of a channel and comprise dopant impurities of a second type of impurity.

[0045] At 1620, a halo implantation is performed to form halo regions comprising dopant impurities of a first type of impurity on both sides of the channel.

[0046] At 1622, source and drain regions comprising dopant impurities of a second type of impurity are formed on both sides of the channel.

[0047] Furthermore, to the extent the terms "includes," "comprising," "has," "with," and / or variations thereof are used herein; such terms are intended to be inclusive in their interpretation—like "comprehensive." Also, "for example" should only denote an example, and not the best. It should also be recognized that the features, layers, and / or elements shown herein are shown with particular dimensions and / or orientation relative to one another for the purpose of simplification and ease of understanding, and that the actual dimensions and / or orientations may vary substantially from those described herein.

[0048] Therefore, some embodiments of the present disclosure relate to a transistor device employing a channel configured to enhance local and global variations between a plurality of such transistor devices arranged within an IC. In some embodiments, the channel is formed in a transistor region of a semiconductor substrate including dopant impurities of a first type of impurity. The channel is composed of a delta-doped layer also including dopant impurities of a first type of impurity and configured to produce a peak retrograde dopant concentration within the channel. The channel is further composed of a layer of a carbon-containing material directly overlying the delta-doped layer and configured to prevent back-diffusion of dopants from the delta-doped layer and the semiconductor substrate.The channel is also composed of a layer of substrate material directly overlying the layer of carbon-containing material and configured to provide a low dopant concentration to achieve a steep retrograde dopant profile near a surface of the channel. In some embodiments, the channel is further composed of a counterdoped layer underlying the delta-doped layer. The counterdoped layer is composed of a dopant impurity of a second type of impurity that is opposite to the first type of impurity. The counterdoped layer is configured to reduce loss within the semiconductor substrate.

[0049] In some embodiments, the present disclosure relates to a transistor device comprising a recess arranged within a transistor region of the semiconductor substrate, wherein the transistor region is doped with dopant impurities of a first type of impurity. The transistor device further comprises a channel region comprising a delta-doped layer arranged within the recess comprising dopant impurities of the first type of impurity, a layer of a carbon-containing material directly overlying the delta-doped layer, and a layer of substrate material directly overlying the layer of carbon-containing material. The transistor device further comprises a gate structure over the channel region.In some embodiments, the delta-doped layer is underlain by a counter-doped layer comprising dopant impurities of a second type of impurity that is opposite to the first type of impurity.

[0050] In some embodiments, the present disclosure relates to a method of forming a transistor device on a semiconductor substrate. The method comprises introducing dopant impurities of a first type of impurity into the transistor region of the semiconductor substrate, and forming a recess within the substrate above the transistor region. The method further comprises forming a delta-doped layer comprising dopant impurities of a first type of impurity within the recess, forming a layer of carbon-containing material directly overlying the delta-doped layer, and forming a layer of substrate material directly overlying the layer of carbon-containing material.In some embodiments, the method further comprises forming a counter-doped layer comprising dopant impurities of a second type of impurity opposite to the first type of impurity underlying the delta-doped layer.

[0051] In some embodiments, the present disclosure relates to a method of forming a transistor device on a semiconductor substrate. The method comprises introducing dopant impurities of a first type of impurity into a transistor region of the semiconductor substrate and forming a recess within the substrate above the transistor region. The method further comprises forming a delta-doped layer comprising dopant impurities of a first type of impurity within the recess, forming a layer of a carbon-containing material on the delta-doped layer, and forming a layer of substrate material on the layer of carbon-containing material. The method further comprises forming a gate dielectric on the layer of substrate material and forming a gate electrode on the gate dielectric.The method further comprises forming lightly doped drain (LDD) regions comprising dopant impurities of a second impurity type, opposite to the first impurity type, on both sides of a channel region comprising the delta-doped layer, layer of carbon-containing material, and layer of substrate material. The method further comprises forming halo regions comprising dopant impurities of a first impurity type on both sides of the channel region, and forming source / drain regions comprising dopant impurities of a second impurity type on both sides of the channel region. In some embodiments, the method further comprises forming a counter-doped layer comprising dopant impurities of a second impurity type, opposite to the first impurity type, underlying the delta-doped layer.

Claims

[1] A transistor device (100A, 100B, 1500) formed on a semiconductor substrate (102), comprising: a recess (114) arranged within a transistor region of the semiconductor substrate (102), the transistor region being doped with dopant impurities of a first type of impurity; a canal region comprising: a delta-doped layer (108, 108A, 108B) comprising dopant impurities of the first type of impurities arranged within the recess (114); a layer of a carbon-containing material (110) lying directly on the delta-doped layer (108, 108A, 108B); and an undoped layer of a substrate material (112) lying directly on the layer of carbon-containing material (110); and a gate structure (1002, 1102) arranged on the channel region. [2] The transistor device (100A, 100B, 1500) of claim 1, further comprising a counter-doped layer (106, 106B) overlying a bottom surface of the recess (114) and underlying the delta-doped layer (108, 108A, 108B), wherein the counter-doped layer (106, 106A) comprises dopant impurities of a second type of impurity that is opposite to the first type of impurity, and wherein the counter-doped layer (106, 106A) is epitaxially deposited within the recess (114). [3] The transistor device (100A, 100B, 1500) of claim 2, wherein the dopant impurities of the first or second type of impurities comprise boron, carbon, indium, or combinations thereof. [4] The transistor device (100A, 100B, 1500) of claim 3, wherein the dopant impurities of the second or first type of impurities comprise phosphorus, antimony, arsenic, or a combination thereof. [5] The transistor device (100A, 100B, 1500) of claim 1, further comprising a counter-doped layer (106, 106B) underlying a bottom or surface of the recess (114) and the delta-doped layer (108, 108A, 108B), wherein the counter-doped layer (106, 106B) comprises dopant impurities of a second type of impurity that is opposite to the first type of impurity, and wherein the counter-doped layer (106, 106B) comprises a doped region of the semiconductor substrate (102) within the recess (114). [6] The transistor device (100A, 100B, 1500) of claim 1, wherein the delta-doped layer (108, 108A) is epitaxially deposited on a bottom surface of the recess (114). [7] The transistor device (100A, 100B, 1500) of claim 1, wherein the delta-doped layer (108, 108B) comprises a doped region of the semiconductor substrate (102) underlying a bottom surface of the recess (114). [8] The transistor device (100A, 100B, 1500) of claim 1, wherein the layer of substrate material (112) has a dopant concentration that is less than 1e18 cm -3 at an interface between the layer of substrate material (112) and the gate structure (1002, 1102). [9] The transistor device (100A, 100B, 1500) of claim 1, wherein the delta-doped layer (108, 108A, 108B) has a dopant concentration less than 2e19 cm-3. [10] The transistor device (100A, 100B, 1500) of claim 1, wherein the substrate material comprises silicon and the carbon-containing material comprises silicon carbide. [11] A method (1600) for forming a transistor device (100A, 100B, 1500) on a semiconductor substrate (102), comprising: introducing dopant impurities of a first type of impurity into a transistor region of the semiconductor substrate (102); Forming a recess (114) within the substrate (102) over the transistor region; Forming a delta-doped layer (108, 108A, 108B) comprising dopant impurities of the first type of impurities within the recess (114); Forming a layer of carbon-containing material (110) directly overlying the delta-doped layer (108, 108A, 108B); and Forming an undoped layer of a substrate material (112) lying directly on the layer of carbon-containing material (110). [12] The method (1600) of claim 11, further comprising forming a counter-doped layer (106, 106A, 106B) underlying the delta-doped layer (108, 108A, 108B) within the recess (114), the counter-doped layer (106, 106A, 106B) comprising dopant impurities of a second type of impurity opposite to the first type of impurity. [13] The method (1600) of claim 12, wherein forming the counter-doped layer (106, 106A) comprises epitaxially depositing the counter-doped layer (106, 106A) on a bottom surface of the recess (114). [14] The method (1600) of claim 12, wherein forming the counter-doped layer (106, 106B) comprises implanting dopant impurities of the second type of impurities into a bottom surface of the recess (114) such that the counter-doped layer (106, 106B) comprises a doped region of the semiconductor substrate (102). [15] The method (1600) of claim 11, wherein forming the delta-doped layer (108, 108A) comprises epitaxially depositing the delta-doped layer (108, 108A) on a bottom surface of the recess (114). [16] The method (1600) of claim 11, wherein forming the delta-doped layer (108, 108B) comprises implanting dopant impurities of the first type of impurities into a bottom surface of the recess (114) such that the delta-doped layer (108, 108B) comprises a doped region of the semiconductor substrate (102). [17] The method (1600) of claim 11, wherein forming the layers of carbon-containing material and substrate material (110, 112) comprises epitaxially depositing the layer of carbon-containing material (110) on the delta-doped layer (108, 108A, 108B), and epitaxially depositing the layer of substrate material (112) on the layer of carbon-containing material (110). [18] A method (1600) for forming a transistor device (100A, 100B, 1500) on a semiconductor substrate (102), comprising: introducing dopant impurities of a first type of impurity into a transistor region of the semiconductor substrate (102); Forming a recess (114) within the substrate (102) over the transistor region; Forming a delta-doped layer (108, 108A, 108B) comprising dopant impurities of a first type of impurities within the recess (114); Forming a layer of carbon-containing material (110) on the delta-doped layer (108, 108A, 108B); Forming an undoped layer of substrate material (112) on the layer of carbon-containing material (110); Forming a gate dielectric (1002) on the layer of substrate material (112); Forming a gate electrode (1102) on the gate dielectric (1002); Forming lightly doped drain regions (1304A, 1304B) comprising dopant impurities of a second type of impurity, which is opposite to the first type of impurity, on both sides of a channel region comprising the delta-doped layer (108, 108A, 108B), the layer of carbon-containing material (110), and the layer of substrate material (112); Forming halo regions (14o4A, 14o4B) comprising dopant impurities of the first type of impurities on both sides of the channel region; and Forming source and drain regions (1504A, 1504B) comprising dopant impurities of a second type of impurities on both sides of the channel region. [19] The method (1600) of claim 18, further comprising forming a counter-doped layer (106, 106A, 106B) within the recess (114), the counter-doped layer (106, 106A, 106B) comprising dopant impurities of the second type of impurities and underlying the delta-doped layer (108, 108A, 108B). [20] The method (1600) of claim 18, further comprising performing annealing after introducing the dopant impurities of the first type of impurities into the transistor region of the semiconductor substrate (102).

Images