Method for manufacturing a semiconductor chip panel

Abstract

A method of manufacturing a semiconductor chip panel, the method comprising: Providing a carrier; Providing a plurality of semiconductor chips, the semiconductor chips each having a first main surface and a second main surface opposite the first main surface, and side surfaces connecting the first and second main surfaces; Placing the semiconductor chips on the carrier, wherein the second main surfaces face the carrier; Applying an encapsulation material to the side surfaces of the semiconductor chips; and further comprising, prior to applying the encapsulation material, covering the first main surfaces of the semiconductor chips such that the encapsulation material is not applied to the first main surfaces.

Description

FIELD OF THE INVENTIONThe present invention relates to a method for manufacturing a semiconductor chip panel and a semiconductor chip package.PRIOR ARTIn power electronics, semiconductor chips with vertical transistors are very often used, such as IGBTs (insulated gate bipolar transistors), or generally transistors in which at least one electrical contact pad is arranged on a first main surface of the semiconductor chip and at least one other electrical contact pad is arranged on a second main surface opposite the first main surface. A plurality of these semiconductor chips may be connected to form power modules or power systems. An example of such power modules are the so-called smart power modules (IPMs).In a manufacturing process of a semiconductor chip package, either a single semiconductor chip or a semiconductor chip module comprising a plurality of semiconductor chips may be embedded in a potting compound, which may comprise any kind of encapsulation material. The manufacturing process may be performed at the level of a wafer. During the manufacturing process, it may be necessary to establish electrical connections between different semiconductor chips within a semiconductor chip module. Since in many cases semiconductor power chips comprise contact elements on both main surfaces thereof, it may be advantageous if semiconductor chips could easily be reached from both sides in order to establish the electrical connections. Another aspect is the emerging and development of new semiconductor materials for power semiconductor chips, such as SiC or GaN, that require different conditions than those in silicon power chips, such as higher temperatures for efficient and fast switching.US 2008 / 0224296 A1 describes a method for producing an article comprising the steps of providing a semiconductor wafer comprising semiconductor chips, separating the semiconductor wafer into a plurality of semiconductor chips, positioning the semiconductor chips on a carrier, and forming a plate by embedding the semiconductor chips in potting material.US 2009 / 0261468 A1 describes a method for producing a semiconductor device, comprising arranging at least two semiconductor chips on a carrier, covering the at least two semiconductor chips with a molding material in order to form a molded body, thinning the molded body until the at least two semiconductor chips are exposed, removing the carrier from the at least two semiconductor chips and singulating the at least two semiconductor chips.U.S. Pat. No. 6,734,534 B1 discloses a microelectronic substrate with integrated components.The publication EP 1 612 021 A1 discloses a separating film for encapsulating a semiconductor chip.The publication US 2006 / 0014328 A1 describes a resin casting method for a semiconductor component.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings serve to further understand embodiments and are incorporated in and form a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of the embodiments. Other embodiments and many intended advantages of embodiments will be readily understood as they are better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding similar parts. FIG. 1 is a flow chart illustrating a method of manufacturing a semiconductor chip panel according to an embodiment;FIGS. 2A-2D are schematic cross-sectional view diagrams illustrating a method of manufacturing a semiconductor chip panel according to an embodiment;FIGS. 3A-3C are schematic cross-sectional view diagrams illustrating a method of manufacturing a semiconductor chip panel including an edge support structure;FIGS. 4A-4E show schematic cross-sectional side view representations of examples of semiconductor chip panels;FIGS. 5A-5C are schematic cross-sectional side view views illustrating a method of manufacturing a semiconductor chip panel by additionally using a carrier strip; FIG. 6 is a schematic cross-sectional side view illustration of an example of a semiconductor chip panel manufactured by additionally using a carrier strip; FIG. 7 is a schematic cross-sectional side view illustration of a semiconductor chip panel after further processing according to an example; andFIGS. 8A-8C show schematic cross-sectional side view diagrams (A, B) and a top view diagram (C) for illustrating an example of a method for manufacturing a semiconductor chip panel and a semiconductor chip package, wherein the encapsulation material overlaps an edge part of a main surface of the semiconductor chip.DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe aspects and embodiments will now be described with reference to the drawings, wherein like reference numerals are generally used throughout to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the embodiments. However, it may be apparent to one skilled in the art that one or more aspects of the embodiments may be practiced with less specific details. In other instances, well-known structures and elements are shown in schematic form to facilitate describing one or more aspects of the embodiments. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be further noted that the drawings are not to scale or are not necessarily to scale.Moreover, while a particular feature or aspect of an embodiment may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects as may be desired or advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," "has," "with," or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprises.". The terms "connected" and "connected", as well as derivatives, may be used. It will be understood that these terms are used to indicate that two elements cooperate or interact with each other whether they are in direct physical or electrical contact or they are not in direct contact with each other. Also, the term "exemplary" is intended to be merely an example and not as "best" or "optimal". The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is determined only by the appended claims.The embodiments of a method for manufacturing a semiconductor die array and a semiconductor die package may use various types of semiconductor dies or semiconductor die modules or circuits integrated into the semiconductor dies, including logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (microelectromechanical systems), power integrated circuits, passive integrated circuits dies, diodes such as free wheeling diodes, etc. The embodiments may also use semiconductor dies, utilize MOS transistor structures, or vertical transistor structures such as IGBT (insulated gate bipolar transistors) structures, or generally transistors or other structures or devices, in which at least one electrical contact pad is arranged on a first main surface of the semiconductor chip and at least one other electrical contact pad is arranged on a second main surface of the semiconductor chip opposite the first main surface of the semiconductor chip. The semiconductor chips may also comprise optical devices, such as light emitting diodes, laser diodes or optical receiving diodes.The semiconductor chips may comprise contact elements or contact pads on one or more of their outer surfaces, wherein the contact elements serve for electrically contacting the semiconductor chips. The contact elements can have any desired shape. They may have the form of pads, i.e. flat contact layers on an outer surface of the semiconductor chip, for example. The contact elements or contact pads may be made of any electrically conductive material, e.g. a metal such as aluminum, gold or copper, or a metal alloy or an electrically conductive material or an electrically conductive semiconductor material. The contact elements can also be formed as layer stacks of one or more of the above-mentioned materials.A semiconductor chip panel may comprise an encapsulant or encapsulation material containing the semiconductor chips or semiconductor chip modules embedded therein. The encapsulation material may be any electrically insulating material, such as any type of molding material, any type of resin material, or any type of epoxy material. The encapsulation material may also be a polymer material, a polyimide material, a thermoplastic material, a silicone material, a ceramic material and a glass material. The encapsulation material may also comprise any of the above materials and may further include fill materials embedded therein, such as thermally conductive increments. These fill increments may be made of AlO or Al 2 O 3, AlN, BN, or SiN, for example. The semiconductor chip panel may have the shape of a wafer, i.e. a circular shape, but is not limited to the shape of a wafer, but may have any size and shape and any suitable arrangement of semiconductor chips or semiconductor chip modules embedded therein.In the claims and in the following description, different embodiments of a method for manufacturing a semiconductor chip panel are described as a particular sequence of processes or measures, in particular in the flow chart. It should be noted that the embodiments should not be limited to the specific sequence described. Specific or all different processes or acts may also be performed simultaneously or in any other convenient and suitable sequence.The semiconductor chip panel may include one or more individual semiconductor chips or semiconductor chip modules. The semiconductor chip modules may comprise two or more semiconductor chips, in particular power transistor chips, and may comprise at least one further semiconductor chip, which may comprise one or more of a logic circuit or a driver circuit. In particular, the semiconductor chip modules may include the so-called smart power modules (IPMs). The semiconductor chip panel may also comprise any other type of semiconductor chip as mentioned above.FIG. 1 shows a flow chart for illustrating a method for manufacturing a semiconductor chip panel according to an embodiment. Method 100 of FIG. 1 includes providing a carrier (110), which may include any type of solid material, such as metal, glass, ceramic, semiconductor (Si), etc. The carrier may be prepared on an upper main surface thereof such that temporary bonding of semiconductor chips is possible. The carrier may comprise, for example, an adhesive layer or film applied to a major surface of the carrier. The method further comprises providing a plurality of semiconductor chips (120), wherein the semiconductor chips each comprise a first main surface and a second main surface opposite the first main surface, and side surfaces connecting the first and second main surfaces. The method further comprises placing the semiconductor chips on the carrier, wherein the second main surfaces face the carrier (130), wherein the semiconductor chips can be attached with their second main surfaces to the adhesive layer or foil located on the carrier. The method further comprises applying an encapsulation material to the side surfaces of the semiconductor chips (140), wherein the encapsulation material may be applied such that only the side surfaces of the semiconductor chips are covered with the encapsulation material and appropriate precautions are taken such that the encapsulation material is not applied to the first main surfaces of the semiconductor chips.According to an embodiment of the method 100 of FIG. 1, the first main surfaces of the semiconductor chips are covered by a so-called release film, which serves to prevent the application of the encapsulation material to the first main surfaces. The release film may comprise a thermoplastic film, a polymer film or a polymer film; it may in particular comprise teflon, PTFE, ETFE or PET. The separating film may also be formed so as to allow forming a supporting structure at the edge of the semiconductor chip panel, which may be advantageous, in particular in case of forming a very thin semiconductor chip panel resulting from very thin semiconductor chips. An embodiment thereof will be shown in more detail later.According to an embodiment of the method 100 of FIG. 1, applying the encapsulation material comprises forming, in particular transfer molding. The encapsulation material may include one or more of an insulating material, a molding material, a polymer material, a polyimide material, a resin material, an epoxy resin material, a silicone material, a ceramic material, and a glass material. According to an embodiment of the method 100 of FIG. 1, the semiconductor chip panel to be manufactured comprises a plurality of semiconductor chips or semiconductor chip modules. The semiconductor chips may include a first main surface and a second main surface opposite the first main surface, wherein the first main surface includes a first contact element and the second main surface includes a second contact element. At least a portion of the semiconductor chips may include one or more of a transistor, a power transistor, a vertical transistor, a MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, and a passive component. The semiconductor chip panel may include one or more individual semiconductor chips or semiconductor chip modules. The semiconductor chip modules may comprise two or more semiconductor chips, in particular power transistor chips, and may comprise at least one further semiconductor chip, which may comprise one or more elements of a logic circuit and a driver circuit. In particular, the semiconductor chip modules may include the so-called smart power modules (IPMs).According to an embodiment of the method 100 of FIG. 1, the thickness of the semiconductor chips may cover a wide range of 5 μm to 800 μm or even 1 mm in case of an unground semiconductor wafer. At least a portion of the semiconductor chips may comprise a thickness in a range of 5 μm-100 μm, in particular of 30 μm-80 μm.According to an embodiment of the method 100 of FIG. 1, the semiconductor chip panel to be manufactured comprises a plurality of similar or identical semiconductor chips. The semiconductor chips may be placed on the carrier with one and the same orientation, which means for example that the semiconductor chips are placed such that active area-containing electrical contact elements are either remote from the carrier or face the carrier. It is also possible to place the semiconductor chips on the carrier with different spatial orientation, wherein for example in a first group of semiconductor chips their active surface faces the carrier and in a second group of semiconductor chips their active surface is remote from the carrier, wherein in particular the semiconductor chips can be placed in another way along a row of semiconductor chips.According to an embodiment of the method 100 of FIG. 1, at least a portion of the semiconductor chips may be first placed on one or more interposers, such as carrier strips, and thereafter the interposers are attached to the carrier.According to an embodiment of the method 100 of FIG. 1, through holes may be formed in the encapsulation material, in particular for forming electrical vias for electrically connecting different semiconductor chips to each other to construct semiconductor chip modules.FIGS. 2A-2D are schematic cross-sectional side view diagrams illustrating an example of a method of manufacturing a semiconductor chip panel. According to FIG. 2A, a carrier 200 is provided, which may have the shape of a wafer, i.e. a circular shape, and which may consist of a solid material, such as metal, ceramic, glass or silicone. On an upper main surface of the carrier 200 may be attached an adhesive layer 210, such as a double-sided adhesive sheet or tape, selected to be easily peeled from the carrier 200 and the manufactured semiconductor chip panel at the end of the molding process. A plurality of semiconductor chips 220 can be fastened on the adhesive layer 210, for example by means of a pick-and-place (pick-and-place) process. The semiconductor chips 220 may be placed in a matrix arrangement. The semiconductor chips 220 may have been produced on a semiconductor wafer in a preceding manufacturing method and have then been cut out from the semiconductor wafer to form a plurality of individually manageable chips, which may then be placed on the adhesive layer 210 with a predetermined spatial distance from each other. The semiconductor chips 220 may consist of semiconductor power chips, in particular those having a vertical structure, for example. The semiconductor chips 220 may also be made of other electrical or mechanical-electrical devices as outlined above. The semiconductor chips 220 comprise first upper main surfaces located remote from the carrier 200 and second lower main surfaces opposite the first main surfaces arranged facing the carrier 200. The semiconductor chips 220 may have a usual rectangular shape so as to include four side surfaces connecting the first and second main surfaces.FIG. 2B shows a situation in which the assembly of the carrier 200 and the deposited semiconductor chips 220 can be brought into a forming device, in particular a press spraying device, the technical details of which are not illustrated here for the sake of simplicity. Within the forming apparatus, a separation film 230 may be provided covering the upper first main surfaces of the semiconductor chips 220. The release film 230 is used to prevent encapsulation material from being applied to the upper first surfaces of the semiconductor chips 220. For this purpose, a stamper 240 may be used to press the release film 230 on the upper surfaces of the semiconductor chips 220.As shown in FIG. 2C, this may be followed by a usual transfer molding process, wherein the encapsulation or molding material is first liquefied by heat and pressure and then forced into the closed and evacuated mold cavity or cavity of the molding apparatus and maintained there under additional heat and pressure until the entire encapsulation material 250 is solidified, i.e. cured. The solidified encapsulation material 250 is indicated by the hatched areas. In the molding process, the encapsulation material 250 flows only into the spaces between the semiconductor chips 220, but does not flow onto the first upper surfaces of the semiconductor chips 220 due to the presence of the separation film 230. FIG. 2C also shows the piston 251 resulting from the transfer molding process.As shown in FIG. 2D, after opening the molding device, the encapsulated semiconductor chips 220 are removed in the form of a semiconductor chip panel 260. In the semiconductor chip panel 260, all semiconductor chips 220 are encapsulated by the encapsulation material 250 only on their four side faces, but not on their first and second main faces. The manufacturing method therefore creates a semiconductor chip panel 260 comprising double exposed semiconductor chips 220 encapsulated by the encapsulation material 250 only at the side surfaces.Next, the release film 230 supplied at one end of the mold and rolled up at the opposite end of the mold may be transported along a length of the mold and a new cycle may begin again by placing a carrier 200 of semiconductor chips 220 within the mold cavity of the molding apparatus.FIGS. 3A-3C illustrate another example of a fabrication method in which very thin semiconductor chips are to be encapsulated, which necessarily results in a semiconductor chip panel having a thickness corresponding to the thickness of the semiconductor chips. This semiconductor chip panel therefore needs a stabilizing structure so as to enable or facilitate the further processing after the forming process.As shown in FIG. 3A, the stabilizing or supporting structure may be manufactured by a separating film 231 comprising an annular protrusion 231.1. Again as in the embodiment of FIGS. 2A-2D, the shape of the release film 231 may be determined by a stamper (not shown here) pressing the release film 231 from above down on the top surfaces of the semiconductor chips 220. Then, the transfer molding process shown in FIG. 3B is performed. The protrusion 231.1 enables the formation of a stabilizing ring 261.1 of the manufactured semiconductor chip panel 261 as shown in FIG. 3C.FIGS. 4A-4E show schematic cross-sectional side view representations of several examples of semiconductor chip panels that may be manufactured by the manufacturing method described above. The semiconductor chips may have an active area, which may be defined as the area on which electrical contact elements are located. In this sense, the semiconductor chips may also have two active areas, as in the case of vertical transistor device chips.FIG. 4A shows an example of a semiconductor chip panel 262 in which the semiconductor chips 222 are oriented such that the active surface is remote from the carrier when the semiconductor chips 222 are placed on the carrier, while FIG. 4B shows an example of a semiconductor chip panel 263 in which the semiconductor chips 223 are placed on the carrier such that the active surface faces the carrier.FIG. 4C shows another example of a semiconductor chip panel in which the semiconductor chips 224 are arranged on the carrier with different spatial orientation, i.e. a first group of semiconductor chips with their active surface facing the carrier and a second group with their active surface remote from the carrier.FIG. 4D shows another example of a semiconductor chip panel 265 in which through holes 251 are formed in the encapsulation material 250. These through holes 251 may be formed after the forming process by, for example, drilling or laser. They may be used for forming electrical connections between different semiconductor chips, as will be shown later.FIG. 4E shows another example of a semiconductor chip panel 266 in which through holes 253 are formed in the encapsulation material 250, and also blind holes 252 are formed in the encapsulation material 250, the blind holes 252 extending from a main surface of the encapsulation material 250 to the active surface of a particular semiconductor chip 225. The blind holes 252 may also be formed by drilling or lasering.FIGS. 5A-5C are schematic cross-sectional side view diagrams illustrating a method of manufacturing a semiconductor chip panel according to an embodiment. According to this embodiment, at least one of the semiconductor chips 220 may be placed on an interposer 235, and then the interposers 235 with the attached semiconductor chips 220 may be attached to the adhesive layer 210 located on the carrier 200. Each of the interposers 235 may carry one, two, or three or even more semiconductor chips 220. Finally, a semiconductor chip panel 267 as shown in FIG. 5C is obtained. In this semiconductor chip panel 267, the upper main surfaces of the at least one semiconductor chip 220 are exposed, i.e., not covered with encapsulation material 250, and the lower main surfaces are fixed to one of the interposers 235, and the lower surfaces of the interposers 235 are themselves exposed. The interposers 235 may in principle comprise any type of solids. They may consist of one or more carrier strips, such that, for example, the interposers 235 shown in FIGS. 5A-5C include portions of one and the same continuous carrier strip. They may also include, for example, an insulator, any type of plastic material, such as a thermally conductive plastic material, a ceramic material, or a direct copper bond (DCB) substrate.In the embodiment, as shown in FIGS. 5A-5C, the interposers 235 are provided on the second main surfaces of the semiconductor chips 220. Alternatively or additionally, it is also possible to provide one or more interposers on the first upper main surfaces of the semiconductor chips 220 so as to be located between the first upper main surfaces and the separation film 231. Also in this case, there may be a continuous interposer covering multiple or all of the semiconductor chips 220, or there may be more than one interposer, each of which covers one or more semiconductor chips.FIG. 6 is a schematic cross-sectional side view diagram illustrating another example of a method of manufacturing a semiconductor chip panel according to an embodiment. A difference with respect to the embodiment of FIGS. 5A-5C is that the encapsulation material 255 also covers the first top surfaces of a part of the semiconductor chips 220, and blind holes 252 are formed in the encapsulation material 255 from the top surface of the encapsulation material 255 down to the first surfaces of the semiconductor chips 220. The blind holes 252 may be formed by drilling or lasering.An advantage of the method of manufacturing a semiconductor chip panel as described so far is that it provides a semiconductor chip panel in which the semiconductor chips are exposed on both main surfaces or one surface is exposed and the other surface is attached to a carrier strip which is exposed (FIG. 5C ) or wherein one surface is exposed through blind holes through the encapsulation material and the other surface is attached to a carrier strip which is exposed (FIG. 6 ). In the following, examples of semiconductor chip panels are shown which have been processed by the method as described so far and which have been further processed by applying an electrical connection wiring and dielectric layers.FIG. 7 shows a schematic cross-sectional side view illustration of examples of a semiconductor chip panel 700 comprising semiconductor chips 720 embedded in an encapsulation material 750. The semiconductor chips 720 are electrically connected to each other through electrical wiring layers 751, and further dielectric layers 735 are deposited on predetermined parts of the upper and lower surfaces of the semiconductor chip panel 700. The through holes and the blind holes formed in the encapsulation material 750 as shown in previous examples are filled with electrically conductive material and may therefore be used for electrically connecting different semiconductor chips to each other. This can be done in a similar manner with the semiconductor chip panels using carrier strips as those shown in Figure 6.FIGS. 8A-8C illustrate another example of a method of manufacturing a semiconductor chip panel and a semiconductor chip package. FIG. 8A shows a partial section of a carrier 800, an adhesive layer 810 applied to the carrier 800, and semiconductor chips 820 placed on the adhesive layer 810. In a molding apparatus, a separation layer 830 is disposed above the upper first surfaces of the semiconductor chips 820 so as not to be completely covered by the separation layer 830, instead the separation layer 830 is raised at an edge portion outward on the entire circumference of the edge on the first upper surface of the semiconductor chip 820. This shape of the separation layer 830 may be provided by a spring loaded plunger 840 pressing down on the separation layer 830 above the semiconductor chips 820. As a result, in the subsequent transfer molding process, the encapsulation material 850 is applied to the semiconductor chips 820 so as to cover the side edges and also a peripheral edge portion of the upper first surface of the semiconductor chips 820, as seen in the cross-sectional view of FIG. 8B and the plan view of FIG. 8C.A possible application of the embodiment of FIGS. 8A-8C is the manufacture of a sensor unit, wherein the semiconductor chip 820 is made of a sensor chip and the upwardly protruding part of the encapsulation material 850 may be used, for example, to attach thereto a membrane which may be held between the inner walls of the protruding part of the encapsulation material 850 and is therefore located above the first upper surface of the semiconductor chip 820.Another application of the embodiment of FIGS. 8A-8C is to fabricate an LED (light emitting diode) device, wherein the semiconductor die 820 comprises a light emitting diode. The upwardly protruding part of the encapsulation material 850 may be used, for example, to attach thereto an optical lens which may be held between the inner walls of the protruding part of the encapsulation material 850 and which has the purpose of concentrating the light emitted by the light emitting diode.The embodiment of FIGS. 8A-8C may also be used for any type of semiconductor chip to be protected on its upper major surface from any type of materials that may be used in the fabrication process. In this application, the edge portion covered by the encapsulation material serves to protect or shield the upper major surface of the semiconductor surface.Although the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples. With particular reference to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components, unless otherwise indicated, are intended to correspond to any component or structure that performs the specific function of the described component (e.g., which is functionally equivalent), although not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.

Claims

A method of manufacturing a semiconductor chip panel, the method comprising: providing a carrier; providing a plurality of semiconductor chips, the semiconductor chips each having a first main surface and a second main surface opposite the first main surface, and side surfaces connecting the first and second main surfaces; placing the semiconductor chips on the carrier, the second main surfaces facing the carrier; applying an encapsulation material to the side surfaces of the semiconductor chips; and further comprising, prior to applying the encapsulation material, covering the first main surfaces of the semiconductor chips such that the encapsulation material is not applied to the first main surfaces.The method of claim 1, wherein the first major surfaces are covered by a polymer film or a polymer film.The method of any preceding claim, wherein applying the encapsulating material comprises transfer molding.The method of any preceding claim, wherein at least some of the semiconductor chips comprise one or more of a power transistor, a vertical transistor, a MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, and a passive component.Method according to one of the preceding claims, wherein the semiconductor chips are identical or different and are arranged on the carrier with the same or different spatial orientation.The method according to any of the preceding claims, wherein the semiconductor chips comprise different electrical devices.The method according to any of the preceding claims, wherein at least some of the semiconductor chips have a thickness in the range of 5 μm - 1000 μm.The method of any preceding claim, wherein all semiconductor chips have a same thickness.The method according to any one of claims 1 to 7, wherein the semiconductor chips have different thicknesses.The method of any preceding claim, wherein the encapsulation material comprises one or more of an insulating material, a molding material, a polymer material, a polyimide material, a resin material, an epoxy resin material, a silicone material, a ceramic material, and a glass material.A semiconductor chip unit, comprising: a semiconductor chip having a first main surface and a second main surface opposite to the first main surface, and side surfaces connecting the first and second main surfaces; and an encapsulating material covering the side surfaces of the semiconductor chip, wherein the encapsulating material does not cover the second main surface, and covers the first main surface only on an edge portion and does not cover the remaining portion of the first main surface.The semiconductor chip of claim 11, wherein the semiconductor chip comprises one or more of a power transistor, a vertical transistor, a MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, a free wheeling diode, and a passive component.The semiconductor chip unit according to claim 11 or 12, wherein the semiconductor chip has a thickness in the range of 30 μm - 80 μm.The semiconductor chip unit according to any one of claims 11 to 13, wherein the encapsulation material comprises one or more of an insulating material, a molding material, a polymer material, a polyimide material, a resin material, an epoxy resin material, a silicone material, a ceramic material, and a glass material.A semiconductor chip unit, comprising: a semiconductor chip module comprising two or more semiconductor chips, wherein at least one of the semiconductor chips comprises a first main surface and a second main surface opposite the first main surface and side surfaces connecting the first and second main surfaces; and an encapsulation material covering the side surfaces of the at least one semiconductor chip, wherein the encapsulation material is not applied to the first and second main surfaces of the at least one semiconductor chip, and wherein another semiconductor chip comprises a first main surface and a second main surface opposite the first main surface and side surfaces connecting the first and second main surfaces, the encapsulation material covering the side surfaces of the other semiconductor chip and being applied to the first and second main surfaces.The semiconductor die unit of claim 15, wherein the at least one semiconductor die comprises one or more of a power transistor, a vertical transistor, a MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, and a passive component.The semiconductor chip unit according to any one of claims 15 to 16, further comprising an annular part of the encapsulation material extending from the side surfaces of the at least one semiconductor chip and protruding beyond a plane from the first or second main surface.

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