Semiconductor device and manufacturing process therefor

Abstract

Field-effect semiconductor device, comprising: - a semiconductor body (40) having a principal surface (101) and comprising in a vertical cross-section orthogonal to the principal surface (101) the following: - a drift layer (1a) of a first conductivity type; - a semiconductor mesa (1b) of the first conductivity type, adjacent to the drift layer (1a), extending to the main surface (101) and comprising a first side wall, wherein a rectifier junction (18) is formed on the first side wall; and - two second semiconductor regions (2) of a second conductivity type, arranged adjacent to the semiconductor mesa (1b), each of the two second semiconductor regions (2) forming a pn junction at least with the drift layer (1a); and - a gate metallization in ohmic contact with a non-monocrystalline semiconductor material (6) of the second conductivity type, which forms the rectifier junction (18) as a hetero junction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to semiconductor devices, particularly to power semiconductor transistors having a vertical channel, and to related methods for fabricating heterojunction semiconductor devices. BACKGROUND

[0002] Semiconductor transistors, particularly field-effect controlled switching devices such as a MISFET (metal-insulator-semiconductor field-effect transistor), also referred to below as a MOSFET (metal-oxide-semiconductor field-effect transistor), a JFET (junction field-effect transistor) and a MESFET (metal-semiconductor field-effect transistor), have been used for various applications, including, but not limited to, use as switches in power supplies and energy converters, as voltage-controlled resistors, in consumer electronics, for example, stereo systems, and communications technology, for example, microwave frequency communications and radar.

[0003] Particularly with regard to power devices that can switch large currents and / or operate at higher voltages, the following are often required: a low on-resistance Ron, a low leakage current, low switching losses and / or low parasitic capacitances, such as the Miller capacitance, which is related to the gate-drain capacitance between the gate electrode and the drain region of the field-effect transistor and the gate-source capacitance between the gate electrode and the source region of the field-effect transistor.

[0004] US 2011 / 0 278 591 A1 describes a SiC JFET semiconductor device with semiconductor mesas between trenches. Along the sidewalls and bottom of the trenches, p-gate regions are formed in the n-type semiconductor material of the semiconductor mesas, forming pn junctions with the n-type semiconductor material.

[0005] US 2009 / 0 068 803 A1 discloses a method for manufacturing an integrated circuit with vertical junction field-effect transistors. The field-effect transistors have trenches between which semiconductor mesas remain. Doping regions are provided at the bottom of the trenches to form pn junctions. The field-effect transistors can have Schottky diodes.

[0006] US 2005 / 0 067 630 A1 discloses a vertical semiconductor junction field-effect transistor formed by a semiconductor structure having a lower layer as the drain layer, a middle layer as the junction and channel layers, and an upper layer as the source layer. A plurality of laterally spaced U-shaped trenches with vertical sidewalls define a plurality of laterally spaced mesas. The mesas have semiconductor regions for forming pn junctions in the mesas, which define a plurality of laterally spaced long and vertical channels. A source contact is formed on the upper source layer, and a drain contact is formed on the lower drain layer.

[0007] JP 2011 - 142 355 A1 discloses a vertical semiconductor diode which can be designed as a Schottky diode.

[0008] US 2004 / 0 135 178 A1 describes a vertical SiC JFET with a Schottky gate.

[0009] Furthermore, there are ongoing developments to increase the yield of semiconductor transistor manufacturing.

[0010] For these and other reasons, there is a need for the present invention. SUMMARY

[0011] According to one embodiment of the invention, a field-effect semiconductor device is provided according to claim 1. According to another embodiment of the invention, a method of forming a field-effect semiconductor device is provided according to claim 11.

[0012] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: illustrated Fig. 1 shows a cross section through a semiconductor body of a field-effect semiconductor device; illustrated Fig. 2 shows a cross section through a semiconductor body of a field-effect semiconductor device according to an illustrative example; illustrated Fig. 3 shows a cross section through a semiconductor body of a field-effect semiconductor device; illustrated Fig. 4 shows a cross section through a semiconductor body of a field-effect semiconductor device according to an illustrative example; illustrated Fig. 5 shows a cross section through a semiconductor body of a field-effect semiconductor device according to an embodiment; and illustrate Fig. 6 to 8 show vertical cross sections through a semiconductor body during method steps of a method according to embodiments. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top," "bottom," "front," "back," "forward," "rear," etc., will be used with reference to the orientation of the figure(s) being described. Since components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It will be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0015] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for purposes of illustration and is not intended to be limiting of the invention. For example, features illustrated or described as part of one embodiment may be used on or in conjunction with other embodiments to provide yet another embodiment. The present invention is intended to embrace such modifications and variations. The examples are described using specific language that is not to be construed as limiting the scope of the appended claims. The drawings are not to scale and are for purposes of illustration only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals throughout the different drawings unless otherwise indicated.

[0016] The term "horizontal," as used in this specification, is intended to describe an orientation substantially parallel to a first or main surface of a semiconductor substrate or body. This may, for example, be the surface of a wafer or a chip.

[0017] The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the first surface, i.e., parallel to the normal direction of the first surface of the semiconductor substrate or body.

[0018] In this description, it is assumed that a second surface of a semiconductor substrate of the semiconductor body is formed in the lower or back surface, whereas the first surface is assumed to be formed by the upper, front, or main surface of the semiconductor substrate. The terms "above" and "below" as used in this description therefore describe a location of a structural feature relative to another structural feature, taking this orientation into account.

[0019] In this specification, n-doped is referred to as the first conductivity type, whereas p-doped is referred to as the second conductivity type. Alternatively, the semiconductor devices may be formed with opposite doping relationships, such that the first conductivity type may be p-doped and the second may be n-doped. Furthermore, some figures illustrate relative doping concentrations by displaying "-" or "+" next to the doping type. "n - “ means, for example, a doping concentration that is lower than the doping concentration of an “n” doping region, whereas an “n +“-doping region has a higher doping concentration than the “n”-doping region. However, the indication of the relative doping concentration does not mean that doping regions with the same relative doping concentration must have the same absolute doping concentration, unless otherwise stated. For example, two different n + -doping regions have different absolute doping concentrations. The same applies, for example, to an n + -doping area and a p + -Doping area.

[0020] Specific embodiments described in this specification relate to, but are not limited to, field-effect semiconductor devices such as MESFETs and JFETs, in particular vertical power field-effect transistors, and to fabrication methods therefor.

[0021] The term "heterojunction," as used in this specification, is intended to describe an interface between two layers or regions of a semiconductor material with different crystal structures. These semiconductor materials typically have different band gaps.

[0022] Typically, the semiconductor device is a power semiconductor device having an active region with a plurality of transistor cells for carrying and / or controlling a load current between load metallizations. Furthermore, the power semiconductor device may have a peripheral region with at least one edge termination structure that, viewed from above, at least partially surrounds an active region of transistor cells.

[0023] The term "power semiconductor device," as used in this specification, is intended to describe a single-chip semiconductor device with high voltage and / or high current switching capabilities. In other words, power semiconductor devices are designed for high current, typically in the ampere range, and / or high voltages, typically above 100 V, more typically above 400 V.

[0024] The term "field effect," as used in this specification, is intended to describe the electric field-mediated formation of a conductive "channel" of a first conductivity type and / or the control of the conductivity and / or the shape of the channel between two regions of the first conductivity type. The conductive channel can be formed and / or controlled in a semiconductor region of a second conductivity type, typically a body region of the second conductivity type, arranged between the two regions of the first conductivity type. Due to the field effect, a unipolar current path is formed and / or controlled through the channel region between a source region or an emitter region of the first conductivity type and a drift region of the first conductivity type in a MOSFET structure or an IGBT structure.The drift region can be in contact with a more highly doped drain region of the first conductivity type or a more highly doped collector region of the second conductivity type. The drain region or the collector region is in low-resistance electrical contact with a drain or collector electrode. The source region or emitter region is in low-resistance electrical contact with a source or emitter electrode. In a JFET structure or a MESFET structure, respectively, the channel region is typically formed by a portion of the drift region forming one or two rectifier junctions with one or two gate regions, and can be controlled by changing the width of the depletion layer(s) formed between the gate region(s) and the channel region.

[0025] In the context of the present description, the terms "in ohmic contact," "in electrically resistive contact," and "in electrically resistive connection" are intended to describe that there is an ohmic current path between respective elements or regions of a semiconductor device at least when no voltages or only low probe voltages are applied to and / or across the semiconductor device. Similarly, the terms "in low ohmic contact," "in low-resistance electrical contact," and "in low-resistance electrical connection" are intended to describe that there is an ohmic current path of low resistance between respective elements or regions of a semiconductor device at least when no voltages are applied to and / or across the semiconductor device.Within this specification, the terms "in low ohmic contact," "in low-resistance electrical contact," "electrically coupled," and "in low-resistance electrical connection" are used interchangeably. In some embodiments, the resistance of a low-resistance current path between respective elements or regions of a semiconductor device, which is low when low voltages are applied to and / or across the semiconductor device, e.g., a probe voltage of less than one or several volts, becomes high above a threshold voltage, e.g., due to the depletion of a semiconductor region forming at least part of the current path.

[0026] In the context of the present description, the term "metallization" is intended to describe a region or layer with metallic or near-metallic properties with respect to electrical conductivity. A metallization may be in contact with a semiconductor region to form an electrode, a contact pad, and / or a terminal of the semiconductor device. The metallization may be made of or comprise a metal such as Al, Ti, W, Cu, Mo, and Co, or a metal alloy such as NiAl, but may also be made of a material with metallic or near-metallic properties with respect to electrical conductivity, such as highly doped n-type or p-type poly-Si, TiN, an electrically conductive silicide such as TaSi2, TiSi2, PtSi, CoSi2, WSi2, MoSi, or an electrically conductive carbide such as AlC, NiC, MoC, TiC, CoC, PtC, WC, or the like.The metallization may also comprise different electrically conductive materials, for example a stack of these materials.

[0027] In the following, embodiments relating to semiconductor devices and manufacturing methods for forming semiconductor devices will be explained primarily with reference to silicon carbide (SiC) semiconductor devices having a monocrystalline SiC semiconductor body. Accordingly, a semiconductor region or layer is typically a monocrystalline SiC region or layer, unless otherwise stated.

[0028] However, it is clear that the semiconductor body may be made of any semiconductor material suitable for producing a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), Group IV semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few.The semiconductor materials listed above are also called homojunction semiconductor materials. When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaNN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaNN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (Si. x C 1-x) and silicon-SiGe heterojunction semiconductor materials. Currently, Si, SiC, GaAs, and GaN materials are mainly used for power semiconductor applications. If the semiconductor body comprises a material with a high band gap, such as SiC or GaN, which has a high breakdown field strength or high critical avalanche field strength, the doping of the respective semiconductor regions can be selected higher, which increases the on-resistance R on reduced.

[0029] With reference to Fig. 1, examples of a field effect semiconductor device 100 are explained. Fig. 1 illustrates a schematic cross section through a semiconductor body 40 of the semiconductor device 100. The semiconductor body 40 comprises a main surface 101 having a vertical direction e n defined, and a rear surface 102 opposite the main surface 101.

[0030] In the exemplary embodiment, an n-type drift layer 1a having a first maximum doping concentration is embedded in the semiconductor body 40 and in ohmic contact with a drain metallization 12 disposed on the rear surface 102 above an n-type drain layer 3 extending to the rear surface 102. The drain layer 3 has a maximum doping concentration that is higher than the first maximum doping concentration.

[0031] According to one embodiment, a plurality of spaced-apart n-type semiconductor mesas 1b are arranged on the drift layer 1. Each of the semiconductor mesas 1b is adjacent to the drift layer 1 and extends substantially to the main surface 101.

[0032] In the context of the present description, the term "semiconductor mesa" is intended to describe semiconductor regions that extend from a common substrate or a common semiconductor layer to a main surface of the semiconductor body or wafer and are spaced apart from one another. Typically, a semiconductor mesa is arranged, in a vertical cross-section that is substantially orthogonal to the main surface, between two adjacent trenches that extend from the main surface into the semiconductor body or wafer. The trenches may be substantially vertical (vertical trenches), i.e., the sidewalls of the trenches or the semiconductor mesa may be substantially orthogonal to the main surface in the vertical cross-section. In the vertical cross-section, the two sidewalls of a trench or a semiconductor mesa may also be tapered. The terms "semiconductor mesa" and "mesa" are used synonymously within this description.In the following, the two sidewalls of a trench or a semiconductor mesa are also referred to as the first sidewall and the second sidewall.

[0033] In vertical cross section in Fig. 1, the mesas 1b are arranged between respective adjacent pairs of vertical trenches 50, which extend from the main surface 102 substantially to the drift layer 1a. The trenches 50 may have a vertical extension of approximately 1 µm to approximately 2 µm, or even to approximately 10 µm or several tens of µm. Each of the mesas 1b is in ohmic contact with a source contact 10a, typically via a respective n-type source contact region 11 formed in the mesas 1b and having a higher maximum doping concentration than the mesas 1b. Each source contact 10a is arranged on the main surface 101 or one of the semiconductor mesas 1b, respectively. The source contacts 10a may be made of a nickel-aluminum alloy, for example. Typically, the aluminum content of the nickel-aluminum alloy ranges from about 2% to about 16% for a SiC semiconductor device 100.

[0034] Typically, a front side metallization 10 forming a source terminal is arranged on the main surface 101 to be in contact with the source contacts 10a and the mesas 1b, respectively.

[0035] In the Fig. 1, a rectifying junction 18 is arranged on each of the sidewalls 19 of the semiconductor mesas 1b. For the sake of clarity, only one of the plurality of sidewalls 19 and rectifying junctions 18 is designated by the respective reference numeral 18, 19. Each rectifying junction 18 is formed between one of the semiconductor mesas 1b and a gate region formation layer 8, which is arranged on a sidewall of the semiconductor mesa 1b and is in ohmic contact with a common gate metallization (in Fig. 1 (not shown). The gate region formation layer 8 is also referred to as the gate layer below. A common gate metallization is also typically arranged on the main surface 101. Accordingly, the semiconductor device 100 is a three-dimensional normally-on field-effect semiconductor device. To control a substantially vertical current between the common source metallization 10 at the source potential V S and the drain metallization 12 at the drain potential V D and through a first n-type semiconductor region 1 formed by the mesas 1b and the drift layer 1a, and through the adjacent drain layer 3, a suitable gate potential V G To turn off the semiconductor device 100, the gate potential or the gate voltage V G and the source potential or source voltage V Sbe selected such that the rectifier junctions 18 are reverse-biased, and a current-blocking depletion region (space charge region) is formed in each of the mesas 1b. The maximum doping concentration of the channel region forming portions of the mesas 1b may, depending on the desired device characteristics, have substantially the same or a different doping concentration than the drift layer 1a.

[0036] In the Fig. In the example illustrated in Figure 1, the semiconductor device 100 is formed as a normally-on n-channel field-effect semiconductor device with a plurality of n-channel regions formed substantially in or by the mesas 1b. Turning off the n-channel device 100 typically requires a negative gate-source voltage V GS =V G -V S <0.

[0037] In other embodiments, the Fig. 1 are reversed to form a p-channel field-effect semiconductor device, which is normally a , and which is controlled by a suitable positive gate-source voltage V GS can be switched off.

[0038] According to an alternative example, the rectifier junctions are 18 Schottky junctions. In this alternative example, the gate layers are 8 Schottky layers, i.e., Schottky contact-forming metal layers, for example, titanium layers. Accordingly, the semiconductor device 100 is a MESFET, typically a power MESFET, with a plurality of unit cells 120. For clarity, only one of the unit cells is designated by reference numeral 120.

[0039] As illustrated in the second vertical trench 50 from the left, a conductive layer 8a with a higher electrical conductivity than the Schottky layer 8 may be disposed on the Schottky layer 8 to improve electrical contact with the common gate metallization. The conductive layer 8a may be a metal layer or a highly doped polysilicon (poly-Si) layer.

[0040] A dielectric region 9 is arranged in each of the trenches 50 and between the front-side metallization 10 and the Schottky layer 8 and the conductive layer 8a. The dielectric regions 9 are arranged at least in respective upper regions of the trenches 50, but may also extend from the main surface 101 to respective bottom walls 59, as shown in Fig. 1. Furthermore, the dielectric regions 9, in vertical cross-section and adjacent to the main surface 101, may extend between adjacent semiconductor mesas 1b. Typically, the trenches 50 are void-free. In other embodiments, one or more voids are provided in each of the trenches 50. Accordingly, the mechanical stress can be reduced.

[0041] According to one embodiment, the bottom wall 59 of each vertical trench 50 adjoins a respective second p-type semiconductor region 2. The maximum doping concentration of the second semiconductor regions 2 is typically higher than about 10 17 cm -3 , typically higher than about 10 18 cm -3Each of the second semiconductor regions 2 forms a pn junction with the drift layers 1a and 1b. The spaced-apart second semiconductor regions 2 and the pn junctions formed with the drift layers 1a and 1b, respectively, may be substantially centered with respect to the trenches 50. Furthermore, each semiconductor mesa 1b may be substantially centered, in vertical cross-section, with respect to the adjacent second semiconductor regions 2.

[0042] During a blocking mode of the semiconductor device 100, in which the rectifier junctions 18 are reverse-biased, space charge regions (depletion regions) are formed, which extend from respective ones of the second semiconductor regions 2 into the drift layer 1a and may even merge with each other and typically also with depletion regions formed in the mesas 1b. Furthermore, high electric fields near the Schottky layer 8 adjacent to the bottom walls of the trenches 50 are avoided during the blocking mode by the implementation of the second semiconductor regions 2. Accordingly, the leakage current can be reduced without significantly changing the unipolar behavior of the semiconductor device 100 compared to semiconductor devices without the second semiconductor regions 2.For this purpose, the second semiconductor regions 2 are typically in ohmic contact with the gate metallization, for example via respective Schottky layers 8 and / or respective conductive layers 8a.

[0043] Typically, the horizontal extension of the second semiconductor regions 2, in the vertical cross-section, is larger than a horizontal extension of the trenches 50. Accordingly, each of the second semiconductor regions 2 borders adjacent semiconductor mesas 1b, and a narrowing of the controllable n-type current path is formed under each mesa 1b. This facilitates the reduction of the leakage current during the blocking mode. For example, a distance w2 between two adjacent second semiconductor regions 2, in the vertical cross-section, may be smaller than approximately 90%, more typically approximately 80%, of a horizontal extension w1 of the mesas 1b.

[0044] The horizontal extension w1 and the maximum doping concentration of the mesas 1b can be selected to adjust their resistance and the Miller capacitance of the semiconductor device 100. The gate-drain leakage current can also depend on the horizontal extension w1 and the maximum doping concentration of the mesas 1b, but is primarily adjustable by the ratio between the horizontal extension w1 of the mesas 1b and the distance w2 between two adjacent second semiconductor regions 2. The nominal blocking voltage of the semiconductor device 100 is primarily determined by the doping concentration of the drift layer 1a. Thus, the semiconductor device 100 can be optimized with respect to its operating conditions by appropriately selecting the doping concentration of the drift layer 1a, the horizontal extension w1, the maximum doping concentration of the mesas 1b, and the distance w2 between two adjacent second semiconductor regions 2.

[0045] Fig. Figure 2 illustrates a vertical cross section through a semiconductor device 200. The semiconductor device 200 is the device described above with reference to Fig. 1 and can also be operated as a MESFET. However, the semiconductor device 200 further comprises at least one trench 50' with a highly doped p-type or metallic contact region 4 extending between the front-side metallization 10 and the adjacent semiconductor regions 2' to provide ohmic contact between the second semiconductor regions 2' and the front-side metallization 10. Accordingly, the semiconductor device 200 comprises an integrated body diode 14 formed between the second semiconductor regions 2' and the drift layer 1a. Accordingly, device operation during an avalanche mode can be improved by providing a stable (non-destructive) current path for the avalanche mode.

[0046] Fig. 3 illustrates a vertical cross section through a semiconductor device 300. The semiconductor device 300 is the one described above with respect to Fig. 1 and can also be operated as a MESFET. For clarity, the drain layer (3) and the drain electrode (12) are shown in Fig. 3 is not shown. However, the semiconductor device 300 further includes an n-type current spreading layer 5 embedded in the drift layer 1a, 1c and having a higher maximum doping concentration than the drift layer 1a, 1c. Accordingly, the on-resistance of the semiconductor device 300 can be reduced. In the illustrated vertical cross-section, the current spreading layer 5 divides the drift layer 1a, 1c into an upper region 1a and a lower region 1c.

[0047] The current propagation layer 5 can also be structured, seen from above.

[0048] Fig. Figure 4 illustrates a vertical cross section through a semiconductor device 400. The semiconductor device 400 is the one described above with reference to Fig. 3 and can also be operated as a MESFET. However, the sidewalls 19 of the mesas 1b and vertical trenches 51 of the semiconductor device 400 are tapered. Accordingly, the fabrication of the semiconductor device 400 is typically facilitated. Typically, an angle α between the sidewalls 19 and the main surface 101 and the respective trench bottom 59 is greater than approximately 92° and less than approximately 105°.

[0049] Typically, the (mathematically) integrated doping concentration of the mesas 1b is essentially the same for all horizontal planes crossing the heterojunctions 18. Accordingly, the mesas 1b in the horizontal planes are depleted at the same blocking voltage.

[0050] Fig. Figure 5 illustrates a vertical cross section through a semiconductor device 500. The semiconductor device 500 is similar to the devices described above with respect to Fig. 1, Fig. 2 and can also be operated as a three-terminal transistor. For clarity, the drain layer 3 and the drain electrode 12 are shown in Fig. 5. However, the rectifier junctions 18 of the semiconductor device 500 are formed as heterojunctions. Similarly, as described above with reference to Fig. 2, one or more trenches 50' may be used to contact a respective second semiconductor region 2' forming a body diode 14 with the drift layer 1a, with the front-side metallization 10, in order to improve the device behavior during an avalanche mode. Furthermore, a current spreading layer 5 may additionally be formed beneath the drift layer 1a, as described above with reference to Fig. 3 explained.

[0051] The use of heterojunctions as rectifier junctions 18 also enables a device in which primarily only electrons contribute to the current during normal operation. To this end, the semiconductor material of the mesas 1b (and the drift layer 1a) typically has a band gap that is at least about 1 eV larger than the band gap of the semiconductor material of the p-type gate layers or gate regions 6 arranged in the trenches 50. For example, the mesas 1b and the drift layer 1a may be made of SiC, e.g., 4H-SiC, and the gate regions 6 may be made of silicon or germanium, typically polysilicon (poly-Si), to facilitate manufacturing. For the same reason, the p-type contact region 4 in the trench 50' is also typically made of silicon or germanium, more typically poly-Si.

[0052] For 4H-SiC / Si heterojunction diodes with a p+ -Zone of Si (low band gap material) forming a heterojunction with an n - -zone of 4H-SiC, the following properties are known. The breakdown voltage is approximately the same for the same doping concentrations compared to a homojunction pn-SiC diode. The leakage current is comparable to a Schottky diode. For example, the leakage current of these heterojunction diodes can be approximately 2 × 10 -5 A / cm 2 at a reverse bias of about 1000 V for a diode with a nominal blocking voltage of 1600 V. During forward bias, no holes are formed in the n - -zone. Similar to Schottky diodes, the electron current is injected from the p + -zone. Furthermore, the density of electrons in the p + -zone at the heterojunction (pn junction) can be tuned by the voltage drop across the heterojunction. Similar to bipolar diodes, the electrons of the pn +-zone at the pn junction during a reverse bias of 100 V about 10 7 cm -3 and at a forward bias of 1.2 V about 10 10 cm -3 (at given doping concentrations of 10 20 cm -3 for the p + -Zone (6) and 10 16 cm -3 for the n - -zone (1b)). Similar device behavior is expected for other wide bandgap / narrow bandgap heterojunction diodes, such as GaN / Si heterojunction diodes or SiC / Ge heterojunction diodes.

[0053] Accordingly, similar device characteristics are available for the semiconductor device 500 and the device described above with reference to Fig. 1 to 4 explained semiconductor devices.

[0054] The semiconductor devices 100 to 500 described above with reference to Fig. 1 to 5 have in common that they comprise a semiconductor body 40 which extends to a main surface 101 and comprises, in a vertical cross-section: a drift layer 1a of a first conductivity type; one or more semiconductor mesas 1b of the first conductivity type, each of which adjoins the drift layer 1a, extends substantially to the main surface 101 and has two sidewalls 19 on which a rectifier junction 18 is formed; and two or more second semiconductor regions 2 forming respective pn junctions at least with the drift layer 1a, such that each sidewall 19 is arranged adjacent to, typically adjoins, one of the second semiconductor regions 2.

[0055] The rectifier junctions 18 may be pn heterojunctions as described above with reference to Fig. 5 explained.

[0056] To avoid high electric fields near the edges between the trench bottom walls 59 and the adjacent side walls 19, the edges may be rounded.

[0057] According to embodiments, similar semiconductor devices as described above with reference to Fig. 3 to 5, the current spreading layer 5 is used to improve the on-state resistance, but without the second semiconductor regions being provided. The semiconductor body 40 of these semiconductor devices also extends to a main surface 101 and comprises, in a vertical cross-section: a drift layer 1a of a first conductivity type; one or more semiconductor mesas 1b of the first conductivity type, each of which adjoins the drift layer 1a, extends substantially to the main surface 101, and has two sidewalls 19 on which a respective rectifier junction 18 is formed; and a current spreading layer 5 of the first conductivity type, which is embedded in the semiconductor body 40, in ohmic contact with the drift layer 1a, which is arranged below the one or more semiconductor mesas 1b, and which has a maximum doping concentration higher than the drift layer 1a.

[0058] The semiconductor devices explained herein have in common that their semiconductor body 40 extends to a main surface 101 and, in a vertical cross-section substantially orthogonal to the main surface 101, comprises: a first semiconductor region 1 of a first conductivity type and made of a first semiconductor material and at least two trenches 50, 51 extending from the main surface 101 partially into the first semiconductor region 1. Accordingly, the first semiconductor region 1 comprises a drift layer 1a and one or more adjacent semiconductor mesas 1b, each of which is arranged between a pair of adjacent trenches 50, 51 of the at least two trenches 50, 51. Each of the at least two trenches 50, 51 has, in vertical cross-section, at least one sidewall 19, typically two sidewalls 19, which may be tapered, and a bottom wall 59.On a lower region of the at least one sidewall 19 of each of the at least two trenches 50, 51, a rectifier junction 18 is formed, typically either by a Schottky layer 8, each forming a Schottky contact with the first semiconductor region 1 and one of the semiconductor mesas 1b, or by a semiconductor layer 6 of a second semiconductor material, each forming a heterojunction with the first semiconductor region 1 and one of the semiconductor mesas 1b. In vertical cross-section, the semiconductor body 40 further comprises an embedded current spreading layer 5 of the first conductivity type, arranged beneath the at least two trenches 50, 51, and / or at least two second semiconductor regions 2 of a second conductivity type.The embedded current spreading layer 5 is in ohmic contact with the first semiconductor region 1 and has a maximum doping concentration that is higher than a maximum doping concentration of the first semiconductor region 1. Each of the at least two second semiconductor regions 2 forms a pn junction with the first semiconductor region 1, typically at least with the drift layer 1a, and adjoins the bottom wall 59 of one of the at least two trenches 50, 51.

[0059] The rectifier junction 18 is typically formed on both of the sidewalls 19 of one or more of the at least two trenches 50, 51, more typically on both of the sidewalls 19 of a plurality of the at least two trenches 50, 51.

[0060] In one or more of the at least two trenches 50', the rectifier junction 18 can be formed only on one of the side walls 19, whereas on the other side wall 19 a highly conductive contact region 4 is formed, which, for example as a metal region, cannot form a rectifier junction 18 with the first semiconductor region 1 or the semiconductor mesa 1b.

[0061] In other embodiments, the highly conductive contact region 4 also forms a rectifier junction 18 with the semiconductor region 1 or the semiconductor mesa 1b. For example, the first semiconductor region 1 may be made of monocrystalline n-type SiC, the at least two second semiconductor regions 2 may be made of monocrystalline p-type SiC, and the contact region 4 may be made of a highly doped polycrystalline p-type Si in order to contact one of the at least two second semiconductor regions 2.

[0062] With reference to Fig. 6 to 8, process steps of a method for forming a semiconductor device are illustrated in respective vertical cross sections through a semiconductor body or semiconductor wafer 40.

[0063] In a first step, a wafer 40, for example, a SiC wafer, is provided, extending between a main surface 101 and a rear surface 102 arranged opposite the main surface 101. The wafer 40 may comprise a conductive substrate 3 extending to the rear surface 102 and one or more epitaxial layers of the first conductivity type forming a first semiconductor layer 1 on the conductive substrate 3 and extending to the main surface 101.

[0064] Furthermore, an embedded current spreading layer 5 can be formed in the first semiconductor layer 1. The current spreading layer 5 can be formed by a masked implantation of dopants of the first conductivity type into the first semiconductor layer 1 or by the deposition of an additional, more highly doped layer, e.g., by epitaxy.

[0065] Thereafter, a hard mask 15 can be formed on the main surface 101. The resulting semiconductor structure 400 is shown in Fig. 6. Forming the hard mask 15 typically includes forming a hard mask layer on the main surface 101, forming a resist mask on the hard mask layer, at least once exposing the hard mask layer to light through the resist mask, removing the mask, and etching the hard mask layer. By using more than one exposure of the hard mask layer to light, smaller structures can be formed in the hard mask.

[0066] In the exemplary embodiment, the current spreading layer 5 divides the first semiconductor layer 1 into an upper region 1ab and a lower region 1c. The upper region 1ab may include an uppermost semiconductor layer extending to the main surface 101 and a lower semiconductor layer extending between the uppermost semiconductor layer and the current spreading layer 5. The uppermost semiconductor layer and the lower semiconductor layer may have substantially the same or different maximum doping concentrations, which can be adjusted in accordance with device characteristics. Regions of the uppermost semiconductor layer typically form mesas or channel regions in the semiconductor device to be fabricated.

[0067] The hard mask 15 is subsequently used to etch trenches and may have tapered sidewalls (flanks) for adjusting an angle between the main surface 101 and the sidewalls of the trenches. The hard mask 15 may be an oxide mask or a metal mask, made, for example, of nickel or a nickel alloy. If the hard mask 15 is a metal mask, the mask 15 may form source contacts in the semiconductor device to be fabricated, as indicated by reference numeral 10a of the second region from the left of the hard mask 15.

[0068] Thereafter, trenches 51 can be etched using the hard mask 15. Typically, a chemical dry etching process is used to form a plurality of trenches 51 with respective sidewalls 19 and bottom walls 59. This forms a plurality of semiconductor mesas 1b, each of which is arranged between adjacent trenches 51.

[0069] A high-temperature anneal in a hydrogen atmosphere can be used to round edges between the sidewalls 19 and the bottom walls 59. Accordingly, high electric fields can be avoided during the blocking mode of the semiconductor device being fabricated. For example, the wafer can be annealed for about 0.4 hours to about 2 hours in a temperature range of about 1600°C to about 1800°C.

[0070] Thereafter, second semiconductor regions 2 of a second conductivity type may be formed in the first semiconductor layer 1, such that the bottom wall 59 of each of the trenches 51 adjoins one of the second semiconductor regions 2. This typically involves implanting dopants of the second conductivity type through the bottom walls 59 and subsequent curing.

[0071] Due to the presence of the second semiconductor regions 2, the electric field strength formed during the blocking mode near the rectifier junctions to be formed on the sidewalls 19 and adjacent to the bottom walls 59 can be reduced. Thus, the leakage current can be reduced. The resulting semiconductor structure 400 is shown in Fig. 7. For clarity, the semiconductor regions under the current spreading layer 5 are shown in Fig. 7 is not shown. The current spreading layer 5 and the formation of the current spreading layer 5 are optional embodiments that include the formation of the second semiconductor regions 2.

[0072] In the exemplary embodiment shown in Fig. As illustrated in Figure 7, the mesas 1b are formed as symmetric trapezoids with tapered sidewalls 19. Typically, an angle α between the sidewalls 19 and the main surface 101 or the bottom walls 59 is greater than about 92°. Accordingly, the subsequent formation of rectifier junctions on the sidewalls 19 is facilitated.

[0073] Thereafter, more highly doped source contact regions 11 of the first conductivity type may be formed in the mesas 1b and on the main surface 101, for example, by implantation, and source contacts 10a may be formed on the mesas 1b. In other embodiments, the source contact regions 11 are formed prior to the formation of the hard mask 15 used to etch the trenches 51, and / or the hard mask 15 is used as source contacts.

[0074] Thereafter, rectifier junctions 18 can be formed on the sidewalls 19 of the trenches 51. The resulting semiconductor structure 400 is shown in Fig. 8. This may include the formation of heterojunctions or a heterojunction formation layer on the sidewalls 19. The rectifier junction 18 may be formed, in one or more of the trenches 51, only on one of the two sidewalls 19, whereas on the other sidewall 19 a highly conductive contact region (in Fig. 8 not shown) which, for example as a metal region, cannot form a rectifier junction 18 on the respective side wall 19.

[0075] The formation of heterojunctions can be achieved by depositing a semiconductor material of a second conductivity type with a lower band gap than the mesas 1b, typically at least 1 eV lower, such as silicon or germanium, and then etching back. The heterojunctions are typically formed between the mesas 1b and a deposited non-monocrystalline semiconductor material, e.g., doped poly-Si, using a suitable PVD (physical vapor deposition) process. Accordingly, mechanical stress resulting from the heterojunction between the mesas 1b and the gate regions formed in the trenches 51 is at least substantially reduced. After deposition, the trenches 51 are typically filled without voids. After etching back, respective uppermost regions of the trenches 51 can be filled with a dielectric region disposed on the respective gate regions.Completely filling the trenches 51 facilitates the later formation of a front side metallization, gate contacts and a gate metallization on the main surface 101.

[0076] Finally, a drain metallization may be formed opposite the front side metallization and on the conductive substrate 3, forming a drain region. The resulting semiconductor device is similar to that described above with reference to Fig. 5, but has tapered side walls 19. To form an integrated body diode, as in Fig. 5, one or more of the trenches 51 may be masked prior to etching back, and the dielectric regions may be deposited.

[0077] In the Fig. In the exemplary alternative embodiment illustrated in FIG. 8, Schottky contact formation layers 8 are formed on the sidewalls 19. This typically involves a PVD process for depositing a layer of a Schottky metal (Schottky metal layer), such as titanium. The Schottky metal layer is typically removed at and adjacent to the main surface 101. This can be achieved by an oxide lift-off process or masked etching.

[0078] Thereafter, a conductive layer of highly doped poly-Si or a metal having a higher electrical conductivity than the Schottky contact forming layer 8 may be formed on the Schottky contact forming layer 8.

[0079] Thereafter, the remaining areas of the trenches 51 can be filled substantially void-free with respective dielectric regions 9 arranged between the main surface 101 and the Schottky contact formation layers 8.

[0080] Thereafter, a front side metallization 10 can be formed in ohmic contact with the first semiconductor layer 1 on the main surface 101.

[0081] Thereafter, a drain metallization 12 may be formed opposite the front side metallization 10 and in ohmic contact with the first semiconductor layer 1. The resulting semiconductor device 400 is shown in Fig. 4 illustrates.

[0082] To integrate a body diode 14 and a contact region 4 to provide ohmic contact with the front side metallization 10 as described above with reference to Fig. 2, a highly conductive layer, for example, made of highly doped poly-Si of the second conductivity type or a metal, may be formed on one or more sidewalls 19 instead of the Schottky contact formation layers 8. Alternatively, forming the contact regions 4 comprises implanting dopants of the second conductivity type through respective sidewalls 19.

[0083] The above with reference to Fig. The methods explained in Figures 6 to 8 enable reliable adjustment of device parameters such as on-resistance, leakage current, switching losses, and / or parasitic device capacitances such as the Miller capacitance. Furthermore, the formation of the front-side metallization 10 is facilitated because a substantially flat surface can be provided prior to the deposition of the front-side metallization 10.

[0084] According to one embodiment of a method for manufacturing a field-effect semiconductor device, the method comprises: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partially into the first semiconductor layer such that each of the at least two trenches comprises, in a vertical cross-section substantially orthogonal to the main surface, a sidewall and a bottom wall, and that a semiconductor mesa is formed between the sidewalls; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer such that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifier junction on the sidewall of at least one of the at least two trenches.

[0085] Spatially-referenced terms such as "below," "beneath," "lower," "above," "upper," and the like are used for convenience of description to explain the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the device in addition to orientations other than those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Throughout the description, similar terms refer to similar elements.

[0086] The terms "having," "containing," "including," "comprising," and the like, as used herein, are open-ended expressions that indicate the presence of specified elements or characteristics, but do not preclude additional elements or characteristics. The articles "a" and "an" and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

Claims

[1] A field-effect semiconductor device comprising: - a semiconductor body (40) having a main surface (101) and comprising, in a vertical cross-section orthogonal to the main surface (101): - a drift layer (1a) of a first conductivity type; - a semiconductor mesa (1b) of the first conductivity type, adjacent to the drift layer (1a), extending to the main surface (101) and comprising a first sidewall, wherein a rectifier junction (18) is formed on the first sidewall; and - two second semiconductor regions (2) of a second conductivity type arranged adjacent to the semiconductor mesa (1b), each of the two second semiconductor regions (2) forming a pn junction at least with the drift layer (1a); and - a gate metallization in ohmic contact with a non-monocrystalline semiconductor material (6) of the second conductivity type, which forms the rectifier junction (18) as a heterojunction. [2] A field effect semiconductor device according to claim 1, wherein the semiconductor mesa (1b) further comprises a second sidewall, and another rectifier junction (18) is formed on the second sidewall. [3] A field effect semiconductor device according to any one of claims 1 to 2, wherein each of the two second semiconductor regions (2) is adjacent to the semiconductor mesa (1b). [4] Field effect semiconductor device according to one of claims 1 to 3, wherein the semiconductor mesa (1b) is centered, in vertical cross section, with respect to the two second semiconductor regions (2). [5] A field effect semiconductor device according to any one of claims 2 to 4, wherein a distance between the first sidewall and the second sidewall of the semiconductor mesa (1b) is greater than a distance between the two second semiconductor regions (2). [6] A field effect semiconductor device according to any one of claims 1 to 5, wherein an angle between the main surface (101) and the first side wall is greater than 92°. [7] A field effect semiconductor device according to any one of claims 1 to 6, wherein the semiconductor body (40) comprises, in vertical cross section, a plurality of semiconductor mesas (1b). [8] A field effect semiconductor device according to claim 7, wherein, in vertical cross section, a void-free filled vertical trench is arranged between each pair of adjacent semiconductor mesas (1b) of the plurality of semiconductor mesas (1b). [9] A field effect semiconductor device according to any one of claims 1 to 8, wherein the drift layer (1a) has a first maximum doping concentration, the field effect semiconductor device further comprising at least one of: - a current spreading layer (5) of the first conductivity type, which is embedded in the semiconductor body (40), is in ohmic contact with the drift layer (1a), and comprises a maximum doping concentration which is higher than the first maximum doping concentration; - a drain layer (3) of the first conductivity type, which extends to a rear surface of the semiconductor body (40) arranged opposite the main surface (101) and is in ohmic contact with the drift layer (1a), wherein the drain layer has a maximum doping concentration which is higher than the first maximum doping concentration; - a drain metallization (12) adjacent to the drain layer; - a source contact (10a) arranged on the main surface (101) and in ohmic contact with the semiconductor mesa (1b); - a front-side metallization (10) arranged on the main surface (101) to contact the source contact; - a contact region (4) of the second conductivity type in ohmic contact with the front-side metallization and one of the two second semiconductor regions (2); and - a dielectric region (9) extending from the main surface (101) into the semiconductor body (40) and adjoining at least one of the semiconductor mesas (1b), the non-monocrystalline semiconductor material, the front-side metallization, and one of the two second semiconductor regions (2). [10] A field effect semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is a substantially unipolar semiconductor device. [11] A method of forming a field-effect semiconductor device, comprising: - providing a wafer (40) comprising a main surface (101) and a first semiconductor layer of a first conductivity type; - forming at least two trenches (50, 51) from the main surface (101) partially into the first semiconductor layer, such that each of the at least two trenches (50, 51) comprises a side wall and a bottom wall in a vertical cross-section orthogonal to the main surface (101), and that a semiconductor mesa (1b) is formed between the side walls of the at least two trenches (50, 51); - forming at least two second semiconductor regions (2) of a second conductivity type in the first semiconductor layer, so that the bottom wall of each of the at least two trenches (50, 51) adjoins one of the at least two second semiconductor regions (2); - forming a rectifier junction (18) on the side wall of at least one of the at least two trenches (50, 51); and - forming a gate metallization in ohmic contact with a non-monocrystalline semiconductor material (6) of the second conductivity type, which forms the rectifier junction (18) as a heterojunction. [12] The method of claim 11, wherein providing the wafer (40) comprises at least one of: - providing a silicon carbide wafer (40); - providing the wafer (40) as a wafer (40) further comprising an embedded current spreading layer of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the first semiconductor layer; - Providing a substrate of the first conductivity type; - forming an epitaxial layer of the first conductivity type on the substrate; - forming a mask on the epitaxial layer; - implanting dopants of the first conductivity type into a layer of the epitaxial layer; - Removing the mask; and - forming another epitaxial layer of the first conductivity type on the epitaxial layer. [13] The method of claim 11 or 12, wherein forming the at least two trenches (50, 51) comprises at least one of: - forming a hard mask, comprising forming a hard mask layer on the main surface (101), forming a resist mask on the hard mask layer and at least once exposing the hard mask layer to light through the resist mask; - forming a metal mask; - masked etching such that an angle between the bottom wall and the side wall of at least one of the at least two trenches (50, 51) is greater than 92°; and - thermal annealing. [14] The method of any one of claims 11 to 13, wherein the first semiconductor layer comprises a first semiconductor material, and wherein forming the rectifier junction (18) comprises at least one of: - a PVD process; - Deposition of polysilicon; - filling the at least two trenches (50, 51) with a second semiconductor material which forms the heterojunction with the semiconductor mesa (1b); - partial etching back of the second semiconductor material. [15] The method of any one of claims 11 to 14, wherein forming the at least two second semiconductor regions (2) comprises implanting dopants of the second conductivity type through the bottom walls of the at least two trenches (50, 51). [16] A method according to any one of claims 11 to 15, further comprising at least one of: - forming a dielectric region at least in an upper region of at least one of the at least two trenches (50, 51); - forming a front-side metallization on the main surface (101) in ohmic contact with the first semiconductor layer; - forming a contact region of the second conductivity type in ohmic contact with the front-side metallization and one of the at least two second semiconductor regions (2); and - Forming a drain metallization opposite the front side metallization and in ohmic contact with the first semiconductor layer.

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