Method for forming an integrated circuit structure

Abstract

Method for forming an integrated circuit structure, the method comprising: - Providing a substrate; - Formation of a first dielectric layer (102) over the substrate; - Forming conductive components (104) in the first dielectric layer (102), wherein the conductive components (104) comprise a copper conductor; - Forming a second dielectric layer (108) over the first dielectric layer (102) with the conductive components (104); - Treating a surface of the second dielectric layer (108) to form a hydrophobic high-density monolayer along the surface of the second dielectric layer (108), wherein the high-density monolayer (109) has a higher density than the dielectric layer, wherein, in forming the high-density monolayer (109), terminal OH groups of the dielectric layer are replaced by Si(CH3)3 groups, and forming an anti-reflective coating layer (114) over the high-density monolayer; - after treating the surface, structuring the second dielectric layer (108) and the high-density monolayer (109) to form openings (230, 232); - Forming a conductive material (330) in the openings (230, 232) of the second dielectric layer (108), and removing excess conductive material from the surface of the second dielectric layer (108) by applying a chemical-mechanical polishing process, whereby Cu2+ / Cu+ residues are reduced or eliminated due to the hydrophobic properties of the surface of the second dielectric layer (108).

Description

BACKGROUND

[0001] In integrated circuit technology, a common method for forming interconnect structures that include metal conductors and vias is known as the "Damascene" process. Generally, this process involves creating an opening in a dielectric layer that separates vertically spaced metallized layers. The opening is typically formed using lithographic and etching techniques. Once formed, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by chemical-mechanical polishing (CMP). The remaining copper or copper alloys form vias and / or metal conductors.

[0002] Copper is commonly used in Damascene structures due to its low resistivity. A typical interconnect structure is formed by multiple metallized layers, each containing several copper conductors. Copper conductors in different metallized layers are connected to each other via vias. While copper is generally preferred for its electrical properties, other materials can also be used.

[0003] US 2006 / 0202311 A1 discloses a low-k dielectric stack with an effective dielectric constant k of about 3.0 or less, the mechanical properties of which are improved by the incorporation of at least one nanolayer. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the layers in the stack and without requiring any post-treatment steps for the dielectric stack according to the invention. Specifically, the disclosure describes a low-k dielectric stack comprising at least one low-k dielectric material and at least one nanolayer contained therein.

[0004] US 2007 / 0190777 A1 discloses barrier layers and methods for forming barrier layers on a porous layer. The methods include the chemical adsorption of several first molecules onto the surface of the porous layer in a chamber and the formation of a first layer of these first molecules on the surface of the porous layer. Subsequently, a plasma can be used to react several second molecules with the first layer of these first molecules to form a first layer of a barrier layer. The barrier layers can close the pores of the porous material, act as a diffusion barrier, be conformal, and / or have a negligible effect on the overall ILD k value of the porous material.

[0005] US 2007 / 0077782 A1 discloses a method and a system for treating a dielectric film in a batch process system, comprising the treatment of at least one surface of the dielectric film with a treatment compound, including a CxHy-containing compound, where x and y are integers greater than or equal to one. The multiple wafers are heated during the introduction of the treatment compound. The dielectric film may be a film with a low dielectric constant, with or without pores, in which an etch feature forms after dry etching.

[0006] US 2003 / 0049460 A1 discloses organofluorosilicate glass films containing both organic and inorganic fluorine compounds, but no significant amounts of fluorocarbons. Preferred films are represented by the formula SivOwCxHyFz, where v + w + x + y + z = 100%, v = 0.01 atomic percent, w = 0.01 atomic percent, y = 0.01 atomic percent, x = 0.01 atomic percent, z = 0.01 atomic percent, and x / z is optionally larger than . The fluorine is practically unbound to carbon. A CVD process comprises: (a) providing a substrate in a vacuum chamber; (b) introducing gaseous reagents into the vacuum chamber, including a fluorine gas, an oxygen gas, and at least one precursor gas selected from an organosilane and an organosiloxane; and (c) applying energy to the gaseous reagents in the chamber to induce a reaction of the gaseous reagents and to form the film on the substrate.

[0007] US 2003 / 0198895 A1 discloses a method for passivating silicon oxide-based low-k materials using a supercritical carbon dioxide passivation solution with a silylating agent. The silylating agent is preferably an organosilicon compound with five carbon atoms, such as hexamethyldisilazane (HMDS) and chlorotrimethylsilane (TMCS), as well as combinations thereof. According to embodiments of the disclosure, the silicon oxide-based low-k material is maintained at temperatures in the range of 10 to 15 °C, preferably at about 15 °C, and pressures in the range of 10 to 15 psi, preferably at about 15 psi, while exposed to the supercritical passivation solution. According to further embodiments of the disclosure, a silicon oxide-based low-k material is simultaneously purified and passivated with a supercritical carbon dioxide cleaning solution.

[0008] The invention is defined in the claims. BRIEF DESCRIPTION OF THE FIGURES

[0009] For a more comprehensive understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the subsequent figures, which show: Fig. 1-4 different intermediate states in the fabrication of a semiconductor device according to one embodiment; and Fig. 5 a flowchart showing a method for forming a semiconductor device according to one embodiment. DETAILED DESCRIPTION OF EXAMPLES

[0010] Methods for forming metallic components in the metallized layers of integrated circuits are provided. The intermediate stages of fabricating embodiments according to the present invention are illustrated. In the different views and exemplary embodiments of the invention, similar reference numerals are used to designate similar elements.

[0011] The Fig. Figures 1-4 show various intermediate states of a method for forming a semiconductor device according to one embodiment. First, reference is made to Fig. Figure 1 shows a wafer 100 with a first dielectric layer 102 formed on it. The wafer 100 may have a substrate (not shown in detail) beneath the first dielectric layer 102, and may, for example, be doped or undoped bulk silicon or an active layer of a semiconductor-on-insulator (SOI; also: semiconductor on an insulator) substrate. In general, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may, for example, be a buried oxide layer (BOX) or a silicon oxide layer. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.

[0012] In one embodiment, electrical circuits are formed on the substrate, and these circuits can be of any type suitable for a particular application. In another embodiment, the electrical circuits include electrical devices formed on the substrate, with one or more dielectric layers covering the electrical devices. Metal layers can be formed between superimposed dielectric layers, as described here, to conduct electrical signals between the electrical devices. Electrical devices can also be formed within one or more dielectric layers.

[0013] For example, the electrical circuits may include various N-channel metal-oxide semiconductor (NMOS) and / or P-channel metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, diodes, photodiodes, fuses, or the like, interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distributors, input / output circuits, or the like. Anyone with normal technical knowledge will understand that the above examples are given for purely illustrative purposes, merely to further explain applications of some of the exemplary designs, and are not intended to limit the disclosure in any way. Other circuits or interconnects may be used depending on the requirements of a particular application.

[0014] The first dielectric layer 102 can, for example, be made of a low-K dielectric (materials with a lower dielectric constant than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiO₂ x C y These materials may include spin-on glass or rotationally coated glass, spin-on polymers or rotationally coated polymers, silicon-carbon materials, mixtures thereof, composite materials thereof, combinations thereof, or the like, which can be produced by any suitable process, such as rotation, chemical vapor deposition (CVD), or plasma-enhanced electrical vapor deposition (PECVD). Other materials, such as ultra-low-k materials (i.e., with a dielectric constant less than approximately 2.9, such as k = 2.5–2.6), may also be used. These materials and processes are given as examples, and other materials and processes may be used.

[0015] Also in Fig. Figure 1 shows conductive components 104 formed in the first dielectric layer 102. These conductive components 104 can be formed, for example, by creating openings in the first dielectric layer using photolithography techniques. Generally, photolithography techniques involve applying a photoresist material (not shown) and exposing the photoresist material according to a predetermined pattern. The photoresist material is then developed to remove a portion of it, thereby exposing the underlying material according to the predetermined pattern. The remaining photoresist material protects the underlying material from subsequent process steps, such as etching, which are performed to create the openings in the first dielectric layer 102 in which the conductive components 104 are to be formed.The etching process can be wet or dry, anisotropic or isotropic, such as an anisotropic dry etching process. After the opening is formed in the first dielectric layer 102, a conductive material can be inserted to fill the opening. The conductive components 104 can include metals, elemental metals, transition metals, or the like, such as a copper conductor. Furthermore, the conductive components 104 can include one or more barrier / adhesive layers.

[0016] Optionally, according to one embodiment, an etch stop layer (ESL) 106 is located above the first dielectric layer 102 and the conductive component 104. In general, the etch stop layers provide a mechanism for stopping an etching process when vias and / or contacts are formed. The etch stop layers are formed by a dielectric material that has a different etch selectivity than adjacent layers, i.e., than the underlying first dielectric layer 102 or the substrate. In one embodiment, etch stop layers can be formed from SiN, SiCN, SiCO, CN, combinations thereof, or the like, deposited by CVD or PECVD techniques.

[0017] According to one embodiment, a second dielectric layer 108 is located above the ESL 106. As described in detail below, the second dielectric layer 108 is the layer that is subsequently structured to form, for example, conductive traces and / or vias. For example, the second dielectric layer 108 can be structured to form vias extending to the conductive components 104 and to create conductive traces for connecting different electrical components.

[0018] The second dielectric layer 108 can be formed using similar methods and materials as those used to form the first dielectric layer 102; however, other materials and methods can also be used. Additionally, the first dielectric layer 102 can be formed from the same or a different material than that used to form the second dielectric layer 108.

[0019] It should be noted that the first dielectric layer 102 and the conductive components 104 are shown for illustrative purposes. In other embodiments, the first dielectric layer 102 may be replaced by a semiconductor substrate with or without the ESL 106. For example, in another embodiment, the second dielectric layer 108 (the layer to be structured) is an intermediate dielectric layer formed above a substrate with electrical devices formed on it. In this embodiment, the optional ESL 106 may, for example, be a silicon nitride contact etch stop / voltage layer formed above transistors formed on the substrate. The second dielectric layer 108 is subsequently structured to form connections to the electrical devices, such as a connection from a source or drain to a transistor.

[0020] In one embodiment, a process is carried out on the exposed surface of the second dielectric layer 108 to form a hydrophobic surface or to reduce the hydrophilicity of the surface. Fig. Figure 1 shows an embodiment in which a high-density monolayer 109 is formed above the second dielectric layer 108. The high-density monolayer 109 can be formed, for example, using hexamethyldisilazane (HMDS), trimethylsilyldiethylamine (TMSDEA), or trimethylsilyl acetate (OTMSA). The high-density monolayer 109 has a higher density than the density of the underlying second dielectric layer 108. In general, low-k dielectrics have a density of about 0.9 g / cm³. 3 up to approximately 1.4 g / cm³ 3 . For example, if the second dielectric layer 108 is made of a material with a density of approximately 1.0 g / cm³ 3 If the high-density monolayer 109 is formed, then it has a higher density than 1.0 g / cm³.3 .

[0021] In one embodiment, the second dielectric layer 108 can be treated with HMDS by positioning the wafer in a process chamber and exposing the second dielectric layer 108 to an HMDS vapor at a temperature of 90°C or higher (e.g., from approximately 90°C to approximately 180°C) for approximately 20 to approximately 40 minutes, for example, for approximately 30 minutes. The HMDS vapor can be pure HMDS vapor or HMDS vapor diluted with toluene, benzene, or the like, such that an HMDS concentration of approximately 5% to approximately 10% is achieved at a partial pressure of approximately 10 mmHg to approximately 30 mmHg. The process chamber can also have a low O2 concentration, such as a partial pressure of approximately 0.0013 mbar. After immersion in the HMDS solution, a cleaning procedure can also be carried out, such as rinsing with deionized water, rinsing with isopropyl alcohol (IPA), rinsing with acetone and / or the like, to remove non-reacted parts.

[0022] In another embodiment, the second dielectric layer 108 is treated with TMSDEA by immersing the wafer in a bath of a dilute TMSDEA solution at a temperature of 90 °C or higher (i.e., between approximately 90 °C and approximately 180 °C) and treating it for approximately 20 to 40 minutes, for example, for approximately 30 minutes. The process chamber can also have a low O2 concentration, for example, a partial pressure of approximately 0.0013 mbar. After immersion in the TMSDEA solution, a cleaning procedure can be performed, such as rinsing with deionized water, rinsing with isopropyl alcohol (IPA), rinsing with acetone, and / or the like, to remove unreacted components.

[0023] In another embodiment, the second dielectric layer is treated with OTMSA by immersing the wafer in a bath of a dilute OTMSA solution at a temperature of 90 °C or higher (i.e., between approximately 90 °C and approximately 180 °C) and treating it for approximately 20 to 40 minutes, for example, approximately 30 minutes. The process chamber can also have a low O2 concentration, for example, a partial pressure of approximately 0.0013 mbar. After immersion in the OTMSA solution, a cleaning procedure can be performed, such as rinsing with deionized water, rinsing with isopropyl alcohol (IPA), rinsing with acetone, and / or the like, to remove unreacted components.

[0024] In such designs, the terminal OH groups are replaced by Si(CH3)3 groups, resulting in a high-density monolayer. A subsequent CMP process will regularly lead to Cu2+ / Cu+ deposits on the surface of the underlying layer, causing problems with time-dependent dielectric breakdown (TDDB) and breakdown voltage (VBD). This is particularly problematic at smaller technology nodes, such as those at 20 nm and below, where the interconnect pitch size decreases.

[0025] Fig. Figure 1 further shows a structured mask 110 for use in a subsequent etching process. In one embodiment, the structured mask 110 comprises a photoresist material applied to the second dielectric layer 108. After the photoresist material has been applied, exposed, and developed to reveal a surface of the underlying layer, as shown in Figure 1, the following steps are taken: Fig. 1 shown.

[0026] A hard mask layer 112 can be used to support the subsequent etching process. Generally, a hard mask layer 112 is formed from a material that has a lower etch rate than the underlying material to be etched. For example, the hard mask layer 112 may be formed from silicon nitride if the second dielectric layer 108 to be structured is formed from silicon oxide. In this situation, the silicon nitride of the hard mask layer 112 has a lower etch rate than the silicon oxide of the second dielectric layer 108, so the hard mask layer 112 can act as a mask for etching the second dielectric layer 108. It should be noted that the hard mask layer 112 can comprise multiple layers. The hard mask layer 112 has a thickness sufficient, based on the materials and etchants used, to provide protection during etching.In one embodiment, the hard mask layer 112 is formed with a thickness between approximately 20 nm and approximately 60 nm.

[0027] Optionally, an anti-reflective coating (ACR) layer 114 can be applied over the high-density layer 109 to facilitate a subsequent photolithographic process for structuring the overlying layer, such as the structured mask 110. During the subsequent photolithographic process, the ACR layer 114 prevents radiation from being reflected from underlying layers and interfering with the exposure process. Such interference can increase the critical dimensions of the photolithographic process. The ACR layer 114 can be composed of SiON, a polymer, or a combination thereof, and can be formed by CVD, a spin-on process, or a combination thereof. The thickness of the ACR layer 114 is sufficient, based on the materials and wavelengths, to provide adequate anti-reflective properties.In one embodiment, the ARC layer 114 is formed with a thickness between approximately 20 nm and approximately 100 nm.

[0028] Fig. Figure 2 shows a wafer 100 after one or more structuring steps for structuring the second dielectric layer 108 according to one embodiment. The structure of the structured mask 110 (see Figure 2) is shown in Figure 2. Fig. 1) is transferred to the underlying layers. The structure shown here is for illustrative purposes only. Patterning can include the formation of traces, vias, traces and vias, or other components, and may include dual-damascene patterning techniques such as via-first patterning and / or trench-first patterning. The techniques described here can also be used with dual-damascene patterning techniques. Some patterning techniques, such as dual-damascene and dual-damascene techniques, use multiple photoresist layers.

[0029] This example shows Fig. Two trench openings 230 and via openings 232 are formed in the second dielectric layer 108. In the subsequent processing, the trench openings 230 and the via openings 232 are filled with conductive material. The shallower trench openings 230 form conductor tracks, and the via openings 232 form conductive vias for connecting metallized layers.

[0030] As a result of the etching steps, the structured mask 110 and / or the hard mask layer 112 and / or the ARC layer 114 are produced (see below). Fig. 1) partially or completely consumed. Fig. Figure 2 shows a version in which part of the hard mask layer 112 remains. Optionally, remaining parts of the structured mask 110 and / or the hard mask layer 112 can be removed.

[0031] Fig. 3 represents the filling of the trench openings 230 and the through-connection openings 232 (see Fig. 2) comprising a conductive material 330 according to one embodiment. The conductive material 330 can be deposited by CVD, electroplating, chemical reduction, electroless electroplating, ALD, or PVD, and can be made of copper, although alternatively other suitable materials such as aluminum, tungsten, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of the aforementioned, combinations thereof, or the like may be used. The conductive material 330 is deposited into the trench openings 230 and the via openings 232, the deposition being continued until the conductive material 330 fills the trench openings 230 and the via openings 232 and extends over the hard mask layer 112 (if present).

[0032] Optionally, one or more barrier / adhesive layers (not shown) can be formed along the sidewalls of the trench openings 230 and the via openings 232 before the conductive material 330 is formed. In such embodiments using a conductive copper material, a barrier layer may be desirable to limit diffusion of the copper into the adjacent dielectric materials. In one embodiment, the barrier layer may be formed from one or more layers of titanium nitride, titanium, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other precious metals, other high-melting-point metals, their nitride compounds, combinations thereof, or the like. The barrier layer may be formed by chemical vapor deposition, although alternatively other techniques, such as PVD or ALD, may be used.

[0033] Fig. Figure 4 shows the removal of excess portions of the conductive material 330 according to one embodiment. In one embodiment, the excess conductive material 30 (and an optional barrier / adhesive layer) formed above the hard mask layer 112 is removed by means of a planarization process, such as a chemical-mechanical polishing (CMP) process. Remaining portions of the ARC layer 114 can also be removed during this planarization process.

[0034] Further processes can then be carried out to complete the manufacturing process. For example, it shows Fig. 4. Another dielectric layer 420 is formed above the high-density monolayer 109. The dielectric layer 420 can, for example, be an etch stop layer for a subsequent etching process, a dielectric layer for a metallized layer located further upstream, a passivation layer, or the like.

[0035] As described above, the high-density monolayer 109 makes the surface of the second dielectric layer hydrophobic, and the hydrophobic properties reduce or eliminate Cu2+ / Cu+ residues on the surface of the underlying second dielectric layer 108. This reduces problems associated with TDDB and VBD, especially at smaller technology nodes, such as those at 20 nm and below.

[0036] Fig. Figure 5 shows steps of a method for forming a compound according to one embodiment. The method begins with step 502, in which a substrate is provided with a dielectric layer to be structured. For example, the layer to be structured may be a dielectric layer, such as a layer used for metallization in a semiconductor device. In step 504, the surface of the dielectric layer is treated to make the dielectric layer more or less hydrophobic. The treatment may include forming a high-density monolayer, as described above. Fig. 1 described.

[0037] Next, in step 506, the dielectric layer is structured, for example using photolithographic techniques, thereby creating openings in the dielectric layer, as described above. Fig. 2 described. The structuring can include the formation of an ARC layer and a hard mask layer, as described above regarding Fig. 1 described. After structuring, the openings are filled with a conductive material, as indicated in step 508 and above regarding Fig. 3 described.

[0038] In step 510, excess conductive material is removed, as described above. Fig. 4 described.

Claims

[1] Method for forming an integrated circuit structure, the method comprising: - Providing a substrate; - Formation of a first dielectric layer (102) over the substrate; - Forming conductive components (104) in the first dielectric layer (102), wherein the conductive components (104) comprise a copper conductor; - Forming a second dielectric layer (108) over the first dielectric layer (102) with the conductive components (104); - Treating a surface of the second dielectric layer (108) to form a hydrophobic high-density monolayer along the surface of the second dielectric layer (108), wherein the high-density monolayer (109) has a higher density than the dielectric layer, wherein, in forming the high-density monolayer (109), terminal OH groups of the dielectric layer are replaced by Si(CH3)3 groups, and forming an anti-reflective coating layer (114) over the high-density monolayer; - after treating the surface, structuring the second dielectric layer (108) and the high-density monolayer (109) to form openings (230, 232); - Forming a conductive material (330) in the openings (230, 232) of the second dielectric layer (108), and removing excess conductive material from the surface of the second dielectric layer (108) by applying a chemical-mechanical polishing process, whereby Cu2+ / Cu+ residues are reduced or eliminated due to the hydrophobic properties of the surface of the second dielectric layer (108). [2] Method according to claim 1, wherein the surface treatment comprises treating the surface of the second dielectric layer (108) with hexamethyldisilazane. [3] Method according to claim 2, wherein the treatment with hexamethyldisilazane comprises treatment with a hexamethyldisilazane vapor. [4] Method according to claim 1, wherein the surface treatment comprises treating the surface of the second dielectric layer (108) with trimethylsilyldiethylamine. [5] Method according to claim 4, wherein the treatment with trimethylsilyldiethylamine comprises immersing the second dielectric layer (108) in a dilute trimethylsilyldiethylamine solution. [6] Method according to claim 1, wherein the surface treatment comprises treating the surface of the second dielectric layer (108) with trimethylsilyl acetate. [7] Method according to claim 6, wherein the treatment with trimethylsilyl acetate comprises immersing the second dielectric layer (108) in a dilute trimethylsilyl acetate solution. [8] Method according to one of the preceding claims, wherein the second dielectric layer (108) is formed from a low-k material. [9] Method according to any one of the preceding claims 1-7, wherein the second dielectric layer (108) is formed from an ultra-low-k material. [10] Method according to any of the preceding claims, wherein the second dielectric layer (108) is treated to form conductors and / or vias. [11] Method according to the preceding claim 8, wherein the second dielectric layer (108) is made of a material having a density of about 1.0 g / cm³ 3 is formed, and the high-density monolayer (109) has a higher density than 1.0 g / cm³ 3 has. [12] Method according to any one of the preceding claims 1-7 or 10, wherein the second dielectric layer (108) is formed from silicon oxide.

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