Integrated circuit with metal conductor connections for improved RRAM reliability, method for operating the same and method for manufacturing them

Abstract

Integrated circuit device comprising: an array of RRAM cells (125); an array of bit lines (BL, 133) connected to the RRAM cells (125) of the array, each of the bit lines (BL, 133) having a first cross-sectional area; and an array of source lines (SL, 137) for the RRAM cells (125) of the array, each of the source lines (SL, 137) having a second cross-sectional area; the second cross-sectional area being larger than the first cross-sectional area; and the source lines (SL, 137) and bit lines (BL, 133) being configured to carry current for setting and resetting the RRAM cells.

Description

PRIORITY CLAIM AND CROSS REFERENCEBACKGROUNDThe present disclosure relates to integrated circuit devices, including resistive random access memory, methods of making such devices, and methods of operating such devices.Resistive random access memory (RRAM) has a simple structure, low operating voltage, high speed, good durability, and CMOS processor compatibility. RRAM is the most promising alternative to provide a reduced replacement for traditional flash memory and has found wide application in devices such as optical disk storage and nonvolatile memory arrays.An RRAM cell stores data within a layer of material that can be caused to undergo a phase change. The phase change may be caused to switch between a high resistance state and a low resistance state within all or part of the layer. The resistance state may be sensed and interpreted as a representation of either a "0" or a "1.".In a typical RRAM cell, the data storage layer includes an amorphous metal oxide. Upon application of a sufficient voltage, a metal bridge is caused to form across the data storage layer, resulting in the low resistance state. The metal bridge can be interrupted and the high resistance state restored by applying a short high current density pulse which melts or tears all or parts of the metal structure. The data storage layer cools rapidly and remains in the high resistance state until the low resistance state is initiated again. RRAM cells are typically formed after front-end-of-line (FEOL) processing. In a typical design, an array of RRAM cells is formed between a pair of metal interconnect layers.EP 1 710 840 A2 describes a multi-bit memory device with resistive material layers as storage nodes and its manufacturing and operating methods. The memory device includes a substrate, a transistor on the substrate, and a storage node coupled to the transistor. The storage node includes a bottom electrode connected to the substrate; a first phase change layer formed on the bottom electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and a top electrode formed on the second phase change layer.Document JP 2013-131 271 A describes a nonvolatile memory cell including: a first variable resistance element and a first selection transistor connected in series between a bit line and a source line SL; and a second variable resistance element and a second selection transistor connected in series between a complementary bit line and the source line. The selection transistors are turned on and off by selection voltage supplied via a word line. When the selection transistors are turned on, a polarity voltage corresponding to the write data is applied between the bit line and the source line and between the complementary bit line and the source line.The publication US 2008 / 0 079 050 A1 describes a semiconductor component and its production method. A semiconductor device includes a substrate having a plurality of isolation structures formed therein defining first and second regions over the substrate. A transistor is formed on a portion of the substrate in the first and second regions, the transistor in the second region being formed only with a pocket doping region in the substrate adjacent a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second regions. The first dielectric layer forms a plurality of first contact plugs that electrically connect a source region and a drain region of the transistor in the second region. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, the capacitor electrically connecting one of the first contact plugs.The document US 2005 / 0 280 120 A1 describes a semiconductor device having an interlayer insulating film, a sealing ring and a dummy structure. The interlayer insulating film has a specific dielectric constant of 3 or less. The seal ring is formed within the interlayer insulating film near an edge of a semiconductor chip to surround a circuit formation region of this semiconductor chip. The dummy pattern is formed within the interlayer insulating film and surrounds the seal ring in a dicing region of the semiconductor chip.US 2013 / 0 020 707 A1 describes a 3D IC-based system comprising: a first semiconductor layer having first alignment marks and first transistors, wherein the first transistors are connected to one another by at least one metal layer including aluminum or copper; a second monocrystallized semiconductor layer containing second transistors and overlying the at least one metal layer, wherein the at least one metal layer is located between the first semiconductor layer and the second monocrystallized semiconductor layer; and wherein the second transistors contain a plurality of N-transistors and P-transistors and wherein the second monocrystallized semiconductor layer is transferred from a reusable donor wafer.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is noted that, consistent with common practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates an RRAM device according to some embodiments of the present disclosure. FIGS. 2A-2C illustrate some example cable sizes suitable for the RRAM device, in accordance with some embodiments of the present disclosure. FIG. 3 is a flow diagram illustrating a method of setting an RRAM cell, in accordance with some embodiments of the present disclosure. FIG. 4 is a graph showing voltages across and currents through an RRAM cell as it undergoes an RRAM cell adjustment process, in accordance with some embodiments of the present disclosure. FIG. 5 is a flow diagram illustrating a method for resetting an RRAM cell, in accordance with some embodiments of the present disclosure. FIG. 6 is a graph showing voltages across and currents through an RRAM cell as it undergoes an RRAM cell reset process, in accordance with some embodiments of the present disclosure. FIG. 7 is a flow diagram illustrating an RRAM cell fabrication method according to some embodiments of the present disclosure. FIGS. 8-10 illustrate cross-sectional views at various intermediate stages of manufacturing an RRAM device, in accordance with some embodiments of the present disclosure. FIGS. 11-15 illustrate cross-sectional views at various intermediate stages of manufacturing an RRAM cell, in accordance with some embodiments of the present disclosure. FIGS. 16-17 illustrate cross-sectional views of the fabrication of an RRAM device, in accordance with some other embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of constituent elements and arrangements are described below in order to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower," "above," "above," and the like may be used herein to facilitate the description to describe an element or the relationship of a feature to (another) element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientation) and the spatially relative descriptors used herein may also be appropriately designed.As integrated circuit densities were increased, the resistance capacitance (RC) delay of cables in metal interconnect layers began to have a significant impact on integrated circuit performance. Modern integrated circuits (ICs) reduce RC delay in metal interconnect layers by using copper instead of aluminum and low dielectric constant dielectrics instead of SiO 2. The RC delay is also reduced by scaling to use thicker cables to create longer connections.Scaling is done by varying cable thickness and width under metal interconnect layers. The lowest metal interconnection layers closest to the backing layer have the thinnest and narrowest cables. Cables in the lowest layers have the highest RC delay and are used to create local interconnects. Cable thicknesses, widths and separations gradually increase because additional interconnect layers are added. The uppermost metal interconnection layers have the thickest, widest, and coarsest distributed cables. The top layers have the lowest RC delay and are used for force and clock distribution and global routing.Modern integrated circuits typically include thousands of components that have complex interactions. Because of this complexity, the placement and routing of cables among the metal interconnect layers is usually determined by computers in an Electronic Design Automation (EDA) process. Typically, a very large number of different circuit designs may meet a functional specification provided to an EDA program. In addition to basic design constraints, there are a variety of different performance goals regarding such concerns as performance, performance, signal integrity, reliability, and yield. Because of the large number of possibilities and the computational requirements that evaluate constraints and real functions, the problem is mathematically inextricable to define an optimum design. Mathematically unreleasably means that an optimum exists, but cannot be determined in a feasible time period. Thus, although EDA searches optimal solutions, the search for solutions by design rules must be limited to solutions that are achieved within practical time limits.It has been determined that the durability of an RRAM device with the 1T1R architecture that provides a transistor for each RRAM cell is often limited by the durability of the transistors. It has also been determined that the transistors age primarily during the reset operation. Due to the body effect, the reset operation requires a much higher voltage at the transistor gates than the set operation. It has been found that a decrease in the sheet resistance of the source lines provides a surprisingly large increase in the recovery speed. For example, by increasing the source lines from an ordinary cable size, which is the size of a cable in the second metal interconnection layer (M 2), to the size of a cable in the sixth metal interconnection layer (M 6), the time taken for a reset operation can be reduced by approximately one order of magnitude. Consequently, the lifetime of the RRAM transistors and the durability of the RRAM device can be increased by approximately an order of magnitude.It is therefore an object of the present invention to provide an integrated circuit which reduces the above problems.The object is achieved by the integrated circuit according to claim 1, the method for resetting an RRAM cell according to claim 14 and the method for producing an integrated circuit device according to claim 16.FIG. 1 provides an illustration of an integrated circuit device 100 in accordance with some embodiments of the present disclosure. The integrated circuit device 100 includes a semiconductor substrate 101 and a plurality of metal interconnection layers 131 (M 1-M 6) formed over the substrate 101. An RRAM cell 125 may be formed in one of these metal interconnect layers 131, between two of these layers, or in a higher layer. In most embodiments, an RRAM cell 125 is formed over the fourth (M4) metal interconnect layer 131 to meet thermal budget constraints. In some embodiments, the RRAM cell 125 is formed between the fourth (M4) and fifth (M5) metal interconnect layers 131, as shown in FIG. 1.The RRAM cell 125 is one in an array of RRAM cells 125 forming a memory block. A bit line 133 for responding to RRAM cells 125 in the memory block is formed in a metal interconnect layer 131 over the RRAM cell 125. In the embodiment of FIG. 1, the bit line 133 is formed in the fifth (M 5) metal interconnect layer 131. In most embodiments, bit line 133 is connected to a top electrode 127 of RRAM cell 125 by via 129.A switching device for selecting RRAM cell 125 is formed on the support layer 101. In the embodiment of FIG. 1, the switching device is a transistor 105. This is characteristic of embodiments having a 1T1R architecture. In some embodiments, the switching device is a diode and the architecture is 1D1R. In some embodiments, the switching device is a bipolar transistor and the architecture is 1BJT1R. In some embodiments, the switching device is a bipolar switch and the architecture is 1S1R.In the embodiment of FIG. 1, transistor 105 is one in an array of transistors 105 separated by isolation regions 103. The transistor 105 includes a source region 107, a drain region 113, a gate 111, and a gate dielectric 109. The drain region 113 is connected to a lowermost electrode 123 of the RRAM cell 125 through a contact plug 115, vias 119 formed in the first to fourth (M1-M4) metal interconnection layers 131, and vias 117 formed between these metal interconnection layers 131. A data word line 135 for switching the transistor 105 is formed in the third (M3) metal interconnection layer 131.A source line 137 supplies current pulses to reset the RRAM cell 125. In device 100, source line 137 is connected to source region 107 through contact plug 145, vias 143 formed in first through fourth (M1-M4) metal interconnect layers 131, and vias 141 formed between these metal interconnect layers 131. According to conventional design rules, source line 137 would be located in second (M2) metal interconnect layer 131 and would have a lower cross-sectional area than bit line 133. According to some embodiments of the present disclosure, source line 137 has a cross-sectional area that is greater than or equal to the cross-sectional area of bit line 133. In most embodiments, source line 137 has a cross-sectional area that is greater than the cross-sectional area of bit line 133. In most embodiments, the source line 137 is formed in a metal interconnect layer 131 over the RRAM cell 125. In most embodiments, the source line 137 is formed in a metal interconnect layer 131 over the metal interconnect layer 131 in which the bit line 133 is formed. In the embodiment of FIG. 1, the source line 137 is formed in the sixth (M 6) metal interconnection layer 131.In most embodiments, metal interconnect layers 131 are in a stacked arrangement. In a stacked arrangement, the average, modal, or maximum value of a cross-sectional area of conductive lines within each metal interconnect layer 131 increases as the height above the carrier layer 101 increases. The widths of conductive lines are generally uniform within a metal interconnect layer 131, and in most embodiments, the average, modal, and maximum value of the cross-sectional area for conductive lines within a metal interconnect layer 131 are all approximately equal.In some embodiments, the average, modal, and maximum value of the cross-sectional area of conductive lines of some adjacent metal interconnect layers 131 may be the same. In most embodiments, the average, modal or maximum value of the cross-sectional area of conductive lines of some metal interconnect layers 131 is greater than for other metal interconnect layers 131, and the metal interconnect layers 131 having the greater values of average, modal or maximum value of the cross-sectional area are above those for which the values are smaller. In some embodiments, conductive lines are approximately rectangular in cross-section, with the cross-sectional area being the product of thickness and width. Thickness refers to a dimension perpendicular, or substantially perpendicular, to the backing layer 101. Width refers to a dimension parallel, or substantially parallel, to the carrier layer 101 and, in some embodiments, differs from length, that length is many times greater than width, for structures referred to as conductive lines. An increase in the cross-sectional area can be realized by an increase in width, an increase in thickness, or an increase in both. In most embodiments, sheet resistance is approximately inversely proportional to cross-sectional area.FIGS. 2A-2C illustrate conductive lines 153, 155, and 157 in accordance with some embodiments of the present disclosure. Conductive lines 153, 155, and 156 have widths 153W, 155W, and 157W, and thicknesses 153T, 155T, and 157T, respectively. In some embodiments, the conductive line 153 is formed in the second (M 2) metal interconnect layer 131. A prior art EDA program would be expected to place source lines in M2. In some embodiments, the conductive line 153 is formed in the third (M 3) metal interconnect layer 131. In some embodiments, conductive line 153 is data word line (WL) 135. In some embodiments, the conductive line 155 is formed in the fifth (M 5) metal interconnect layer 131. In some embodiments, conductive line 155 is bit line (BL) 133. In some embodiments, the conductive line 157 is formed in the sixth (M 6) metal interconnection layer 131. In some embodiments, the conductive line 157 is the source line (SL) 137. The following table provides ranges for the relative dimensions and cross-sectional areas of these conductive lines, in accordance with some embodiments of the present disclosure:M5 to M2BL to WLThickness: Thickness1,4 2,5M5 to M2BL to WLWidth Width1,5 up to 3,0M5 to M2BL to WLCross-sectional area2,0 up to 6,0M6 to M5SL to BLThickness: Thickness1,1 From 1 to 1,4M6 to M5SL to BLWidth Width1,0 From 1 to 1,3M6 to M5SL to BLCross-sectional area1,1 From 1 to 1,8M6 to M2SL to WLThickness: Thickness1,5 up to 3,0M6 to M2SL to WLWidth Width1,5 up to 4,0M6 to M2SL to WLCross-sectional area2,2 from 10 to 10,0Placement of source line 137 over fourth (M 4) metal interconnect layer 131, in accordance with some embodiments of the present disclosure, increases its cross-sectional area and decreases its sheet resistance by a factor of two or more compared to the cross-sectional area and sheet resistance when source line 137 has been adjusted or positioned according to conventional design rules. In some embodiments, the cross-sectional area of source line 137 is equal to that of bit line 133. In most embodiments, the cross-sectional area of source line 137 is greater than that of bit line 133. In some embodiments, bit line 133 and RRAM cell 125 are located or formed in layers that are between metal interconnect layers 131 that include source line 133 and data word line 135. In most embodiments, data word line 135 is below bit line 133 and RRAM cell 125.Bit line 133, data word line 135, and source line 137 are used to set or reset RRAM cell 125. FIG. 3 provides an example of a process 300 for setting the RRAM cell 125. Process 300 includes an operation 301 for setting source line 137 to a reference voltage, which is typically ground, an operation 303 for setting data word line 135 to a sufficient bias voltage to turn on transistor 105, and an operation 305 for pulsing bit line 133 to provide a voltage-current loop as shown in FIG. 4. In most embodiments, a bias voltage of 1.4 V is sufficient to turn on transistor 105 for the set mode 300.FIG. 5 provides an example of a process 310 for resetting the RRAM cell 125. Process 310 includes an operation 311 for setting bit line 133 to a reference voltage, which is typically ground, an operation 313 for setting data word line 135 to a sufficient bias voltage to turn on transistor 105, and an operation 315 for pulsing source line 137 to provide a voltage-current loop as shown in FIG. 6. In most embodiments, a bias voltage above 2V, for example 2.4V, is necessary to turn on transistor 105 for reset operation 310. As shown in FIGS. 4 and 6, the reset operation 310 requires a pulse having a higher amplitude than the adjustment operation 300. The voltages shown are voltages across cell 125. Operations 303 and 313 pulse bit line 133 or source line 137 at slightly higher voltages to overcome the parasitic resistances of these lines. Providing the source line 137 with a lower sheet resistance than the bit line 133 makes the pulse requirements of set and reset operations approximately equal.FIG. 7 provides a flow diagram for a process 200 for forming an RRAM cell 125, which is an example in accordance with another embodiment of the present disclosure. The process 200 may form the RRAM device 100 according to some embodiments of the present disclosure. FIGS. 8-10 and 16-17 illustrate the RRAM device 100 at intermediate stages of its manufacture, in accordance with some embodiments of the present disclosure. FIGS. 11-15 illustrate cross-sectional views at various stages for forming an RRAM cell 125 and the structure within the area 126 indicated in FIG. 16, in accordance with some embodiments of the present disclosure.The process 200 begins with front-end-of-line (FEOL) processing 210. The FEOL processing 210 may include operations constituting a switching device for selecting an RRAM cell 125. In the example of FIG. 7, the FEOL processing 210 includes an operation 211 of forming isolation regions 103 in the substrate 101, an operation 213 of forming the transistor 105 on the substrate 101, an operation 215 of salicideing the source region 107 and the drain region 113 of transistor 105, and an operation 217 of forming the source contact 145 and the drain contact 115. FIG. 8 illustrates the device 100 immediately after the FEOL processing 210.The process 200 continues with an operation 220 for forming the first through fourth (M 1-M 4) metal interconnect layers 131, as shown in FIG. 9 for the device 100. Operation 220 includes an operation 221 for forming data word line 135. In most embodiments, the data word line 135 is formed in one of the first (M1) to third (M3) metal interconnect layers 131. In some embodiments, the data word line 135 is formed in the third (M3) metal interconnect layer 131, as shown in FIG. 9.The metal interconnect layers 131 include conductive lines and vias in matrices of the dielectric 139. The conductive lines and vias may be formed of any conductive material. In some embodiments, the conductive material for all metal interconnect layers 131 over the first (M 1) is copper. Dielectric 139 may be any suitable dielectric and may include multiple layers of different dielectrics. In most embodiments, dielectric 139 is a low dielectric constant dielectric. In some embodiments, dielectric 139 is an extremely low dielectric constant dielectric. An extremely low dielectric constant dielectric material is a material having a dielectric constant of about 2.1 or less. An extremely low dielectric constant dielectric is generally formed by a low dielectric material having 20% or more voids (pores or air gaps). In most embodiments, an etch stop dielectric layer 121 is formed over each of the first (M 1) to fourth (M 4) metal interconnect layers 131. In most embodiments, metal interconnect layers 131 are formed by damascene or dual damascene processes.The process 200 continues with a series of operations 230 forming the RRAM cell 125. The first of these operations is to form a hole 124 through which the RRAM cell 125 may form a contact with a via 119 in the underlying metal interconnect layer 131, as shown in FIGS. 10 and 11. The hole 124 may be formed through the dielectric 139 or only through etch stop layer 121, as shown in the figures.The series of operations 230 continues with an operation 233 for forming an RRAM stack 160 from which the RRAM cell 125 is formed. In some embodiments, the hole 124 is filled with conductive material to create a lowermost electrode via prior to operation 233. In other embodiments, the RRAM stack 160 is formed over the hole 124 and fills the hole 124, as shown in FIG. 12. In most embodiments, the RRAM stack 160 includes a diffusion barrier layer 161, a lowermost electrode layer 163, an RRAM dielectric layer 165, a capping layer 167, and an uppermost electrode layer 169, as shown in FIG. 12. The order of these layers applies to the case that the bit line 133 is coupled to the top electrode layer 169. When a capping layer 167 is included, the bit line may be referred to as the response line coupled to the same side of the RRAM dielectric layer 165 as capping layer 167.The diffusion barrier layer 161 is an optional layer. It may be included to prevent contamination of the lowermost electrode layer 163 by material from a lowermost contact, such as via 119. In some embodiments in which the diffusion barrier layer 161 is included, the lowermost contact is copper and the lowermost electrode 163 is a material that is prone to contamination by copper. In some of these embodiments, the lowermost electrode layer 163 is TiN. The diffusion barrier layer 161 may have any suitable composition and may be formed by any suitable process. In most embodiments, the diffusion barrier layer 161 is a conductive oxide, nitride, or oxynitride of a metal selected from the group consisting of Al, Mn, Co, Ti, Ta, W, Ni, Sn, Mg. In some embodiments, the diffusion barrier layer 161 is TaN. The diffusion barrier layer 161 may have any suitable thickness. A suitable thickness is large enough to provide an effective diffusion barrier without being so large as to cause excessive resistance. In most embodiments, the thickness of the diffusion barrier layer 161 is in the range of 2 nm to 30 nm. In some embodiments, the thickness of the diffusion barrier layer 161 is in the range of 10 nm to 30 nm, for example, 20 nm.The lowermost electrode layer 163 may have any suitable composition and may be formed by any suitable process. Examples of suitable compositions include, without limitation, metals, metal nitrides and doped polysilicon. In some embodiments, the lowermost electrode layer 163 is a metal. The metal could be, for example, Al, Ti, Ta, Au, Pt, W, Ni, Ir or Cu. In some embodiments, the lowermost electrode layer 163 is a metal nitride. The metal nitride could be, for example, TaN. In some embodiments, the lowermost electrode layer 163 is a doped polysilicon. A doped polysilicon may be either a p+ doped polysilicon or an n+ doped polysilicon. In most embodiments, the thickness of the lowermost electrode layer 163 is in the range of 2 nm to 20 nm. In some embodiments, the thickness of the lowermost electrode layer 163 is in the range of 5 nm to 15 nm, for example, 10 nm.The RRAM dielectric 165 may be any material suitable for the data storage layer of an RRAM cell. A material suitable for the data storage layer of an RRAM cell is that which can be caused to undergo a reversible phase change between a high resistance state and a low resistance state. In some embodiments, the phase change is between an amorphous state and a metallic state. The phase change may be accompanied by or associated with a change in chemical composition. For example, an amorphous metal oxide may lose oxygen when it undergoes a phase change to a metallic state. The oxygen may be stored in a portion of the RRAM dielectric 165 that remains in the amorphous state or in an adjacent layer. Although described as a dielectric, only the low resistance state needs to be a dielectric. In most embodiments, the RRAM dielectric 165 is a high dielectric constant dielectric while in the low resistance state. In some embodiments, the RRAM dielectric 165 is a temporary metal oxide. Examples of materials that may be suitable for a dielectric 165 include NiOx, Ta y O X, TiO X, HfO X, Ta y O X, WO X, ZrO X, Al y O X and SrTiOX. In most embodiments, the thickness of the RRAM dielectric 165 is in the range of 2 nm to 10 nm. In some embodiments, the thickness of the RRAM dielectric 165 is in the range of 3 nm to 7 nm, for example, 5 nm.The cover layer 167 is optional. In some embodiments, the capping layer 167 provides an oxygen storage function that simplifies the phase change within the RRAM dielectric 165. In some embodiments, the capping layer 167 is a metal or metal oxide having a relatively low oxygen concentration. Examples of metals that may be suitable for the capping layer 167 include Ti, Hf, Pt, and Al. Examples of metal oxides that may be suitable for the capping layer 167 include TiO X, HfO X, ZrO X, GeO X, CeO X. The cover layer 167 may have any suitable thickness. In most embodiments, the thickness of the cover layer 167 is in the range of 2 nm to 10 nm. In some embodiments, the thickness of the cover layer 167 is in the range of 3 nm to 7 nm, for example, 5 nm. When provided, the capping layer 167 is on the same side of the RRAM dielectric 165 as the side to which the bit line 133 is connected.The top electrode layer 169 may have any of the compositions referred to as suitable for the bottom electrode layer 163. The top electrode layer 169 may have any suitable thickness. In most embodiments, the top electrode layer 169 has a thickness in the range of 10 nm to 40 nm. In typical embodiments, the top electrode layer 169 has a thickness in the range of 15 nm to 30 nm, for example 25 nm.The series of operations 230 forming the RRAM cell 125 may proceed with an operation 235 for patterning the top electrode layer 169 and an operation 237 for forming spacers 171, as shown in FIG. 13. In most embodiments, the act 235 of patterning the top electrode layer 169 includes an etch that continues through the cap layer 167. In most embodiments, the RRAM dielectric 165 provides an etch stop for patterning the top electrode 169. The act 237 of forming spacers 171 includes depositing a layer of spacer material and etching to form spacers 171. The spacer 171 may be formed of any suitable spacer material. Examples of suitable materials for forming spacers 171 include, without limitation, SiN, SiON, and SiO 2.The series of processes 230 proceeds with a process 239 for patterning the lowermost electrode layer 163 to form a pattern as shown in FIG. 14. As shown in FIG. 14, patterning the lowermost electrode layer 163 may include patterning the cap layer 161.The process 200 continues with an operation 240 of forming an uppermost electrode via 129 to form a structure as shown in FIGS. 15 and 16. In most embodiments, forming the top electrode via 129 includes forming a dielectric layer 139, patterning a hole through the dielectric layer 139 for the top electrode via 129, and filling the hole with metal to form top electrode via 129, as shown in FIGS. 15 and 16.The process 200 continues with an operation 250 of forming the fifth (M 5) metal interconnect layer 131 to form a structure as shown in FIG. 17. In this example, forming the fifth (M 5) metal interconnect layer 131 includes an operation 251 of forming bit line 133. The sequence of process 200 places bit line 133 over RRAM cell 125.The process 200 continues with an operation 250 of forming the sixth (M 6) metal interconnect layer 131 to form a structure as shown in FIG. 1. In this example, forming the sixth (M 6) metal interconnect layer 131 includes an operation 261 of forming source line 137. The sequence of process 200 places the source line 137 over the RRAM cell 125 and over the bit line 133. With conventional staggering of metal interconnect layers 131, this makes the cross-sectional area of source line 137 larger than the cross-sectional area of bit line 133 and larger than the cross-sectional area of a source line formed before RRAM cell 125.An embodiment of the present disclosure is an integrated circuit device that includes an array of RRAM cells, an array of bit lines connected to the RRAM cells of the array, and an array of source lines for the RRAM cells of the array. The source lines and the bit lines are designed to carry current for setting and resetting the RRAM cells. The source lines have a larger cross-sectional area than the bit lines.Another embodiment of the present disclosure is an integrated circuit device including a semiconductor carrier layer, a plurality of metal interconnect layers formed over the semiconductor carrier layer, an RRAM cell sandwiched between two of the metal interconnect layers, a bit line coupled to the RRAM cell, and a source line configured to be coupled to the RRAM cell. Both the source line and the bit line are located in metal interconnect layers higher above the semiconductor carrier layer than the RRAM cell.Another embodiment of the present disclosure is a method of resetting an RRAM cell. The method includes coupling a top electrode of the RRAM cell to a bit line, coupling the bottom electrode of the RRAM cell to a source line having a lower sheet resistance than the bit line, and driving the voltage of the source line to send a current pulse through the RRAM cell. The current pulse resets the RRAM cell.Another embodiment of the present disclosure is a method of operating an integrated circuit device with an RRAM cell. The RRAM cell has a top electrode and a bottom electrode, and a high resistance state and a low resistance state. The method includes setting the RRAM cell to the high resistance state and resetting the RRAM cell to the low resistance state. The resetting of the RRAM cell to the low resistance state includes connecting the lowermost electrode of the RRAM cell to a source potential through a source line while the uppermost electrode of the RRAM cell is connected to a reference potential through a bit line. The source line has a larger cross-sectional area than the bit line.Another embodiment of the present disclosure is a method of manufacturing an integrated circuit device. The method includes subjecting a semiconductor substrate to front-end-of-line processing, forming a first set of metal interconnect layers over the substrate, forming an RRAM cell over the first set of metal interconnect layers, and forming a second set of metal interconnect layers over the first set of metal interconnect layers and the RRAM cell. Forming the second set of metal interconnect layers includes forming a bit line and a source line for setting and resetting the RRAM cell.

Claims

An integrated circuit device comprising: an array of RRAM cells (125); an array of bit lines (BL, 133) connected to the RRAM cells (125) of the array, each of the bit lines (BL, 133) having a first cross-sectional area; and an array of source lines (SL, 137) for the RRAM cells (125) of the array, each of the source lines (SL, 137) having a second cross-sectional area; wherein the second cross-sectional area is greater than the first cross-sectional area; and the source lines (SL, 137) and bit lines (BL, 133) are configured to carry current for adjusting and resetting the RRAM cells.The integrated circuit device of claim 1, further comprising: an array of transistors (105) for selecting a respective RRAM cell (125) of the array of RRAM cells (125), the transistors (105) comprising source regions (107), drain regions (113), and gate electrodes (111); wherein the source regions (107) are connected to the source lines (SL, 137); and the drain regions (113) are connected to the RRAM cells (125).The integrated circuit device of claim 2, further comprising: an array of data word lines (WL, 135) configured to select the RRAM cells (125); wherein the data word lines (WL, 135) are connected to the gate electrodes (111).The integrated circuit device of claim 3, further comprising: a substrate (101); a plurality of metal interconnect layers (131, M1-M6) at different heights above the substrate (101); wherein the array of RRAM cells (125) is located between two of the metal interconnect layers (131, M1-M6); the source lines (SL, 137) are located in a metal interconnect layer (131, M6) that is higher above the substrate (101) than the array of RRAM cells (125); the bit lines (BL, 133) are located in a metal interconnect layer (131, M5) that is higher above the substrate (101) than the array of RRAM cells (125); and the data word lines (WL, 135) are located in a metal interconnect layer (131, M3) which is not as high above the substrate (101) as the array of RRAM cells (125).The integrated circuit device of claim 1, further comprising: a substrate (101); a plurality of metal interconnect layers (131, M1-M6) at at different heights above the substrate (101); wherein the array of RRAM cells (125) is located between two of the metal interconnect layers (131, M1-M6); and the source lines (SL, 137) are located in a metal interconnect layer (131, M1-M6) that is higher above the substrate (101) than the array of RRAM cells (125).The integrated circuit device of claim 5, wherein: the bit lines (BL, 133) are connected to top electrodes (127) of the RRAM cells (125); and the bit lines (BL, 133) are located in a metal interconnection layer (131, M5) that is higher above the support layer (101) than the array of RRAM cells (125).The integrated circuit device according to claim 6, wherein: the source lines (SL, 137) are located in a metal interconnection layer (131, M6) higher than the metal interconnection layer (131, M5) in which the bit lines (BL, 133) are formed.The integrated circuit device of claim 7, wherein at least two metal interconnection layers (131, M1-M4) are formed under the array of RRAM cells (125).The integrated circuit device of claim 8, further comprising: an array of transistors (105) formed on the substrate (101) under the metal interconnection layers (131, M1-M6), the transistors (105) comprising source regions (107), drain regions (113), and gate electrodes (111); wherein source regions (107) of the transistors (105) are connected to the source lines (SL, 137); and the drain regions (113) of the transistors (105) are connected to lowermost electrodes (123) of the RRAM cells (125).The integrated circuit device of claim 9, wherein at least four metal interconnect layers (131, M1-M4) are formed under the array of RRAM cells (125).The integrated circuit device of claim 1, further comprising: a substrate (101) having a surface; and a plurality of metal interconnect layers (131, M1-M6) over the substrate surface; wherein the array of RRAM cells (125) is located between two of the metal interconnect layers (131, M1-M6); the RRAM cells (125) comprise top electrodes (127), bottom electrodes (123), and RRAM dielectric layers (165) between the top and bottom electrodes (127, 123); the bit lines (BL, 133) are connected to the top electrodes (127); the bottom electrodes (123) are connected to first contacts (115) on the substrate surface; and the source lines (SL, 137) are connected to second contacts (145) on the substrate surface.The integrated circuit device of claim 11, wherein the source lines (SL, 137) are located in a metal interconnect layer (131, M6) that is higher above the substrate surface than the array of RRAM cells (125).The integrated circuit device of claim 11, wherein the source lines (SL, 137) are located in a metal interconnection layer (131, M6) that is higher above the substrate surface than the bit lines (BL, 133).A method for resetting an RRAM cell (125) of the array of RRAM cells of claim 1 having a top electrode (127) and a bottom electrode (123), comprising: coupling the top electrode (127) to the respective bit line (BL, 133); coupling the bottom electrode (123) to the respective source line (SL, 137) having a lower sheet resistance than the bit line (BL, 133) due to the second cross-sectional area being greater than the first cross-sectional area; and driving the voltage of the source line (SL, 137) to send a current pulse through the RRAM cell (125); wherein the current pulse resets the RRAM cell (125).The method of claim 14, wherein: the lowermost electrode (123) is coupled to the source line (SL, 137) by a transistor (105) having a gate (111); and the coupling of the lowermost electrode (123) to the source line (SL, 137) comprises driving the voltage of the gate (111).A method of manufacturing an integrated circuit device, comprising: subjecting a semiconductor substrate (101) to front-end-of-line processing; forming a first set of metal interconnect layers (131, M1-M4) over the semiconductor substrate (101); forming an RRAM cell (125) over the first set of metal interconnect layers (131, M1-M4); and forming a second set of metal interconnect layers (131, M5-M6) over the first set of metal interconnect layers (131, M1-M4) and the RRAM cell (125); wherein forming the second set of metal interconnect layers (131, M5-M6) comprises forming a bit line (BL, 133) and a source line (SL, 137) for setting and resetting the RRAM cell (125), wherein a cross-sectional area of the source line (SL, 137) is larger than a cross-sectional area of the bit line (BL, 133).The method of claim 16, wherein a metal interconnection layer (131, M1-M4) of the first set of metal interconnection layers (131, M1-M4) has a thickness lower than metal interconnection layers (131, M6) in which source lines (SL, 137) are formed.The method of claim 16, wherein: subjecting the semiconductor substrate to front-end-of-line processing comprises forming contacts (115, 145) on the substrate (101); and forming a first set of metal interconnect layers (131, M 1- M 4) comprises forming vias (117, 119, 141, 143) that connect the source line (SL, 137) and the RRAM cell (125) to the contacts (115, 145).The method of claim 16, wherein the bit lines (BL, 133) are formed before the source lines (SL, 137).The method of claim 16, wherein the first set of metal interconnect layers (131, M1-M4) comprises at least four metal interconnect layers (131, M1-M4).

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