Method, circuit arrangement and integrated circuit chip for use in signal processing

Abstract

Method for use in signal processing, comprising - providing an amplifier block (110, 310), - Providing a calibration block (120, 320), - coupling a control block (130, 330) to the amplifier block (110, 310) and to the calibration block (120, 320), - combining a signal output from the amplifier block (110, 310) and a signal output from the calibration block (120, 320) to obtain a combined signal, - using the control block (130, 330) to control the calibration block (120, 320) and the amplifier block (110, 310) based on the combined signal; and - clocking the control circuit (130, 330) so as to time a switching of a calibration block signal input terminal end between coupling to a reference input terminal end of the amplifier block (110, 310) and coupling to a sample input terminal end of the amplifier block (110, 310).

Description

[0001] The application relates to a method, a circuit arrangement, and an integrated circuit chip for use in signal processing. Background of the invention

[0002] During operation, an operational amplifier designed to sense a voltage signal and output an amplified voltage signal is typically shifted due to environmental influences. Environmental influences can vary over time. For example, the operational amplifier may heat up, depending on the contacting coolant and its properties. A change in operating temperature can result in a change in the operational amplifier's operating point, which is shifted relative to a fixed design operating point.

[0003] To ensure that the operational amplifier operates according to the design, the operational amplifier is biased, i.e. the amplified voltage signal is based on a superposition of the detected voltage signal and an essentially constant bias voltage.

[0004] One challenge is ensuring that the bias voltage adequately compensates for effects that shift the operational amplifier's operating point. Furthermore, it is difficult to accommodate changing environmental influences on the operational amplifier's operation without interrupting operation to allow recalibration to update the bias voltage.

[0005] WO 01 / 91288 A1 discloses a hybrid multi-carrier RF power amplifier linearization architecture that combines ACT and feedforward amplifier stages to achieve high output distortion rejection and improved amplifier linearity. A carrier compensation loop is coupled to a main RF power amplifier stage comprising parallel RF power amplifiers coupled via intermod complementary predistortion paths. The carrier compensation loop is coupled to a feedforward loop containing a feedforward RF power amplifier to generate a composite amplified output signal with greatly reduced intermodulation products. Vector modulators in the main amplifier and feedforward amplifier stages are controlled by a digital signal processor using outputs from various monitoring subsystems, including pilot tone detection, correlator, distortion, and power detector circuits.

[0006] US 5,594,385 A discloses a feedforward linear amplifier, and in particular a multi-channel linear amplifier, providing an adaptive control system and method, wherein analyzed distortion or error detection of nonlinear distortion components of the output signal of a main amplifier element is used to correct distortion in the amplification of an information signal. The distortion analysis is based on a sweep of the entire operating frequency band from which the distortion components are extracted. In the analog-to-digital conversion of an IF signal, IF sampling (subharmonic sampling) can be used to detect distortion within a passband.

[0007] A method for use in signal processing according to claim 1, a circuit arrangement for use in signal processing according to claim 2, and an integrated circuit chip for use in processing signals according to claim 12 are provided. Further embodiments are described in the dependent claims. Short description of the drawings

[0008] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention. Fig. 1 is a block diagram schematically illustrating an amplifier system according to some embodiments. Fig. 2 is a flowchart illustrating a method according to some embodiments implemented in the amplifier system of Fig. 1 are implemented. Fig. 3 is a block diagram illustrating an exemplary amplifier arrangement 300 that incorporates the amplifier system of Fig. 1 using various electronic components according to some embodiments. Fig. 4 is a timing diagram showing operating modes of the amplifier system in Fig. 3 according to some implementations. Fig. Figure 5 is a timing diagram showing operating modes of the amplifier system in Fig. 1 according to some implementations.

[0009] The elements in the drawings are not necessarily to scale. Like reference numerals indicate similar parts.

[0010] Because components of embodiments according to the present invention can be arranged in a number of different orientations, directional terminology may be used for purposes of illustration but is not limiting unless expressly stated to the contrary. Other embodiments according to the present invention and many of the intended advantages of the present invention will be readily appreciated when understood by reference to the more detailed description below. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, accordingly, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. Detailed description

[0011] Embodiments, implementations and associated effects are disclosed below with reference to the accompanying drawings.

[0012] Fig. 1 is a block diagram schematically illustrating an amplifier system according to some embodiments. The amplifier system 100 includes an operational amplifier block 110. The amplifier system 100 further includes a calibration block 120 coupled to the operational amplifier block 110. Furthermore, the amplifier system 100 includes a control block 130 coupled to the operational amplifier block 110 and to the calibration block 120. The amplifier system 100 includes a switch block 140 coupled between the control block 130 and the calibration block 120. The amplifier system 100 also includes an amplifier system signal input terminal 150, a reference signal terminal 160, and an amplifier system signal output terminal 170. In some embodiments, the amplifier system 100 includes other terminals such as a power supply (in Fig. 1 not shown) and / or earth (in Fig. 1 not shown).

[0013] The amplifier block 110 is coupled to the reference signal terminal 160 via an amplifier reference signal path 161. The amplifier block 110 is coupled to the amplifier system signal input terminal 150 via an in-signal path 151. The amplifier block 110 is coupled to the amplifier system signal output terminal 170 via an out-signal path 117. The amplifier block 110 is configured to receive an in-signal from the amplifier system signal input terminal 150, amplify the received in-signal, and output a corresponding amplifier out-signal to the amplifier system signal output terminal 170.

[0014] Calibration block 120 has a calibration reference terminal end (not shown) coupled to reference signal terminal 160 via a calibration reference signal path 162. Calibration block 120 is coupled to amplifier system signal input terminal 150 via an activatable / deactivatable in signal path 154. Calibration block 120 is coupled to control block 130 via an error signal path 123. Calibration block 120 is configured to output a calibration error signal on error signal path 123. Calibration block 120 is configured to cooperate with control module 130 to thereby—in some embodiments, continuously—calibrate amplifier block 110. The calibration block 120 is configured to cooperate with the control block 130 so as to calibrate the calibration block 120 in dependence on a setting made on the switch block 140.It should be noted that in some implementations, such as the embodiment shown in . Fig. 1, the reference voltage at the reference signal terminal 160 is used for both the amplifier block 110 and the calibration block 120. However, in some implementations, the amplifier reference terminal end and the calibration reference terminal end are kept separate from each other and configured to be set to different voltage levels.

[0015] Control block 130 is coupled to amplifier block 110 via an out signal path 113 and / or to calibration block 120 via error signal path 123. Control block 130 is coupled to amplifier block 110 via an amplifier control signal path 131, to calibration block 120 via a calibration control signal path 132, and to switch block 140 via a switch control signal path 134. Further, control block 130 is configured to receive the calibration error signal from calibration block 120. In some embodiments, control block 130 is configured to derive a difference signal reflecting a difference between the amplifier out signal and the calibration error signal.

[0016] Because a difference signal representing a calibration deficiency is an analog signal, an analog-to-digital block (not shown) may be coupled between the amplifier block 110 and the control block 130 (e.g., as part of the out signal path 113) and / or between the calibration block 120 (e.g., as part of the error signal path 123) and the control block 130. In some implementations, the analog-to-digital block forms part of the control block 130. The analog-to-digital block is configured to receive at least one of the amplifier out signal and the calibration error signal and to provide a digital representation of the received (analog) signal. In some embodiments, the digital representation is 1 bit, i.e.The analog-to-digital converter is configured to assign either a zero or a one of the digital signal to an analog signal value, depending on whether or not a predetermined voltage level in the received analog signal is exceeded. For example, the analog-to-digital converter may be implemented using at least one inverter that associates an input voltage level with either a zero or a one output by the inverter. At least one effect may be that sequences of bits can be stored by means of the control block 130 as setting value(s) for delayed use, for example, after a shutdown of the amplifier system 100 during a subsequent initialization of the amplifier system 100.

[0017] The control block 130 is configured to derive, based on the amplifier-out signal from the amplifier block 110 and the calibration error signal from the calibration block 120, an amplifier control signal to be provided to the amplifier block 110 via an amplifier control signal coupling 131 for use in controlling, in particular calibrating, the amplifier block 110. In some embodiments, the control block 130 is configured to use a difference between the amplifier-out signal from the amplifier block 110 and the calibration error signal from the calibration block 120 to derive the amplifier control signal. In some embodiments, the calibration block 120 is similar to the amplifier block 110, at least with respect to a characteristic electrical behavior, to such an extent that both the amplifier block 110 and the calibration block 120 operate in substantially the same manner.For example, in some embodiments where amplifier block 110 is provided as an operational amplifier of a certain circuit structure, calibration block 120 may be provided as a calibration amplifier having substantially the same circuit structure as the operational amplifier. In another example, multiple calibration amplifiers may form calibration block 120, wherein the calibration amplifiers are structured such that a characteristic curve of calibration block 120 results that is similar to a characteristic curve of amplifier block 110.Therefore, the difference between the amplifier out signal from amplifier block 110 and the calibration error signal from calibration block 120 should disappear during operation of amplifier system 100, and the amplifier control signal should indicate a correct setting of amplifier block 110 and / or the fact that there is currently no need to adjust any setting of amplifier block 110.

[0018] In some embodiments, the control block 130 is configured to derive a calibration control signal for use in calibrating the calibration block 120 based on the calibration error signal from the calibration block 120 to be provided to the calibration block 120 via a calibration control signal coupling 132. Deriving the calibration control signal requires that the same signal, for example, a reference voltage signal received from the reference signal terminal 160, be provided to the calibration block 120 at both the reference terminal end and the sense terminal end of the calibration block 120, such that in a calibrated state, a level of the out signal from the calibration block should reflect identical signal levels at the reference terminal end and the sense terminal end of the calibration block 120.

[0019] The control block 130 is further configured to derive a switch control signal provided to the switch block 140 via a switch control signal coupling 134 for use in controlling the switch block 140 to switch between the calibration of the amplifier block 110 and the calibration of the calibration block 120.

[0020] Thus, the control block 130 is configured to output the amplifier control signal to the amplifier control signal coupling 131, the calibration control signal to the calibration control signal coupling 132, and the switch control signal to the switch control signal coupling 134.

[0021] In some embodiments, the control block 130 is coupled to a memory configured to store digital representations of adjustment values and / or other values suitable for use in resetting the amplifier block 110 and / or the calibration block 120 such that the amplifier block 110 and / or the calibration block 120 are reset to operate in a calibrated manner or to operate in an auto-calibrated manner, respectively.

[0022] The switch block 140 is configured to either enable or disable the in-signal path 154 depending on the switch control signal received from the control block 130. In some implementations, if the in-signal path 154 is enabled, the switch block 140 is configured to output the in-signal to the calibration block 120. If the in-signal path 154 is disabled, the switch block 140 is configured to output the reference signal as an auto-reference signal to the calibration block 120.

[0023] In some embodiments, the reference signal terminal 160 is configured to be set to a constant reference voltage level. However, some implementations do not assign a constant voltage level to the reference signal terminal 160, but rather allow the voltage level at the reference signal terminal 160 to fluctuate. It should be understood that the amplifier system 100 is not limited to having a single reference voltage, but in some embodiments includes another reference voltage terminal (not shown) configured to be set to, for example, a constant reference voltage.

[0024] The operation of the amplifier system 100 according to some implementations will now be briefly described with reference to Fig. 2 and Fig. 5, where Fig. 2 is a flowchart illustrating a method according to some embodiments implemented in the amplifier system of Fig. 1 are implemented, while Fig. 5 is a timing diagram showing operating modes of the amplifier system in Fig. 1 according to some implementations.

[0025] At S200, corresponding to a time prior to t0, operation of amplifier system 100 is started. In some implementations where the coupled memory stores digital representations of adjustment values and / or other values suitable for use in resetting amplifier block 110 and / or calibration block 120, control block 130 reads such values from the coupled memory for use, for example, in resetting amplifier block 110 and / or calibration block 120 to operate in a calibrated or auto-calibrated manner.

[0026] After a time prior to t0 has been exceeded, the switch block 140 deactivates the in-signal path 154 at S210. Now, at time t0, the switch block 140 outputs the auto-reference signal to the calibration block 120.

[0027] Thus, at S220, amplifier system 100 enters an autocalibration (AC) mode at time t0. In autocalibration (AC) mode, calibration block 120 outputs an autocalibration error signal to control block 130. Control block 130 generates, based on the autocalibration error signal, an autocalibration control signal provided to calibration block 120 to reduce the error that caused the autocalibration error signal. Control block 130 outputs the autocalibration control signal to calibration control signal coupling 132 for delivery to calibration block 120. It should be understood that, at least in some implementations, other information may additionally be provided to calibration block 120, such as configuration page data and / or control structure values, e.g., configuration seed values, and the like.

[0028] Based on timing information, at time t1, control block 130 generates a switch control signal for switch block 140 to activate in-signal path 154. Control block 130 outputs the switch control signal to switch control signal coupling 134 to deliver it to switch block 140. Accordingly, switch block 140 activates in-signal path 154 and outputs the in-signal to calibration block 130. Thus, amplifier system 100 enters an amplifier calibration (OP) mode for calibrating amplifier block 110 at S230.

[0029] Calibration block 120 outputs an amplifier calibration error signal to control block 130. Based on a combination of the amplifier calibration error signal and an operational amplifier out signal received from amplifier block 110, control block 130 generates an amplifier calibration control signal provided to amplifier block 110 to reduce the error that resulted in the amplifier calibration error signal. Control block 130 outputs the amplifier calibration control signal to amplifier control signal coupling 131 for delivery to amplifier block 110.

[0030] In some implementations, when amplifier calibration is complete, control block 130 signals switch block 140 to disable in-signal path 154, and switch block 140 disables in-signal path 154, whereby the in-signal received at signal input terminal 150 of the amplifier system is no longer provided to calibration block 120.

[0031] According to some implementations, at time t2, based on timing information, control block 130 generates a calibration block idle signal for calibration block 120 to enter an idle mode (IDLE). In some embodiments, calibration block 120 consumes less power than when operating in auto-calibration (AC) mode and / or in the amplifier calibration (OP) block. Thus, calibration block 120 enters idle mode (IDLE) at S2 140.

[0032] At S250, control block 130 returns to S210 based on timing information, and if the in-signal path 154 is active at that point, at S220, deactivates the in-signal path 154, causing the amplifier system 100 to enter the amplifier calibration (OP) mode. Thus, control block 130 repeats a cycle of auto-calibration (AC) mode, amplifier calibration (OP) mode, and idle (IDLE) mode.

[0033] It should be understood that, depending on the structural characteristics of the amplifier system 100 as well as the circumstances under which it is operating, the sequence of modes entered between S210 and S250 may, in some implementations, not include all of the auto-calibration mode (AC), the amplifier calibration mode (OP), and the idle mode (IDLE) in each cycle. For example, in some embodiments, a first cycle 501 includes the auto-calibration mode (AC), the amplifier calibration mode (OP), and the idle mode (IDLE). However, assuming that the calibration block 120 is sufficiently calibrated after undergoing auto-calibration during the auto-calibration mode of the first cycle 501, there is no need for auto-calibration during a second cycle 502. Therefore, as in the Fig. 5, the second cycle 502 merely includes, starting at time t3, the amplifier calibration mode (OP) and, starting at time t4, the sleep mode (IDLE).

[0034] Finally, at S250, if it is decided that the operation should be terminated, in some embodiments the method proceeds to S260, where the operation of the amplifier system 100 ends (in Fig. 5 no corresponding time point is shown).

[0035] In some implementations, the control block 130 writes to the coupled memory digital representations of adjustment values and / or other values suitable for use in resetting the amplifier block 110 and / or the calibration block 120, such that the amplifier block 110 and / or the calibration block 120 are reset to operate in a calibrated or auto-calibrated manner, respectively.

[0036] At least one effect of the system described above may be that the amplifier block 110, although subject to calibration, continues to sense and amplify a signal corresponding to the in-signal received at the signal input terminal 150 of the amplifier system and continues to provide a correspondingly amplified amplifier-out signal at the signal output terminal 170 of the amplifier system. Furthermore, intervals in which the amplifier block 110 is not subject to calibration, i.e., intervals other than those in which the amplifier system 100 is in the amplifier calibration (OP) mode, may be used to calibrate the calibration block 120 itself, i.e., to provide an interval in which the amplifier system 100 is in the auto-calibration (AC) mode.

[0037] An implementation of the amplifier system 100 according to some embodiments will now be described in more detail with reference to Fig. 3, which is a block diagram illustrating an exemplary amplifier arrangement 300 comprising the amplifier system of Fig. 1 implemented using various electronic and / or electrical components.

[0038] The amplifier assembly 300 includes an operational amplifier 310 and a calibration amplifier 320. The amplifier assembly 300 further includes an in-signal terminal 350, a reference voltage terminal 360, and an out-signal output terminal 370. The amplifier assembly 300 also includes a switch 340, a control circuit 330, a clock generator 380, and a ground terminal 390. Some embodiments include a supply voltage terminal (not shown) configured to couple some or all of the components of the amplifier assembly 300 to a supply voltage (not shown).

[0039] The operational amplifier 310 is provided as a comparator having a first input terminal end (in Fig. 3 by a “-“ sign, ie as inverting), which is also referred to herein as the reference terminal end, a second input terminal end (in Fig. 3 by a “+” sign, ie as non-inverting), which is also referred to herein as a key terminal end, and an output terminal end (in Fig. 3 by an "o"). The first input terminal end (-) of the operational amplifier 310 is coupled to the reference voltage terminal 360 via the reference line 361. The second input terminal end (+) of the operational amplifier 310 is coupled to the in-signal terminal 350 via the in-signal line 351. The output terminal end (o) of the operational amplifier 310 is coupled to the out-signal terminal 370 via the out-signal line 317. Furthermore, the output terminal end (o) of the operational amplifier 310 is coupled to the ground terminal end 390 via an operational voltmeter 319.

[0040] The operational amplifier 310 is configured to set the output terminal (o) to an amplifier-out signal voltage (VAOS) indicative of a difference between a reference signal voltage (VREF) at the first input terminal (-) and an amplifier-in signal voltage (VAIS) at the second input terminal (+). The operational amplifier 310 further includes a control signal input 311 and is configured to apply an amplifier bias voltage upon comparing the in signal voltage with the reference signal voltage, in accordance with an amplifier control signal (ACS) received at the control signal input 311.In some embodiments, the control signal input 311 of the operational amplifier 310 is configured to be set to the amplifier bias voltage to establish an amplifier operating point at which the operational amplifier 310 is biased to operate, for example, in a substantially linear manner and / or according to another predetermined and / or desired function.

[0041] The calibration amplifier 320 is provided as a comparator having a first input terminal end (in Fig. 3 by a “-“ sign, ie as inverting), which is also referred to herein as the reference terminal end, a second input terminal end (in Fig. 3 by a "+" sign, i.e., non-inverting), which is also referred to herein as the calibration terminal end, and an error terminal end. The first input terminal end (-) of the calibration amplifier 320 is coupled, for example, to the reference voltage terminal 360 at least via a reference line 362. The second input terminal end (+) of the calibration amplifier 320 is coupled to the switch 340 via a calibration signal line 342. The error terminal end of the calibration amplifier 320 is coupled to the ground terminal end 390 via the calibration voltmeter 329.

[0042] The calibration amplifier 320 is configured to set the error terminal end to the calibration error voltage (VERR), which depends on a difference between the reference signal voltage (VREF) applied to the first input terminal end (-) and a calibration signal voltage (VCAL) applied to the second input terminal end (+). The calibration amplifier 320 further includes a control signal input 321 and is configured to apply a calibration bias voltage upon comparing the calibration signal voltage with the reference signal voltage, in accordance with a calibration control signal received at the control signal input 321.In some embodiments, the control signal input 321 of the calibration amplifier 320 is configured to be set to the calibration bias voltage so as to establish a calibration operating point at which the calibration amplifier 320 is calibrated to operate, for example, substantially linearly and / or according to another predetermined and / or desired function.

[0043] The operational voltmeter 319 is configured to provide to the control circuit 330, via the signal line 313, an operating voltage difference signal (DVO) indicative of a difference between the amplifier out signal voltage VAOS that the operational amplifier 310 outputs to the output voltage terminal 370 at the output terminal (o) of the operational amplifier, and the error voltage (also referred to herein as the calibration amplifier out voltage) VERR that the calibration amplifier 320 outputs to a circuit node 327 at the output terminal (o) of the calibration amplifier. In some embodiments, this difference itself directly constitutes the signal provided by the operational voltmeter 319 to the control circuit 330.

[0044] The calibration voltmeter 329 is configured to provide to the control circuit 330 via a signal line 323 a calibration voltage difference signal (PVC) indicative of a difference between the out voltage VERR that the calibration amplifier 320 outputs from the output terminal (o) of the calibration amplifier to the circuit node 327 and a ground voltage at the ground terminal 390. In some embodiments, this difference itself directly forms the signal provided by the calibration voltmeter 329 to the control circuit 330.

[0045] The switch 340 is coupled, for example, at least via an in-signal line 352 to the in-signal terminal 350 and, for example, at least via the reference line 362 to the reference voltage terminal 360. Furthermore, the switch 340 has a control signal input 341 and is configured to switch the switch 340 according to a switch control signal (SCS) received at the control signal input 341, at least either into an auto-calibration connection state (in Fig. 3 with the label “AC”) or into an operational amplifier calibration connection state (in Fig. 3 labeled "OP"). In the auto-calibration connection state (AC), switch 340 connects calibration signal line 342 to reference line 362; thus, switch 340 couples the second input terminal (+) of calibration amplifier 320 to reference voltage terminal 360. In the operational amplifier calibration connection state (OP), switch 340 connects the calibration signal line to in-signal line 352; thus, switch 340 couples the second input terminal (+) of calibration amplifier 320 to in-signal terminal 350.

[0046] The control circuit 330 is configured to control the operation of the amplifier arrangement 300. Accordingly, the control circuit 330 is coupled to a clock generator 380 via the clock line 383 and configured to receive a clock signal (CLK) from the clock generator 380. Furthermore, the control circuit 330 is coupled to the operational voltmeter 319 via the signal line 313 and configured to receive the operational voltage difference signal (DVO) from the operational voltmeter 319. The control circuit 330 is also coupled to the calibration voltmeter 329 via the signal line 323 and configured to receive the calibration voltage difference signal (PVC) from the calibration voltmeter 329. The control circuit 330 is coupled via control signal line 331 and configured to provide amplifier control signals ACS to the control signal input 311 of the operational amplifier 310.Furthermore, the control circuit 330 is coupled via control signal line 332 to the control signal input 321 of the calibration amplifier 320 and is configured to provide calibration control signals CCS at the control signal input 321 of the calibration amplifier 320. The control circuit 330 is also coupled via a control signal line 334 to a control signal input 341 of the switch 340 and is configured to provide switch control signals SCS at the control signal input 341 of the switch 340.

[0047] In some embodiments, an analog-to-digital converter (not shown) is coupled between the operational amplifier 310 and the control circuit 330 (e.g., on signal line 313). The analog-to-digital converter is configured to receive the operational voltage difference signal (DVO) as an analog signal and generate a digital representation of the received analog signal. In some embodiments, the digital representation is 1 bit, meaning the analog-to-digital converter is configured to assign either zero or one to an analog signal value of the digital signal depending on whether a predetermined voltage level in the received analog signal is exceeded or not. Similarly, in some embodiments, an analog-to-digital converter (not shown) is coupled between the calibration amplifier 320 and the control circuit 330 (e.g., on signal line 323).The analog-to-digital converter is configured to receive the calibration voltage difference (DVC) signal as an analog signal and generate a digital representation of the received analog signal. For example, particularly when the associated operational amplifier has a large gain, the analog-to-digital converter includes an inverter that distinguishes small differences in voltage level from a target zero voltage level according to the gain and is thus suitable for forming a basis for a fine control signal for use in controlling the amplifier(s). At least one effect may be that little area is required when the described implementation is provided in an integrated circuit.In some embodiments, the analog-to-digital converter is embodied as an 8-bit converter, with a bias voltage ramped up to maintain a ramp-up voltage at which a threshold is reached, resulting in a change in the output level from zero to one or vice versa. The threshold, particularly if represented by 8 bits, for example, can be used to bias the amplifier. At least one effect can be that sequences of bits can be stored by the control block 130 as setting values for delayed use, for example, after a shutdown of the amplifier arrangement 300 during a subsequent initialization of the amplifier arrangement 300.

[0048] The control circuit 330 is configured to process, clocked by the clock signal CLK, the operational voltage difference signal DVO and / or the calibration voltage difference signal DVC to generate control signaling SCS, CCS, ACS for use in controlling the switch 340, for use in controlling the calibration amplifier 320, and / or for use in controlling the operational amplifier 310. Some embodiments of the control circuit 330 are configured to couple to a memory unit 333. In some embodiments, the memory unit 333 forms part of the control circuit 330. In some embodiments, the control circuit 330 is adapted to provide a digital representation of information for use in control signaling to the memory unit 333, for example, by writing the digital representation to the memory unit 333.Furthermore, the control circuit 330 is configured to read digital representations of information for use in control signaling from the memory unit 333, for example, a digital representation of an amplifier bias value, and to communicate the represented information to at least one of switch 340, calibration amplifier 320, and / or operational amplifier 310, as appropriate, for use in generating control signaling and / or for direct communication of the information.

[0049] The operation of the amplifier arrangement 300 according to some implementations will now be briefly described with reference again to Fig. 2 and with reference to Fig. 4. As described above, Fig. 2 is a flowchart illustrating a method according to some embodiments implemented in the amplifier system 100 of Fig. 1 and / or in the amplifier arrangement of Fig. 3 are implemented. Fig. Figure 4 is a timing diagram showing operating modes of the amplifier arrangement in Fig. 3 according to some implementations. In some embodiments and implementations described below, control circuitry 330 bases progression from one method step to another on timing information. It should be understood that this timing information may be based on the clock signal CLK received at control circuitry 330 via clock line 383 from clock generator 380, where control circuitry 330 may process the clock signal CLK to determine, for example, the beginning and / or end of an interval during which the described processing should be performed.

[0050] At S200, corresponding to a time prior to t0, operation of the amplifier arrangement 300 is started. In some implementations where the storage unit 333 stores digital representations of bias values and / or other values suitable for use in adjusting the operational amplifier 310 and / or the calibration amplifier 320, the control circuit 330 reads such values from the storage unit 333 for use, for example, in determining an initial bias voltage for the operational amplifier 310 and / or in determining an initial bias voltage for the calibration amplifier 320 to operate in a calibrated or auto-calibrated manner.

[0051] The first input terminal end (-) of operational amplifier 310 is set to the reference voltage VREF at reference voltage terminal 360 via reference line 361. The second input terminal end (+) of operational amplifier 310 senses the in-signal voltage VSEN at in-signal terminal 350 via in-signal line 351. Operational amplifier 310 sets the output terminal end (o) to an amplifier-out signal voltage VAOS that reflects a difference between the in-signal voltage VSEN to which the second input terminal end (+) of operational amplifier 310 is set and the reference signal voltage VREF to which the first input terminal end (-) is set. The amplifier-out signal voltage VAOS is provided to out-signal terminal 370 via out-signal line 317.

[0052] After crossing a time prior to t0 at S210, while the operation of the operational amplifier 310 continues as described above, the switch 340 deactivates the in-signal coupling of the second input terminal (+) of the calibration amplifier 320 and the in-signal terminal 350 at S220 in some embodiments; in some embodiments, the in-signal coupling of the second input terminal (+) of the calibration amplifier 320 and the in-signal terminal 350 has already been deactivated in an earlier phase following a previous execution of an auto-calibration.

[0053] At S220, at time t0, switch 340 enables the in-signal coupling of the second input terminal end (+) of calibration amplifier 320 to the reference voltage terminal 360 by connecting calibration signal line 342 to reference line 362. Thus, amplifier arrangement 300 enters an auto-calibration (AC) mode. In auto-calibration (AC) mode, calibration amplifier 320 sets the error terminal end (o) to an auto-calibration error voltage VERR, which reflects a difference between the calibration signal voltage VCAL (e.g., in an embodiment where the coupling to the reference voltage terminal 360 via switch 340 is provided by a direct connection: VCAL = VREF) to which the second input terminal end (+) of calibration amplifier 320 is set, and the reference signal voltage VREF to which the first input terminal end (-) is set.Because both the first input terminal end (-) and the second input terminal end (+) are connected to the same reference line 362, any difference in the voltages VCAL - VREF should be zero during perfect calibration. Accordingly, the error terminal end (o) of the calibration amplifier 320 should be set to VERR = 0 V. The auto-calibration error voltage VERR is detected by the calibration voltmeter 329, and a detection signal DVC indicative of the calibration error voltage VERR is provided to the control circuit 330 via the signal line 323.

[0054] Still at S220, during an interval 401, the control circuit 330 processes the detection signal DVC received from the calibration voltmeter 329 to generate an auto-calibration control signal CCS intended for the calibration amplifier 320 to reduce the error that caused the auto-calibration error signal to assume a value other than zero. The control circuit 330 outputs the auto-calibration control signal CCS to the control signal input 321 of the calibration amplifier 320 via the control signal line 332. For example, according to the auto-calibration control signal CCS, a bias voltage, also referred to as an offset voltage, of the calibration amplifier 320 is reduced. In some embodiments, at S220, several adjustments are made to the settings of the calibration amplifier 320 during the interval 401.

[0055] Based on the timing information, at time t1, the control circuit 330 generates a switch control signal for the switch 340 to activate the in-signal coupling of the calibration amplifier 320, wherein the first input terminal end (-) of the calibration amplifier 320 is set to the reference voltage VREF at the reference voltage terminal 360 via the reference line 362 and the reference line 361, and wherein the second input terminal end (+) of the calibration amplifier 320 senses an in-signal voltage VSEN provided at the in-signal terminal 350 via the calibration signal line 342, the switch 340, and the in-signal line 352. Thus, the amplifier arrangement 300 enters an amplifier calibration (OP) mode for calibrating the amplifier 310.

[0056] Now in amplifier calibration mode (OP), during an interval 402, the calibration amplifier 320 sets the error terminal end (o) of the calibration amplifier 320 to an amplifier calibration error voltage that reflects a difference between the in-signal voltage VSEN to which the second input terminal end (+) of the calibration amplifier 320 is set and the reference signal voltage VREF to which the first input terminal end (-) is set.

[0057] At the same time, ie, still at S230 and during interval 402, the first input terminal end (-) of operational amplifier 310 continues to be set to the reference voltage VREF at reference voltage terminal 360 via reference line 361. The second input terminal end (+) of operational amplifier 310 continues to sense the in-signal voltage VSEN at in-signal terminal 350 via in-signal line 351.Further, the operational amplifier 310 continues to set the output terminal (o) to the amplifier out signal voltage VAOS, which reflects the difference between the in signal voltage (e.g., in an embodiment where the coupling to the in signal terminal is provided via a direct connection: VSEN) to which the second input terminal (+) of the operational amplifier 310 is set, and the reference signal voltage (e.g., in an embodiment where the coupling to the reference voltage terminal 360 is provided via a direct connection: VREF) to which the first input terminal (-) of the operational amplifier 310 is set. The operational amplifier 310 continues to provide the amplifier out signal voltage VAOS to the out signal terminal 370 via the out signal line 317.In addition, the operational amplifier 310 also provides the amplifier-out signal voltage VAOS via the node 318 to a first terminal end of the operational voltmeter 319.

[0058] Meanwhile, the calibration amplifier 320 sets the error terminal end (o) to a calibration error voltage VERR which, similar to what was described above with reference to S220, reflects the difference between the calibration signal voltage VCAL (for example, in an embodiment where coupling to the in-signal terminal 350 via the switch 340 is provided by a direct connection: VCAL = VSEN) to which the second input terminal end (+) of the calibration amplifier 320 is set, and the reference signal voltage VREF to which the first input terminal end (-) of the calibration amplifier 320 is set.

[0059] Calibration amplifier 320 provides calibration error voltage VERR to a second terminal end of operational voltmeter 319. Where both the first input terminal end (-) of operational amplifier 310 and the first input terminal end (-) of calibration amplifier 320 are connected to the same reference voltage terminal 360 via reference line 362, and further where both the second input terminal end (+) of operational amplifier 310 and the second input terminal end (-) of calibration amplifier 320 are connected to the same in-signal terminal 350, the out-signal voltage VAOS at the output terminal end (o) of operational amplifier 310 and the calibration error voltage VERR at the output terminal end (o) of calibration amplifier 320 should be the same with perfect calibration. Therefore, any difference in voltages VAOS - VERR should be zero with perfect calibration.Accordingly, when the operational amplifier 310 is perfectly calibrated, the operational voltmeter 319 should detect a zero voltage between node 318 on the out signal line 317 and node 327 on the calibration error signal line connected to the error terminal end (o) of the calibration amplifier 320.

[0060] Any difference between the out-signal voltage VAOS of operational amplifier 310 and the calibration error voltage VERR of calibration amplifier 320 is detected by operational voltmeter 319, and a detection signal DVO indicative of the calibration voltage difference is provided to control circuit 330 via signal line 313. Control circuit 330 processes the detection signal DVO received from operational voltmeter 319 to generate an amplifier calibration control signal ACS intended for operational amplifier 310 to reduce the error that caused the difference between the out-signal voltage of operational amplifier 310 and the error voltage of calibration amplifier 320 to assume a value other than predetermined as indicating an acceptable error.The control circuit 330 outputs the amplifier calibration control signal ACS via the control signal line 331 to the control signal input 311 of the operational amplifier 310. In some embodiments, several adjustments to the settings of the operational amplifier 310 are performed in this manner during the interval 402 at S230.

[0061] In some embodiments, at S240, the control circuit 330 disables the in-signal coupling of the second input terminal end (+) of the calibration amplifier 320 to the in-signal terminal 350 (in Fig.4 not shown). In some implementations, as late as S240, the control circuit 330 generates a calibration amplifier sleep signal for the calibration amplifier 320 based on timing information to switch to a sleep mode in which the calibration amplifier 320 consumes less power than when operating in the auto-calibration mode and / or the amplifier calibration mode.

[0062] At S250, the control circuit 330 returns to S210 based on timing information and then, at S220, in some embodiments where the in-signal coupling of the second input terminal end (+) of the calibration amplifier 320 to the in-signal terminal 350 is still active, disables the in-signal coupling of the second input terminal end (+) of the calibration amplifier 320 to the in-signal terminal 350. Further, at S220, the control circuit 330 again enables the reference signal coupling of the second input terminal end (+) of the calibration amplifier 320 to the reference voltage terminal 360. Thus, the control circuit 330 repeats a cycle of auto-calibration mode (AC), amplifier calibration mode (OP), and sleep mode (IDLE).It should be understood, however, that in some implementations, depending on the structural characteristics of the amplifier assembly 300 and the operating circumstances, a cycle may not include all of the auto-calibration mode (AC), the amplifier calibration mode (OP), and the idle mode (IDLE). For example, in some embodiments, a first cycle 501 includes the auto-calibration mode (AC), the amplifier calibration mode (OP), and the idle mode (IDLE). However, assuming that the calibration amplifier 320, which has undergone auto-calibration during the auto-calibration mode (AC) of the first cycle 501, continues to be sufficiently calibrated such that auto-calibration is not required during a second cycle 502, the second cycle 502 includes only the amplifier calibration mode (OP) and the idle mode (IDLE).Finally, if it was decided at S250 that operation should be terminated, in some embodiments the method proceeds to S260 where operation of the amplifier arrangement 300 ends.

[0063] Further embodiments, implementations, and associated effects are disclosed below.

[0064] This description describes, in one aspect, according to some embodiments, a method for use in signal processing. The method includes providing an operational amplifier and a reference amplifier. The method includes coupling a control unit to the operational amplifier and to the reference amplifier. In some implementations, control of the reference amplifier and the operational amplifier are performed one after the other. In some implementations, control of the reference amplifier and the operational amplifier are performed alternately. In some implementations, control of the operational amplifier is based on a signal output from the operational amplifier or on a signal output from the reference amplifier.Some embodiments include combining a signal output from the operational amplifier and a signal output from the reference amplifier to obtain a combined signal, and using the control unit to control the reference amplifier and the operational amplifier based on the combined signal. Some embodiments include configuring the reference amplifier such that at least a portion (reference portion) of a characteristic of the reference amplifier coincides with a portion of a characteristic of the operational amplifier, wherein the reference portion includes an operating point of the operational amplifier.At least one effect may be that an amplification of a signal by the reference amplifier when it is operated in the reference section of the characteristic of the reference amplifier is like the amplification of a signal by the operational amplifier when it is operated at the operating point of the characteristic of the operational amplifier.

[0065] Some embodiments include timing a clocked control circuit so as to time a switching of a reference amplifier signal input terminal between coupling to a reference input terminal of the operational amplifier and coupling to a sensing input terminal of the operational amplifier.

[0066] This description describes, in one aspect, circuitry comprising an operational amplifier and a reference amplifier, according to some embodiments. The circuitry further comprises a control unit configured to control the reference amplifier based on a signal received from the operational amplifier. In some embodiments, the control unit is configured to control the operational amplifier based on a signal received from the reference amplifier. The control unit is coupled to the reference amplifier and to the operational amplifier. In some embodiments, the signal input terminal of the control unit is coupled to a signal output terminal of the operational amplifier, and a control output terminal of the control unit is coupled to a control input terminal of the reference amplifier.

[0067] Some embodiments include a switch coupled to a signal input terminal end of the reference amplifier. In some embodiments, the switch is configured to couple the signal input terminal end of the reference amplifier to either a reference terminal end of the reference amplifier or a strobe signal terminal end of the operational amplifier. In some embodiments, the switch is coupled to the control unit. In some embodiments, the switch is configured to receive a switching control signal from the control unit.At least one effect may be that the control unit can put the reference amplifier into either a self-calibration mode or an operational calibration mode by setting the signal input terminal of the reference amplifier to the same voltage as the reference terminal of the reference amplifier in the self-calibration mode, and by setting the signal input terminal of the reference amplifier to the same voltage as the sense terminal of the operational amplifier in the operational calibration mode.

[0068] In some embodiments, the control unit is configured to receive a reference amplifier output signal to derive a reference control signal for use in controlling the reference amplifier. In some embodiments, the control unit is configured to receive an operational amplifier output signal and derive an operational control signal for use in controlling the operational amplifier. In some embodiments, the operational amplifier output signal is provided as a voltage between a signal output terminal of the operational amplifier and a signal output terminal of the reference amplifier. At least one effect may be that the control signal used in controlling the operational amplifier is based on a voltage difference that, if the reference amplifier is calibrated, indicates a lack of calibration of the operational amplifier.

[0069] Some embodiments include an analog-to-digital converter coupled between a signal output of the reference amplifier and a signal input of the control unit. At least one effect may be that the analog signal output from the signal output terminal of the reference amplifier can be assigned to either one or the other of two states. Thus, an analog signal output from the signal output terminal of the reference amplifier can be represented by a sequence of bits. In some embodiments, the analog-to-digital converter includes an inverter. At least one effect may be that a single inverter can provide a digital signal representing 1 bit of information at a time. Thus, the inverter can implement a 1-bit analog-to-digital converter.

[0070] Some embodiments include a register coupled to the control unit. In some embodiments, the register is configured to hold a digital representation of a signal for use in controlling the operational amplifier and / or for use in controlling the reference amplifier. At least one effect may be that the register can store data of a setting of the operational amplifier and / or the reference amplifier for use in initializing the operational amplifier and / or for use in operating the operational amplifier.

[0071] In some embodiments, the reference amplifier and the operational amplifier are configured to have the same characteristic curve. In some embodiments, the reference amplifier and the operational amplifier are configured according to a same structural design of the electrical elements. At least one effect may be that the reference amplifier operates substantially the same as the operational amplifier. Accordingly, the reference amplifier and the operational amplifier have the same characteristic curve with each other. At every point on the characteristic curve, the reference amplifier and the operational amplifier operate in the same way.Thus, if corresponding input terminals of the reference amplifier and the operational amplifier are set to the same voltage level, then to the extent that both the reference amplifier and the operational amplifier are calibrated, a reference output voltage signal at the output terminal of the reference amplifier and an operating output voltage signal at the output terminal of the operational amplifier are the same.

[0072] In some embodiments, the control unit is provided with a clock terminal. In some embodiments, the control unit is configured to use a clock signal received at the clock terminal when controlling the calibration of the reference amplifier.

[0073] In some embodiments, the reference amplifier and the operational amplifier are integrated using the same layout. At least one effect may be that both the reference amplifier and the operational amplifier have the same characteristic and, accordingly, operate in the same way.

[0074] In some embodiments, the control unit is provided as a programmable arithmetic logic unit. At least one effect may be that the control unit flexibly provides control functionality so that, for example, the operation of the reference amplifier can be controlled to meet operational requirements such as a priority regarding power saving or a priority regarding the accuracy of the signal amplification during operation. Where the operational amplifier is to be implemented to cooperate with a programmable arithmetic logic unit provided for other functions, then the programmable arithmetic logic unit can be programmed to also control the operational amplifier as disclosed herein.Thus, savings in chip area can be achieved when compared to a case where dedicated circuitry is used for controlling the operational amplifier. In some embodiments, the control unit is provided as a state machine. At least one effect may be that the control unit provides control functionality while using fewer resources, such as chip area, than in a case where the control unit is provided as an arithmetic logic unit.

[0075] Some embodiments include at least one further reference amplifier. In some embodiments, the characteristic curve of the at least one further reference amplifier differs from the characteristic curve of the operational amplifier. At least one effect may be that different reference amplifiers can be configured to operate at different operating points while being configured to consume fewer resources overall, such as chip area and / or power, than a single reference amplifier whose structure is based on the same design as that underlying the operational amplifier.The characteristic of each reference amplifier at the operating point of the reference amplifier may be similar to the characteristic of the operational amplifier at the operating point of the reference amplifier such that the reference amplifiers as a whole may cooperate to create a reference characteristic over a longer portion of the operational amplifier characteristic than a single reference amplifier would.

[0076] This description describes, in one aspect, according to some embodiments, an integrated circuit chip comprising an operational amplifier and a reference amplifier. The integrated circuit chip further comprises a control unit. In some embodiments, the control unit is coupled to the reference amplifier and to the operational amplifier. The control unit is configured to control the operational amplifier based on a combination of a signal received from the reference amplifier and a signal received from the operational amplifier. In some embodiments, the control unit is configured to control the reference amplifier based on the signal received from the reference amplifier. In some embodiments, a signal input terminal of the control unit is coupled to a signal output terminal of the operational amplifier.In some embodiments, a control output terminal of the control unit is coupled to a control input terminal of the reference amplifier.

[0077] Some embodiments include a switch coupled to a signal input terminal of the reference amplifier. In some embodiments, the switch is configured to switch a signal input terminal of the reference amplifier for coupling to either a reference terminal of the reference amplifier or a keying signal terminal of the operational amplifier. In some embodiments, the switch is coupled to the control unit. In some embodiments, the switch is configured to receive a switch control signal from the control unit.

[0078] In some embodiments, the control unit is configured to receive a reference amplifier output signal derived from a reference control signal for use in controlling the reference amplifier. In some embodiments, the control unit is configured to receive an operational amplifier output signal to derive an operational control signal for use in controlling the operational amplifier. In some embodiments, the operational amplifier output signal is combined with the reference amplifier output signal to form a combined signal. In some implementations, combining is forming a voltage difference signal that indicates or represents a voltage difference, in some examples, between the voltage at the output terminal of the operational amplifier and the voltage at the output of the reference amplifier.

[0079] Some embodiments include an analog-to-digital converter coupled between a signal output of the reference amplifier and a signal input of the control unit. In some embodiments, the analog-to-digital converter includes an inverter. At least one effect may be that a single inverter can provide digital signals representing 1 bit of information at a time. Thus, the inverter forms a 1-bit analog-to-digital converter. Some embodiments include more than one inverter to form a multi-bit analog-to-digital converter.

[0080] Some embodiments include at least one register coupled to the control unit. In some embodiments, the register is configured to hold a digital representation of a signal for use in controlling the operational amplifier and / or for use in controlling the reference amplifier. At least one effect may be that a digital representation of control information may be stored in the register as operational amplifier calibration data to place the operational amplifier in a calibrated state. Similarly, a digital representation of control information may be stored in the register as reference amplifier calibration data to place the reference amplifier in a calibrated state.In some implementations, the control unit is configured to read the calibration data from the memory, for example when powering up the integrated circuit chip or when turning on a circuit portion of the integrated circuit chip that includes the operational amplifier, in order to use the reference calibration data at least when controlling the reference amplifier, for example immediately after turning on, and / or the operational calibration data at least when controlling the operational amplifier, for example immediately after turning on.

[0081] In some embodiments, the reference amplifier and the operational amplifier are configured to have the same characteristic curve. In some embodiments, the reference amplifier and the operational amplifier are configured according to a similar design with respect to the structure of electrical elements.

[0082] In some embodiments, the control unit is provided with a clock terminal. In some embodiments, the control unit is configured to use a clock signal in controlling the calibration of the at least one reference amplifier. In some embodiments, the control unit is configured to use the clock signal alternately in controlling the calibration of the operational amplifier.

[0083] In some embodiments, the control unit is provided as a programmable arithmetic logic unit. In some embodiments, the control unit is provided as a state machine. Some embodiments include at least one further reference amplifier. In some embodiments, a characteristic curve of the at least one further reference amplifier differs from the characteristic curve of the operational amplifier.

[0084] Some or all of the method steps described herein may be performed by (or using) a hardware device such as a microprocessor, a programmable computer, or an electronic circuit. Some embodiments include a processing means, such as a computer or a programmable logic device, configured or adapted to perform any of the methods described herein. In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein.In general, any device capable of implementing a state machine capable of implementing the type of method described and illustrated herein may be used to implement the various methods, protocols, and techniques according to the implementations. In some embodiments, a field-programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. In general, the methods may be performed by any hardware device. Some embodiments include a storage medium having electronically readable control signals capable of interacting with a programmable computer system to perform any of the methods described herein.Arrangements, procedures, and protocols of the described implementations may be implemented on a special-purpose computer, a programmable microprocessor or microcontroller and peripheral integrated circuit element(s), an ASIC or other integrated circuit, a digital signal processor, a flashable device, a hard-wired electronic or logic circuit such as a discrete element circuit, a programmable logic device such as a PLD, PLA, FPGA, PAL, a modem, a transceiver, any comparable device, or the like. The disclosed arrangements may be implemented in part or in whole in hardware using logic circuitry or VLSI design.

[0085] In some embodiments, well-known features are omitted or simplified to clarify the description of the example implementations. The implementations are described herein as example embodiments. However, it should be understood that individual aspects of the implementations may be claimed separately, and one or more features of the various embodiments may be combined. Although some aspects are described in the context of an apparatus, those aspects represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block, piece, or feature of a corresponding apparatus.Example implementations / embodiments discussed herein may include various components in a common arrangement; however, it should be understood that the components of the arrangements may be combined in one or more devices.

[0086] As used herein, the articles “a” and “an” should generally be construed to mean “one or more” unless otherwise specified or the context makes it clear that they refer to the singular.

[0087] As used herein, the terms "comprising," "including," "having," or variations thereof, and similar terms are open-ended terms intended to encompass. These terms indicate the presence of specified elements or features, but do not preclude additional elements or features.

[0088] As used herein, the word "exemplary" means serving as an example, embodiment, or illustration. Any aspect or design described herein as "exemplary" should not necessarily be construed as being preferred or advantageous over other aspects or designs. Rather, the use of the word exemplary is intended to present concepts and techniques in a concrete manner. The terms "techniques" may refer to, for example, one or more devices, apparatuses, systems, methods, articles of manufacture, and / or computer-readable instructions, as indicated by the context described herein.

[0089] As used herein, terms such as “first,” “second,” and the like are also used to describe various elements, regions, sections, etc., and are not intended to be limiting.

[0090] As used herein, the phrase "enhancing a signal" encompasses a meaning such as a common meaning of amplifying a signal amplitude, but also encompasses, as appropriate in a particular implementation, attenuating the signal amplitude or keeping the signal amplitude the same.

[0091] As used herein, the terms "coupled" and "connected" may be used to describe how different elements at an interface behave with each other. Unless explicitly stated or at least otherwise implied, such interface behavior of different elements may be direct or indirect.

[0092] As used herein, the phrase "A coupled to B" means an ability of A to provide C to B, provided B is capable of accepting C, where C is a signal, energy, message, or other abstract or concrete thing described in the context of the phrase, as the case may be.

[0093] As described herein, the term “terminal” refers to a conductive line or other circuit element or circuit arrangement configured to interconnect coupled components.

Claims

[1] A method for use in signal processing, comprising - providing an amplifier block (110, 310), - Providing a calibration block (120, 320), - coupling a control block (130, 330) to the amplifier block (110, 310) and to the calibration block (120, 320), - combining a signal output by the amplifier block (110, 310) and a signal output by the calibration block (120, 320) to obtain a combined signal, - using the control block (130, 330) to control the calibration block (120, 320) and the amplifier block (110, 310) based on the combined signal; and - clocking the control circuit (130, 330) so as to time a switching of a calibration block signal input terminal end between coupling to a reference input terminal end of the amplifier block (110, 310) and coupling to a sample input terminal end of the amplifier block (110, 310). [2] Circuit arrangement for use in signal processing, comprising - an amplifier block (110, 310), - a calibration block (120, 320), and - a control block (130, 330) configured to control the calibration block (120, 320) based on a combination of a signal received from the amplifier block (110, 310) and a signal received from the calibration block (120, 320); and - a switch (140, 340) coupled to a signal input terminal end of the reference amplifier (120, 320), wherein the switch is configured to couple the signal input terminal end of the calibration block (120, 320) to either a reference terminal end of the reference amplifier (120, 320) or to a key terminal end of the amplifier block (110, 310). [3] The circuit arrangement of claim 2, wherein the switch (140, 340) is coupled to the control block (130, 330), and wherein the switch (140, 340) is configured to receive a switching control signal from the control block (130, 330). [4] The circuit arrangement of claim 2, wherein the control block (130, 330) is configured to receive a calibration block output signal to derive a reference control signal for use in controlling the calibration block (120, 320). [5] The circuit arrangement of claim 4, wherein the control block (130, 330) is configured to receive an amplifier block output signal to derive an operation control signal for use in controlling the amplifier block (110, 310). [6] The circuit arrangement of claim 5, wherein the control block (130, 330) is configured to combine the amplifier block output signal with the calibration block output signal by forming a differential voltage signal indicative of a voltage between a signal output terminal end of the amplifier block (110, 310) and a signal output terminal end of the calibration block (120, 320). [7] The circuit arrangement of claim 2, comprising an analog-to-digital converter coupled between a signal output of the calibration block (120, 320) and a signal input of the control block (130, 330). [8] The circuit arrangement of claim 2, wherein the analog-to-digital converter comprises an inverter. [9] The circuit arrangement of claim 2, comprising a register coupled to the control block (130, 330), the register being configured to hold a digital representation of a signal for use in controlling the amplifier block (110, 310) and / or for use in controlling the calibration block. [10] The circuit arrangement of claim 2, wherein the control block (130, 330) is provided with a clock terminal end, the control block (130, 330) being configured to use a clock signal received at the clock terminal end in controlling the calibration block (120, 320). [11] The circuit arrangement of claim 2, comprising at least one further calibration block, wherein a characteristic curve of the at least one further calibration block (120, 320) differs from the characteristic curve of the amplifier block (110, 310). [12] Integrated circuit chip for use in processing signals, comprising: - an amplifier block (110, 310), - a calibration block (120, 320), - a control block (130, 330) configured to be coupled to the calibration block (120, 320) and to the amplifier block (110, 310), and a switch (140, 340) coupled to a signal input terminal end of the calibration block (120, 320); wherein the control block (130, 330) is configured to control the amplifier block (110, 310) based on a combination of a signal received from the calibration block (120, 320) with a signal received from the amplifier block (110, 310), and wherein the switch (140, 340) is configured to have a signal input terminal end of the Reference amplifier (120, 320) for coupling either to a reference terminal end of the calibration block (120, 320) or to a Switch the key signal connection end of the amplifier block (110, 310). [13] The integrated circuit chip of claim 12, wherein the control block (130, 330) is configured to receive a calibration block output signal and derive a reference control signal for use in controlling the calibration block (120, 320). [14] The integrated circuit chip of claim 12, comprising an analog-to-digital converter coupled between a signal output of the calibration block (120, 320) and a signal input of the control block (130, 330). [15] The integrated circuit chip of claim 12, comprising a register coupled to the control block (130, 330), the register configured to hold a digital representation of a signal for use in controlling the amplifier block (110, 310) and / or for use in controlling the calibration block (120, 320). [16] The integrated circuit chip of claim 12, wherein the control block (130, 330) is provided with a clock connection end, wherein the control block (130, 330) is configured to use a clock signal in controlling the calibration of the at least one calibration block (120, 320), and wherein the control block (130, 330) is configured to use the clock signal alternately in controlling the calibration of the amplifier block (110, 310).

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