Semiconductor device and method for manufacturing the semiconductor device

Abstract

Semiconductor device, comprising: a first semiconductor die (103) bonded to a second semiconductor die (102), a contact etch stop layer (201) which is in physical contact with at least three sides of the first semiconductor die and one upper surface of the second semiconductor die, a dielectric material (203) located on the opposite side of the contact etch stop layer from the second semiconductor die and having an upper surface that is flush with the contact etch stop layer, a first via (903) extending through the contact etch stop layer and the first semiconductor die, and a second via (905) extending through the dielectric material and the contact etch stop layer.

Description

GENERAL STATE OF THE ART

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density stems from repeated reductions in the minimum feature size (e.g., a reduction in the semiconductor technology node toward the sub-20 nm node), allowing more components to be integrated into a given area. As the demand for miniaturization, higher speed and wider bandwidth, as well as lower power consumption and lower latency, has increased in recent years, the requirement for smaller and more creative semiconductor die packaging technologies has increased.

[0002] With the continued advancement of semiconductor technologies, stacked semiconductor devices, such as 3D integrated circuits (3DICs), have been used as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits, such as logic, memory, processor circuits, and the like, are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be mounted on top of each other to further reduce the form factor of the semiconductor device.

[0003] Two semiconductor wafers or dies can be bonded together using suitable bonding techniques. Commonly used bonding techniques include direct bonding, chemically activated bonding, plasma-activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompressive bonding, reactive bonding, and / or the like. An electrical connection can be provided between the stacked semiconductor wafers. The stacked semiconductor devices can provide higher density with smaller form factors, enabling increased performance and lower power consumption.

[0004] US 2011 / 0 175 215 A1 discloses a semiconductor device comprising a first semiconductor die, a second semiconductor die, two vias, an etch stop layer, and a dielectric material arranged on the surface of the first semiconductor die. Further prior art relating to the subject matter of the invention can be found, for example, in US 2010 / 0 218 818 A1, US 2007 / 0 045 814 A1, US 2012 / 0 193 814 A1, and US 2008 / 0 116 584 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 illustrates a first semiconductor device, a second semiconductor device, and a third semiconductor device bonded to a first wafer according to some embodiments. Fig. 2 illustrates disposing an etch stop layer and a dielectric material over the first semiconductor device, the second semiconductor device, and the third semiconductor device, according to some embodiments. Fig. 3 illustrates a planarization process and disposing an anti-reflective coating and an interlayer according to some embodiments. Fig. 4 illustrates disposing a first photoresist according to some embodiments. Fig. 5A to 5C illustrate a sequence of etches performed using the first photoresist as a mask, according to some embodiments. Fig. 6 illustrates removal of a first photoresist according to some embodiments. Fig. 7 illustrates deposition of a liner material according to some embodiments. Fig. 8 illustrates etching of the liner material according to some embodiments. Fig. 9 illustrates forming silicon vias according to some embodiments. Fig. 10 illustrates singulating the first wafer according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0008] With reference to Fig. 1 shows a first wafer 101 with a first semiconductor device 103, a second semiconductor device 105, and a third semiconductor device 107 bonded to the first wafer 101 in a chip-on-wafer (CoW) bonding arrangement. In one embodiment, the first wafer 101 includes a first substrate 109, a first active device layer 111, first metallization layers 113, a first passivation layer 114, and first contact pads 115.

[0009] In one embodiment, the first substrate 109, the first active component layer 111, the first metallization layers 113, the first passivation layer 114, and the first contact pads 115 are fabricated to form, for example, a fourth semiconductor device 102, a fifth semiconductor device 104, and a sixth semiconductor device 106. The fourth semiconductor device 102 is configured to operate, for example, together with the first semiconductor device 103, the fifth semiconductor device 104 is configured to operate together with, for example, the second semiconductor device 105, and the sixth semiconductor device 106 is configured to operate together with, for example, the third semiconductor device 107.

[0010] The first substrate 109 may comprise doped or undoped bulk silicon or an active layer of an SOI (silicon on an insulator) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon germanium on an insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, glass substrates, ceramic substrates, or hybrid orientation substrates.

[0011] The optional first active device layer 111 within the first wafer 101 may include a wide variety of active devices and passive devices, such as transistors, capacitors, resistors, inductors, and the like, that can be used to implement the desired structural and functional design requirements for the first wafer 101. The active devices within the first wafer 101 may be formed using any suitable methods either within or otherwise on the first substrate 109.

[0012] The first metallization layers 113 are formed over the first substrate 109 and, if present, the active devices within the first active device layer 111, and they can be used, for example, to connect the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107, which are subsequently attached, to the active devices within the active device layer 111. In one embodiment, the first metallization layers 113 are formed from alternating layers of a dielectric and a conductive material and can be formed using any suitable process (such as deposition, damascene, dual damascene, etc.).In one embodiment, four metallization layers may be present, but the exact number of layers of dielectric and conductive material depends on the configuration of the fourth semiconductor device 102, the fifth semiconductor device 104, and the sixth semiconductor device 106.

[0013] The first contact pads 115 may be formed over and in contact with the first metallization layers 113 to provide external connections for the fourth semiconductor device 102, the fifth semiconductor device 104, and the sixth semiconductor device 106. The first contact pads 115 are formed from a conductive material, such as aluminum, although other suitable materials, such as copper, tungsten, or the like, may alternatively be used. The first contact pads 115 may be formed using a process such as CVD, although other suitable materials and methods may alternatively be used. After the material for the first contact pads 115 has been deposited, the material may be formed into the first contact pads 115 using, for example, a photolithographic masking and etching process.

[0014] The first passivation layer 114 may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. The first passivation layer 114 may be formed using a process such as chemical vapor deposition (CVD), although any suitable process may be used, and it may have a thickness between about 0.5 µm and about 5 µm, such as about 9.25 kÅ. After being formed, the first passivation layer 114 may be patterned using a photolithographic masking and etching process to expose at least a portion of the first contact pads 114.

[0015] The first semiconductor device 103 may include a second substrate 117, a second active device layer 119, second metallization layers 121, a second passivation layer 122, and second contact pads 123. In one embodiment, the second substrate 117, the second active device layer 119, the second metallization layers 121, the second passivation layer 122, and the second contact pads 123 may be similar to the first substrate 109, the first active device layer 111, the first metallization layers 113, the first passivation layer 114, and the first contact pads 115 (described above), although they may alternatively be different. However, in this embodiment, the first semiconductor device 103 has already been singulated into a single chip prior to bonding.

[0016] The second semiconductor device 105 may include a third substrate 125, a third active device layer 127, third metallization layers 129, a third passivation layer 130, and third contact pads 131. In one embodiment, the third substrate 125, the third active device layer 127, the third metallization layers 129, the third passivation layer 130, and the third contact pads 131 may be similar to the first substrate 109, the first active device layer 111, the first metallization layers 113, the first passivation layer 114, and the first contact pads 115 (described above), although they may alternatively be different. However, in this embodiment, the second semiconductor device 105 has already been singulated into a single chip prior to bonding.

[0017] The third semiconductor device 107 may include a fourth substrate 133, a fourth active device layer 135, fourth metallization layers 137, a fourth passivation layer 138, and fourth contact pads 139. In one embodiment, the fourth substrate 133, the fourth active device layer 135, the fourth metallization layers 137, the fourth passivation layer 138, and the fourth contact pads 139 may be similar to the first substrate 109, the first active device layer 111, the first metallization layers 113, the first passivation layer 114, and the first contact pads 115 (described above), although they may alternatively be different. However, in this embodiment, the third semiconductor device 107 has already been singulated into a single chip prior to bonding.

[0018] In one embodiment, the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 are manufactured using similar designs and similar processes. However, due to process variations, the exact thickness of each of the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 may be imprecise. For example, as shown in Fig. 1, the third semiconductor device 107 may have a total thickness greater than either that of the first semiconductor device 103 or that of the second semiconductor device 105.

[0019] The first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 may be bonded to the first wafer 101, for example, using a fusion bonding process. In one embodiment, the fusion bonding process may be initiated by subjecting the first wafer 101, where the bonds are desired, to an initial cleaning process. In a particular embodiment, the first wafer 101 may be cleaned, for example, using a wet cleaning process, such as an SC-1 or SC-2 cleaning process, to form a hydrophilic surface.After cleaning, the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 are aligned into their respective desired positions on the first wafer, and the hydrophilic surface is brought into physical contact with the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 to begin the bonding procedure. After the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 have been contacted to the first wafer 101, a thermal anneal can be used to solidify the bonds.

[0020] However, the description of the fusion bonding described above is merely an example of one type of process that may be used to bond the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 to the first wafer 101 and is not intended to be limiting with respect to the embodiments. Rather, any suitable bonding process may alternatively be used to bond the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 to the first wafer 101, and all such processes are intended to be fully encompassed by the embodiments.

[0021] Fig. 2 illustrates disposing a contact etch stop layer (CESL) 201 and depositing a dielectric material 203 over the first semiconductor device 103, the second semiconductor device 105, the third semiconductor device 107, and the first wafer 101. The CESL 201 is used to protect the first semiconductor device 103, the second semiconductor device 105, the third semiconductor device 107, and the first wafer 101 from damage caused by further processing and to provide a checkpoint for further etching processes. In one embodiment, the CESL 201 may be formed from silicon nitride using plasma-enhanced chemical vapor deposition (PECVD), although alternatively, other materials, such as nitride, oxynitride, carbide, boride, combinations thereof, or the like, and alternative techniques for forming the CESL 201, such asLow-pressure CVD (LPCVD), PVD, or the like may be used. The CESL 201 may have a thickness of between about 50 Å and about 2000 Å, such as about 200 Å.

[0022] After the CESL 201 has been formed, the dielectric material 203 may be formed over the CESL 201 and between the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. In one embodiment, the dielectric material 203 may be a material such as silicon oxide, silicon oxynitride, a high-k dielectric material, combinations of these, or the like, with an etch selectivity different from that of the CESL 201, such that the dielectric material 203 and the CESL 201 may act as etch stop materials with respect to each other. Furthermore, the dielectric material 203 may be formed using a deposition process such asChemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), combinations of these, or the like, although any suitable manufacturing method, which may be specific to the particular material, may alternatively be used. In one embodiment, the dielectric material 203 may be deposited to a thickness of between about 1 μm and about 10 μm, such as about 6 μm.

[0023] Fig. 3 illustrates planarizing the dielectric material 203 with the CESL 201. In one embodiment, the planarization process is one or more chemical mechanical polishing processes (which are described in Fig. 3 are represented by the plate labeled 300), in which etching agents and abrasives are applied to the dielectric material 203, and the dielectric material 203 is ground with a plate to planarize and remove the dielectric material 203. The CESL 201 also acts as a planarization stop layer, so that the planarization process planarizes the dielectric material 203 with the CESL 201.

[0024] However, as one of ordinary skill in the art will appreciate, the chemical-mechanical polishing process described above is intended to serve merely as an example and is not intended to be limiting with respect to the embodiments. Rather, any suitable planarization process, such as a physical grinding process or a series of one or more etches, may alternatively be used. All such processes are intended to be fully encompassed within the scope of the embodiments.

[0025] Fig. 3 also illustrates a bottom anti-reflective coating (BARC) layer 301 and an interlayer 303 that may be formed over the planarized CESL 201 and the planarized dielectric material 203. In one embodiment, the BARC layer 301 is formed over the planarized CESL 201 and the dielectric material 203 in preparation for the application of a first photoresist 401 (in Fig. 3 not shown, but below with reference to Fig. 4). The BARC layer 301 operates, as the name suggests, to prevent the uncontrolled and unwanted reflection of energy (e.g., light) back into the overlying first photoresist 401 during exposure of the first photoresist 401, thereby preventing the reflected light from causing reactions in an unwanted area of ​​the first photoresist 401.

[0026] In one embodiment, the BARC layer 301 comprises a polymer resin having a chromophore moiety, a catalyst, and a crosslinker, all added for dissolution into a BARC solvent. The crosslinking monomer may be used to crosslink the monomer with other polymers within the polymer resin to alter the solubility of the BARC layer 301 and may optionally include an acid-labile group. The catalyst may be a compound used to generate a chemically active species and initiate a crosslinking reaction between the polymers within the polymer resin and may be, for example, a thermal acid generator, a photoacid generator, or a photobase generator, or combinations of these or the like. The BARC layer 301 may be used by first coating the material for the BARC layer 301 onto the planarized CESL 201 and the planarized dielectric material 203, for example,applied using a spin-coating process or the like. In one embodiment, the material for the BARC layer 301 may be applied to have a thickness over a top surface of the planarized CESL 201 and the planarized dielectric material 203 of between about 50 nm and about 500 nm, such as 300 nm.

[0027] The interlayer 303 may be disposed over the BARC layer 301. In one embodiment, the interlayer 303 is a hard mask material, such as silicon nitride, oxides, oxynitrides, silicon carbide, combinations of these, or the like. The hard mask material for the interlayer 303 may be formed using a process such as chemical vapor deposition (CVD), although other processes such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), spin-coating, or even silicon oxide formation followed by nitriding may alternatively be used. Any suitable method or combination of methods for forming or otherwise disposing the interlayer 303 may be used, and all such methods or combinations are intended to be fully encompassed within the scope of the embodiments.The intermediate layer 303 may be formed to a thickness of between about 10 nm and about 80 nm, such as 30 nm.

[0028] Fig. 4 also illustrates disposing and patterning the first photoresist 401 over the intermediate layer 303. In one embodiment, the first photoresist 401 is a photosensitive material and may be disposed, e.g., using a spin-coating technique, on the intermediate layer 303 to a height of between approximately 50 µm and approximately 250 µm, such as approximately 120 µm. After disposing, the first photoresist 401 may then be patterned by exposing the first photoresist 401 to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction, thereby inducing a physical change in those portions of the first photoresist 401 exposed to the patterned light source.A developer is then applied to the exposed first photoresist 401 to utilize the physical changes and selectively remove either the exposed portion of the first photoresist 401 or the unexposed portion of the first photoresist 401, depending on the desired structure.

[0029] The first photoresist 401 is patterned to form first openings 403 over the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. In one embodiment, the first openings 403 are used to form a conductive connection through the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. The first openings 403 may be formed to have a first diameter D1 of between approximately 1 µm and approximately 10 µm, such as 6 µm. However, any suitable dimensions and shapes for the first openings 403 may alternatively be used.

[0030] The first photoresist 401 is further patterned to form second openings 405 over the dielectric material 203, which are arranged between the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. The second openings 405 are used to form conductive vias through the dielectric material 203 between the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. In one embodiment, the second openings 405 may be formed to have a second diameter D2 of between approximately 1 µm and approximately 10 µm, such as 6 µm. However, any suitable dimensions and shapes for the second openings 405 may alternatively be used.

[0031] Fig. Figure 5A shows that a first etching process (in Fig. 5A by the arrows labeled 501) after the first photoresist 401 has been disposed and patterned. In one embodiment, the first etch process 501 is an anisotropic etch process that uses the first photoresist 401 as a mask. The first etch process 501 is used to transfer the pattern of the first openings 402 and the second openings 405 to the interlayer 303, the BARC layer 301, and, if present directly beneath the BARC layer 301, to the CESL 201.

[0032] In one embodiment, the first etch process 501 may be performed using etchant and process conditions that extend the first openings 403 to extend through the interlayer 303, the BARC layer 301, and the CESL 201. Although the specific etchants and process conditions depend at least in part on the materials chosen for the interlayer 303, the BARC layer 301, and the CESL 201, in one embodiment, the first etch process 501 may generally use an etchant, such as CF4 or C4F8, at a temperature of between about 0°C and about 20°C, such as about 10°C, and a pressure of between about 10 mTorr and about 150 mTorr, such as about 60 mTorr. In addition, the RF power can be set between about 1200 W and about 2500 W, such as about 1600 W, and the bias can be set between about 800 W and about 2500 W, such as 2000 W.However, any suitable process conditions may be used alternatively.

[0033] However, although the first etch process 501 is used to etch through the interlayer 303, the BARC layer 301, and the CESL 201 where they are exposed through the first openings 403, the first etch process 501 does not etch through the second openings 405 in the same way. In particular, since the dielectric material 203 has a different etch selectivity than the CESL 201, the first etch process 501 removes the interlayer 303 and the BARC layer 301 through the second openings 405, but does not remove the dielectric material 203 after the dielectric material 203 has been exposed. In other words, the dielectric material 203 serves as an etch stop for the first etch process 501.Therefore, the first etch process 501 extends the structure of the second openings 405 such that they extend through the interlayer 303 and the BARC layer 301, but it does not substantially remove the dielectric material 203 and it does not remove the CESL 201 underlying the dielectric material 203.

[0034] Fig. 5B illustrates a second etch process (represented by the arrows labeled 503) in which the pattern of the second openings 405 is extended to extend through the dielectric material 203. However, the second etch process 503 is also performed such that it does not substantially etch the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107. In particular, the second etch process 503 is performed such that it selectively etches the dielectric material 203 and stops at the CESL 201 disposed beneath the dielectric material 203, but does not substantially etch the second substrate 117, the third substrate 125, or the fourth substrate 133 exposed by the first openings 403 in the first etch process 501.

[0035] In one embodiment, the second etch process 503 may be performed using etchant and process conditions that extend the second openings 405 to extend through the dielectric material 203. Although the specific etchants and process conditions depend at least in part on the materials chosen for the dielectric material 203, in one embodiment, the second etch process 503 is fundamentally an anisotropic etch process and may use an etchant, such as CF4 or C4F8, at a temperature of between about 0°C and about 20°C, such as about 10°C, and a pressure of between about 10 mTorr and about 150 mTorr, such as about 60 mTorr. Furthermore, the RF power may be set to between about 1200 W and about 2500 W, such as about 1600 W, and the bias may be set to between about 800 W and about 2500 W, such as 2000 W.However, any suitable process conditions may be used alternatively.

[0036] Fig. Figure 5C shows a third etching process (which is Fig. 5C by the arrows labeled 505). In one embodiment, the third etch process 505 is used to etch through the second substrate 117 (of the first semiconductor device 103), the third substrate 125 (of the second semiconductor device 105), and the fourth substrate 133 (of the third semiconductor device 107) exposed by the first openings 403. However, the third etch process 505 does not etch through the CESL 201 disposed beneath the dielectric material 203 and exposed by the second openings 405.

[0037] In one embodiment, the third etch process 505 may be performed using etchant and process conditions that extend the first openings 403 to extend through the second substrate 117, the third substrate 125, and the fourth substrate 133, and also through the second active device layer 119, the third active device layer 127, and the fourth active device layer 135, and partially into the second metallization layer 121, the third metallization layer 129, and the fourth metallization layer 137. Although the specific etchants and process conditions depend at least in part on the materials chosen for these layers, in one embodiment, the third etch process 505 is fundamentally an anisotropic etch process and may utilize an etchant, such as SF6 or Ar, at a temperature of between approximately -10°C and approximately 10°C, such asapproximately 3 °C, and a pressure of between approximately 10 mTorr and approximately 100 mTorr, such as approximately 60 mTorr. Furthermore, the RF power can be set to between approximately 1000 W and approximately 5000 W, such as approximately 3000 W, and the bias can be set to between approximately 50 V and approximately 1000 V, such as 100 V. However, any suitable process conditions may alternatively be used.

[0038] In one embodiment, the first etch process 501, the second etch process 503, and the third etch process 505 may be performed within a single etch chamber without breaking the vacuum and exposing the structure to the ambient atmosphere. However, alternative etch chambers, or even other clustered devices, may also be used. Any number or combination of devices may be used, and all such combinations are intended to be fully encompassed within the scope of the embodiments discussed herein.

[0039] Fig. 6 illustrates a removal of the first photoresist 401 and a cleaning process after removal. In one embodiment, the first photoresist 401 may be removed, for example, using an ashing process in which a temperature of the first photoresist 401 is increased until the first photoresist 401 is thermally decomposed and can be easily removed. However, any other removal process may alternatively be used.

[0040] After the ashing process is performed, the structure may be cleaned using a first cleaning process to assist in removing the first photoresist 401. In one embodiment, the cleaning step may include immersing the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 in an etchant to ensure that any remaining portions of the photoresist 401 are removed from the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 prior to subsequent processing. For example, the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 may be immersed in an etchant, such as HF, for between approximately 10 seconds and 30 seconds, such as 20 seconds.

[0041] Fig. 7 illustrates deposition of a liner material 701 over the intermediate layer 303 and lining the first openings 403 (which now extend through the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107) and lining the second openings 405 (which now extend through the dielectric material 203). In one embodiment, the liner material 701 is a dielectric material, such as silicon oxide, silicon nitride, or the like, to separate the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107 from a subsequently formed conductive material 902 (in Fig. 7 not shown, but below with reference to Fig. 9 shown and described).

[0042] The liner material 701 may be deposited using chemical vapor deposition (CVD) or any other suitable deposition process, and may be formed to a thickness above the intermediate layer 303 of between approximately 10 nm and approximately 1000 nm, such as approximately 400 nm. Furthermore, the liner material 701 is deposited such that it lines the first openings 403 and the second openings 405, but does not fill the first openings 403 and the second openings 405. Therefore, the liner material 701 may be deposited such that it forms a third opening 703 within the first openings 403 and a fourth opening 705 within the second openings 405. In one embodiment, the third opening 703 may have a third diameter D3 of between approximately 0.6 μm and approximately 3 μm, such asabout 1.5 µm, while the fourth opening 705 may have a fourth diameter D4 of between about 0.6 µm and about 3 µm, such as about 2 µm.

[0043] Fig. 8 represents a fourth etching process (which is Fig. 8 by the arrows labeled 801). The fourth etching process 801 removes the liner material 701 located above the intermediate layer 303, as well as removes the liner material 701 from the bottom surface of the third openings 703 and the fourth openings 705, without substantially removing the liner material 701 from the sidewalls of the third openings 703 and the fourth openings 705. Such removal of the liner material 701, which leaves a portion on the sidewalls of the third openings 703 and the fourth openings 705, forms self-aligning spacers 802 along at least a portion of the sidewalls of the third openings 703 and the fourth openings 705.

[0044] Furthermore, after the liner material 701 has been removed from the bottom of the third openings 703 and the fourth openings 705, the fourth etch process 801 continues to extend the third openings 703 to extend through the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107, and exposes the first contact pads 115 on the first wafer 101. If desired, the third openings 703 may also expose the second contact pads 123 (on the first semiconductor device 103), the third contact pads 131 (on the second semiconductor device 105), and the fourth contact pads 139 (on the third semiconductor device 107).

[0045] In addition, the fourth etch process 801 also extends the fourth openings 705 to extend through the CESL 201 (initially exposed during the second etch process 503) to expose additional first contact pads 115 on the first wafer 101. Such an extension of the fourth openings 705 provides a direct path through the dielectric material 203, bypassing the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107.

[0046] In one embodiment, the fourth etch process 801 may be performed using etchant and process conditions that extend the third openings 703 and the fourth openings 705. Although the specific etchants and process conditions depend at least in part on the materials chosen for the various layers, in one embodiment, the fourth etch process 801 is fundamentally an anisotropic etch process and may use an etchant, such as CF4 or C4F8, at a temperature of between about 0°C and about 20°C, such as about 10°C, and a pressure of between about 10 mTorr and about 150 mTorr, such as about 60 mTorr. Furthermore, the RF power may be set to between about 1200 W and about 2500 W, such as about 1600 W, and the bias may be set to between about 800 W and about 2500 W, such as 2000 W.However, any suitable process conditions may be used alternatively.

[0047] Fig. 9 illustrates filling the third openings 703 and the fourth openings 705 with a conductive material 902 to form substrate vias 903 within the third openings 703 (and thus through the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107) and to form dielectric vias 905 through the dielectric material 203 (between the first semiconductor device 103 and the second semiconductor device 105, and between the second semiconductor device 105 and the third semiconductor device 107). In one embodiment, the third openings 703 and the fourth openings 705 may be filled with a barrier layer (not shown) and a conductive material 902 to form the substrate vias 903 and the dielectric vias 905. The barrier layer may be a conductive material, such asTitanium nitride, although other materials such as tantalum nitride, titanium, a dielectric, or the like may alternatively be used. The barrier layer may be formed using a CVD process such as PECDV. However, other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD) may alternatively be used. The barrier layer is formed to mimic the underlying shape of the third openings 703 and the fourth openings 705.

[0048] The conductive material 902 may comprise copper, although other suitable materials, such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be used. The conductive material 902 may be formed by depositing a seed layer and then electroplating copper on the seed layer such that the third openings 703 and the fourth openings 705 are filled and overfilled. After the third openings 703 and the fourth openings 705 are filled, excess barrier material and excess conductive material 902 outside the third openings 703 and the fourth openings 705 are removed using an abrasive process, such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0049] After the substrate vias 903 and the dielectric vias 905 have been formed, a redistribution layer 907 may be formed to either interconnect the substrate vias 903 and the dielectric vias 905 or otherwise to provide connectivity between the substrate vias 903 and the dielectric vias 905 and, for example, external terminals 909 (discussed below). In one embodiment, the redistribution layer 907 is formed by first forming a seed layer (not separately shown), for example, from a titanium-copper alloy, using a suitable formation process, such as CVD or sputtering.A second photoresist (also not shown) may then be formed to cover the seed layer, and the second photoresist may then be patterned to expose those portions of the seed layer that are located at locations where the redistribution layer 907 is desired to be located.

[0050] After the second photoresist has been formed and patterned, a conductive material for the redistribution layer, such as copper, may be formed on the seed layer using a deposition process, such as plating. The conductive material for the redistribution layer may be formed to have a thickness of between approximately 1 μm and approximately 10 μm, such as approximately 5 μm, and a width of between 5 μm and approximately 300 μm, such as 5 μm. Although the material and methods discussed herein are suitable for forming the conductive material, these materials are merely examples. Any other suitable materials, such as AlCu or Au, and any other suitable formation processes, such as CVD or PVD followed by a patterning process, may alternatively be used to form the redistribution layer 907.

[0051] After the conductive material for the redistribution layer has been formed, the second photoresist can be removed using a suitable removal process, such as ashing. After removing the second photoresist, those portions of the seed layer that were covered by the second photoresist can also be removed, for example, using a suitable etching process and using the conductive material as a mask.

[0052] The conductive material for the redistribution layer can then be replaced by a dielectric material (not separately in Fig. 9) to protect the conductive material for the redistribution layer. In one embodiment, the dielectric material may be silicon oxide or another dielectric material formed using a suitable process, such as chemical vapor deposition. After covering, the process may be repeated to form additional redistribution layers until a desired number of layers is reached.

[0053] Fig. Fig. 9 also shows that, after the redistribution layer 907 has been formed, external terminals 909 can be formed which are in electrical connection with the redistribution layer 907 in order to provide a connection possibility, for example, with external components (not separately in Fig. 9). The external connections 909 may be contact bumps, such as ball grid array bumps, microbumps, or C4 bumps (controlled collapse chip connection), and may comprise a material such as tin, or other suitable materials such as silver or copper. In one embodiment where the external connections 909 are tin solder bumps, the external connections 909 may be formed by first forming a layer of tin to a thickness of approximately 100 µm using any suitable method such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc. After a layer of tin is formed on the structure, reflow is performed to shape the material into the desired bump shapes.

[0054] Fig. 10 illustrates a singulation of the first wafer 101 into separate components. In one embodiment, the singulation may be performed using a saw blade (described in Fig. 10 by the dashed box labeled 1001) to cut through the dielectric material 203 between the first semiconductor device 103 and the second semiconductor device 105. However, the dicing process cuts through the dielectric material 203 on one side of the dielectric via 905, such that the dielectric via 905 remains within the dielectric material 203 adjacent to the first semiconductor device 103 with the structure of the first semiconductor device 103 when the first wafer 101 is singulated.

[0055] Furthermore, as one of ordinary skill in the art will appreciate, using a saw blade to dicing the first wafer 101 is merely an embodiment and is not intended to be limiting. Alternative methods for dicing the first wafer 101, such as using one or more etches to dicing the first semiconductor device 103, the second semiconductor device 105, and the third semiconductor device 107, may alternatively be used. These methods and any other suitable methods may alternatively be used to dicing the first wafer 101.

[0056] By implementing the CESL 201 together with the dielectric material 203, a single mask process utilizing the first photoresist 401 can be used to create a heterogeneous interconnect structure with both the substrate vias 903 and the dielectric vias 905. Using the CESL 201 also contributes to acting as a moisture blocker to prevent unwanted moisture penetration.

[0057] According to one embodiment, a semiconductor device is provided comprising a first semiconductor die bonded to a second semiconductor die. A contact etch stop layer is in physical contact with at least three sides of the first semiconductor die and a top surface of the second semiconductor die. A dielectric material is located on an opposite side of the contact etch stop layer than the second semiconductor die and has a top surface planar with the contact etch stop layer. A first via extends through the contact etch stop layer and the first semiconductor die, and a second via extends through the dielectric material and the contact etch stop layer.

[0058] According to another embodiment, a semiconductor device is provided comprising a first semiconductor die bonded to a second semiconductor die. A first via extends through an etch stop layer and the first semiconductor die, wherein the first semiconductor die is located between the etch stop layer and the second semiconductor die. A second via extends through a dielectric material and the etch stop layer, wherein the etch stop layer is located between the dielectric material and the second semiconductor die, wherein the dielectric material is in physical contact with the etch stop layer.

[0059] According to yet another embodiment, a method of manufacturing a semiconductor device is provided, comprising bonding a first semiconductor die and a second semiconductor die to a wafer. An etch stop layer is deposited over the first semiconductor die and the second semiconductor die. A dielectric material is deposited over the etch stop layer between the first semiconductor die and the second semiconductor die. A first etch process is performed to pattern the etch stop layer over the first semiconductor die and the second semiconductor die, but not the etch stop layer beneath the dielectric material. A second etch process is performed to form a first opening in the dielectric material. A third etch process is performed to form a second opening in the first semiconductor die. A liner material is deposited within the first opening and the second opening.The first semiconductor die below the first opening and the etch stop layer below the second opening are etched using the liner material as a mask. A remaining portion of the first opening and the second opening is filled with a conductive material.

Claims

[1] A semiconductor device comprising: a first semiconductor die (103) bonded to a second semiconductor die (102), a contact etch stop layer (201) in physical contact with at least three sides of the first semiconductor die and an upper surface of the second semiconductor die, a dielectric material (203) located on an opposite side of the contact etch stop layer than the second semiconductor die and having a top surface that is planar with the contact etch stop layer, a first via (903) extending through the contact etch stop layer and the first semiconductor die, and a second via (905) extending through the dielectric material and the contact etch stop layer. [2] The semiconductor device according to claim 1, wherein the first via (903) extends to the second semiconductor die (102). [3] A semiconductor device according to claim 1 or 2, wherein the first via (903) is at least partially lined with a dielectric material (802). [4] The semiconductor device of claim 3, wherein the dielectric material (802) covers only a portion of a sidewall of the first via. [5] A semiconductor device according to any one of the preceding claims, wherein the first via (903) is in physical contact with a first contact pad (123) within the first semiconductor die (103) and a second contact pad within the second semiconductor die (102). [6] A semiconductor device according to any one of the preceding claims, wherein the first via (903) has a first top surface, the second via (905) has a second top surface, and the first top surface is planar with the second top surface. [7] A semiconductor device according to any preceding claim, further comprising an anti-reflective layer (301) over the first semiconductor die and the dielectric material, wherein the first via extends through the anti-reflective layer. [8] A semiconductor device comprising: a first semiconductor die (103) bonded to a second semiconductor die (102), a first via (903) extending through an etch stop layer (201) and the first semiconductor die (103), wherein the first semiconductor die (103) is located between the etch stop layer (201) and the second semiconductor die (102), and a second via (905) extending through a dielectric material (203) and the etch stop layer (201), the etch stop layer (201) being located between the dielectric material (203) and the second semiconductor die (102), the dielectric material (203) being in physical contact with the etch stop layer (201). [9] The semiconductor device of claim 8, further comprising a redistribution layer (907) in electrical communication with the second via. [10] The semiconductor device of claim 9, further comprising external terminals (909) in electrical communication with the redistribution layer. [11] The semiconductor device of any one of claims 8 to 10, further comprising a liner material (802) lining the first via. [12] The semiconductor device of claim 11, wherein the liner material (802) extends along only a portion of a sidewall of the first via. [13] A semiconductor device according to any one of claims 8 to 12, wherein the first via (903) extends to the second semiconductor die. [14] A semiconductor device according to any one of claims 8 to 13, further comprising an anti-reflective layer (301) over the etch stop layer and the dielectric material. [15] A method of manufacturing a semiconductor device, the method comprising: Bonding a first semiconductor die (103) and a second semiconductor die (105) to a wafer (101), Depositing an etch stop layer (201) over the first semiconductor die and the second semiconductor die, Depositing a dielectric material (203) over the etch stop layer between the first semiconductor die and the second semiconductor die, Performing a first etching process (501) to pattern the etch stop layer above the first semiconductor die and the second semiconductor die, but not the etch stop layer below the dielectric material, Performing a second etching process (503) to form a first opening (405) in the dielectric material, Performing a third etching process (505) to form a second opening (403) in the first semiconductor die, Depositing a liner material (701) within the first opening and the second opening, Etching the first semiconductor die under the first opening and the etch stop layer under the second opening using the liner material as a mask, and Filling a remaining portion of the first opening and the second opening with a conductive material (902). [16] The method of claim 15, further comprising forming an anti-reflective layer (301) over the etch stop layer and the dielectric material prior to patterning the etch stop layer. [17] The method of claim 15 or 16, wherein etching the first semiconductor die below the first opening exposes a first contact pad (115) within the first semiconductor die (103) and also exposes a second contact pad (115) within the second semiconductor die (105). [18] The method of any one of claims 15 to 17, further comprising singulating the first semiconductor die (103) from the second semiconductor die (105) after filling the first opening and the second opening. [19] The method of any one of claims 15 to 18, further comprising planarizing the dielectric material after depositing the dielectric material. [20] The method of any one of claims 15 to 19, wherein filling a remaining portion of the first opening and the second opening with a conductive material forms a first via (903) within the first opening and a second via (905) within the second opening, and wherein the method further comprises forming a redistribution layer (907) in electrical communication with the second via.

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