METHOD FOR USE IN A MEASURING SYSTEM, AS WELL AS MEASURING SYSTEM, CONTROL UNIT AND INTERFACE THEREOF

Abstract

A method for use in a measuring system (100) comprising a barrier separating a first earth potential (101) from a second earth potential (106), the method comprising - at an interface (150) provided at the barrier, receive, on a control device side of the barrier, a clock receiving signal that represents a clock signal (CLK) and control information, - To provide, based on the clock reception signal, a control signal that represents at least the control information, - Transmission of the control signal from the interface (150) to a sensor unit (110) on the sensor side of the barrier, and - Operating the sensor unit (110) according to the control information.

Description

BACKGROUND

[0001] The concepts and embodiments disclosed herein relate to the technical field of acquiring measurement data. Typically, measurement data is obtained using a sensor unit. The sensor unit comprises a transducer coupled to the sample, which is sensitive with respect to a physical quantity to be detected. The transducer is configured to output an analog measurement signal (hereinafter also referred to as the analog sensor signal) corresponding to a quantity of the physical quantity as 'seen' by the sample.

[0002] In many applications, it is impossible to place the processing device in close proximity to the transducer. Therefore, the analog measurement signal must travel a certain distance before being processed. The longer the distance the analog measurement signal must travel, for example, along a transmission line, the more the analog measurement signal becomes distorted or otherwise degraded, for example, due to attenuation or noise on the transmission line, and the less accurately the analog measurement signal seen at the end can represent the measured quantity. Therefore, the sensor unit can include an analog-to-digital converter (ADC) located near and coupled to the transducer to receive the analog sensor signal and configured to output a digital acquisition signal that essentially represents the information acquired by the transducer.In a typical application, the sensor unit is coupled to the processing unit and configured to transmit the digital acquisition signal to the processing unit for processing. Because the transmission of digital signals is generally less susceptible to adverse effects of attenuation and noise, the digital acquisition signal received at the processing unit creates a representation of the measured quantity that is closer to the truth than a direct transmission of the analog signal from the converter to the processing unit could achieve.

[0003] Sometimes, measuring a given physical quantity requires the corresponding sensor unit to operate under harsh electrical conditions. In particular, a reference voltage, such as one provided by ground, can fluctuate significantly. Therefore, a barrier can be provided to electrically isolate the sensor unit from the control unit. At this barrier, a sensor reference voltage, hereinafter also referred to as the sensor ground potential, used for acquiring measurement data, and a control reference voltage, hereinafter also referred to as the control unit ground potential, used for processing acquired data, are separated.

[0004] Interfaces to communicate across barriers that effectively separate electrical conditions on the control unit side from the harsh electrical conditions on the sensor unit side require significant technical and qualitative effort.

[0005] DE 10 2012 019 781 A1 discloses a system for synchronizing measurements of analog-to-digital converters. According to one aspect, a driver for a switch is provided, wherein the driver comprises a primary side with a trigger input and a secondary side with an analog-to-digital converter (ADC), wherein the primary side and the secondary side are separated by means of a galvanic isolator and communicate with each other via communication means, wherein the primary side is configured to receive a trigger signal at the trigger input and forwards the trigger signal via the communication means to the ADC of the secondary side of the driver, and the ADC is configured to start a measurement upon receipt of the trigger signal.

[0006] DE 602 02 557 T2 discloses an isolated analog-to-digital converter system with at least two channels, wherein the isolated analog-to-digital converter system comprises: a first and a second analog-to-digital converter for receiving respective analog input signals and for outputting respective digital data signals; and a first and a second calibration resistor coupled to the respective inputs of the first and second analog-to-digital converters for use in calibrating the relative gain of the first and second analog-to-digital converters, characterized in that the relative gain of the first and second analog-to-digital converters is calibrated from the ratio of the resistance values ​​of the first and second calibration resistors. SUMMARY

[0007] A method for use in a measuring system according to claim 1, an interface according to claim 9, a control unit according to claim 17, and a measuring system according to claim 19 are provided. Further embodiments are described in the dependent claims.

[0008] The following is a simplified summary intended to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, nor is it intended to identify key or critical elements of the invention, nor to outline its scope. Rather, the essential purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that will follow.

[0009] Representative implementations of devices and techniques establish communication between one or more sensor units and a control unit in a measurement system. Some embodiments are particularly useful when the communication crosses a barrier that separates the sensor unit(s) from the control unit.

[0010] Below are described embodiments relating to a method for use in a measuring system, an interface for use in a measuring system, a control unit for use in a measuring system, a measuring system and a sensor unit.

[0011] This summary is submitted with the understanding that it is not intended to be used to interpret or limit the scope or meaning of the claims. This summary is not intended to identify key features or essential characteristics of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Other methods, devices, and systems are also disclosed. Those skilled in the art will recognize additional features and advantages after reading the following detailed description and examining the accompanying drawings.

[0012] The independent claims define the invention in various respects. The dependent claims define embodiments of the invention in various respects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following description is presented with reference to the accompanying drawings. In the drawings, the left-hand digits of a reference numeral identify the drawing in which the reference numeral appears. The use of the same second and third digits in different figures indicates similar or identical elements. Fig. Figure 1 shows a block diagram of a measurement system according to some embodiments. Fig. Figure 2 represents a time sequence of signals according to some implementations. Fig. Figure 3 represents a time sequence of signals according to some implementations. Fig. Figure 4 shows a block diagram of my sensor unit according to some embodiments. Fig. Figure 5 shows a block diagram of a measurement system according to some embodiments. Fig. Figure 6 shows a block diagram of a measurement system according to some embodiments. Fig. Figure 7 shows a block diagram of a control unit according to some embodiments. Fig. Figure 8 represents a time sequence of signals according to some implementations. Fig. Figure 9 shows a block diagram of a measurement system according to some embodiments. Fig. Figure 10 presents a flowchart of a method according to some embodiments, which is implemented in a measurement system. Fig. Figure 11 shows a block diagram of a system according to some embodiments. Fig. 12. A block diagram of a system according to some embodiments is shown later. Fig. Figure 13 represents a representation of data according to some implementations. DETAILED DESCRIPTION OF THE INVENTION

[0014] As will become clear from the following detailed description, especially when read in conjunction with the accompanying drawings, the embodiments described herein can be useful, for example, in the field of measurement data acquisition. Compared with conventional solutions, at least one benefit can be improved efficiency when using sensor units for measurement data acquisition. For example, a control unit configured to control measurement data acquisition can signal setting information to the sensor unit so that the sensor unit performs data acquisition according to the setting information, or, for example, to save energy.To give another example, after booting up or waking up, the sensor unit can transmit an initial measurement result to the control unit, indicating that the control unit itself is about to be put into operational shutdown, and / or indicating whether a physical quantity is present or absent.

[0015] In some embodiments, an analog-to-digital converter is biased, i.e., referenced to a sensor reference voltage, while the control unit is referenced to a control unit reference voltage, whereby the sensor reference voltage may differ from the control unit reference voltage. At least one effect can be that, with a stable reference voltage, the control unit operates essentially independently of fluctuations in the sensor reference voltage, thus ensuring safe operation.

[0016] Some embodiments involve modulating a clock signal for use by sensor unit(s) according to information other than time. In some embodiments, the modulation involves varying sigma-delta clock cycles to generate the clock signal so that a bit value is represented. At least one effect can be that, for example, based on a communication protocol such as the Universal Asynchronous Receiver Transmitter (UART) communication protocol, other information can be communicated via the interface. In particular, a fixed timing relationship can be established at the interface between the transmission of the clock signal from the interface to the sensor unit and the reception of the digital signal by the sensor unit at the interface.At least one effect can be that the number of communication lines requiring an interface at the barrier can be kept low.

[0017] Implementations are explained in more detail below using several examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples. In many applications, multiple sensor units together form part of a measurement system, which may additionally include a control unit configured as the processing unit for handling the measurement data. The sensor units share an interface with the control unit.Furthermore, many applications, while the sensor units are configured to transmit the digital data signals to the control unit via the interface, do not allow the control unit to communicate requests to the sensor unit because they do not provide a communication line from the control unit via the interface to the sensor unit.

[0018] Fig. Figure 11 shows a block diagram of a system 1100 according to some embodiments. The system 1100 comprises a first measurement channel, which in some embodiments includes, for example, a first sensor unit 1142 and a first signal line 1143. The system 1100 further comprises a second measurement channel, which in some embodiments includes, for example, a second sensor unit 1144 and a second signal line 1145. The system 1100 further comprises a multiplexer 1114. The multiplexer 1114 is coupled to the first sensor unit 1142 via a first signal line 1143 and to the second sensor unit 1144 via a second signal line 1145. The multiplexer 1114 is coupled to a control unit 1160 via an output signal line 1151.The multiplexer 1114 is configured to multiplex signals received from the first sensor unit 1142 and from the second sensor unit 1144 and to provide a serial digital data signal DD, which is also referred to herein as DS, to the data receiving unit 1160 via the output signal line 1151.

[0019] The control unit 1160 comprises a first receiver 1165 for data from the first measurement channel and a second receiver 1166 for data from the second measurement channel. The control unit is configured to provide DS, or data represented by the serial digital signal DD(DS), to the first receiver 1165 and to the second receiver 1166, in accordance with the origin of the provided data, which is the first sensor unit 1142 or the second sensor unit 1144, respectively. In some embodiments, the first receiver 1165 is configured as an SD demodulator. In some embodiments, the second receiver 1166 is configured as a comparator. The first receiver 1165 and the second receiver 1166 are configured to provide first measurement channel data and second measurement channel data, respectively, to enable, for example, further processing. A person skilled in the art could consider variations.For example, the number of sensor units and corresponding measurement data channels does not have to be two.

[0020] Fig. Figure 12 shows a block diagram of a system 1200 according to some embodiments. System 1200 is a variant of system 11, which is described in Fig. 11 is shown. Like the 1100 system, which is in Fig. As shown in Figure 11, the system 1200 comprises a first measurement channel, which in some embodiments includes, for example, a first sensor unit 1242 and a first signal line 1243. The system 1200 also comprises a second measurement channel, which in some embodiments includes, for example, a second sensor unit 1244 and a second signal line 1245. Furthermore, the system 1200 also comprises a multiplexer 1214. The multiplexer 1214 is coupled to the first sensor unit 1242 via the first signal line 1243 and to the second sensor unit 1244 via the second signal line 1245. The multiplexer 1214 is coupled to a control unit 1260 via an output signal line 1251.The multiplexer 1214 is configured to multiplex signals received from the first sensor unit 1242 and the second sensor unit 1244 and to provide a serial digital signal DD / DS to the data receiving unit 1260 via the output signal line 1251.

[0021] The control unit 1260 comprises a single receiver 1266 for data from the first measurement channel and for data from the second measurement channel. The control unit 1260 is configured to provide the serial digital signal DD, or data represented by DS, to the single receiver 1266. The single receiver 1266 is configured to output first measurement data on a first data output line 1253 and second measurement data on a second data output line 1255, in accordance with the origin of the provided data, which is the first sensor unit 1242 or the second sensor unit 1244. In some embodiments, the single receiver 1266 is provided as an SD demo modulator. In some embodiments, the single receiver 1266 is provided as a comparator. The single receiver 1266 is configured to output the first measurement channel data and the second measurement channel data via the first and second data output lines 1253 and 1254, respectively.to provide 1255, for example to enable further processing.

[0022] Regarding the examples mentioned above, a person skilled in the art can consider variations. For instance, the number of sensor units and corresponding measurement data channels need not be two. Signal lines, especially when configured to transmit digital signals, need not be single lines; they can also be arranged as multi-bit parallel bus lines. However, as will become clear when further implementations are examined below with reference to the figures, in some implementations the output line of the system for transmitting signals from the sensor unit(s) to the control unit may be a serial signal line rather than a multi-bit parallel bus.

[0023] Fig. Figure 13 represents an exemplary combined representation 1310 of measurement data according to some implementations, for example, in the digital signal DD (DS) output by the multiplexer 1114,1214. In some embodiments, the measurement data originates from the first measurement channel and the second measurement channel. In the example, the representation 1310 is 64 bits wide. The representation 1311 comprises a first byte 1311 (bits 0 to 7) and a first 24-bit word 1312 (bits 8 to 31), as well as a second 24-bit word 1313 (bits 32 to 55) and a second byte 1314 (bits 56 to 63). In some implementations, the first 24-bit word 1312 is assigned to the first byte 1311, and the second byte 1314 is assigned to the second 24-bit word. In some embodiments, the first byte 1311 and / or the second byte 1314 are used to represent control information such as an identity of the sensor unit, which is provided by the data in the associated 24-bit word.In some implementations, the first byte 1311 and the second byte 1314 are not used. At least one effect of this may be that data transmission can be more secure because very low and / or very high voltage levels can be ignored by avoiding the use of mostly significant bits and least significant bits in a digital representation of an analog signal.

[0024] In some implementations, the first receiver 1165 and the second receiver 1166, or the single receiver 1266, are configured to interpret the serial digital signal DD / DS for validity. In the example shown in Fig. As shown in Figure 13, bit values ​​in the range of bit 8 to bit 31 can be interpreted as valid to represent the measurement data of the first channel, while other bit values ​​are interpreted as invalid with respect to the measurement data of the first channel. To give another example, bit values ​​in the range of bit 32 to bit 55 can be interpreted as valid to represent measurement data of the second channel, while other bit values ​​are interpreted as invalid with respect to the measurement data of the second channel.

[0025] The person skilled in the art could, of course, consider different numbers of bits to be used in the representation, and also a different division. Furthermore, the person skilled in the art could consider nesting the first and second bytes and / or the first and second 24-bit words within each other, for example, using odd-numbered bits for the first 24-bit word and even-numbered bits for the second 24-bit word. At least one effect could be increased resistance to errors during data transmission from the multiplexer 1114, 1214 to the control unit 1160, 1260. Example configurations with clock signal modulation

[0026] In some implementations, as in Fig. As shown in Figure 1, a measuring system 100 comprises a sensor unit 110 and a control unit 160. Although reference is made here to a single sensor unit 110, it should be understood that the number of sensor units included in the measuring system 100 is not limited to one. The measuring system 100 can include more than one sensor unit. The sensor unit 110 and the control unit 160 are electrically separated from each other by an isolation barrier. In particular, the sensor unit 110 is coupled to a first ground 101, which defines a measurement ground potential, while the control unit 160 is coupled to a second ground 106, which defines a The control ground potential is defined. The measurement ground potential at the first ground 101 and the control ground potential at the second ground 106 are essentially independent of each other and can therefore differ. The sensor unit 110 and the control unit 160 are communicatively coupled. This coupling is established at the barrier via an interface 150.

[0027] In some implementations, the sensor unit 110 comprises a transducer 112, an input stage 114, and a sigma-delta modulator 116. The transducer 112 is coupled to the input stage 114 via a signal line 113. Furthermore, the input stage 114 is coupled to the sigma-delta modulator 116 via a signal line 115. The transducer 112 is configured to sense, i.e., detect, a physical quantity, for example, a phase current, and output a corresponding signal as an analog key signal AS on the signal line 113 to the input stage 114. The input stage 114 is configured to amplify the analog key signal and process it as needed, for example, by filtering out noise from the analog key signal, and output a processed analog key signal PAS on the signal line 115 to the sigma-delta modulator 116.The sigma-delta modulator 116 is configured to generate a digital key signal DS based on the processed analog key signal and to output the digital key signal to a signal output terminal 117 of the sensor unit 110. In some implementations, the number of zeros and ones provided in the serial data bit representation of the digital key signal during a predetermined duration represents a level of the analog key signal AS. The sensor unit 110 includes a control input terminal 119, which is configured to receive a control signal. In some implementations, the sigma-delta modulator 116 is coupled to the control input terminal 119 and configured, for example, to use a clock signal CLK, received at the control input terminal 19, when generating the digital key signal DS.

[0028] In some embodiments according to the concepts disclosed herein, the sensor unit 110 comprises a clock demodulator 122 coupled to the control input terminal 119. In some implementations, the coupling of the control input terminal 119 to the clock demodulator 122 is established by a clock signal line 121. The clock demodulator 122 is configured to demodulate or otherwise decode a signal received from the control input terminal 119 in order to extract encoded information from the signal and to output a control signal, CTRL, representing this extracted information.

[0029] In some embodiments, the sensor unit 110 includes a communication interface 124, which is coupled to the demodulator 122, for example, via a control signal line 123, and which is configured to receive the control signal CTRL from the clock demodulator 122. In some implementations, the communication interface 124 is configured to extract control information such as commands, parameter settings, address data, and the like from the control signal CTRL. In some embodiments, the communication interface 124 is coupled, for example, via a control signal line 125 to an input and modulator configuration module 126, which in some embodiments is coupled to at least one of the components converter 112, input stage 114, and SD modulator 116 and is configured to provide configuration information, such as setting information, to the respective component.In some embodiments, the communication interface 124 is coupled, for example by a control signal line 129, to a sensor unit configuration and control module 130, which is configured to configure, for example, the sensor unit 110 and / or other devices. More generally, the sensor unit configuration and control module 130 can also be referred to as a device configuration and control module because, according to the techniques disclosed herein, devices other than the sensor unit 110 can also be configured and / or controlled using the device configuration and control module 130. It should be understood that the input and modulator configuration module 126 and the sensor unit configuration and control module 130 are described herein as separate units only for the purpose of giving an example.However, a person skilled in the art can arrange these units together or provide one as part of the other. The communication interface 124 is configured to communicate control information to the input and modulator configuration module 126 and / or to the sensor unit configuration and control module 130 according to the functions assigned to the respective module within the sensor unit 110. Thus, the communication interface 124 can provide setting information, commands, and / or other control signals to at least one of the input and modulator configuration module 126 and the control unit configuration and control module 130.

[0030] Still referring to Fig. The control unit 160 comprises a signal input port 169, a sigma-delta demodulator 166, and a processing unit. In some embodiments, the processing unit is provided as a data processing unit 162. The signal input port 169 is coupled to the sigma-delta demodulator 166 via a serial input line 168. The sigma-delta demodulator 166 is coupled to the processing unit 162 via a parallel bus 163. The sigma-delta demodulator 166 is configured to receive a digital key signal DS, which is received at the signal input port 168, and to demodulate the serial data stream of the digital key signal DS to output key data in a parallel data signal PDS to the processing unit 162 on the bus 163. The Sigma-Delta Demodulator 166 includes a decimation filter configured to change a data format from a serial data stream to a parallel data word.In some embodiments, the decimation filter forms part of a configuration for performing oversampling. At least one effect may be to improve the resolution of the digital representation of the analog sample signal and / or to reduce undesirable effects in the digital representation of the analog sample signal, such as noise and convolution distortion. In some implementations, the sigma-delta demodulator 166 is configured to output parallel 8-bit data word representations of the digital sample data. The 8-bit example is chosen merely to illustrate the concept. A person skilled in the art could, without deviating from the concept, consider other numbers of bits to be used for the parallel bit representation, for example, 10 bits, 16 bits, 24 bits, 32 bits, etc.Furthermore, it should be understood that when the sigma-delta demodulator 166 typically starts operating in an initial state and / or when a non-zero digital test signal DS is applied to the sigma-delta demodulator 166 (for example, during a wake-up process), time is required for the sigma-delta demodulator 166 to enter a state of inactivity. This ensures that data output in parallel by the sigma-delta demodulator 166 corresponds to a serial stream of test data supplied to the sigma-delta demodulator 166. In some implementations, the period required for the sigma-delta demodulator 166 to enter an inactivity state, expressed in clock cycles of the clock used by the sigma-delta analog-to-digital converter, can be as long as the product of the size of the sigma-delta demodulator and its oversampling ratio.

[0031] As described above, in some implementations the sensor unit 110 and control unit 160 are electrically separated from each other by an isolation barrier that separates their respective ground potentials, i.e., the measurement ground potential from the control ground potential. In some embodiments, the interface 150 is configured to communicatively couple the sensor unit 110 with the control unit 160 in order to enable communication across the isolation barrier. In some implementations, the interface 150 includes optical coupling elements such as optocouplers. In some implementations, the interface 150 includes capacitive coupling elements. In some implementations, the interface 150 includes magnetic coupling elements such as coreless magnetic couplers, which are sometimes referred to simply as CT couplers.In another embodiment, the isolation barrier is incomplete. In such an embodiment, the measurement ground potential and the control ground potential are not completely separated from each other, but offset from each other by a voltage that can vary within a predetermined range. Some embodiments include transistor circuits to implement level shifters configured to provide communicative coupling.

[0032] The control unit 160 includes a clock generator 173, which is configured to generate or otherwise provide a clock signal CLK for use in the operation of at least some of the components of the measurement system 100 described above. In some implementations, the clock generator 173 is configured to provide the clock signal CLK such that it comprises a sequence of periodic changes in the signal voltage, alternating from a high voltage level to a low voltage level and vice versa, thereby creating a rising clock edge and a falling clock edge. In some implementations, the components described above are configured to use either the rising edges or the falling edges in the clock signal to define a clock cycle in the operation of the respective component, as required.

[0033] The control unit 160 comprises a clock modulator 175, which is coupled to a control output port 167 via a clock signal line 176. In some embodiments, the clock modulator 175 is also coupled to the processing unit 162, for example, via the SD modulator 166. The clock modulator 175 is configured to modulate a clock signal CLK received by the clock generator 174 in order to provide a modulated clock signal mCLK at the control output port 167 and / or the processing unit 162. The clock modulator 175 is configured to modulate the sensor unit control data onto the clock signal in order to obtain a modulated clock signal mCLK that carries both the clock signal and the sensor unit control data.

[0034] In some embodiments, the processing unit 162 is configured to provide sensor unit control data to the clock modulator 175. In particular, in some embodiments, the processing unit 162 is coupled to a communication interface 171 via a control signal line 161. In some embodiments, the control signal line 161 is provided by a communication bus. In some implementations, the communication interface 171 is configured to support a standardized communication protocol. For example, in some implementations, the communication interface 171 is configured to support a universal asynchronous receiver-transmitter (UART) communication protocol. Accordingly, in some embodiments, the communication interface 171 is configured to represent data in bit sequences contained within frames of a fixed length.In some implementations, each frame includes a start bit (SOF), several data bits (in some implementations, a range of 5 to 9 data bits), an optional parity bit, and a stop bit (STOP). At least one effect may be that, while no clock signal needs to be transmitted (UART communication is synchronous), in some embodiments, the communication is timed according to UART based on a clock frequency of the clock signal CLK. At least one effect may be that a fixed timing relationship is established between a transmit communication interface, i.e., communication interface 171, and a receive communication interface, for example—this is described in more detail below in some embodiments—the communication interface 124 provided in the sensor unit 110.It should be understood that the UART protocol is mentioned as an example; the person skilled in the art may consider the use of other communication protocols, including a protocol specifically designed for use in a measurement system.

[0035] The communication interface 171 is coupled to the clock modulator 175 via a clock control line 172. In some implementations, the communication interface 171 is configured to receive a control data signal CD from the processing unit 162. In some embodiments, the processing unit 162 is configured, for example, using the communication interface 171, to control the operation of the clock modulator 175, for example, to set a frequency of the modulated clock signal mCLK or to set a duty cycle of the modulated clock signal mCLK.In some embodiments, while one edge (rising or falling) in the modulated clock signal mCLK is used to encode the clock information, the other edge (falling or rising) in the modulated clock signal mCLK can be used to encode other information, in particular control information such as a parameter value to be set as a configuration of the sensor unit 110, and / or control commands.

[0036] The coupling between the sensor unit 110 and the control unit 160 will now be described in more detail. In some embodiments, the coupling of the signal output terminal 117 of the sensor unit 110 to the signal input terminal 169 of the control unit 160 via the interface 150 is established by a digital signal line 152 between the interface 150 and the input terminal 169 of the control unit 160. Furthermore, in some embodiments, the coupling of the control output terminal 167 of the control unit 160 to the control input terminal 119 of the sensor unit 110 via the interface 150 is established by a control signal line 156 between the control unit 160 and the interface 150, and by a control signal line 157 between the interface 150 and the sensor unit 110.

[0037] Assuming the coupling described above between the sensor unit 110 and the control unit 160, the sigma-delta modulator 116 and the sigma-delta demodulator 166 are configured in some embodiments to work together as an analog-to-digital converter to convert the analog keying signal AS into the parallel digital keying signal PDS as a parallel data bit representation of sampling information carried by the analog keying signal.

[0038] The exemplary measurement system can be used, for example, to perform phase current measurements, such as in an electric drive system, a smart meter application, or a switched-state power supply (SMPS). It should be understood that the example of phase current as a quantity to be measured is mentioned only for illustrative purposes. The measurement system 100, particularly when used with a suitable transducer, is not limited to a configuration for measuring phase current; it can be configured to measure any other physical quantity as needed, such as direct current, static charge, voltage, pressure, acceleration, and the like.

[0039] Exemplary embodiments of the time setting are now described, which can be implemented, for example, in embodiments referred to above. Fig. 1 were described.

[0040] Fig. Figure 2 represents a time sequence of 200 of a modulated clock signal according to some implementations, such as those found in Fig. Figure 1 shows where the clock modulator 175 is configured to modulate the clock signal by varying a duty cycle of the clock signal. As an example, it shows Fig. 2. A case in which the clock SD clock modulator 175 receives a sequence of zeros and ones (001 in the example), i.e., a binary representation of the sensor unit control data from the communication interface 171, which in turn has received a corresponding bitword from the processing unit 162. In some implementations, such as in Fig. As shown in Figure 2, a zero is modulated onto the clock signal by a short duty cycle, and a one is modulated onto the clock signal by a long duty cycle. Fig. In example 2, a short duty cycle is one-third, while a long duty cycle is two-thirds. To give another example, a short duty cycle could be 30%, while a long duty cycle could be 70%. To give yet another example, a short duty cycle could be 40%, while a long duty cycle could be 60%. Other values ​​can also be considered; for example, asymmetrical implementations such as a short duty cycle of 30% and a long duty cycle of 50% can be considered. The person skilled in the art will select duty cycle percentages that are distinguishable from others in a given implementation, in order to enable the sensor unit to decode zeros and ones in the modulated clock signal mCLK.While the embodiments described herein use a binary representation of control data by implementing modulation with two different duty cycles, it should be understood that implementations can be designed that use more than two different duty cycles, such as three duty cycles, for example 25%, 50% and 75%, to encode the control data to be carried by the clock signal.

[0041] Well, upon closer examination of the example that is in Fig. As shown in Figure 2, rising edges 221, 222, and 223 in the modulated clock signal mCLK define the start of a corresponding clock pulse at times 201, 202, and 203, respectively. It should be understood that a falling edge could just as easily be used to define the start of a clock pulse instead of a rising edge. The duration T of each clock cycle is the same. At times 211, 212, and 213, falling edges 231, 232, and 233 in the modulated clock signal mCLK terminate intervals 241, 242, and 243 of the modulated clock signal mCLK at the high level, thus defining the respective duty cycle as the intervals 241, 242, and 243 of the modulated clock signal mCLK at the high level as a part of a total pulse length T. Therefore, falling edges define the encoded bit values ​​0, 0, and 1, respectively, which are modulated onto the clock signal CLK.It should be understood that, instead of defining the represented bit as zero if the duty cycle of the modulated clock signal is small, and as one if the duty cycle of the modulated clock signal is large, the assignment of represented bits could also be defined in reverse.

[0042] Fig. Figure 3 represents a timeline 300 of a modulated clock signal according to some other implementations similar to the example shown in Figure 2. In the implementations with the timeline shown in Fig. As shown in Figure 3, the SD clock modulator 175 is configured to modulate the clock signal by varying a sampling ratio of the clock signal. In the example of Fig. 3, as in the example of Fig. 2. The SD clock modulator 175 receives a sequence of zeros and ones (001 in this example) from the communication interface 171. Furthermore, in this example, a zero is modulated onto the clock signal by a short duty cycle, and a one is modulated onto the clock signal by a long duty cycle. As in the example of Fig. 2 is also the case in the example of Fig. 3. A short duty cycle is one-third, while a long duty cycle is two-thirds. A person skilled in the art may consider other ratios than those mentioned above with reference to Fig. 2 are explained. Fig. At times 301, 302, and 303, respectively, rising edges 321, 322, and 323 in the modulated clock signal mCLK define the beginning of a corresponding clock cycle 361, 362, and 363 in the clock signal CLK. At times 311, 312, and 313, respectively, falling edges 331, 332, and 333 in the modulated clock signal mCLK end intervals 341, 342, and 343 of the modulated clock signal mCLK at the high level, thus defining the respective duty cycle as the intervals 341, 342, and 343 of the modulated clock signal mCLK at the high level as a segment of the total sampling length. Thus, falling edges 331, 332, and 333 define the encoded bit values ​​0, 0, and 1, respectively, which are modulated onto the clock signal CLK. The implementation, which is in Fig. However, the implementation shown in 3 differs from the implementation shown in Fig. 2 is shown by the fact that each sampling ratio is transmitted from communication interface 171 in a sequence of more than one clock cycle of length T. For the purpose of illustrating a simple example, Fig. 3. An implementation in which a sampling rate is transmitted using two consecutive clock cycles, providing, for example, the sequence of clock cycles 361a, 361b, 362a, 362b, 363a, and 363b shown. However, other implementations may define the sampling rate as comprising a larger number of clock cycles, such as three, four, or more. Because two consecutive clock cycles are used to transmit the sampling information in the modulated clock signal mCLK, the receiver, for example, the sensor unit 110, may base its decoding of the modulated clock signal on an integrated sampling rate or on an average sampling rate, which may result in more accurate decoding than in the case described in Fig. Figure 2 shows where the sampling ratio is based on one clock cycle in the modulated clock signal mCLK. At least one effect may be increased resistance to noise and / or other effects that negatively impact communication.

[0043] Using control signal encoding to provide the modulated clock signal mCLK to the sensor unit 110, the control unit 160 can thus send commands such as switch off, switch on, reset, and the like to the sensor unit 110. At least one effect can be that the control unit 160 enables the sensor unit 110 to use energy efficiently and to operate only to the extent required in the measurement system 100. Using the modulated clock signal mCLK, the control unit 160 can also be configured to communicate other information, such as gain and offset range settings of the input stage 114, to the sensor unit 110.In further embodiments, the control unit can communicate timing information using the modulated clock signal mCLK, which is to be used when operating filters such as low-pass filters that are built into the input stage 114. In still other embodiments, the control unit 160 can use the modulated clock signal mCLK to control an output driver (in . Fig. (1 not shown) configure or otherwise adjust the sensor unit 110, which is installed in such a way that the digital key signal DS is output at a desired power level at the signal output port 117.

[0044] Furthermore, the control unit 160 can be configured to encode address data in the modulated clock signal mCLK in order to selectively address one sensor unit 110 among several sensor units if the measurement system 100 comprises more than one sensor unit 110. At least one effect can be that the control of one or more sensor units 110, which are connected to a measurement ground potential that is essentially independent of a control ground potential, can be carried out, while avoiding an additional control signal line that would have to be provided with an interface across the barrier between the control ground potential and the measurement ground potential.This can create significant savings, and as a result, the techniques described herein can be implemented in many additional applications as conventional solutions that require the clock signal to be used only for transmitting the clock signal, but not for transmitting other information such as control information or control commands.

[0045] In some implementations, data received at the sensor unit 110 can be used as a control data word or a configuration data word, thereby synchronizing an updated configuration of the sensor unit's SD modulator 116 with a configuration of the control unit's SD demodulator 166. The update can be performed according to a predetermined update schedule or on demand by the control unit 160. In some embodiments, the control unit 160 is configured to discard data received via the digital key signal DS during a predetermined period after the transmission of a configuration request or a synchronization request.In some implementations, a configuration operation and / or a configuration synchronization of the sensor unit 110 may prevent the sensor unit 110 from generating the digital keying signal that carries an accurate representation of the physical quantity to be detected. For example, a configuration operation may require the sensor unit 110 to establish a predetermined input stage gain, which may take some time before regulation can occur. To give another example, a configuration operation may require the sensor unit's SD modulator 116 to be set before it is able to output any meaningful digital signal.If the control unit 160 is configured to count a predetermined number of clock cycles after the transmission of a request before accepting the digital key signal DS as a representation of measurement data, at least one effect may be to avoid processing impaired or otherwise incorrect data that does not reflect a value of a physical quantity.

[0046] In some embodiments, the sensor unit 110 is configured, as described in more detail below, to provide a digital signal DS1 of a first type and a digital signal DS2 of a second type. The digital signal DS1 of the first type can be generated to represent low-resolution status data and / or measurement data, which are collectively referred to herein as miscellaneous data, while the digital signal DS2 of the second type can be generated to represent high-resolution measurement data. In some implementations, the sensor unit 110 is configured to generate the data signal DS1 of the first type during startup, configuration, and / or when the SD modulator 116 is synchronized, for example, to the SD demodulator 166. In some implementations, the sensor unit 110 can be configured to generate the digital signal of the second type after the aforementioned operational processes have been completed.At least one effect can be to provide the control unit 160 with an indication of the state of the sensor unit 110, or of the presence of a physical quantity whose measurement is imminent, at an early stage, for example, while the SD modulator 116 is still being set, before the sensor unit 110 transmits any higher-resolution measurement data using the second-type digital key signal DS2. As used herein, state information includes setting information. In some embodiments, error information, for example, resulting from a self-test of the sensor unit, and the like, can provide a basis for determining the plausibility of other data, such as serial data provided by the digital key signal DS. In some implementations, the state information indicates a connection, for example, between the sensor unit 110 and the control unit 160.

[0047] In some embodiments, the control unit 160 is configured, as described in more detail below, to interpret the digital key signal DS to determine whether the signal represents data to be processed. In some embodiments, the determination includes an interpretation regarding the type of data represented by the digital key signal DS. At least one effect may be that the control unit 160 can adjust the processing of the data according to the result of the determination.

[0048] Fig. Figure 4 shows a block diagram of a sensor unit 410 according to some embodiments and some other embodiments. The sensor unit 410 comprises components of a sensor unit 110, which are described above with reference to Fig. 1 was described. Furthermore, the sensor unit 410, as described in Fig. As shown in Figure 4, the sensor unit 410 is configured to selectively detect a number of physical quantities, namely phase current and temperature. For this purpose, in some embodiments, the sensor unit 410 comprises a first transducer 442, a second transducer 444, and a multiplexer 432, which is coupled via an analog signal line 433 to an input stage 414 that essentially corresponds to the input stage 114 in the sensor unit 110 shown in Figure 410. Fig. Figure 1 is shown. While the multiplexer 432 and the input stage 414 are described separately herein for the purpose of illustration, it should be understood that the multiplexer 432 may be arranged together with the input stage 414 and / or may form part of the input stage 414.

[0049] The first transducer 442 is configured to generate an analog electrical signal AS1, which is also referred to herein as an analog temperature signal carrying temperature information. In some embodiments, the temperature information is a value of an ambient temperature, which represents the temperature at the location of a sensor element (in Fig. (Figure 4 not shown) reflects the first converter. The first converter 442 is coupled to the multiplexer 432 via an analog signal line 443 and is configured to output the analog temperature signal AS1 to the multiplexer 432.

[0050] The second transducer 444 is configured to generate an analog electrical signal AS2, which is also referred to herein as an analog phase current signal, carrying phase current information. In some embodiments, the transducer's sensor element includes a shunt resistor (in Fig. (4 not shown) and phase current information is a voltage value that reflects the phase current flowing through the shunt resistor. The second converter 444 is coupled to the multiplexer 432 via an analog signal line 445 and is configured to output the analog phase current signal AS2 to the multiplexer 432.

[0051] In some embodiments, the multiplexer 432 is coupled to an input and modulator configuration module 426 via a selection signal line 431 and is configured to receive a configuration signal from the input and modulator configuration module 426, which carries configuration information from the configuration module 426. In particular, where the configuration information is selection information, the multiplexer 432 is configured to select one of the analog temperature signal AS1 or the analog phase current signal AS2 for supply to the input stage 414. When using the sensor unit 410 in a measuring system 100 instead of the sensor unit 110, that is, if the sensor unit 410 is coupled to the control unit 160, the modulated clock signal mCLK can be used to select in the sensor unit 410 which physical quantity is to be currently measured.

[0062] Fig. Figure 5 represents a block diagram of a measuring system 500, which includes sensor elements 542, 544, a sensor unit 510 coupled to the sensor elements 542, 544, and a control unit 560 coupled to the sensor unit 510. Many of the components that are in Fig. The figures shown in 5 are similar to those shown in measuring system 100, which is in Fig. Figure 1 is shown. In particular, in some implementations, an interface 550 may be coupled between the sensor unit 510 and the control unit 560. At least one effect may be that, as described above, while an isolation barrier may be provided at the interface 550 to safely separate a first ground potential at the sensor elements 542, 544 and / or the sensor unit 510 from a second ground potential at the control unit 560, the interface 550 may enable communication between the sensor unit 510 and the control unit 560. While the communication interface 550 is located at the isolation barrier between the sensor ground potential 501 and the control unit 560, the first ground potential at the sensor elements 542, 544 and / or the sensor unit 510 may be separated from a second ground potential at the control unit 560, the second ground potential at the control unit 560 may be separated from the first ground potential at the sensor elements 542, 544 and / or the sensor unit 510.The control ground potential 506 is located at this point. It should be understood that in some embodiments, no communication interface needs to be provided where the sensor ground potential and the control ground potential are the same, so that a direct connection between the sensor unit 510 and 560 is sufficient. Furthermore, it should be understood that while the system is in . Fig. The 5 sensor elements 542, 544 outside the sensor unit 510 show that one or more of the sensor elements 542, 544 form part of the sensor unit in some implementations (see for example Fig. 4).

[0052] According to some embodiments, the measuring system 500 is adapted to use a frequency-modulated clock signal to communicate control information from the control unit 560 to the sensor unit 510. In some embodiments, the first sensor element 542 is configured as a temperature-sensitive transducer configured to output an analog electrical signal AS1 representing an ambient temperature (hereafter referred to as an analog temperature signal). In some embodiments, the second sensor element 544 is configured as a phase-current-sensitive transducer. The transducer of the second sensor element 544 is configured to output an analog electrical signal AS2 representing a nearby phase current (hereafter referred to as an analog phase current signal).

[0053] The measuring system 500 is configured to feed the analog temperature signal AS1 and the analog phase current signal AS2 to a multiplexer 514, which is provided in the sensor unit 510, using the analog signal lines 543 and 545. The multiplexer 514 is configured to selectively provide one of the analog temperature signal AS1 and the analog phase current signal AS2 to a sigma-delta modulator (SD modulator) 556 via an analog signal line 515. The SD modulator 556 is configured to provide a digital key signal DS at an output port 517 of the sensor unit 510.

[0054] In some implementations, the sensor unit 510 is configured to receive a frequency-modulated clock signal mCLK at a control input port 519. The sigma-delta modulator 516 is coupled to the control input port 519 and configured to use the frequency-modulated clock signal mCLK when generating the digital key signal DS. The sensor unit 510 also includes a clock demodulator 522, which is coupled to the control input port 519. The coupling of the control input port 519 to the clock demodulator 522 is provided, for example, by a clock signal line 521. The clock demodulator 522 is configured to demodulate or otherwise decode the frequency-modulated clock signal received from the control input port 519 in order to extract encoded selection information from the signal.In some embodiments, the clock demodulator 522 is configured to distinguish between different frequencies used in the frequency-modulated clock signal mCLK. In some embodiments, the clock demodulator 522 is configured to assign a selection bit value of either one or zero if a frequency of the frequency-modulated clock signal is high or low, respectively. In some implementations, the clock demodulator 522 is configured to output a selection signal SEL to the multiplexer 514 via a selection signal line 531, representing the extracted selection information, such as the selection bit. The multiplexer 514 is configured to select, according to the selection information, one of the analog temperature signal AS1 and one of the analog phase current signal AS2 for output to the SD modulator 556.

[0055] Now with reference to Fig. 5; the control unit 560 comprises a sigma-delta demodulator (SD demodulator) 566 and an SD clock modulator 575. In some embodiments, the SD demodulator 566 is provided like the SD modulator 166 described above with reference to Fig. 1 is described. In particular, the SD demodulator 566 is configured to receive the digital keying signal DS and to derive a serial data stream from the digital keying signal DS for output, for example, to a processing unit (in Fig. 5 not shown) to demodulate.

[0056] In some embodiments, the clock modulator 575 is connected to a clock generator (in Fig. (5 not shown), to a control output port 567 and / or to the processing unit. The clock modulator 575 is configured to frequency-modulate a clock signal CLK received from the clock generator to provide a frequency-modulated clock signal mCLK at the control output port 567. The clock modulator 575 is configured to frequency-modulate the sensor unit control data onto the clock signal to obtain a modulated clock signal mCLK that carries both the clock signal and the sensor unit control data. In some embodiments, the clock modulator 575 includes a frequency divider that can be used to, for example, output a high-frequency clock signal and a low-frequency clock signal. In some implementations, the high-frequency clock signal has a frequency in the range of 10 to 20 MHz.In contrast, in some embodiments the low-frequency clock signal has a frequency in the range of 1 to 5 MHz. In some embodiments, the frequency is selected to be suitable for direct use in the operation of the SD modulator 556 of the sensor unit. For example, where the frequency of the modulated clock signal is in the range of 10 to 20 MHz, a fast analog-to-digital conversion rate of an analog sample signal with high resolution can be achieved, such as a digital signal resolution in the range of 12 to 14 bits. Example configurations with transfers of multiple data types

[0057] Fig. Figure 6 represents a block diagram of a measuring system 600 according to some embodiments. Because embodiments of the measuring system 600 include some or all components of the measuring system described above with reference to Fig. As described in Section 1, only some of the components will now be described, although it should be understood that other components described above may also be provided. In particular, the measuring system 600 comprises a sensor unit 610 and a control unit 660. The sensor unit 610 and the control unit 660 are electrically separated from each other by an isolation barrier. Specifically, the sensor unit 610 is coupled to a first ground 601, which defines a measurement or sensor ground potential, while the control unit 660 is coupled to a second ground 606, which defines a control ground potential. The measurement ground potential at the first ground 601 and the control ground potential at the second ground 606 are essentially independent of each other, and therefore they can be different. The sensor unit 610 and the control unit 660 are communicatively coupled to each other.The coupling is established at the isolation barrier via an interface 650.

[0058] In some implementations, the sensor unit 610 comprises a transducer 612, an input stage 614, and a sigma-delta modulator 616. The sigma-delta modulator 616 is coupled to a signal output terminal 617 of the sensor unit 610. The transducer 612 is coupled to the input stage 614 via a signal line 613. Furthermore, the input stage 614 is coupled to the sigma-delta modulator 616 via a signal line 615. The transducer 612 is configured to sample a physical quantity, for example, a phase current, and to provide a corresponding output as an analog sample signal AS on a signal line 613 to the input stage 614. The input stage 614 is configured to amplify and otherwise process the analog keying signal and output a processed analog keying signal PAS on the signal line 615 to the sigma-delta modulator 616.The Sigma-Delta Modulator 616 is configured to form a digital key signal DS based on the processed analog key signal and to output the digital key signal to the signal output port 617 of the sensor unit 610.

[0059] The sensor unit 610 includes a control input port 619 configured to receive a control signal. In some implementations, the sigma-delta modulator 616 is coupled to the control input port 619 and configured to use, for example, a clock signal CLK received at the control input port 619 when it forms the digital key signal DS. In some embodiments (in Fig. (Figure 6 not shown), which are disclosed herein, the sensor unit 610 comprises a clock demodulator coupled to the control input port 619. In some implementations, the coupling of the control input port 619 to the clock demodulator is provided by a clock signal line. The clock demodulator is configured to demodulate or otherwise decode a signal received from the control input port 619 in order to extract encoded information from the signal and to output a control signal CTRL representing this extracted information.

[0060] In some embodiments, the sensor unit 610 comprises a comparator 683, which has a key input terminal that is coupled, for example, to the converter 612 via an analog signal line 681, and a reference input terminal that is coupled to a threshold voltage terminal 682 that is set to a threshold voltage VTH. Furthermore, in some embodiments, the comparator 683 is coupled, for example, via a bit signal line 684 to a transmitter 687. The comparator 683 is configured to compare an analog key signal AS with the threshold voltage VTH and to output a bit signal BS to the transmitter 687 via the bit signal line 684, indicating a comparison result.

[0061] In some embodiments, the sensor unit 610 comprises a state circuit section 685, which is coupled to the transmitter 687, for example, via a data line 686. In some embodiments, the state circuit section 685 is configured, for example, as a register, to store state data indicating the state of a sensor unit and to output some or all of this data to the transmitter 687.

[0062] In some embodiments, a selector 690, coupled between the sigma-delta modulator 616 and the signal output terminal 617, is arranged to receive the digital key signal DS from the sigma-delta modulator 616. In some implementations, for example, the transmitter 687 is coupled to the selector 690 via the data line 688. An output terminal end of the selector 690 is coupled to the output terminal 617, for example, via a digital signal line 691.

[0063] Transmitter 687 can be configured to transmit data received from state circuit section 685 to selector 690. Transmitter 687 can also be configured to transmit a selection signal SEL to selector 690. In some embodiments, transmitter 687 is configured to base the transmission of state data and / or the selection signal SEL on the bit signal BS received from comparator 683. At least one effect of this configuration is that the transmission of state data to a receiver may implicitly provide information about the bit signal BS, if the receiver is aware that transmitter 687 decided to transmit the state data based on the bit signal BS received from comparator 683.

[0064] In some implementations, for example, if the bit signal BS indicates that a level of the analog key signal AS is equal to or above a level of the threshold voltage VTH, the transmitter 687 immediately outputs a selection data signal SEL to the selector 689 to select data received by the state circuit section 685 for transmission to the control unit 660. Conversely, if the bit signal BS indicates that a level of the analog key signal AS is below the level of the threshold voltage, the transmitter 687 outputs the selection data signal SEL to request a selection of the digital key signal DS for transmission to the control unit 660. At least one effect can be to avoid the transmission of an invalid key signal to the control unit 660 when a signal strength below the threshold voltage implies invalidity.The person skilled in the art can consider other validity criteria, such as excessively high voltage or signal strength, and accordingly implement a maximum voltage that the analog keying signal must not exceed if the digital keying signal is to be considered valid for transmission to the control unit 660. Another effect can be to improve the use of time: if no valid keying signal is available at the sensor unit 610 for transmission to the control unit 660, the sensor unit 610 can transmit information about its state to the control unit 660 instead of transmitting the invalid keying signal. Where the threshold voltage VTH is appropriately set, yet another effect can be that, based on an output from the comparator 683, an early, i.e.,Even while the Sigma-Delta Modulator 616 may not yet be in operation, for example during initialization when starting up or when the sensor unit 610 is waking up, an approximate sample value of a physical quantity can be provided by the comparator 683.

[0065] The selector 690 is configured to selectively forward the digital key signal DS to the output terminal 617, as described in more detail below. In some embodiments, the selector 690 is configured to selectively forward either the digital key signal received by the SD modulator 616 or the status signal received by the transmitter 687 to the output terminal 617. In some embodiments, the status data signal may, for example, include setting information, commands, and / or other control signals to at least one of the input and modulator configuration module 626 and the sensor unit configuration and control module 630.

[0066] It should be understood that the comparator 683, the state circuit section 685, the transmitter 687 and / or the selector 689 are described herein as separate units only for the purpose of providing an example. However, a person skilled in the art can arrange these units together or create one as part of the other.

[0067] In some embodiments, the control unit 660 comprises a sigma-delta demodulator (SD demodulator) 666, a processing unit 662, which is coupled to the SD demodulator 666, for example, via a bus 663, and an SD clock circuit section 675, which is coupled to an output port 667 of the control unit 660. In some embodiments, the SD demodulator 666 is provided like the SD modulator 166, which is described above with reference to Fig. 1 is described. In particular, in some implementations, the SD demodulator 666 is configured to receive the digital key signal DS and to demodulate a serial data stream of the digital key signal DS for output to the processing unit 662 as a parallel data signal PDS. The clock circuit section 675 is configured to provide a clock signal CLK at the output port 667 of the control unit 660 and / or at the SD demodulator 666. In some implementations, the control unit 660 is configured to operate as described above with reference to the Fig. 1 to 5. In particular, in some implementations, the clock circuit section 675 includes a clock generator and a clock modulator, as described above with reference to the Fig. 1 to 5 are described.

[0068] Fig. Figure 7 shows a block diagram of an alternative control unit 760 configured for use in a measurement system according to some embodiments, as described above with reference to the Fig. 1 to 6 are described. In particular, the control unit 760 comprises components such as the control unit 660, which are described above with reference to the Fig. 6. In some embodiments, the control unit 760 comprises a sigma-delta demodulator (SD demodulator) 766, which is coupled, for example, via a node 768 for serial data signals to an input port 769 of the control unit 760. Furthermore, the control unit 760 comprises a processing unit 762, which is coupled, for example, via a parallel bus 763 to the SD demodulator 766. The control unit 760 further comprises a clock circuit section 775, which is coupled, for example, via a node 776 to both an output port 767 of the control unit 760 and to the SD demodulator 766. In some implementations, the control unit 760 is configured as described above with reference to the Fig. The control unit 760 is operated as described in sections 1 to 6. In particular, the control unit 760 can be coupled to an earth 706 at a control ground potential. In some implementations where one or more sensor units are coupled to the control unit 760, while the control unit 760 is kept electrically isolated from the sensor units, the control ground potential can be independent and thus temporarily differ from any sensor ground potential.

[0069] The control unit 760 will now be described in more detail; in some embodiments, the SD demodulator 766 is provided structurally and / or functionally just like the SD modulator described above with reference to Fig. 1 is described. In particular, in some implementations, the SD demodulator 766 is configured to receive the digital key signal DS and to demodulate a serial data stream from the digital key signal DS for output as a parallel data signal PDS to the processing unit 762. In some embodiments, the clock circuit section 775 is configured to provide a clock signal CLK at the output terminal 767 of the control unit 760 and / or at the SD demodulator 766. In particular, in some implementations, the clock circuit section 775 includes a clock generator and a clock modulator configured to provide a modulated clock signal, for example, a frequency-modulated clock signal, or, to give another example, a clock signal modulated with respect to the duty cycle, as described above with reference to the Fig. 2 and Fig. 3 is described.

[0070] In some implementations, the control unit 760 includes a data receiving circuit section 799, which is also referred to herein as an analyzer, which is coupled, for example, via a data line 797 to the input port 769 of the control unit 760. In some embodiments, the data receiving circuit section 799 is also coupled, for example, via a control line 798 to the clock circuit section 775. The data receiving circuit section 799 is configured to receive data signals provided by the input port 769. Furthermore, in some implementations, the data receiving circuit section 799 is configured to receive control signals provided by the clock circuit section 775. In some embodiments, the data receiving circuit section 799 is configured to analyze data signals provided by the input port 769.In particular, the analyzer 799 is configured to distinguish digital key signals DS from other data signals DD in data signals provided by the input port 769, such as a signal carrying a predetermined state bit pattern.

[0071] In some implementations, a sensor unit can be coupled to the control unit 760, which is configured to output a predetermined state bit pattern, for example, during startup and / or wake-up. This state bit pattern is associated with the sensor unit's identity and / or the fact that the sensor unit is operational. In some implementations, the sensor unit coupled to the control unit 760 is configured to output the predetermined state bit pattern for a duration that is sufficiently long or longer than a predetermined duration during which the sigma-delta demodulator adjusts itself.In some implementations, the control unit 760 is configured, while receiving the bit pattern, to check whether the received bit pattern is one of a predetermined state bit pattern associated with a sensor unit known to the control unit 760 to be available for coupling and / or operation with the control unit 760. In some implementations, the control unit 760 is configured to output a message signal according to a predetermined state bit pattern of the sensor unit that identifies the control unit 760 as a source of the received bit pattern. In some implementations, the control unit 760 is configured to output an error signal if the received bit pattern differs from any predetermined state bit pattern.If, on the other hand, the received bit pattern corresponds to a predetermined bit pattern that is assigned to a sensor unit which is to be coupled to the control unit 760 in an operational state, the control unit 760 is configured to trust that the sensor unit is working as expected and is cooperating properly with the control unit 760.

[0072] In some implementations, the control unit 760 is configured to control a startup and / or wake-up operation with a sensor unit coupled to the control unit 760. Given that the sigma-delta modulator of the sensor unit typically requires some time to adjust before it is able to output any meaningful digital key signal DS, the control unit 760 can predetermine a time interval from the request for startup and / or wake-up, for example, by counting a predetermined number of clock cycles, with the circuit section 775 outputting a control signal CTRL to the data reception circuit section 799 via the signal line 798, which activates an interpretation of the received data.Thus, the data reception circuit section 799 can, for example, interpret the received data as sensor unit status data, extract sensor unit status information from the received data, and provide the sensor unit status information to the processing unit 762.

[0073] In some implementations, particularly in embodiments where the control line 798 is absent, and in implementations where the control line 798 is inactive or otherwise not used, the receiving circuit section 799 may be configured to analyze the received data signals so that the received data can be interpreted. In some implementations, interpreting the data involves determining a data type represented by the received data signal. In some embodiments, the interpretation, particularly the determination of the data type, is based on attribute information inherent in the received data signal. At least one effect may be that the interpretation of the received data signal can take into account different types of information representation in the received data signal.For example, in one embodiment where a sensor unit is coupled to the control unit 760, which is configured to measure pressure, the data reception circuit section 799 is configured to interpret the received data not as measurement data but as state data if the received data represents an impossible measurement value, such as a negative pressure value (“negative” is an attribute here). To give another example, the data reception circuit section 799 is configured to interpret the received data as measurement data if the received data cannot be assigned to any predetermined state bit pattern associated with the sensor unit coupled to the control unit 760 (“unassignable” is an attribute here).

[0074] Fig. Figure 8 represents a timeline 800 with both a clock signal CLK and a digital signal according to some implementations, for example as above with reference to the Fig. 6 and Fig. 7 is described. In some implementations, the sensor unit 610 is configured to transmit status data before transmitting digital key data to the control unit 660, 760 when starting up, which is sometimes also referred to as switching on, or when waking up from a power-saving mode, i.e., an operating pause 879, during which the energy consumption of the sensor unit is reduced relative to the energy consumption during a full operating mode. In some implementations described above, the clock signal CLK at the sensor unit 660 is received by the control unit 660, 760. It should be understood that in some embodiments described in Fig. 8 not shown, the received clock signal may be modulated, for example to create a wake-up request as above, for example with reference to Fig. 1 described how to communicate from the control unit to the sensor unit.

[0075] In some embodiments, the transmitter 687 of the sensor unit 610 is configured to frame status data according to a communication protocol such as a universal asynchronous receiver-transmitter (UART) protocol. For example, in some implementations, the transmitter 687 is configured to first transmit a UART data frame containing a start bit SOF 860 during a start interval 881, which lasts ten clock cycles; then a data transmission interval 882 to transmit one byte of a status data word (bits 861 to 868); and finally a stop transmission interval 891 to transmit a stop bit 870. Afterward, during an interval 892, the SD modulator 616 begins streaming digital key data DS bits 870, 871, ... to the control unit 660.At least one effect can be that status data can be transmitted from the sensor unit 610 to the control unit 660 while the SD modulator 616 is adjusting itself. It should be understood that in some implementations, status data may include control data, configuration data, a command (for example, to retransmit setting values ​​from the control unit 660 to the sensor unit 610), and so on. While the example describes a UART frame, it should be understood that a person skilled in the art may consider using other communication protocols to implement the techniques described herein.Meanwhile, in some implementations, the control unit 660 is configured to "know" about the protocol used by the sensor unit 610, and accordingly counts the clock cycles to interpret the received data, first as state data, and then as digital touch data representing a physical quantity. Exemplary company

[0076] The operation of some exemplary embodiments will now be briefly described. It should be understood that the features of the various embodiments described herein can be combined with one another, unless explicitly stated otherwise.

[0077] Accordingly, the following description refers to the Fig. 9 taken, which represents a block diagram of a measuring system 900 according to some embodiments, comprising many components described above with reference to the embodiments described in the Fig. Figures 1 to 8 are shown. Because the components, including the coupling of the components to each other and the functionality of the components of the measuring system 900 according to the embodiments shown in Fig. As shown in Figure 9, and already described above with reference to other figures, a separate description of the embodiment shown in Figure 9 is omitted here; Fig. 9 is shown.

[0078] Fig. Figure 10 represents a flowchart of a process that is implemented, for example, in the measuring system 900 according to some embodiments.

[0079] At S 10, the clock generator 973 generates a clock signal CLK, for example as in Fig. Figure 8 shows a clock edge 821. At S15, the communication interface 971 receives a request from the processing unit 962 to wake up the sensor 1, which is configured, for example, to measure temperature. The communication interface 971 provides a bit code

[001] that corresponds to the processing unit's request to the sigma-delta clock modulator 975. At S20, the sigma-delta clock modulator 975 modulates a duty cycle of the clock signal CLK, as shown, for example, in Fig. Figure 2i shows how to encode the bit code

[001] into a modulated clock signal mCLK. At S25, the sigma-delta clock modulator 975 transmits the modulated clock signal mCLK via a clock output port 967 of the control unit 960 and further via an interface 950 at an electrical isolation barrier, which separates a control ground potential 906 from a sensor ground potential 901, to a clock input port 919 of the sensor unit 910. At S30, still connected to the control unit 960, a counter (not shown) counts clock cycles.

[0080] At S 35, now at the sensor unit 910, a sigma-delta clock demodulator 922 receives the modulated clock signal mCLK in order to extract the bit sequence

[001] encoded in the modulated clock signal mCLK. At S40, a communication interface 924 receives the bit sequence

[001] from the sigma-delta clock demodulator 922 and outputs a corresponding request signal to an input and modulator configuration module 926. Still at S40, the input and modulator configuration module 926 outputs a selection signal to the multiplexer 914. Furthermore, the input and modulator configuration module 926 outputs an amplifier setting signal to the input stage 914.

[0081] At S45, the multiplexer 914 selects a first analog signal AS1, received from a temperature sensor element 942 via a sensor unit input terminal 943, according to the selection signal received from the input and modulator configuration module 926, and forwards the selected first analog signal AS1 to the input stage 914 and to the comparator 983. At S45, the comparator 983 compares the first analog signal AS1 with a threshold voltage level set at the reference voltage terminal 982. The comparator 983 outputs a bit signal BS = 0 to a transmitter 987, and the transmitter 987 outputs a corresponding selection signal SEL to a multiplexer 990. Additionally, the transmitter 987 outputs state data received by the state circuit section 985 to the multiplexer 990 in a data state data signal DD. According to some embodiments, the digital status data signal DD lasts for a number of clock cycles.In some implementations, the state data transmitted in a data frame, as shown in one implementation, is according to the Universal Asynchronous Receiver-Sender (UART) protocol, which is described in . Fig. Figure 8 is shown. Meanwhile, the input stage 914 processes the selected first analog signal AS1 according to the gain setting signal received from the input and modulator configuration module 926. The input stage 914 provides a processed analog signal PAS to the sigma-delta modulator 916. The sigma-delta modulator 916 outputs a digital key signal DS to the multiplexer 990.

[0082] At S 50, the multiplexer 990 selects the status data received from transmitter 987 according to the selection signal SEL received from transmitter 987. At S55, the digital status data signal DD is transmitted by the multiplexer 990 via an output port 917 of the sensor unit 910 and via the interface 950 to an input port 969 of the control unit 960.

[0083] At S60, the digital signal received at the control unit 960 is provided at the signal input port 969 of the sigma-delta demodulator 966, as well as at the data receiving circuit section 999. As long as the number of clock cycles, counted at S30, does not exceed the predetermined limit, for example, ten clock cycles, the clock circuit section 975 outputs a control signal CTRL to the data receiving circuit section 999, which requires an interpretation of the received digital signal in order to extract state information from it, i.e., based on the fact that the received digital signal is indeed the digital state data signal DD.Accordingly, the data reception circuit section 999 provides a bitword to the processing unit 962 via a bus 963 for further processing, according to which the bitword indicates that the sensor element 942 is responding to the request and is ready for operation, and that the sensor element 942 will soon provide measurement data to the control unit 960.

[0084] After a number of clock cycles have been completed, the sensor element 942 provides a stronger signal than at the beginning of the wake-up process. Now, again at S45, if the analog signal AS1 provided by the first sensor element 942 exceeds the voltage level VTH, the comparator 983 outputs a bit signal BS = 1 to the transmitter 987, and the transmitter 987 outputs a corresponding selection signal SEL to a multiplexer 990. Again at S50, according to the selection signal SEL received from the transmitter 987, the multiplexer 990 selects the digital key signal DS received by the sigma-delta modulator 916. Again at S55, the digital key signal DS is transmitted by the multiplexer 990 via the output port 917 of the sensor unit 910 and via the interface 950 to the input port 969 of the control unit 960.

[0085] At S60, the digital signal received at the control unit is routed from a signal input port 969 to the sigma-delta demodulator 966 and to a data receiving circuit section 999. Once the number of clock cycles, counted at S30, exceeds the predetermined limit—for example, if more than ten clock cycles have passed since the wake-up request was issued to the sensor unit 910—the clock circuit section 975 then outputs a control signal CTR L to the data receiving circuit section 999, instructing it to terminate the interpretation of the received digital signal. Instead, the sigma-delta demodulator 966 provides a parallel digital signal to the processing unit 962 via bus 963 for further processing.Thus, the control unit 960 interprets the received digital signal as a digital representation of an analog signal and extracts measurement information from the received digital signal, based on the fact that the received digital signal is indeed a digital key signal DS representing the processed analog signal PAS.

[0086] Further embodiments are described below. However, it is intended that this invention is limited only by the claims and their equivalents. Exemplary embodiments with clock signal modulation

[0087] In one respect, the description describes a method for use in a measurement system. In some embodiments, the measurement system includes a barrier that electrically isolates a first ground potential from a second ground potential. Thus, the second ground potential can differ from the first ground potential. The method includes receiving, at an interface provided on the barrier, on a control side of the barrier, a clock receive signal representing a clock signal and control information, which includes, for example, configuration information. The method includes providing, based on the clock receive signal, a control signal representing at least the control information. In some embodiments, the provision occurs on a sensor side of the barrier.The method includes transmitting the control signal from the interface to a sensor unit on the sensor side of the barrier. Some embodiments include operating the sensor unit according to the control information. Some embodiments include configuring the sensor unit according to the configuration information included in the control information. Some embodiments include, based on the clock reception signal, providing a clock transmission signal containing the clock signal and transmitting the clock transmission signal to the sensor unit.

[0088] Some implementations, particularly on the control side of the barrier, involve modulating the clock signal according to the control information to obtain the received clock signal. Specifically, the clock signal is modulated according to information other than the timing signal. At least one effect of this is that the modulated clock signal, which serves as the received clock signal, allows the control information to be transmitted across the barrier along with the clock signal. Therefore, in some implementations, no extra line is required. In some embodiments, the clock signal modulation involves varying the duty cycle of the clock signal. In some implementations, this variation is performed between at least two predetermined duty cycle values, which are associated with a binary representation, i.e., in some implementations, specifically a binary representation of the control information.For example, a duty cycle of 0.3 can be modulated to a duty cycle of 0.7, and vice versa. In some embodiments, a bit value can be assigned to the respective duty cycle value, for example, a bit value of zero to a duty cycle of 0.7 and a bit value of one to a duty cycle of 0.3, or vice versa. Or, to give another example, a duty cycle of 0.4 can be modulated to 0.6, and vice versa. Other modulations can be asymmetrical, such as a duty cycle of 0.3 being modulated to 0.6, and vice versa. In some embodiments, the modulation involves varying a number of clock cycles to form a clock pulse width such that a bit value is represented that is assigned to the clock pulse width.

[0089] Some embodiments include providing a clock transmission signal containing the clock signal on the sensor side of the barrier, based on the clock reception signal. Some implementations of the method then include transmitting the clock transmission signal from the sensor unit to the sensor unit.

[0090] In some embodiments, the sensor unit includes an analog-to-digital converter. Some embodiments include providing an analog keying signal to the analog-to-digital converter. Furthermore, some implementations include clocking based on the clock signal from the analog-to-digital converter. Some implementations include converting the analog keying signal into a digital keying signal. In some embodiments, the analog-to-digital converter is used in the conversion process.

[0091] Some embodiments include referencing the analog-to-digital converter to a sensor unit reference voltage. Some embodiments include referencing the control unit to a control unit reference voltage. In some implementations, the sensor unit reference voltage differs from the control unit reference voltage. In some embodiments, at least one of the following is performed according to and / or based on configuration information included in the control information: receiving the analog key signal, converting the analog key signal to the digital key signal, and transmitting the digital key signal to the interface.

[0092] Some embodiments involve transmitting the digital touch signal from the sensor side of the barrier to the interface. Some embodiments involve transmitting the digital touch signal from the interface to the control side of the barrier. At least one effect can be that the digital touch signal is transmitted across the barrier, i.e., from the analog-to-digital converter via the interface to the control unit.

[0093] In another respect, the description describes an interface for use in a measurement system comprising a barrier that electrically isolates a first ground potential on a sensor side of the barrier from a second ground potential on a control side of the barrier. Some embodiments of the interface include a first receive terminal configured to receive a digital receive signal from a sensor unit on a sensor side of the barrier, wherein the interface is configured to provide a digital transmit signal representing the digital receive signal, i.e., information carried or otherwise represented by the digital receive signal. Furthermore, the interface includes a first transmit terminal configured to transmit the digital transmit signal to a control unit on the control side of the barrier.In some embodiments, at least one effect may consist of the interface being configured to receive the digital receive signal from the sensor side of the barrier, which is referenced to a first reference voltage, and further in that the interface being configured to forward the transmit signal across the barrier to the control side of the barrier, which is referenced to a second reference voltage. Some embodiments include a second receive terminal configured to receive the clock receive signal from the control side of the barrier. In some embodiments, the interface is configured to provide a control transmit signal based on the clock receive signal, which includes control information provided with the clock receive signal.Some embodiments include a second transmission terminal configured to transmit the control transmission signal from the interface to the sensor unit. In some embodiments, the interface is configured to extract control information, such as configuration information, from the clock receive signal. At least one effect may be that the interface interprets the control information, if any, provided with the clock receive signal. In some embodiments, at least one effect may be that the interface can work with a conventional analog-to-digital converter that is not configured to use control information, while the interface provides the control information to the sensor unit regardless of whether the sensor unit interprets the information or not.For example, in some embodiments, the interface emits the control information represented by the clock transmission signal. In some embodiments, the sensor unit uses the clock signal provided with the clock transmission signal, for example, to clock the operation of a sigma-delta converter, but it does not use any control information provided with the clock transmission signal.

[0094] In some embodiments, the interface is configured to provide a control transmission signal representing the control information based on the clock reception signal. At least one effect can be that the interface, using the control transmission signal, can transmit the received control information, for example, from the control unit on a control side of the barrier to the sensor unit on the sensor side of the barrier. In particular, the interface can provide configuration information as control information for use in operating an analog-to-digital converter contained in the sensor unit.

[0095] In some embodiments, the interface is configured to provide the control transmission signal in such a way that it represents both the clock signal and the control information. At least one effect can be that when transmitting the clock transmission signal, both the clock signal and control information, in particular the configuration information, can be transmitted on a single line.

[0096] Some embodiments include a third transmission terminal configured to transmit the control transmission signal separately from the clock transmission signal. At least one effect may be that another receiver on the sensor side of the barrier can receive the control transmission signal. Thus, for example, if another receiver is a setting register of the sensor unit, control information can be transmitted to the sensor unit to adjust the setting register according to the setting information contained in the control information.

[0097] In some embodiments, the interface is configured to extract the control information from the clock receive signal, for example, by demodulating the clock receive signal. In some embodiments, the interface is configured to extract the control information from the clock receive signal by interpreting the width of pulses contained in the clock receive signal. In some embodiments, the interface is configured to extract the control information from the clock receive signal by interpreting the duty cycle of the clock receive signal. In some implementations, the extracted control information is configuration information for use when configuring the sensor unit.

[0098] In some embodiments, the interface is configured to form the clock transmission signal in such a way that the control transmission information is excluded. At least one effect of this is that the interface can work with a conventional sensor unit that requires a predetermined clock signal shape.

[0099] In some embodiments, the first receive terminal end on the sensor side of the barrier is configured to be referenced to a sensor-side reference voltage, such as a first ground potential, which is also referred to herein as a sensor-side ground potential, while the first transmit terminal end is configured to be referenced to a control-side reference voltage, such as a second ground potential, which is also referred to herein as a control ground potential. In some embodiments, the second receive terminal end is configured to be referenced to the control-side reference voltage, and the second transmit terminal end is configured to be referenced to the sensor-side reference voltage.At least one effect can be that the interface electrically isolates the control side from the sensor side in order to achieve operation, particularly on the control side, that is resistant to variations in the reference voltage on the sensor side.

[0100] In another respect, the description describes a control unit for use in a measurement system that includes a barrier electrically isolating a control-side reference voltage from a sensor-side reference voltage. The control unit is configured to operate at a control-side reference voltage and to process data acquired and / or received by at least one sensor unit. The control unit is further configured to connect to an interface provided at the barrier, which is configured to communicate across the barrier with one or more sensor units operating at a sensor-side reference voltage. The control unit is also configured to connect to a clock unit connected to the interface, thereby providing a clock signal at the interface.Furthermore, the control unit is configured to provide control information to the clock unit for modulating the clock signal in order to form a modulated clock signal that represents the control information.

[0101] In a further respect, the invention comprises a measuring system including a barrier that electrically isolates a first reference voltage from a second reference voltage. The measuring system is configured for use in acquiring measurement data. The measuring system includes a control unit configured to operate with a control-side reference voltage, such as a control-side ground potential. In some embodiments, the control unit is configured to process data acquired, for example, from at least one sensor unit. The measuring system further includes an interface coupled to the control unit. This interface is also configured to couple to one or more sensor units that operate with a sensor-side reference voltage, such as a sensor-side ground potential.The measurement system is configured to provide a clock signal at the interface. Some embodiments include a clock unit coupled to the interface. In some embodiments, the clock unit is configured to provide the clock signal at the interface. In some embodiments, the interface is configured to create a control transmission signal based on the clock signal. In some embodiments, the control unit is configured to provide control information to the clock unit. In some embodiments, the clock unit is configured to create a clock receive signal at the interface, which is designed to include both the clock signal and the control information in a single clock receive signal provided at the interface.In some embodiments, the clock unit is configured to generate the received clock signal by modulating the clock signal according to information other than the time input. In some embodiments, the modulation involves varying a number of sigma-delta clock cycles to generate a clock signal pulse width that corresponds to a binary representation of the control information, i.e., in some embodiments, such that a bit value is represented.

[0102] In yet another respect, the disclosure includes a sensor unit for use in acquiring measurement data. The sensor unit comprises an analog-to-digital converter configured to convert an analog keying signal into a digital keying signal. In some embodiments, the sensor unit is configured to receive a clock signal. The sensor unit is configured to extract a clock signal from the clock signal. In some embodiments, the sensor unit is configured to extract control information from the clock signal. In some embodiments, the sensor unit is configured to configure the analog-to-digital converter according to configuration information contained in the control information.At least one possible effect is that the sensor unit can be configured to switch data acquisition modes, enabling the acquisition of data regarding different physical quantities. For example, the sensor unit can be configured to switch between measuring temperature and current.

[0103] In yet another respect, the description includes a medium for storing instructions which, when executed, cause one or more processors to perform steps of a procedure for use in acquiring measurement data. The procedure includes receiving a clock signal at an interface; providing, based on the clock signal, a control transmission signal representing control information contained in the clock signal; transmitting the control transmission signal to an analog-to-digital converter; and adjusting the analog-to-digital converter according to the control information. Exemplary embodiments with data transmission of different types

[0104] This description describes a method for use in a measurement system. The system includes a sensor unit. The number of sensor units included in the system need not be limited to one. In some embodiments, the system includes multiple sensor units. The measurement system includes a control unit. In some implementations, the control unit is configured to process data provided by the sensor unit. In some embodiments, the sensor unit is configured to detect a quantity, in particular a physical quantity such as acceleration, current (especially phase current), voltage, and the like. In some embodiments, the sensor unit is configured to generate a sensor data signal representing the quantity. The sensor data signal is to be transmitted from the sensor unit to the control unit.In some embodiments, the method includes receiving a data reception signal at the control unit. In some embodiments, the data reception signal is the sensor data signal received by the sensor unit, for example, when it is provided by the sensor unit. In some embodiments, the method includes translating the data reception signal to be at least one of the sensor data signal and another data signal. In some embodiments, the interpretation is the selection of a predetermined interpretation, and the selection is based on predetermined selection criteria. At least one effect may be that the translation of the data reception signal can take into account the plausibility of the data reception signal with respect to a representation of one type of information among several possible types of information.

[0105] In some embodiments, the interpretation relies on attribute information inherent in the received data signal. At least one effect can be that the interpretation of the received data signal can take into account different types of information representation within the signal. For example, a first type of information representation might be a coarse, few-bit representation of a number, while a second type of information representation might be a more precise representation of the number with many bits. In some embodiments, the few-bit representation of the number is provided as a single-bit representation that indicates whether the quantity to be detected exceeds a predetermined threshold.At least one further effect can be that the transmission of control information containing attribute information from the sensor unit to the control unit can be avoided. In particular, in an embodiment where the use of bandwidth for information transmission is very limited, the use of bandwidth can be restricted to such an extent that only load data is transmitted. Thus, at least one effect can be that a single data signal can be used to transmit information about multiple parameters. For example, where the parameter is sensor control, the information is interpreted as sensor control information. For example, where the parameter is a measurement of a first quantity, the information is interpreted as a detected value of the first quantity.For example, where the parameter is a measurement of a second quantity, the information is interpreted as a recorded value of the second quantity. At least one effect can be that the single data signal can be used to transmit information about the same parameter with different levels of accuracy. To give another example, where the parameter is a representation of a measured quantity with a first level of accuracy, a 1-bit representation, for instance, is interpreted as a low-precision digital representation. Conversely, where the parameter is a representation of a measured quantity with a second level of accuracy, the information is interpreted as a high-precision digital representation of the measured quantity; for example, a multi-bit representation is interpreted as a high-precision digital representation.Thus, in some cases, the value can be acquired quickly with a low degree of accuracy during the sensor unit's startup, while a measurement with a comparatively higher degree of accuracy may require more time after startup or wake-up. Accordingly, the value is adequately represented by a coarse digital representation during startup, while at a later time it is more appropriately represented by a digital representation with high accuracy. The single data signal can therefore initially be used to transmit the result of a measurement with low accuracy before being used later to transmit the result of a measurement with higher accuracy.

[0106] In some embodiments, the attribute information is time information. In some embodiments, the time information is the duration of an interval between a time at which a control signal was sent to the sensor unit and a time at which the data reception signal was received. At least one effect may be that the time information can be used to imply plausibility.For example, where a wake-up request has been sent to the sensor unit, which is assumed to be in a substantially non-operational sleep state or other power-saving mode, and where the data reception signal is received a short time later, it is plausible that the sensor unit has not yet responded by transmitting any meaningful measurement data because the sensor unit needs time to transition from the sleep state in a power-saving mode to an operational state with full power. In some embodiments, a transition time is predetermined that is sufficiently long to allow the sensor unit to transition from a first state to an operational state that differs from the first state. In some embodiments, the first state is a low-power mode, and the control signal indicates a wake-up request.

[0107] In some embodiments, the attribute information is a bit pattern received with the data receive signal. At least one effect may be that, in a system with a single data signal line, information relating to multiple parameters can be transmitted particularly efficiently. In some embodiments, the attribute information is a value represented by the data receive signal. At least one effect may be that, if the data receive signal is interpreted as representing a value of the first data type, it provides an implausible value, for example, a negative scalar velocity value; the data receive signal can be plausibly interpreted as representing a value of the second data type, for example, a negative temperature in degrees Celsius.

[0108] This discloses, in another respect, a sensor unit for use in measurement data acquisition, comprising a first analog-to-digital converter configured to output a digital signal at a first resolution derived from an analog keying signal, and a second analog-to-digital converter configured to output a digital keying signal at a second resolution derived from the analog keying signal. The sensor unit is configured to selectively transmit either the digital keying signal at the first resolution or the digital keying signal at the second resolution, depending, for example, on whether a predetermined condition is met.Assuming that, during the startup of the sensor unit, the digital keying signal in the first resolution can be generated as a true representation of a detected quantity faster than the digital keying signal in the second resolution can be generated as a true representation of the detected quantity, at least one effect can be that the sensor unit can quickly provide a true representation of the detected quantity, albeit of low resolution, by using the first analog-to-digital converter, before it is able to provide a true representation of the detected quantity at high resolution by using the second analog-to-digital converter.

[0109] In some embodiments, the first analog-to-digital converter is provided as a comparator configured to compare the analog test signal with a threshold value. In some embodiments, the first-resolution digital test signal is the 1-bit comparison result signal. In some embodiments, other information, such as sensor unit status information, is convolved onto the 1-bit comparison result signal. For example, where a comparison bit value of 1 indicates that the sensor unit is not yet ready for a high-resolution measurement, but rather that the sensor unit is operating and / or that the physical quantity is being acquired, configuration data, such as an identification mark associated with a sensor element or converter used in the measurement, is ORed or otherwise combined with the comparison bit value 1 and transmitted to the control unit.In some embodiments, the second-resolution digital keying signal includes a multi-bit representation derived from the analog keying signal. In some embodiments, the first analog-to-digital converter forms a structural part of the second analog-to-digital converter; for example, the first analog-to-digital converter forms a section containing the most significant bit of the second analog-to-digital converter. In some embodiments, the sensor unit is configured to transmit the 1-bit comparison result signal for a predetermined duration after startup before transmitting the second-resolution digital keying signal.

[0110] In some embodiments, the measuring system includes a barrier that electrically isolates a first reference voltage, such as a first ground potential, from a second reference voltage, such as a second ground potential. The sensor unit is provided on a sensor side of the barrier, while the control unit is provided on a control side of the barrier. A communication interface is provided on the barrier. In some embodiments, the sensor unit transmits the status data signal and the second digital key signal to the control unit via the communication interface on the barrier. In some embodiments, the control unit transmits control information and / or a clock signal to the sensor unit via the communication interface on the barrier. Furthermore, the description discloses a sensor unit for use in acquiring measurement data.The sensor unit includes an analog-to-digital converter configured to output a first-resolution digital key signal derived from an analog key signal. The sensor unit also includes a second analog-to-digital converter configured to output a second-resolution digital key signal derived from the first analog key signal. The sensor unit is configured to output either the first-resolution digital key signal or the second-resolution digital key signal, selectably.

[0111] In some embodiments, the first analog-to-digital converter is provided as a comparator configured to compare the analog test signal to a threshold. In some embodiments, the first-resolution digital test signal is the 1-bit comparison result signal. In some implementations, the sensor unit is configured to transmit the 1-bit comparison result signal for a predetermined duration after the sensor unit has powered on or woken up, before transmitting the second-resolution digital test signal. In some embodiments, the second-resolution digital test signal includes a multi-bit representation derived from the analog test signal.

[0112] In another respect, a sensor unit is disclosed herein, comprising an analog-to-digital converter that can be operated to derive a digital key signal from an analog key signal, and a control unit configured to derive a status data signal from status information. In some embodiments, the status information relates to a state of the sensor unit, for example, settings and / or a configuration of the analog-to-digital converter. In some embodiments, the control unit is further configured to receive operating information. The control unit is configured, in some embodiments, to derive a selection signal based on the operating information. The sensor unit further comprises a transmission selection unit, for example, a multiplexer, configured to receive the selection signal.In some embodiments, the transmission selection unit is configured to generate a digital transmission signal, based on operational information such as the selection signal, which indicates the status data signal or the digital key signal. At least one effect may be that a given transmission device and / or transmission medium, such as a wire (e.g., for serial communication), can be used to transmit status data instead of the digital key signal, for example, when the digital key signal is unlikely to represent meaningful data, such as during analog-to-digital converter initialization. In some implementations, the status data signal includes the result of a comparison of the analog key signal with a reference signal.In some embodiments, the reference signal is provided as a predetermined threshold voltage level.

[0113] In some embodiments, the transmission selector unit is configured to receive the digital keying signal and the status data signal. In some embodiments, the reception of the digital keying signal and the reception of the status data signal can be independent of each other; for example, in some implementations of such embodiments, the reception of both signals can occur simultaneously.

[0114] In some embodiments, the transmission selection unit is configured to output the status data signal or the digital keying signal as a sensor unit output signal according to the digital transmission signal.

[0115] In some embodiments, the sensor unit is configured to couple to an interface with a measurement system control unit. At least one effect of this is that, where the interface is configured to electrically isolate the measurement system control unit from the sensor unit, the sensor unit can operate at a sensor reference voltage, while the measurement system control unit can operate at a control unit reference voltage. In some implementations, the sensor reference voltage and the control unit reference voltage can drive independently and / or vary randomly relative to each other. In some embodiments, the sensor unit is configured to provide the sensor unit output signal at the interface.

[0116] In some embodiments, the sensor unit is configured to receive a clock signal from the interface. In some embodiments, the sensor unit is configured to extract a clock signal from the clock signal for use in the operation of the analog-to-digital converter. In some embodiments, the sensor unit is configured to extract control information from the clock signal. In some embodiments, the sensor unit is configured to configure the analog-to-digital converter according to the control information.

[0117] In yet another respect, the description describes a device configured to control measurement data acquisition. The device comprises a discriminator unit configured to be coupled to an interface configured to communicate with the sensor unit. The discriminator unit is configured to receive a digital signal from the interface. In some embodiments, the discriminator unit is further configured to distinguish a status data signal, representing, for example, information about a state of the sensor unit, from a digital key signal contained within the digital signal received from the interface. The device also includes a processing unit coupled to the discriminator unit and configured to process the digital key signal.

[0118] In some embodiments, the processing unit is configured to extract state data from the state data signal. In some embodiments, the discriminator unit is configured to base the discrimination on at least one of the following: time information, a bit pattern contained in the digital signal, and a bit value represented by the digital signal. At least one effect can be that the discrimination can be based on an appearance of the digital signal received from the interface. In some embodiments, the time information is a difference from a point in time at which the device, for example using the interface, directed a control signal to the sensor unit.At least one effect can be that the control signal can be used to initiate a configuration of the control unit or to transition the sensor unit from a first operating mode to a second operating mode. For example, the control signal can indicate a request for the sensor unit to wake up from a low-power or reduced-power state, such as a sleep or hibernation state, to a full-power mode, such as an operating mode or state. In some embodiments, the difference is sufficiently predetermined to allow the sensor unit to transition from a first state to an operating state that differs from the first state. At least one effect can be that the difference can be sufficiently large to allow the sensor unit to transition from a low-power mode to a full-power mode.

[0119] In yet another respect, the description describes a measurement system for use in the acquisition of measurement data. The measurement system comprises at least one sensor unit configured to generate an analog key signal based on a detected quantity and to create a digital key signal based on the analog key signal. The measurement system includes an interface coupled to the at least one sensor unit and configured to receive the digital key signal, a discriminator unit configured to extract a digital key signal from the digital data signal received at the discriminator, and a processing unit coupled to the interface and configured to receive the digital key signal from the interface.In some embodiments, the discriminator unit is coupled to the control unit and configured to extract state data from a state data signal contained within the digital data signal received at the discriminator. The state data includes, for example, setting information, configuration information, power supply information, identification information about the coupled sensor element, and / or input stage gain information used at the sensor unit. At least one effect may be that the processing unit can use the state data when processing the digital data signal.

[0120] Some embodiments include a clock unit coupled to the interface and configured to transmit a clock transmission signal over the interface, representing a clock signal. In some embodiments, the clock unit is configured to form the clock transmission signal such that, in addition to the clock signal, it represents control information, such as a configuration request and / or a setting value.

[0121] In yet another respect, the description describes a medium that includes a sequence of operational processes which, when executed, perform operations of a method for use in acquiring measurement data. The method comprises receiving a data receive signal at a control unit, provided by a sensor unit configured to detect a quantity and to generate a sensor data signal corresponding to the data receive signal. The method further comprises interpreting the data receive signal to represent at least one of the following: a sensor data signal and other data signals, wherein the interpretation is based on attribute information inherent in the data receive signal. In some embodiments, the attribute information is a difference from a time at which a control signal was sent to the sensor unit.In some embodiments, the difference is sufficiently large to allow the sensor unit to transition from a low-power mode to a high-power mode. In some embodiments, the attribute information is a value represented by the received data signal. In some embodiments, the medium includes a state machine configured to perform the operations. In some embodiments, the medium is configured to store instructions which, when executed, cause one or more processors to perform the operations.

[0122] Other embodiments include the computer program for performing one of the methods described herein, which is stored on a machine-readable data carrier. One embodiment is a data carrier (or a digital storage medium or a computer-readable medium) that contains, recorded on it, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium, or the recorded medium is usually physical and / or non-perishable.

[0123] As used herein, 'extracting the clock signal and / or extracting the other signal', particularly where the clock signal and the other signal are multiplexed or interwoven, do not in every case require a separation of the one from the other, but also include linear processing of the received clock signal, for example by amplifying the received clock signal to form the transmitted signal.

[0124] Some or all of the process steps described herein may be performed by (or using) a hardware device such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, a device with programmable logic (for example, a field-programmable gate array) may be used to perform some or all of the functionalities of the processes described herein. In some embodiments, a field-programmable gate array may cooperate with a microprocessor to perform one of the processes described herein.

[0125] In general, the procedures can be carried out by any hardware device.

[0126] The disclosed arrangements can be implemented in hardware, either partially or entirely, using logic circuits or VLSI design.

[0127] As used herein, various connections, including a communication channel connecting elements, may be wired connections or wireless connections, or any combination thereof, or any other or subsequently developed elements capable of providing data to and from the connected elements and / or communicating.

[0128] As used herein, the terms 'unit' or 'module' can refer to any known or subsequently developed hardware, software, firmware or combination thereof capable of performing the functionality assigned to the element.

[0129] As used herein, the word 'terminal end' means a conductive line or other circuit element or circuit configured to connect the coupled components. In some implementations, two terminal ends, that is, a first terminal end and a second terminal end, may be implemented in essentially the same location and / or formed in a single physical structure, for example, as a single segment of a signal bus line.

[0130] As used herein, the word 'exemplary' means to serve as an example, instance, or representation. Any viewpoint or design described herein as 'exemplary' should not necessarily be understood as preferable or advantageous in relation to any other viewpoint or design. Rather, the use of the word exemplary is intended to present concept and techniques in a specific way.

[0131] As used herein, the term ‘techniques’ may, for example, refer to one or more devices, apparatus, systems, processes or manufactured articles and / or to computer-readable commands, as indicated in the context described herein.

[0132] As used herein, the articles 'ein', 'eine' and 'eines' should generally be understood to mean 'one or more' unless otherwise stated or it is clear from the context that the singular is meant.

[0133] As used herein, the term 'or' is intended to mean an inclusive 'or' and not an exclusive 'or'.

[0134] As used herein, terms such as 'first', 'second' and the like are also used to describe different elements, areas, sections, etc., and are not intended to be restrictive.

[0135] As used here, the terms 'low resolution' and 'high resolution' are meant in relation to each other. Thus, 'low resolution' means a resolution that is lower than the high resolution, and 'high resolution' means a resolution that is not as low as the low resolution.

[0136] As used herein, the terms 'coupled' and 'connected' can be used to describe an interface between different elements. Unless explicitly stated or at least implied otherwise, such described interfaces between different elements can be either direct or indirect.

[0137] As used herein, the terms 'exhibit', 'contain', 'include', 'with' or variants thereof, and similar terms are open terms intended to be inclusive. These terms indicate the presence of the element or feature mentioned, but they do not exclude additional elements or features.

[0138] As used herein, the word 'transceiver' means a complete arrangement of transmitter functionality and receiver functionality. In some implementations, the transmitter functionality and the receiver functionality are combined in a single device such as a single circuit, but the transmitter functionality and the receiver functionality need not necessarily be located together.

[0139] The order in which the embodiments / implementations and procedures / processes are described should not be considered a restriction, and any number of the described implementations and processes can be combined.

[0140] The implementations described herein are exemplary embodiments. However, it should be understood that individual aspects of the implementations can be claimed separately and that one or more features of the different embodiments can be combined.

[0141] Exemplary implementations / designs described herein may have different components arranged together; however, it should be understood that the components of the arrangements may be combined in one or more devices.

[0142] In some examples, well-known features have been omitted or simplified to make the description of the exemplary implementations easier to understand.

[0143] Although some aspects are described in connection with an apparatus, these aspects also constitute a description of the corresponding process, where a block or device corresponds to a process step or a feature of a process step. In the same way, aspects described herein in connection with a process step also constitute a description of a corresponding block or point or feature of a corresponding apparatus.

[0144] Although certain embodiments are presented and described herein, the person skilled in the art will understand that a multitude of other and / or equivalent implementations may replace the specific embodiment shown and described without departing from the scope of the present invention. The application is intended to cover any adaptations and variations of the specific embodiments explained herein.

Claims

[1] A method for use in a measuring system (100) comprising a barrier separating a first earth potential (101) from a second earth potential (106), the method comprising - at an interface (150) provided at the barrier, receive, on a control device side of the barrier, a clock receiving signal that represents a clock signal (CLK) and control information, - To provide, based on the clock reception signal, a control signal that represents at least the control information, - Transmission of the control signal from the interface (150) to a sensor unit (110) on the sensor side of the barrier, and - Operating the sensor unit (110) according to the control information. [2] The method of claim 1, comprising: - Modulating the clock signal (CLK) according to the control information to obtain the clock reception signal. [3] The method according to claim 1, wherein modulating the clock signal (CLK) comprises: varying a duty cycle of the clock signal (CLK) between at least two predetermined duty cycle values ​​which are associated with a binary representation of the control information. [4] The method according to claim 3, wherein the modulation comprises: varying a number of clock cycles to form a clock signal pulse having a length such that it represents a bit value associated with the length. [5] The method according to claim 1, comprising - based on the clock reception signal, providing, at the sensor side of the barrier, a clock transmission signal that includes the clock signal (CLK), and - Transferring the clock transmission signal to the sensor unit (110). [6] The method according to claim 5, wherein the sensor unit (110) comprises an analog-to-digital converter, the method comprising - at the analog-to-digital converter, providing an analog test signal, - Clocking, based on the clock signal (CLK), of the analog-to-digital converter, and - Converting the analog key signal into a digital key signal, using the analog-to-digital converter in the conversion process. [7] The method according to claim 6, comprising - Referencing the analog-to-digital converter to a sensor unit reference voltage, and - Referencing a control unit (160) to a control unit reference voltage, wherein the sensor unit reference voltage is different from the control unit reference voltage. [8] The method according to claim 6, further comprising - Transmission of the digital touch signal from the analog / digital converter on the sensor side of the barrier, via the interface (150), to the control side of the barrier. [9] An interface (150) for use in a measuring system (100) comprising a barrier that electrically isolates a first earth potential (101) at a sensor side of the barrier from a second earth potential (106) at a control side of the barrier, comprising a first receiving terminal configured to receive a digital receive signal from a sensor unit (110) on the sensor side of the barrier, wherein the interface (150) is configured to provide a digital transmit signal representing the digital receive signal; a first transmission terminal configured to transmit the digital transmission signal to a control unit (160) on the control side of the barrier; a second receive terminal configured to receive a clock receive signal from the control side of the barrier, wherein the interface (150) is configured to transmit a control transmit signal based on the clock receive signal, which includes control information provided by the clock receive signal; and a second transmission terminal end configured to transmit the control transmission signal to the sensor unit (110). [10] The interface (150) according to claim 9, wherein the interface (150) is configured to transmit a clock transmission signal to the sensor unit (110) on the basis of the clock reception signal, which represents a clock signal (CLK) that is provided with the clock reception signal. [11] The interface (150) according to claim 10, wherein the interface (150) is configured to provide the control transmission signal in order to represent both the control information and the clock signal (CLK). [12] The interface (150) according to claim 10, wherein the interface (150) is configured to perform one of a group comprising: Demodulating the clock reception signal; Interpreting a pulse width contained in the clock reception signal; and Interpreting the duty cycle of the clock reception signal to extract the control information from the clock reception signal. [13] The interface (150) according to claim 9, wherein the interface (150) is configured to provide the clock transmission signal in such a way that the control transmission signal is excluded. [14] The interface (150) according to claim 13, further comprising a third transmission terminal end configured to transmit the control transmission signal separately from the clock transmission signal. [15] The interface (150) according to claim 9, wherein the first receiving terminal end on the sensor side of the barrier is configured to reference the first earth potential (101) as a reference voltage, and the first transmit signal on the control side of the barrier is configured to reference the second earth potential as a control-side reference voltage. [16] The interface (150) according to claim 9, wherein the second receive terminal end is configured to be referenced to the second earth potential (106) as a control-side reference voltage and the second transmit terminal end is configured to be referenced to the first earth potential (101) as a sensor-side reference voltage. [17] A control unit (160) for use in a measuring system (100) comprising a barrier that separates a control-side reference voltage from a sensor-side reference voltage, wherein the control unit (160) is configured to process data acquired by at least one sensor unit (110), wherein the control unit (160) is further configured to couple to an interface which is configured to communicate across the barrier with one or more sensor units (110) which are operated at the sensor-side reference voltage, wherein the control unit (160) is further configured to couple to a clock unit which is coupled to the interface (150) to the interface (150) to provide a clock signal (CLK), wherein the control unit (160) is configured to provide control information to the clock unit to modulate the clock signal (CLK) so that it forms a modulated clock signal (CLK) that represents the control information. [18] The control unit (160) according to claim 17, wherein the control unit (160) is configured to operate at the control-side reference voltage, wherein one or more sensor units (110) are configured to operate at the sensor-side reference voltage, and where the control-side reference voltage and / or the sensor-side reference voltage are independent of each other and / or vary over time. [19] A measuring system (100) comprising a barrier that electrically separates a first reference voltage from a second reference voltage, wherein the measuring system (100) is configured for use in the acquisition of measurement data, the measuring system (100) comprising a control unit (160) configured to operate at a control-side reference voltage and to process data acquired from at least one sensor unit (110); the measuring system (100) comprising an interface (150) which is provided at the barrier and which is coupled to the control unit (160), wherein the interface (150) is configured to couple to one or more sensor units (110) which are operated at a sensor-side reference voltage; and that measuring system (100) further comprising a clock unit which is connected to the interface (150) is coupled and is configured to provide a clock signal (CLK) at interface (150), wherein the interface (150) is configured to provide a clock transmission signal for transmission to the one or more sensor units (110) based on the clock signal (CLK), wherein the control unit (160) is configured to provide control information to the clock unit, and the clock unit is configured to modulate the clock signal (CLK) so that it represents the control information. [20] The measuring system (100) according to claim 19, wherein the clock unit is configured to modulate the clock signal (CLK) by varying a number of sigma-delta clock cycles to form a clock signal pulse width that is associated with a binary representation of the control information.

Images