Component and method for manufacturing a component

Abstract

component comprising at least one optoelectronic semiconductor chip (42) with - comprising a connection substrate (4), a mounting surface (4a) and electrical contact structures and - a plurality of structured semiconductor units (2), each comprising a plurality of monolithically connected pixels (21) which are partially interconnected by means of at least one common semiconductor layer and each comprising an active layer which emits light during operation, wherein - the semiconductor units (2) are arranged laterally spaced apart from each other on the mounting surface (4a) and pixels (21) of adjacent semiconductor units (2) are not monolithically connected and are not connected to each other by means of semiconductor material, - the pixels (21) can be controlled separately electrically, - a separation trench (22) with a width (B) of at least 5 µm and at most 25 µm is arranged between the active layers of adjacent pixels (21), and - a distance (d) between adjacent semiconductor units (2) deviates by no more than + / - 10 % from a mean width of the separation trenches (22).

Description

[0001] A component and a method for manufacturing a component are specified.

[0002] For example, document DE 10 2011 102 032 A1 describes a semiconductor module having a plurality of light-emitting areas during operation, or a display with a plurality of such semiconductor modules, as well as a method for manufacturing a semiconductor module or display. Further components, modules, and manufacturing methods are described, for example, in documents DE 10 2011 056 888 A1, WO 2008 / 109 296 A1, and US 2007 / 0019 430 A1.

[0003] One task to be solved is to specify a component with reduced manufacturing costs. Furthermore, a method for manufacturing a component with reduced manufacturing costs should be specified.

[0004] A component is specified. This component is specifically designed for the emission of light. For example, the component could be a light source. In particular, the component could be a headlight, especially an adaptive front-lighting system (AFS).

[0005] According to at least one embodiment of the component, it comprises at least one optoelectronic semiconductor chip, hereinafter also referred to as the "semiconductor chip". The semiconductor chip is specifically designed for the emission of light. For example, the semiconductor chip is a pixelated LED chip. "Pixelated" here and in the following can mean that the LED chip has a plurality of pixels, which are particularly electrically separately controllable.

[0006] According to at least one embodiment, the semiconductor chip has a connection substrate. The connection substrate comprises a mounting surface and electrical contact structures. The electrical contact structures can be provided for electrically contacting the semiconductor chip. For this purpose, the electrical contact structures can comprise or consist of an electrically conductive material, such as a metal.

[0007] The connection substrate has a principal plane of extension in which it extends laterally. Perpendicular to this principal plane, in a vertical direction, the connection substrate has a thickness. The thickness of the connection substrate is small compared to its maximum lateral extension. One principal plane of the connection substrate forms the mounting surface.

[0008] The connection substrate can be designed as a mechanically stabilizing component of the semiconductor chip. "Mechanically stabilizing" here and in the following means that the mechanical handling of the semiconductor chip is improved by the stabilizing part of the housing, allowing, for example, a higher external force to be applied to the semiconductor chip without it being damaged. In particular, the connection substrate can make the semiconductor chip mechanically self-supporting, meaning that the semiconductor chip can be handled during a manufacturing process with tools such as tweezers without the need for an additional supporting element.

[0009] According to at least one embodiment, the semiconductor chip comprises a plurality of structured semiconductor units. Each of the semiconductor units has a plurality of monolithically connected image points, each with an active layer that emits light during operation. The image points can, in particular, be pixels, i.e., separate emission regions of the semiconductor unit. Each image point can have a light-emitting surface facing away from the substrate. It is possible that the light emitted by the active layer is coupled out of the image points through this light-emitting surface.

[0010] "Monolithically connected" can mean, here and in the following, that the pixels are formed from a single, and in particular, a continuous, sequence of semiconductor layers. Specifically, the pixels can be produced from a monolithic sequence of semiconductor layers. For example, it is possible that, for the production of the pixels, the semiconductor layer sequence is first deposited onto a growth substrate, and the pixels are then provided by means of a subsequent, at least partial, singulation of the semiconductor layer sequence.

[0011] For example, the semiconductor layer sequence consists of an n-type semiconductor layer, an active semiconductor layer, and a p-type semiconductor layer. The active layers of the pixels can originate from the active semiconductor layer. Furthermore, each pixel can have a p-type layer and an n-type layer, which originate from the p-type and n-type semiconductor layers, respectively. The phrase "originating from" a semiconductor layer, as used here and in the following, can mean that the layer was created by isolating the semiconductor layer and is part of that semiconductor layer.

[0012] According to at least one embodiment, the pixels are partially interconnected by means of at least one common semiconductor layer, which can be the n-type or the p-type semiconductor layer. In particular, the pixels can be interconnected by several semiconductor layers, for example, the n-type semiconductor layer, the p-type semiconductor layer, and the active layer.

[0013] According to at least one embodiment, the semiconductor units are arranged laterally spaced apart from each other on the mounting surface. In other words, there is a gap between the semiconductor units. According to at least one embodiment, pixels of adjacent semiconductor units are not monolithically connected and are not joined together by means of semiconductor material.

[0014] According to at least one embodiment, the distance between adjacent semiconductor units is at least 5 µm and at most 55 µm, preferably at least 10 µm and at most 20 µm. This distance is, in particular, the smallest distance between the side surfaces of two adjacent semiconductor units in the lateral directions. The side surfaces of the semiconductor units can be external surfaces of the semiconductor units extending along the vertical direction.

[0015] According to at least one embodiment, the pixels can be controlled electrically independently. In particular, it is possible for each pixel to be uniquely assigned at least one electrical contact structure. This makes it possible to selectively switch the emission of individual pixels on or off. Two or more pixels can thus be operated at the same or at different times.

[0016] According to at least one embodiment of the component, it comprises at least one optoelectronic semiconductor chip with a mounting substrate having a mounting surface and electrical contact structures, and a plurality of structured semiconductor units, each comprising a plurality of monolithically connected pixels, each with an active layer that emits light during operation. The semiconductor units of the semiconductor chip are arranged laterally spaced from one another on the mounting surface. The distance between adjacent semiconductor units is at least 5 µm and at most 55 µm. Furthermore, the pixels can be addressed electrically independently.

[0017] According to at least one embodiment of the device, the active layers of the pixels are monolithically connected. For example, the active layers are part of a single active semiconductor layer. Furthermore, the pixels can be electrically controlled separately by means of several laterally spaced semiconductor contacts. The lateral distance between adjacent semiconductor contacts is at least 1 µm and at most 25 µm. For example, each pixel is electrically connected to at least one semiconductor contact. Furthermore, the electrical contact structure associated with a pixel can be electrically connected to the semiconductor contact of the respective pixel. The semiconductor contacts can be formed from or consist of an electrically conductive material, such as a metal. In particular, the device can have several semiconductor contacts, each of which is associated with at least one pixel.For example, the semiconductor contacts are arranged laterally spaced apart from each other on a base surface facing the connection substrate and / or on the light transmission surface of the pixels.

[0018] According to at least one embodiment, a separating trench is arranged between the active layers of adjacent pixels. It is possible that the active layers of the pixels are not interconnected. In particular, each pixel can be uniquely assigned an active layer. The active layers can, for example, be surrounded by the separating trenches in a frame-like manner. "Frame-like" here and in the following means that each pixel and / or each active layer is completely surrounded by separating trenches in lateral directions when viewed from the mounting surface. In this top view, the separating trenches then appear as a grid or mesh, with the pixels enclosed by individual meshes of the grid or mesh. The separating trenches can, for example, be produced by etching.

[0019] According to at least one embodiment, the width of a separating trench is at least 1 µm and at most 25 µm, preferably at least 5 µm and at most 20 µm. The width of a separating trench is, in particular, the smallest extent of the separating trenches in lateral directions. Specifically, the width of a separating trench is the smallest distance between the lateral surfaces of two adjacent pixels. The lateral surfaces of the pixels can be their outer surfaces extending along the vertical direction.

[0020] According to at least one embodiment, the pixels are optically separated from one another. Optical separation of the pixels can be achieved, for example, by means of the separation channels. It is also possible that absorbing and / or reflective material is arranged between adjacent pixels. Hereinafter, a material is considered "absorbing" or "reflective" if it has a transmittance of at most 0.4, preferably at most 0.3, or a reflectance of at least 0.5, preferably at least 0.7, and particularly preferably at least 0.85, for the radiation emitted by the active layers. Due to the optical separation of the pixels in conjunction with the separate electrical controllability, it is possible, for example, to selectively illuminate only individual areas of the component.

[0021] According to at least one embodiment, at least two of the semiconductor units have a different number of pixels. For example, it is possible to assign at least one semiconductor unit to a first group of semiconductor units and at least one further semiconductor unit to a second group of semiconductor units. The semiconductor units of the first group can each have a first number of pixels, and the semiconductor units of the second group can each have a second number of pixels, wherein the first number and the second number differ.

[0022] It is possible for semiconductor units with a different number of pixels to have different sizes. The size of a semiconductor unit and / or pixel, as defined here and subsequently, is its respective lateral dimension. It is possible that the pixels themselves have different sizes. Alternatively, within the limits of manufacturing tolerances, the pixels of different semiconductor units may be the same size.

[0023] Alternatively, it is possible that semiconductor units with a different number of pixels are the same size within the manufacturing tolerances. In this case, the pixels themselves may have different sizes.

[0024] According to at least one embodiment, the connection substrate comprises at least one integrated circuit. For example, the connection substrate has doped regions that enable switching operations. In particular, the integrated circuit can be the electrical contact structures of the connection substrate. For example, the connection substrate comprises transistors, capacitors, resistors, and / or other electronic components as integrated circuits.

[0025] The connection substrate can be made of or consist of silicon. In particular, the connection substrate can be an active-matrix silicon substrate. An active-matrix silicon substrate can contain a matrix of transistors by means of which the individual pixels can be controlled. The transistors can be manufactured, for example, using CMOS or thin-film technology.

[0026] According to at least one embodiment, the connection substrate contains a plurality of current sources. Each of the current sources is uniquely assigned to one of the pixels. Furthermore, each of the current sources is electrically connected to its assigned pixel. In particular, each pixel is electrically connected to a current source. The current source can, for example, be a miniaturized current source.

[0027] According to at least one embodiment, the spacing between adjacent semiconductor units deviates by at most + / - 10% from the mean width of the separating channels. Within the manufacturing tolerances, the spacing between adjacent semiconductor units can correspond to the mean width of the separating channels. In other words, pixels of adjacent semiconductor units can have essentially the same spacing as pixels of the same semiconductor unit. The mean width of the separating channels can, for example, be an arithmetic mean of the respective widths of the separating channels. In particular, it is possible for both the spacing between adjacent semiconductor units and the width of the separating channels to be at least 5 µm and at most 55 µm.

[0028] According to at least one embodiment, the distances between adjacent semiconductor units deviate by at most + / - 10% from a mean distance between adjacent semiconductor units. The mean distance between adjacent semiconductor units can be an arithmetic mean of the respective distances between the semiconductor units. In other words, the semiconductor units are placed at regular intervals on the connection substrate.

[0029] According to at least one embodiment, the luminous area of ​​the component is at least 8 mm². 2 , preferably at least 32 mm 2 The luminous area of ​​the component is, in particular, the sum of all light-emitting surfaces of the pixels of the component.

[0030] According to at least one embodiment, the total number of pixels is at least 128, preferably at least 2048, and / or the luminous flux of the light emitted by the total number of pixels is at least 1600 lumens, preferably at least 6400 lumens. The component can, for example, be a high-resolution light source and / or a light source with high luminance. In particular, manufacturing a single pixelated semiconductor unit with a luminous flux exceeding 6400 lumens would not be economically viable. Dividing the component into individual semiconductor units, each with a large number of pixels, enables the cost-effective and economically viable production of a component with high resolution and / or high luminous flux.

[0031] According to at least one embodiment, the component comprises at least two semiconductor chips. Each of the semiconductor chips can be structured as described above. In particular, each semiconductor chip comprises a plurality of semiconductor units arranged on a connection substrate.

[0032] According to at least one embodiment, the at least two semiconductor chips are arranged on a printed circuit board (PCB). This PCB can be, for example, a metal-core board or a so-called submount. The PCB can be used, in particular, for electrical control and / or cooling of the semiconductor chips arranged on the PCB.

[0033] Furthermore, a method for manufacturing a component is specified. The component is preferably manufacturable using a method described herein. That is to say, all features disclosed for the component are also disclosed for the method and vice versa.

[0034] According to at least one embodiment of the method, the plurality of semiconductor units with the plurality of pixels are provided. Each semiconductor unit is deposited on a growth substrate. The growth substrate can, for example, be a monocrystalline substrate, which may be made of sapphire. It is possible that the pixels of each semiconductor unit originate from a common sequence of semiconductor layers that were epitaxially grown on the growth substrate, with individualization into pixels occurring after epitaxial growth.

[0035] According to at least one embodiment of the method, the connection substrate is provided with the mounting surface and the electrical contact structures. The semiconductor units are applied to the mounting surface of the connection substrate. The semiconductor units are applied such that they are arranged laterally spaced apart from one another on the mounting surface, with the distance between adjacent semiconductor units being at least 5 µm and at most 55 µm, preferably at least 10 µm and at most 20 µm. Furthermore, the pixels can be addressed electrically independently of one another.

[0036] According to at least one embodiment of the method, the growth substrate is at least partially removed. In particular, the growth substrate can be completely removed, for example, by means of an etching process or a laser lift-off process. In this case, only the light-emitting semiconductor layers of the pixels remain on the substrate. Alternatively, the growth substrate can be thinned, for example, by means of an etching process or by physical ablation such as grinding or polishing. In this case, parts of the growth substrate remain attached to the pixels.

[0037] According to at least one embodiment of the method for manufacturing a component, it comprises the following process steps: - Providing a plurality of semiconductor units, each comprising a plurality of monolithically connected or fabricated pixels, which are partially interconnected by means of at least one common semiconductor layer and each have an active layer which emits light during operation, wherein each semiconductor unit is deposited on a separate growth substrate and pixels of adjacent semiconductor units are not monolithically connected and are not interconnected by means of semiconductor material, - Providing a connection substrate with a mounting surface and electrical contact structures, - Applying the semiconductor units to the mounting surface in such a way that the semiconductor units are arranged laterally spaced apart from each other on the mounting surface, wherein - the distance between adjacent semiconductor units is at least 5 µm and in particular at most 55 µm, - a separation trench with a width of at least 5 µm and at most 25 µm is introduced between the active layers of adjacent pixels, and - the distance between adjacent semiconductor units deviates by no more than + / - 10% from the mean width of the separation trenches, - the pixels can be controlled separately electrically, and - at least partial detachment of the growth substrate.

[0038] The procedure steps can be carried out in the specified order.

[0039] According to at least one embodiment of the method, the semiconductor units are provided by singulation from a wafer array containing a multitude of pixels. For example, singulation is carried out by sawing, scribing and breaking, or laser cutting.

[0040] According to at least one embodiment of the method, providing the semiconductor units includes identifying semiconductor units with defective pixels and sorting out these units such that, within the manufacturing tolerances, only semiconductor units with intact pixels are applied to the mounting surface. In other words, the method includes selecting for intact pixels. This ensures that only fully functional semiconductor units are transferred to the substrate.

[0041] A defective pixel is characterized, for example, by having a lower luminance and / or lower luminous flux or a higher voltage drop than intact pixels. For example, a defective pixel emits no light.

[0042] For example, pixels are manufactured in the wafer array, with epitaxial growth followed by a singulation step into semiconductor units. Identifying semiconductor units with defective pixels can be done before or after singulation. For instance, it is possible to identify defective pixels before singulation and remove them from the wafer array during the singulation process. Alternatively, it is possible to first singulate the components into individual semiconductor units and then sort out the units containing defective pixels.

[0043] The method for manufacturing a component described here, as well as the component described here, particularly pursues the idea of ​​combining the monolithic fabrication of pixels with the individual placement of semiconductor units onto a connection substrate.

[0044] This enables the provision of a component with a high number of pixels positioned close together on a connection substrate.

[0045] In contrast to monolithically manufactured high-pixel components, the division into individual semiconductor units allows for the selection of defective semiconductor units. This makes it possible to sort out defective pixels, which, for example, exhibit statistically distributed defects in the semiconductor material or structure, before they are transferred to the substrate. This significantly increases the yield of fully functional components with a correspondingly large luminescent area.

[0046] Furthermore, unlike individual pixel placement, a small distance between pixels is possible. This eliminates the need for additional optics or significantly reduces their number. Moreover, the ability to distribute the total required luminescent area across multiple semiconductor units and / or chips allows for greater design flexibility. The number and / or arrangement of pixels within a semiconductor unit and / or chip can be selected to achieve optimal yield and thus optimal cost, depending on the chosen interconnection process and / or pixel defect rate.

[0047] The following section provides a more detailed explanation of the component and method described here, using exemplary embodiments and the accompanying figures.

[0048] Based on the schematic representations of the Fig. 1A and Fig. Figure 1B is an embodiment of a semiconductor unit of a component described herein, which is explained in more detail.

[0049] Based on the schematic representations of the Fig. 2A, Fig. 2B, Fig. 2C and Fig. Figures 2D are an embodiment of a method for manufacturing a component described here, and an embodiment of a component described here is explained in more detail.

[0050] Based on the schematic representations of the Fig. 3, Fig. 4A and Fig. 4C are exemplary embodiments of a component described here and are based on the Fig. Section 4B explains an example of a component in more detail.

[0051] Identical, similar, or similarly effective elements in the figures are marked with the same reference symbols. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or better understanding.

[0052] Based on the schematic representations of the Fig. 1A and Fig. 1B is an embodiment of a semiconductor unit of a component described herein, which is explained in more detail. The embodiment is described in the Fig. 1B compared to the Fig. 1A shown rotated by 180°.

[0053] A semiconductor unit 2 (shown schematically in the figures) is deposited on a growth substrate 1. The semiconductor unit 2 has a plurality of pixels 21. The pixels 21 are separated from each other by separating grooves 22. The width b of the separating grooves 22 is at least 5 µm and at most 25 µm.

[0054] Each pixel 21 can have an n-type layer, a p-type layer, and an active layer. For example, the n-type layer and the p-type layer are formed from an n-type semiconductor layer and a p-type semiconductor layer, respectively. It is possible that the n-type layer or the p-type layer corresponds to the n-type semiconductor layer or the p-type semiconductor layer. For example, the n-type semiconductor layer and the p-type semiconductor layer are formed with or consist of a (compound) semiconductor material.

[0055] Based on the schematic representations of the Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D is an embodiment of a method for manufacturing a component described here, which is explained in more detail.

[0056] In the Fig. In process step 2A, a semiconductor unit 2 deposited on a growth substrate 1 is provided and equipped with initial solder balls 31, which may be formed with a solder metal. In the step shown in the Fig. In the process step shown in Figure 2B, a connection substrate 4 with a mounting surface 4a is provided. Connection areas 33 are defined on the mounting surface 4a, each equipped with connection pads 32 that can be arranged according to the first solder balls 31. The connection pads 32 can be formed with or made of a metal. A semiconductor unit 2 is applied to each connection area 33 together with the growth substrate 1. Subsequently, the first solder balls 31 and the connection pads 32 can be heated, thereby mechanically and / or electrically connecting the semiconductor units 2, and in particular the pixels 21, to the connection substrate 4. Alternatively or additionally, a mechanical and / or electrical connection of the semiconductor units 2, and in particular the pixels 21, can be achieved by bonding.

[0057] In the Fig. In the process step shown in 2C, a plurality of semiconductor units 2, each provided with a growth substrate 1, are applied to the mounting surface 4a of the connection substrate 4.

[0058] In the Fig. In the 2D process step, the growth substrates 1 are detached from the semiconductor units 2. Alternatively, the growth substrates 1 can only be partially detached or thinned. The multitude of semiconductor units 2, each with a multitude of pixels 21, then forms a semiconductor chip 42 together with the mounting substrate 4. The semiconductor units 2 of the semiconductor chip 42 are arranged laterally spaced from one another on the mounting surface 4a of the mounting substrate 4. The distance d between adjacent semiconductor units 2 is at least 5 µm and at most 55 µm.

[0059] Based on the schematic representation of the Fig. Figure 3 describes an embodiment of a component described herein. The component comprises a plurality of semiconductor chips 42 mounted together on a printed circuit board 51. A conversion element 53 is applied to each semiconductor chip 42 on a surface facing away from the printed circuit board 51. The conversion element 53 can be a ceramic plate or a polymer layer with wavelength-converting particles.

[0060] An electrical interface 52 enables electrical contacting and / or control of the connection substrates 4 of the semiconductor chips 42 and, in particular, the individual pixels 21 of the semiconductor units 2. Specifically, the electrical contacting of the connection substrate 4 can be carried out from the top side facing away from the printed circuit board 51 after the connection substrate 4 has been applied to the printed circuit board 51, for example, by means of bond wires leading to bond pads arranged on the top side. Alternatively, the connection substrate 4 can be provided with vias. In this case, the component can be a surface-mountable device (SMD).

[0061] Based on the schematic representations of the Fig. 4A, Fig. 4B and Fig. 4C are embodiments of a semiconductor chip 42 for a component described here, or an example of a semiconductor chip is explained in more detail.

[0062] The Fig. Figure 4A shows a semiconductor chip 42 with a plurality of semiconductor units 2, each comprising a plurality of pixels 21. The semiconductor units 2 are mounted on a connection substrate 4. As shown in the Fig. As shown in Figure 4A, the semiconductor units 2 can each have the same number of pixels 21. Furthermore, the semiconductor units 2 can be of similar or identical size. A conversion element 53 can be applied to a cover surface of the semiconductor units 2 facing away from the connection substrate 4.

[0063] In the Fig. In the example shown in Figure 4B, the semiconductor chip 42 comprises only a single semiconductor unit 2 with a plurality of pixels 21. The semiconductor unit 2 can optionally have a conversion element 53 on its top surface (in the Fig. 2B not shown).

[0064] In the Fig.In the embodiment shown in Figure 4C, the semiconductor chip 42 comprises a plurality of semiconductor units 2, wherein the semiconductor units 2 have a different number of pixels 21, each with different sizes.

[0065] The invention is not limited to the description provided by means of the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the claims, even if these features or this combination itself is not explicitly stated in the claims or exemplary embodiments. Reference symbol list: 1 Growth substrate 2 semiconductor units 21 pixels 22 Separation trench B Width d distance 31 first solder balls 32 connection surfaces 33 Connection area 4 Connection substrate 4a Mounting surface 42 optoelectronic semiconductor chip 51 circuit board 52 electrical interface 53 Conversion element

Claims

[1] Component comprising at least one optoelectronic semiconductor chip (42) with - comprising a connection substrate (4), a mounting surface (4a) and electrical contact structures and - a plurality of structured semiconductor units (2), each comprising a plurality of monolithically connected pixels (21) which are partially interconnected by means of at least one common semiconductor layer and each comprising an active layer which emits light during operation, wherein - the semiconductor units (2) are arranged laterally spaced apart from each other on the mounting surface (4a) and pixels (21) of adjacent semiconductor units (2) are not monolithically connected and are not connected to each other by means of semiconductor material, - the pixels (21) can be controlled separately electrically, - a separation trench (22) with a width (B) of at least 5 µm and at most 25 µm is arranged between the active layers of adjacent pixels (21), and - a distance (d) between adjacent semiconductor units (2) deviates by no more than + / - 10 % from a mean width of the separation trenches (22). [2] Component according to the previous claim, wherein a distance (d) between adjacent semiconductor units (2) is at least 5 µm. [3] Component according to one of the preceding claims, wherein - the active layers of the pixels (21) are monolithically connected and - the pixels (21) can be electrically controlled separately by means of several laterally spaced semiconductor contacts, wherein - a distance (a) between adjacent semiconductor contacts is at least 1 µm and at most 25 µm. [4] Component according to one of the preceding claims, wherein the pixels (21) are optically separated from each other. [5] Component according to any of the preceding claims, wherein the connection substrate (4) has at least one integrated circuit. [6] Component according to one of the preceding claims, wherein the connection substrate (4) contains a plurality of current sources, each of the current sources being uniquely assigned to one of the pixels (21) and being electrically connected to that pixel (21). [7] Component according to one of the preceding claims, wherein the distances between adjacent semiconductor units (2) deviate by no more than + / - 10 % from a mean distance (a) between adjacent semiconductor units (2). [8] Component according to one of the preceding claims, wherein a luminous surface of the component is at least 8 mm 2 amounts. [9] Component according to one of the preceding claims, wherein a luminous surface of the component is at least 40 mm 2 amounts. [10] Component according to one of the preceding claims, wherein the total number of pixels (21) of the component is at least 2500 and / or the luminous flux of the light emitted by the total number of pixels (21) is at least 1600 lumens. [11] Component according to one of the preceding claims, wherein at least two of the semiconductor units (2) have a different number of pixels (21). [12] Component according to one of the preceding claims, comprising at least two optoelectronic semiconductor chips (42) arranged on a printed circuit board (51). [13] Method for manufacturing a component comprising the following process steps: - Providing a plurality of semiconductor units (2), each comprising a plurality of monolithically manufactured pixels (21) which are partially interconnected by means of at least one common semiconductor layer and each have an active layer which emits light during operation, wherein each semiconductor unit (2) is deposited on a growth substrate (1) and pixels (21) of adjacent semiconductor units (2) are not monolithically connected and are not interconnected by means of semiconductor material; - Providing a connection substrate (4) with a mounting surface (4a) and electrical contact structures, - Applying the semiconductor units (2) to the mounting surface (4a) such that the semiconductor units (2) are arranged laterally spaced apart from each other on the mounting surface (4a), wherein - a distance (d) between adjacent semiconductor units (2) is at least 5 µm, - a separation trench (22) with a width (B) of at least 5 µm and at most 25 µm is introduced between the active layers of adjacent pixels (21), and - the distance (d) of adjacent semiconductor units (2) deviates by no more than + / - 10 % from a mean width of the separation trenches (22), - the pixels (21) can be controlled separately; and - at least partial detachment of the growth substrate (1). [14] Method according to the previous claim, wherein the semiconductor units (2) are provided by singulation from a wafer composite with a plurality of pixels (21). [15] Method according to the preceding claim, wherein the provision of the semiconductor units (2) further comprises the following process steps: - Detecting semiconductor units with defective pixels (21), - Sorting out the semiconductor units (2) with defective pixels (21) such that, within the manufacturing tolerances, only semiconductor units with intact pixels (21) are applied to the mounting surface (4a).

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