Semiconductor chip package including sidewall marking

Abstract

The semiconductor chip package comprises a semiconductor chip and an encapsulation body which encapsulates the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body which encapsulates the semiconductor chip, wherein the encapsulation body comprises two opposing main surfaces and side surfaces which connect the two main surfaces, wherein the side surfaces each have a smaller surface area than the main surfaces and wherein a marking is provided on at least one of the side surfaces.

Description

AREA OF TECHNOLOGY

[0001] The present disclosure relates to the field of semiconductor chip packages. BACKGROUND

[0002] A semiconductor chip package can comprise a semiconductor chip, an encapsulation body that encapsulates the semiconductor chip, and electrical contact elements that are connected to the semiconductor chip and extend through the encapsulation body to form external contact elements. The external contact elements can be configured in various ways to meet different customer requirements. In one configuration, the semiconductor chip package is configured as a through-hole device in which the external contact elements are configured as contact pins for insertion into through-hole sockets on the customer's side. In another configuration, the semiconductor chip package is configured as a surface-mount device in which the external contact elements have flat, coplanar bottom surfaces for mounting on a suitable contact surface on the customer's side.

[0003] Other aspects must also be considered in the manufacture of semiconductor chip packages and their electrical contact elements. One aspect is that the semiconductor chip can generate heat during operation, and the overall design of the semiconductor chip package may need to be optimized to allow for the most efficient heat dissipation. Another aspect concerns the marking of the semiconductor chip package, specifically the question of how and where markings are provided to enable the customer or other individuals to identify the type or nature of the semiconductor chip package or the semiconductor chip itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings are included to provide a deeper understanding of the examples and are incorporated into, and form part of, this description. The drawings illustrate examples and, together with the description, serve to explain the principles underlying them. Further examples and many of the intended benefits of the examples will be readily apparent as they are better understood with reference to the detailed description that follows.

[0005] The elements in the drawings are not necessarily to scale with respect to each other. Identical reference symbols denote corresponding similar parts.

[0006] Fig. 1 includes Fig. 1A– Fig. Figure 1C shows a schematic perspective top view (A), a schematic side view (B) and a schematic cross-sectional side view (C) of a semiconductor chip package designed for surface mount technology according to an example.

[0007] Fig. Figure 2 shows a schematic perspective bottom view of an exemplary arrangement, which is to be encapsulated to house a semiconductor chip package, such as the one from Fig. 1. To train.

[0008] Fig. 3 includes Fig. 3A– Fig. Figure 3C shows a schematic side view (A), a schematic cross-sectional side view (B) and a top view (C) of a semiconductor chip package designed for through-hole mounting technology according to an example. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form part of this document and illustrate specific examples in which the disclosure can be put into practice. In this context, directional terminology such as "above," "below," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the described figure(s). Since components of the examples can be arranged in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other examples may be used and structural or logical modifications may be made without infringing upon the scope of protection of this disclosure.The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present disclosure is defined by the attached claims.

[0010] It is understood that the characteristics of the various examples described herein can be combined with one another, unless expressly stated otherwise.

[0011] As used in this description, the terms “bonded”, “connected”, “linked”, “coupled”, and / or “electrically connected / coupled” do not necessarily mean that the elements or layers must be in direct contact with each other; intermediate elements or layers may be provided between the respective “bonded”, “connected”, “linked”, “coupled”, and / or “electrically connected / coupled” elements. However, according to the disclosure, the aforementioned terms may also have the specific meaning that the elements or layers are brought into direct contact with each other, that is, that no intermediate elements or layers are provided between the respective “bonded”, “connected”, “linked”, “coupled”, and / or “electrically connected / coupled” elements.

[0012] Furthermore, the word "over," used herein in reference to a part, element, or layer of material formed or arranged "over" a surface, can mean that the part, element, or layer of material is arranged (e.g., positioned, formed, deposited, etc.) "indirectly on" the implied surface, with one or more additional parts, elements, or layers arranged between the implied surface and the part, element, or layer of material. However, the word "over," used in reference to a part, element, or layer of material formed or arranged "over" a surface, can optionally also have the specific meaning that the part, element, or layer of material is arranged (e.g., positioned, formed, deposited, etc.) "directly on" the implied surface, e.g., in direct contact with it.

[0013] Furthermore, although a particular feature or aspect of an embodiment may be disclosed with respect to only one of several implementations, such a feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desirable or advantageous for any given or particular application. Moreover, insofar as the terms “include,” “have,” “with,” or other variants thereof are used either in the detailed description or in the claims, it is intended that these terms be inclusive, in a similar manner to the term “comprise.” The terms “coupled” and “connected” may be used together with derivatives.It should be understood that these terms can be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact or not. Furthermore, the term "exemplary" is meant merely as an example, rather than as the best or optimal solution. The following detailed description is therefore not to be interpreted in a limiting sense, and the scope of protection of the present invention is defined by the attached claims.

[0014] Devices or semiconductor chip packages containing semiconductor chips are described below. The semiconductor chips can be of various types, manufactured using different technologies, and may include, for example, integrated electrical, electro-optical, or electromechanical circuits and / or passive elements. The semiconductor chips may be designed, for example, as logic integrated circuits, analog integrated circuits, integrated mixed-signal circuits, integrated power circuits, memory circuits, or integrated passive elements. They may include control circuits, microprocessors, or microelectromechanical components.Furthermore, they can be designed as power semiconductor chips, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), bipolar power transistors, or power diodes. In particular, semiconductor chips with a vertical structure can be involved, meaning that the semiconductor chips can be manufactured in such a way that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip with a vertical structure can have contact elements, in particular, on its two main surfaces, i.e., on its top and bottom surfaces. Specifically, power semiconductor chips can have a vertical structure.For example, the source electrode and the gate electrode of a power MOSFET can be arranged on one main surface, while the drain electrode of the power MOSFET is arranged on the other main surface. Furthermore, the electronic devices described below can include integrated circuits to control the integrated circuits of other semiconductor chips, such as the integrated circuits of power semiconductor chips. The semiconductor chips can be made from a specific semiconductor material, such as Si, SiC, SiGe, GaAs, GaN, or AlGaAs, or they can be made from a different semiconductor material and can also contain inorganic and / or organic materials that are not semiconductors, such as insulators, plastics, or metals.

[0015] Examples of semiconductor chip packages can include an encapsulating material for embedding the semiconductor chip, or other insulating or dielectric materials. These encapsulating, insulating, or dielectric materials can be any electrically insulating material, such as any type of molding material, resin, or epoxy. The materials can also include one or more polymers, polyimides, thermoplastics, silicones, ceramics, or glass. Furthermore, the materials can include any of the above-mentioned materials and embedded filler materials, such as thermally conductive increments. These filler increments can be made of materials such as AlO or Al₂O₃, AlN, BN, or SiN.Furthermore, the filler increments can be in the form of fibers and, for example, made of carbon fibers or nanotubes. After deposition, the encapsulating material can be partially cured or fully cured after the application of energy (e.g., heat, UV light, etc.) to form a complete encapsulating layer. Various techniques can be used to coat the semiconductor chips with the encapsulating material, such as one or more compression molds, transfer molds, injection molding, powder molding, liquid molding, dispensing, or lamination.

[0016] Fig. 1 includes Fig. 1A– Fig. 1C and shows an example of a semiconductor chip package according to an example in a schematic perspective top view (A), a schematic side view (B) and a schematic cross-sectional side view (C), the latter being in a plane as defined by line CC in Fig. 1A is displayed. The semiconductor chip package 10 includes a semiconductor chip 11 and an encapsulation body 12 , which is the semiconductor chip 11 encapsulated. The encapsulation body 12 comprises two opposing main areas 12A and 12B and side surfaces 12C , which are the two main areas 12A and 12B connect the side surfaces 12C have a smaller surface area than the main surfaces. 12A or 12B on, and a label 14 is on at least one of the side surfaces 12Cprovided.

[0017] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the marking 14 information about the semiconductor chip 11 According to another example, the information about the semiconductor chip includes 11 a label or code, wherein the label or code indicates the type or nature of the semiconductor chip 11 characterized.

[0018] According to an example of the semiconductor chip package 10 out of Fig. 1 contains the information about the semiconductor chip 11 one or more of the following information elements: type or species of semiconductor chip, current class, voltage class, power class, polarity, blocking capability, date of manufacture (date code).

[0019] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the marking 14Information about the semiconductor chip package 10 or the encapsulation body 12 According to another example, the information includes a label or code, where the label or code specifies the type or nature of the semiconductor chip package. 10 or the encapsulation body 12 characterized.

[0020] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the marking 14 at least one alphanumeric character or a combination of alphanumeric characters, such as the identifier “L5719H”, as in Fig. 1 shown. The designation “L5719H” is merely symbolic here and has no technical meaning.

[0021] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the marking 14a part comprising the company logo or trademark of the semiconductor chip package manufacturer 10 .

[0022] According to an example of the semiconductor chip package 10 out of Fig. 1 will be the marking 14 produced by one or more of the following: printing, laser engraving, burning in, and applying a liquid, especially printing ink, to the side surface 12C .

[0023] According to an example of the semiconductor chip package 10 out of Fig. 1 will be the marking 14 on two opposite side surfaces 12C provided.

[0024] According to an example of the semiconductor chip package 1 out of Fig. 1 includes the semiconductor chip package 10 the shape of a cuboid. According to another example, the semiconductor chip package comprises 10 four side surfaces 12C , 12D, where the four face surfaces form a first pair of first opposite face surfaces 12C a first surface area and a second pair of second opposite side surfaces 12D a second surface area, wherein the first surface area is larger than the second surface area. According to another example, the marking 14 on one or both of the first opposite side faces 12C provided.

[0025] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the semiconductor chip package 10 furthermore electrical contact elements 13.1 , which is connected to the semiconductor chip 11 are connected and extend outwards, with the electrical contact elements 13.1 through two opposite side surfaces 12Dextend and the marking on one of the other two opposite side surfaces 12C is provided. According to another example, the electrical contact elements extend 13.1 exclusively through two opposite side surfaces 12D , which have smaller surface areas than the other two opposite side faces 12C exhibit.

[0026] According to an example of the semiconductor chip package from Fig. 1 includes the semiconductor chip package 10 also a chip pad 13.2 , where the semiconductor chip 11 on the chip pad 13.2 is arranged and a first from the semiconductor chip 11 main surface of the chip pad facing away from the side 13.2 is at least partially exposed to the outside. According to another example, the first main surface of the chip pad is... 13.2 to the outside on one of the two opposite main surfaces 12Aand 12B of the encapsulation body 12 exposed. In the example, as in Fig. Figure 10 shows the first main area of ​​the chip pad. 13.2 on the main area 12A of the encapsulation body 12 Exposed. The exposed first main surface of the chip pad. 13.2 It is intended to allow a substrate or carrier of a heat sink to be applied to it, particularly on the customer's side.

[0027] According to an example of the semiconductor chip package 10 out of Fig. 1 includes the semiconductor chip package 10 furthermore, a lead frame or ladder frame 13 including the electrical contact elements 13.1 and the chip pad 13.2 According to another example, the electrical contact elements include 13.1 first electrical contact elements, which are located on one side of the two opposite side surfaces 12D are arranged and with the chip pad13.2 are electrically connected, and second electrical contact elements which are located on a second side of the two opposite side surfaces 12D are arranged and from the chip pad 13.2 are electrically insulated.

[0028] According to an example of the semiconductor chip package 10 out of Fig. 1 will be the marking 14 also (or exclusively) on one or both of the opposite main surfaces 12A and 12B of the encapsulation body 12 provided.

[0029] According to an example of the semiconductor chip package 10 out of Fig. 1 comprises the semiconductor chip 11one or more transistors, metal-oxide-semiconductor transistors, vertical transistors, insulated-gate bipolar transistors (IGBTs), and power transistors. According to another example, the semiconductor chip comprises 11 a first main surface, a second main surface opposite the first main surface, a first contact pad arranged on the first main surface, and a second contact pad arranged on the second main surface, wherein the semiconductor chip 11 with the second main surface on a chip pad 13.2 is arranged. According to another example, the first contact pad is connected to at least one of the electrical contact elements by a wire bond. 13.1 tied together.

[0030] According to an example of the semiconductor chip package 10 out of Fig. 1 include one or both of the semiconductor chip package10 and the encapsulation body 12 A cuboid shape. According to another example, the ratio between the length of a long side of the cuboid and the length of a short side of the cuboid is between 2 and 3, or greater than 3. In another example, the length of the long side of the cuboid is in the range of 10 mm–25 mm, and the length of the short side of the cuboid is in the range of 4 mm–10 mm.

[0031] According to an example of the semiconductor chip package 10 out of Fig. 1. The electrical contact elements extend 13.1 outwards in a lateral or horizontal direction and are then bent in such a way that their lower surfaces are coplanar with each other and, in particular, also coplanar with a lower main surface 12B of the encapsulation body 12 are. One such example is in Fig. 1 shown.

[0032] According to an example of the semiconductor chip package 10 out of Fig. 1 is the semiconductor chip package 10 designed as a surface-mounted device, as in Fig. One example is shown. According to another example, the semiconductor chip package 10 one of type TO 252 or TO 263.

[0033] According to another example of a semiconductor chip package, the semiconductor chip package is designed as a through-hole device, as shown in another example below. According to one such example, the semiconductor chip package is of type TO 220 or TO 247.

[0034] According to an example of the semiconductor chip package 10 out of Fig. 1 comprises a main area 12A of the semiconductor chip package 10 a central part, which is located on the exposed main surface of a chip pad 13.2is formed, and an edge part which is formed by a part of the encapsulation body 12 is formed. According to another example, the central part can have a rectangular shape. According to another example, the central part can comprise more than 50%, in particular more than 60%, in particular more than 70%, in particular more than 80%, in particular more than 90%, of the total surface area of ​​the main surface. 12A of the encapsulation body 12 cover. According to an example, the edge part is designed to surround the central part and is further designed such that opposite parts of the edge part have the same widths.

[0035] On the customer's side, a semiconductor chip package can be used. 10 , such as the one in Fig. 1 shown, by attaching a heat sink to the main surface 12A of the encapsulation body 12can be used, allowing the heatsink to be placed directly on the exposed main surface of the chip pad. 13.2 is attached. In this way, a very efficient heat dissipation path can be created from the semiconductor chip. 11 to the outside, which is particularly useful in the case of power devices such as power transistors, especially IGBTs (Insulated Gate Bipolar Transistors).

[0036] In the event that a heat sink is attached to the main surface 12A of the encapsulation body 12 If attached, each one would be placed on the edge part of the main surface. 12A The provided marking will likely not be visible to the customer, as it would be covered by the heat sink. In this case, however, the customer can... 14 on the side surface 12C still recognizes and can therefore recognize either one or both of the semiconductor chip package 10or the semiconductor chip 11 recognize and identify.

[0037] Fig. Figure 2 shows an arrangement comprising a lead frame 23 and a semiconductor chip 21 , which is connected to the lead frame 23 is connected. The way in Fig. The arrangement shown in Figure 2 illustrates how the semiconductor chip package 10 out of Fig. 1 in a perspective bottom view before the application of the encapsulation body 12 what it might have looked like. The lead frame 23 includes electrical contact elements 23.1 and a chip pad 23.2 The semiconductor chip 21 can have a bipolar transistor with an insulated gate electrode (IGBT, Insulated Gate Bipolar Transistor), which has its drain pad surface on the chip pad 23.2 is attached. The electrical contact elements 23.1 include upper right electrical contact elements 23.1and lower left electrical contact elements 23.1 The upper right electrical contact elements 23.1 can be connected or integrated with the chip pad 23.2 be and can therefore be at the same electrical potential as the drain contact of the semiconductor chip. 21 are located. The upper surface of the semiconductor chip 21 It comprises a large source pad area and smaller gate pad and source sense pad areas. The large source pad area is connected to three of the lower left electrical contact elements. 23.1 by means of two wire bonds 24 connected, both of which are connected to two different contact areas of the large source contact pad. The other two lower left electrical contact elements 23.1 are secured by wire bonds 25 connected to the Gate and Source sense pads.

[0038] Fig. 3 includes Fig. 3A to Fig. 3C and shows an example of a semiconductor chip package according to an example in a schematic side view (A), a schematic cross-sectional side view (B) and a top view (C), wherein the cross-sectional side view is made up of Fig. 3B is along a plane which is defined by line AA in Fig. 3C is indicated. The semiconductor chip package 30 out of Fig. 3 includes a semiconductor chip 31 and an encapsulation body 32 , which is the semiconductor chip 31 encapsulated. The encapsulation body 32 comprises two opposing main areas 32A and 32B and side surfaces 320 , which are the two main areas 32A and 32B connect the side surfaces 32C Each have a smaller surface area than the main surfaces 32A and 32B on. A label 34is on at least one of the side surfaces 32C Provided. The designation “34B6221” is purely symbolic and has no technical meaning.

[0039] The semiconductor chip package 30 out of Fig. 3 can be a chip pad 33.2 with the semiconductor chip mounted on it 31 and electrical contact elements 33.1 , which is connected to the semiconductor chip 31 are connected and are connected by the encapsulation body 32 extend outwards in one direction, encompassing the electrical contact elements. 33.1 can be designed as contact pins, as in Fig. 3A and Fig. 3B shown, so that the semiconductor chip package 30 is designed as a through-hole device.

[0040] In addition to the differently designed electrical contact elements 33.1 , compared to the semiconductor chip package 10 out of Fig. 1. All features associated with the semiconductor chip package can be used. 10 as described, also on the semiconductor chip package 30 out of Fig. 3. They must be applied so that they are not repeated.

[0041] In particular, the electrical contact elements can 33.1 The first electrical contact elements are located on the side surface. 32D are arranged and connected or integral with the chip pad 33.2 can be, and second electrical contact elements 33.1 can be found on the side surface 12C be arranged in a manner that is not contiguous or integral with the chip pad 33.2 are. More precisely, it could be that the semiconductor chip 31It consists of an insulated-gate bipolar transistor (IGBT) with a drain contact pad on its upper surface, a gate contact pad on its lower surface, a source contact pad on its lower surface, and a source sensing contact pad on its lower surface. In this case, the first electrical contact elements are 33.1 , which are located on the side surface 32D are arranged, all electrically connected to the chip pad 33.2 and thus connected to the drain contact element and are therefore labelled with “D” in Fig. Designated 3C. The second electrical contact elements 33.1 are spelled with "S" and "G" in Fig. 3C designation means that they are made using wire bonds 34 with one of the gate, source, or source-sense contact pads on the lower surface of the semiconductor chip 31are connected.

[0042] The present disclosure also relates to a method for manufacturing a semiconductor chip package, the method comprising: Providing a semiconductor chip, Manufacturing an encapsulation body by encapsulating the semiconductor chip such that the encapsulation body comprises two opposing main surfaces and side surfaces connecting the two main surfaces, wherein the side surfaces each have a smaller surface area than the main surfaces, and Providing a marking on at least one of the side surfaces.

[0043] According to one example of the process, the marking is produced by one or more of the following: printing, laser engraving, burning, and applying a liquid, in particular printing ink, to the side surface. In the case of laser engraving or burning, the mechanism can be such that an upper layer of the encapsulation body is ablated or altered, both in such a way as to create a contrast by which the marking becomes recognizable and visible.

[0044] According to further examples of the procedure, the examples described above with reference to the semiconductor chip packages are transformed into examples of the procedure, which means that suitable procedure steps are carried out to produce a semiconductor chip package according to one or more of the semiconductor chip package examples described above.

[0045] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that a multitude of alternative and / or equivalent implementations can be substituted for the specific embodiments shown and described without departing from the scope of protection of the present disclosure. This application is intended to cover all adaptations or variations of the specific embodiments discussed herein. Therefore, the present invention is to be limited only by the claims and their equivalents.

Claims

[1] Semiconductor chip package, comprising: a semiconductor chip; an encapsulation body that encapsulates the semiconductor chip; wherein the encapsulation body comprises two opposing main surfaces and side surfaces which connect the two main surfaces, the side surfaces each having a smaller surface area than the main surfaces; and wherein a marking is provided on at least one of the side surfaces. [2] Semiconductor chip package according to claim 1, wherein the characterization includes information about the semiconductor chip. [3] Semiconductor chip package according to claim 2, wherein the information about the semiconductor chip comprises a label or a code, wherein the label or code characterizes the type or kind of semiconductor chip. [4] Semiconductor chip package according to claim 2 or 3, wherein the information comprises one or more of the following group of information elements: Type or species of semiconductor chip, current class, voltage class, power class, polarity, blocking capability, date of manufacture. [5] Semiconductor chip package according to one of the preceding claims, wherein the characterization includes information about the semiconductor chip package or the encapsulation body. [6] Semiconductor chip package according to claim 5, wherein the information comprises a label or a code, wherein the label or code characterizes the type or nature of the semiconductor chip package or encapsulation body. [7] Semiconductor chip package according to one of the preceding claims, wherein the characterization comprises at least one alphanumeric character or a combination of alphanumeric characters. [8] Semiconductor chip package according to one of the preceding claims, wherein the marking includes a part comprising the company logo or trademark of the manufacturer of the semiconductor chip package. [9] Semiconductor chip package according to any of the preceding claims, further comprising: a first pair of first opposite side faces of a first surface region; and a second pair of second opposite side faces of a second surface area, wherein the first surface area is larger than the second surface area and the marking is provided on one of the first opposite side surfaces. [10] Semiconductor chip package according to any of the preceding claims, further comprising: four side faces; and electrical contact elements which are connected to the semiconductor chip and extend outwards, wherein The electrical contact elements extend through two opposite side surfaces and the marking is provided on one of the other two opposite side surfaces. [11] Semiconductor chip package according to claim 10, wherein the electrical contact elements extend exclusively through two opposing side surfaces which have the smallest surface areas of all side surfaces. [12] Semiconductor chip package according to any of the preceding claims, further comprising: a chip pad, wherein the semiconductor chip is arranged on the chip pad and a first main surface of the chip pad is at least partially exposed to the outside away from the semiconductor chip. [13] Semiconductor chip package according to claim 12, wherein the first main surface of the chip pad is exposed to the outside on one of the two opposite main surfaces of the encapsulation body. [14] Semiconductor chip package according to one of the preceding claims, wherein the semiconductor chip package is designed as a through-hole device. [15] Semiconductor chip package according to claim 14, wherein the semiconductor chip package is of type TO220 or TO247. [16] Semiconductor chip package according to any one of claims 1 to 13, wherein the semiconductor chip package is designed as a surface mounting device. [17] Semiconductor chip package according to claim 16, wherein the semiconductor chip package is of type TO252 or TO263. [18] Electronic component package comprising: an electronic device; an encapsulation body which encapsulates the electronic device; wherein the encapsulation body comprises two opposing main surfaces and side surfaces which connect the two main surfaces, the side surfaces each having a smaller surface area than the main surfaces; and wherein a marking is provided on at least one of the side surfaces. [19] Electronic component package according to claim 18, wherein the electronic device comprises a semiconductor chip, the semiconductor chip comprising one or more of a transistor, a metal oxide semiconductor transistor, a vertical transistor, a bipolar transistor with an insulated gate electrode and a power transistor. [20] Electronic component package according to claim 18 or 19, further comprising: a lead frame comprising electrical contact elements and a chip pad, wherein an electronic component is arranged on the chip pad.