Integrated circuit for operation on a bus and method for operating the integrated circuit

Abstract

Integrated circuit with at least one transmit (Tx_ASIC) and at least one receive (Rx_ASIC) interface and at least one address (ADDR; ADDR0, ADDR1), - with a memory or memory area (I, II) that has a number of memory sections (BA1, BA2) into which activation information can be written, - where the number of memory sections (BA1, BA2) is equal to the number of activatable integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') that can be operated on a common bus and encoded by the at least one address pin (ADDR; ADDR0, ADDR1), - with a control unit configured to compare the address encoded by the at least one address port (ADDR; ADDR0, ADDR1) with an address received at the receive port (Rx_ASIC) and, in case of a match, to write a defined bit pattern into the memory section (BA1, BA2) assigned to the address and, in case of a mismatch, to suppress a non-acknowledgment signal (NACK) at the transmit port (Tx_ASIC), wherein the integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') is configured to be activated by the defined bit pattern in the memory section (BA1, BA2) corresponding to the address defined at the at least one address port (ADDR; ADDR0, ADDR1) for communication with a microprocessor (µC) connected to the at least one transmit port (Tx_ASIC) and at least one receive port (Rx_ASIC) via the common bus.

Description

[0001] A high-speed serial link (HSSL), as described in DE 10 2013 004 542 A1, makes it possible to connect a microcontroller and a counterpart, such as another microcontroller or a less powerful component like an ASIC (applicant specific integrated circuit), with few lines and still achieve a high data rate.

[0002] This interface is designed as a bidirectional point-to-point connection, allowing both participants to send messages at any time. Each message is acknowledged with either an acknowledge signal or a not-acknowledge signal. It can be sent on various prioritizable logical channels. Longer messages are split into multiple message packets. This makes it possible to interrupt longer, lower-priority messages and embed higher-priority messages. The logical channels also allow the acknowledgment and not-acknowledge signals to be associated with a message. The protocol allows for the transmission of an address, enabling the sender to write directly to the receiver's memory areas. The electrical protocol also allows the outputs of an individual bus participant to be switched to high impedance.

[0003] Due to the limited point-to-point connection, only one counterpart – typically a custom integrated circuit (ASIC) in engine control units – can communicate with the microcontroller. This is not always practical; for system partitioning purposes, it would be advantageous to be able to operate multiple ASICs on this interface. The difficulty here, however, lies in the fact that the microcontrollers are already available and the interface specification cannot be changed.

[0004] DE 198 25 292 A1 discloses a method for controlling a parallel port so that multiple devices can be connected to it. In this method, the connection between a computer and the peripheral devices is controlled by suitable access codes assigned to the peripheral devices. In addition, a disconnect code is defined that applies to all peripheral devices. When the disconnect code is sent, all peripheral devices are disconnected from the computer.

[0005] US 6 438 624 B1 discloses a method for configuring a data communication system by changing a default communication address of a logical component to a first assigned address and automatically connecting the logical component to a communication bus in response to the address change.

[0006] DE 195 22 335 A1 discloses a method and a device for setting the input / output base addresses of system elements in jumper-free configuration.

[0007] US 2003 / 0093607A1 discloses an LPC input / output bridge device and a method for a portable computer with a variety of legacy ports and a docking port.

[0008] US 5,953,509 A discloses a telephone media processing server that includes a clock pulse control circuit for controlling clock pulses to a plurality of digital processors under the control of a main processor. Other signals, such as a frame clock for generating frame pulses, address and data lines, are distributed by means of single wires connected to output pins of a control processor.

[0009] The object of the invention is therefore to provide an integrated circuit (ASIC) and a method by which it is possible to operate several counterparts with a microcontroller with such a high-speed interface on a bus.

[0010] The problem is solved by an integrated component according to claim 1 and a method according to claim 3. Advantageous further developments are described in the dependent claims.

[0011] Accordingly, the integrated circuit comprises at least one transmit and at least one receive terminal, as well as at least one address terminal, and includes a memory or memory area with a number of memory sections into which activation information can be written. The number of memory sections is equal to the number of activatable integrated circuits that can be operated on a common bus and encoded by the at least one address terminal. The integrated circuit also includes a control unit configured to compare the address encoded by the at least one address terminal with an address received at the receive terminal. In the case of a match, the control unit writes a defined bit pattern to the memory section associated with the address. In the case of a mismatch, the control unit suppresses a non-acknowledgment signal at the transmit terminal.The integrated circuit is configured to be activated for communication with a microprocessor connected via the common bus to at least one transmit and at least one receive terminal by the defined bit pattern in the memory section corresponding to the address defined at the at least one address terminal.

[0012] In the inventive method for activating an integrated circuit from a group of at least two integrated circuits connected to a master unit via a bus for communication with the master unit, wherein the bus comprises at least one transmit line leading from the master unit to the integrated circuits and one receive line leading from the integrated circuits to the master unit, and the integrated circuits are configured according to claim 1, the following steps are performed: the master unit sends a signal to the integrated circuits connected to the bus, which contains a command to write a defined bit pattern into the memory section that corresponds to the address encoded at the at least one address pin of the integrated circuit selected for communication. In each integrated circuit, the transmitted memory section address is compared with the address encoded at at least one address pin, and the defined bit pattern is only written to the corresponding memory section and an acknowledgment signal is sent to the master unit if a match is found. If a mismatch is detected, no non-acknowledge signal is sent from the affected integrated circuits connected to the bus to the master unit, and no further response to signals from the master unit occurs until a new command to write to one of the memory sections is received.

[0013] The logic of the integrated circuits to be connected to the bus is implemented in such a way that the microcontroller always sees a specification-compliant point-to-point connection. Nevertheless, the microcontroller is able to communicate with all integrated circuits connected to the bus by activating only the intended communication circuit for communication by passing a "token"—namely, the defined bit pattern—into the appropriate memory section. Since the serial high-speed interface is fixed in existing microcontrollers and cannot be changed, the other bus participants, namely the integrated circuits (ASICs), are designed according to the invention in such a way that their logic enables bus operation of this serial high-speed interface.

[0014] The electrical specifications and protocols of the high-speed serial interfaces implemented in commercially available microcontrollers prohibit the simultaneous transmission of data by multiple bus participants. In the system described here, the microcontroller acts as the arbitration master for the individual integrated circuits. It grants or revokes transmission permission by assigning transmission authorization—the so-called token—to each bus participant or integrated circuit (ASIC). An integrated circuit according to claim 1 is used for this purpose. The integrated circuit with the token activates its transmit outputs and receive inputs. In all other integrated circuits, the transmit outputs are high-impedance, and while the receive inputs receive every message, this does not result in any response. In principle, any number of bus participants can be connected.

[0015] To select an integrated circuit, each integrated circuit has a special memory section—the so-called token memory section—for activating / deactivating the integrated circuit. In this memory section, the microcontroller stores the token in the form of a defined bit pattern, which can also consist of just one bit. It is also possible to store additional communication-specific parameters in the token memory section. The integrated circuit with the token is active, and all other integrated circuits are passive.

[0016] The base address of the token memory section is determined by address pins on the integrated circuit. After a reset, the integrated circuit reads this bit combination, determined by the voltages at the address pins, and thus sets its base address. The microcontroller knows the base addresses of all integrated circuits.

[0017] Normally, an integrated circuit would respond to a write attempt to a non-existent address with a non-acknowledgment signal, thus disrupting the token allocation of such a system.

[0018] Therefore, all integrated circuits are aware of every possible token memory section because a memory or memory area within the integrated circuit has an assigned memory section for every possible bit combination at the address terminals. If a write operation is performed to the token memory section corresponding to the base address defined by the bit combination at the address terminals, the integrated circuit responds with an acknowledgment signal. If a write operation is performed to a different token memory section, the integrated circuit does not respond. This behavior allows a token to be allocated to an integrated circuit—if no other integrated circuit already possesses the token—without other integrated circuits interfering with this allocation by sending non-acknowledgment signals.

[0019] In this way, the microcontroller can allocate the token by simple write accesses to the memory section assigned to the base address of an integrated circuit.

[0020] In a further development of the invention, before another of the integrated circuits connected to the common bus is activated, the previously activated integrated circuit is first deactivated by a signal sent from the master unit to the activated integrated circuit, which causes a change in the content of the memory section described with the defined bit pattern. In this way, the token is removed from the integrated circuit. This can be done, for example, by inverting the contents of the memory section or deleting them.

[0021] The invention will be described in more detail below using exemplary embodiments and the accompanying figures. These figures show... Fig. 1 a point-to-point connection of a microcontroller with a state-of-the-art integrated circuit, Fig. 2 an arrangement with three integrated circuits according to the invention on a bus connected to a microcontroller, Fig. 3 an arrangement with two integrated circuits according to the invention on a bus connected to a microcontroller, Fig. 4. A schematic representation of a memory area with memory sections, Fig. 5 a memory section with and without tokens, Fig. 6 a flowchart of a method according to the invention for token allocation and Fig. 7 a flowchart of a method according to the invention for token withdrawal and token reissuance.

[0022] Fig. Figure 1 shows a point-to-point connection between a microcontroller (µC) and an integrated circuit (ASIC) using only three wires. A transmit terminal Tx_µC is connected to a receive terminal Rx_ASIC, a receive terminal Rx_µC is connected to a transmit terminal Tx_ASIC, and the respective clock signal terminals CLK of the microcontroller (µC) and the integrated circuit ASIC are connected. The connection shown is intended to be implemented as a high-speed serial interface, for example, according to DE 10 2013 004 542 A1 – as described above – meaning that the integrated circuit ASIC acknowledges each signal received by the microcontroller (µC) by confirming a correct reception (ACK) or by sending a non-acknowledgment signal (NACK) if the transmission was faulty or if the microcontroller (µC) addressed an address that does not exist in the integrated circuit ASIC.

[0023] For this reason, it is not possible to connect further integrated circuits to this known interface, because when an integrated circuit is addressed by the microcontroller µC, all other integrated circuits connected to the interface, which necessarily cannot have this address, would acknowledge with a non-acknowledgment signal NACK and thus disrupt the signal transmission.

[0024] An arrangement according to Fig. 2. In this configuration, several integrated circuits (ASIC1, ASIC2, ASIC3) can be connected to a microcontroller (µC) via a high-speed serial interface as described above, without interfering with communication between the microcontroller and any of the integrated circuits (ASIC1-ASIC3), even though the standard protocol is used and the interface in the microcontroller (µC) is also implemented according to the standard. This is desirable because, for example, in applications within a motor vehicle's control unit, different loads such as a solenoid injector (INJ), a light (LEU), or a motor (MOT) should be controllable via the outputs of the integrated circuits in ASIC1-ASIC3, while the integrated circuits themselves should be operated by the microcontroller (µC) on only one bus.

[0025] In accordance with the invention, the integrated circuits ASIC1 - ASIC3 are first equipped with address pins ADDR0, ADDR1, which can be set to specific potentials in order to address the integrated circuits ASIC1 - ASIC3 by means of a different bit combination. In the illustrated example of the Fig. In this case, only two address pins, ADDR0 and ADDR1, are available, allowing for a total of four possible bit combinations. Therefore, a maximum of four integrated circuits can be connected to the interface shown. Depending on how many integrated circuits are to be operated on such an interface, a corresponding number of address pins must be provided.

[0026] The further internal structure of the integrated circuits and the procedure for activating a respective integrated circuit for communication with the microcontroller will be explained using the example of only one address pin and thus the possibility of addressing only two integrated circuits with the help of the Fig. 3 - 5 will be explained in more detail.

[0027] In Fig. 3 is equivalent to the representation of the Fig. 2 The connection of a microcontroller µc via a previously described high-performance serial interface to two integrated circuits ASIC1' and ASIC2' is shown, which in this case only have one address pin ADDR, which are supplied with different voltage levels in order to represent their base addresses with "log. 0" and "log. 1".

[0028] Both integrated circuits ASIC1' and ASIC2' have, in addition to their address pins ADDR, a memory or memory area which has a memory section I, II for each possible address - in the example shown, for two possible addresses - whose physical addresses are known to the microcontroller µC, and into which it can write a defined bit combination, which can also consist of only one bit, as a token.

[0029] In the example shown, a first memory section I is assigned to the base address "log. 0" and a second memory section II to the base address "log. 1". If the microcontroller µC wants to activate the first integrated circuit ASIC1', it sends a write command via the transmit line to the base address BA1. This command is received by both integrated circuits ASIC1' and ASIC2' and compared with the base address at their address pin ADDR. Only the first integrated circuit ASIC1' detects a match and allows the write operation to its first memory section at address BA1, where the token is then written. It also sends an acknowledgment signal to the microcontroller µC.

[0030] The second integrated circuit ASIC2' also checks the transmitted base address with that at its address pin ADDR and detects a mismatch. According to the invention, however, in this case it will not send a non-acknowledgment signal to the microcontroller µC, thus disrupting the information flow between the microcontroller µC and the first integrated circuit ASIC1', but will instead switch its transmit output to high impedance and subsequently only monitor the data traffic at its receive input. As in the Fig. As shown in Figure 4, a memory section can consist not only of a first address to which the token can be written, but can also contain further addresses for additional information.

[0031] In the Fig. Figure 4 shows a memory section in the upper part containing a token in the form of a bit combination of eight hexadecimal fives, while in the lower part these hexadecimal fives are inverted, resulting in a hexadecimal A. This would indicate that the token has been removed and possibly reassigned to another integrated circuit. Token removal can also involve, for example, deleting the contents at the memory address assigned to the token within the memory section.

[0032] The process of token allocation by the microprocessor µc is to be carried out with the help of the Fig. 6. This will be illustrated using a flowchart. In step 10, the system is first reset. Then, in step 20, the system is initialized. In step 30, the microcontroller µC assigns the token to the first integrated circuit ASIC1' by sending a defined bit pattern, for example according to the following, to the base address BA1 of the first integrated circuit ASIC1' known to the microcontroller µC, as already described. Fig. Step 5 is written. In step 40, the integrated circuits arranged at the high-speed serial interface check whether the addressed base address matches their address set at the ADDR address input. If there is a match and a successful token entry in the memory section, the first integrated circuit, ASIC1', responds with an acknowledgment signal, ACK. As a result, it is activated and can, in step 50, begin communicating with the microcontroller µC. This continues until the token is removed from the first integrated circuit, ASIC1'. If the write operation fails, the process jumps back from step 40 to step 20 and the token assignment is performed again.

[0033] In the Fig. Figure 7 shows how the token is withdrawn again. In step 100, the first integrated circuit ASIC1' is to be installed as before in step 50. Fig. 6. The token communicates with the microcontroller µC according to standard procedure. In step 200, the token is to be removed from the first integrated circuit ASIC1'. For this purpose, the corresponding information is sent from the microcontroller µC to the first integrated circuit ASIC1' in step 300. In step 400, the first integrated circuit ASIC1' checks whether the write operation to the memory section containing the token was successful, for example, by inverting the defined bit combination representing the token. If the check is successful, it sends an acknowledgment signal ACK to the microcontroller µC. If the write operation failed, the process jumps back to step 100.

[0034] After step 400, none of the integrated circuits connected to the high-speed serial interface are initially active, so a new token can and must be assigned. This new token is assigned in step 500. In step 600, the microcontroller (µC) sends a write command to the base address of the second integrated circuit, ASIC2'. This command is checked by both integrated circuits, ASIC1' and ASIC2'. Only the second integrated circuit, ASIC2', can detect a match and, if the check is successful, sends an ACK confirmation signal to the microcontroller.

[0035] Should the writing process fail, the following will be done according to the Fig.Step 6 jumped back to step 600. Subsequently, in step 800, standard communication takes place between the microcontroller µC and the second integrated circuit ASIC2' by activating the second integrated circuit ASIC2', until the token is possibly removed again to reactivate the first integrated circuit ASIC1'.

[0036] In the ASIC design described above, multi-ASIC operation can be implemented in software. No additional hardware resources (e.g., chip select signals) are required, thus minimizing costs. The actual HSSL / ZIPWIRE protocol remains unchanged; only the memory area containing the token storage sections is introduced. This implementation is therefore compatible with all existing and future microcontrollers.

Claims

[1] Integrated circuit with at least one transmitting (Tx_ASIC) and at least one receiving connection (Rx_ASIC) as well as at least one address connection (ADDR; ADDR0, ADDR1), - with a memory or a memory area (I, II) having a number of memory sections (BA1, BA2) into which activation information can be written, - wherein the number of memory sections (BA1, BA2) is equal to the number of activatable integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') that can be operated on a common bus and can be coded by the at least one address connection (ADDR; ADDR0, ADDR1), - with a control unit which is configured to compare the address encoded by the at least one address connection (ADDR; ADDR0, ADDR1) with an address received at the receive connection (Rx_ASIC) and, in the event of a match, to write a defined bit pattern into the memory section (BA1, BA2) assigned to the address and, in the event of a mismatch, to suppress a non-acknowledgement signal (NACK) at the transmit connection (Tx_ASIC), wherein the integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') is configured to be activated by the defined bit pattern in the memory section (BA1, BA2) corresponding to the address defined at the at least one address connection (ADDR; ADDR0, ADDR1) for communication with a microprocessor (µC) connected to the at least one transmit connection (Tx_ASIC) and at least one receive connection (Rx_ASIC) via the common bus. [2] Integrated circuit according to claim 1, which is arranged to switch the transmitting terminal (Tx_ASIC) to high impedance in the event of a mismatch between the address coded by the at least one address terminal (ADDR; ADDR0, ADDR1) and the address received at the receiving terminal (Rx_ASIC). [3] Method for activating an integrated circuit from a group of at least two integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') connected to a master unit (µC) via a bus for communication with the master unit (µC), wherein the bus comprises at least one transmit line leading from the master unit (µC) to the integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') and one receive line leading from the integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') to the master unit (µC), wherein the integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') are designed according to claim 1, - in which the master unit (µC) sends a signal to the integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') connected to the bus, which signal contains a command to write a defined bit pattern into the memory section (BA1, BA2) which corresponds to the address of the integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') selected for communication, coded at the at least one address terminal (ADDR; ADDR0, ADDR1), - in which in each integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') the transmitted memory section address is compared with the address coded at the at least one address connection (ADDR; ADDR0, ADDR1) and the defined bit pattern is written only into the corresponding memory section (BA1, BA2) and an acknowledgment signal (ACK) is sent to the master unit (µC) if a match is detected, - in which, when a mismatch is detected, no non-acknowledgement signal (NACK) is sent from the affected integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') connected to the bus to the master unit (µC) and no further reaction to signals from the master unit (µC) takes place until a new command to write to one of the memory sections (BA1, BA2) is received. [4] Method according to claim 3, wherein when the non-conformity is detected, the transmitting terminal (Tx_ASIC) is switched to high impedance. [5] Method according to one of claims 3 or 4, in which, before the activation of another of the integrated circuits (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') connected to the common bus, the previously activated integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2') is first deactivated by a signal sent from the master unit (µC) to the activated integrated circuit (ASIC1, ASIC2, ASIC3; ASIC1', ASIC2'), which signal causes a change in the content of the memory section (BA1, BA2) written with the defined bit pattern. [6] Method according to claim 5, wherein the change in the content of the memory section (BA1, BA2) described with the defined bit pattern is carried out by inverting the content. [7] Method according to claim 5, wherein the change in the content of the memory section (BA1, BA2) described with the defined bit pattern is carried out by deleting the content.

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