Power semiconductor device with a field electrode

Abstract

Power semiconductor device (1) comprising the following: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) and a second load terminal (12) of the power semiconductor device (1); - a source region (101), a channel region (102) and a drift volume (100), each contained in the semiconductor body (10), wherein the source region (101) is electrically connected to the first load terminal (11) and wherein the channel region (102) isolates the source region (101) from the drift volume (100); - a semiconductor zone (108) contained in the semiconductor body (10) which couples the drift volume (100) to the second load terminal (12), whereby a first transition (1008) is established between the semiconductor zone (108) and the drift volume (100); - a control electrode (131) which is insulated from the semiconductor body (10) and the load terminals (11, 12) and is configured to control a path of the load current in the channel area (102); - a trench (14) extending along an expansion direction (Z) into the drift volume (100) and including a field electrode (141), wherein: - in a plane parallel to the direction of expansion (Z) the cross-sectional area of ​​the field electrode (141) is smaller than the cross-sectional area of ​​the control electrode (131); and - the drift volume (100) contains a superjunction structure formed by at least one drift region (104) with dopants of a first conductivity type and by an adjacent compensation region (105) with dopants of a second conductivity type; wherein the power semiconductor device (1) further comprises - a first path (15) that electrically connects the field electrode (141) to either the first load terminal (11) or a control terminal (13) of the power semiconductor device (1); and - a second path (16) that connects the control electrode (131) to the control terminal (13).

Description

Technical field

[0001] This description relates to embodiments of a power semiconductor device, embodiments of a method for processing a power semiconductor device, and embodiments of a switching power circuit. In particular, the description relates to embodiments of a power semiconductor device with a control electrode and a field electrode, and to corresponding embodiments of a processing method and corresponding embodiments of a switching power circuit. background

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name just a few, have been used for various applications, including, among others, switches in power supplies and power converters.

[0003] For example, a power semiconductor device can comprise one or more MOS control heads (MOS: Metal-Oxide-Semiconductor), each control head having at least one control electrode and a source region and an adjacent channel region. The control electrode is typically referred to as the "gate electrode".

[0004] In order to put the power semiconductor device into a conducting state, during which a load current can be passed in a forward direction between load terminals of the device, the control electrode can be supplied with a control signal having a voltage within a first region, so that a load current path is induced within the channel region.

[0005] To put the power semiconductor device into a blocking state, during which a forward voltage applied to the load terminals of the semiconductor device can be blocked and the forward flow of the load current is inhibited, the control electrode can be supplied with the control signal, which has a voltage within a second region distinct from the first, thus cutting off the load current path in the channel region. The forward voltage can then include a depletion region at a boundary layer formed by a transition between the channel region and a drift region of the power semiconductor device. This depletion region is also called a "space charge region" and can extend mainly into the drift region of the semiconductor device. In this context, the channel region is often also referred to as a "body region" in which the load current path, e.g.,An inversion channel through which a control electrode can be induced to bring the semiconductor device into the conducting state. Without the load current path in the channel region, the channel region can form a barrier layer with the drift region.

[0006] A general goal is to minimize losses occurring in semiconductor devices, where losses are primarily caused by conduction and / or switching losses, so that the application, e.g., the power supply or power converter, can exhibit high efficiency. For this purpose, compensation structures, also known as "superjunction structures," have been proposed.

[0007] Beyond a control electrode, a power semiconductor device may also include a field electrode, which may be electrically connected to one of the load terminals and extend into the drift region towards the other load terminal. The presence of the field electrode in the power semiconductor device can influence the capacitance formed by the load terminals. Capacitance is sometimes also referred to as Ccap. DS designated.

[0008] Furthermore, the capacity C DS and / or a capacitance formed between the control electrode and one of the load terminals, which in some cases is also referred to as C DG This refers to influencing the degree of voltage and / or current oscillation during a switching procedure.

[0009] German patent application DE 10 2014 112 186 A1 describes a power semiconductor chip package comprising a housing, a semiconductor chip embedded in the housing, and at least four terminals that are partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip comprises a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first grooves comprising gate electrodes and first field electrodes that are electrically insulated from the gate electrodes.One of the four terminals is electrically connected to the first metal layer, one of the four terminals is electrically connected to the second metal layer, one of the four terminals is electrically connected to the gate electrodes of the first trenches, and one of the four terminals is electrically connected to the first field electrodes of the first trenches.

[0010] German patent application DE 103 46 838 A1 describes the following: The P-type pylons in a superjunction device exhibit an increased concentration at their upper end to modify the charge balance such that the upper part of the P-type regions is not completely depleted during reverse bias operation, while the remainder of the P-type pylons is in charge equilibrium with the surrounding N-body region. An avalanche breakdown current can then be diverted to the middle part of the P-body (for an N-channel device) channel region at the top of the pylon and by a resistor below the source to increase robustness (turn-on of the parasitic bipolar transistor due to the avalanche breakdown current flow through the resistor) with only a slight loss of breakdown voltage due to the increased concentration at the top of the pylons. Brief description

[0011] The invention is defined by independent claim 1. Features of exemplary embodiments are specified in the dependent claims.

[0012] According to one embodiment, a power semiconductor device comprises: a semiconductor body configured to conduct a load current between a first load terminal and a second load terminal of the power semiconductor device; a source region, a channel region, and a drift volume, each contained within the semiconductor body, wherein the source region is electrically connected to the first load terminal and the channel region isolates the source region from the drift volume; a semiconductor zone contained within the semiconductor body that couples the drift volume to the second load terminal, with a first transition being established between the semiconductor zone and the drift volume; and a control electrode that is isolated from the semiconductor body and the load terminals and is configured to control a path of the load current in the channel region.and a trench extending into the drift volume along a direction of expansion and containing a field electrode. The ohmic resistance of the field electrode is greater than the ohmic resistance of the control electrode. Furthermore, the distance between the field electrode and the first transition is at least 70% of the total extent of the drift volume in the direction of expansion.

[0013] According to a further embodiment, a power semiconductor device comprises the following: a semiconductor body configured to conduct a load current between a first load terminal and a second load terminal of the power semiconductor device; a source region, a channel region, and a drift volume, each contained within the semiconductor body, wherein the source region is electrically connected to the first load terminal and wherein the channel region isolates the source region from the drift volume, with at least one total extent of the drift volume along an extent direction defining a blocking voltage of the semiconductor device; a control electrode isolated from the semiconductor body and the load terminals and configured to control a path of the load current in the channel region;and a trench extending into the drift volume along the direction of expansion and containing a field electrode insulated from the drift volume by a field insulator. The ohmic resistance of the field electrode is greater than the ohmic resistance of the control electrode. Furthermore, the first thickness of the field insulator along a first lateral direction and / or the second thickness of the field insulator along the direction of expansion is less than the blocking voltage multiplied by a factor of 2 nm / V.

[0014] According to a further embodiment, a switching power device is configured to receive an input power signal comprising an input voltage and / or an input current. The switching power device comprises a circuit arrangement including at least one power semiconductor device according to one of the aforementioned embodiments. The circuit arrangement is configured to convert the input power signal into an output power signal comprising an output voltage and / or an output current, wherein the output power signal is different from the input power signal; and wherein the switching power device is configured to deliver the output power signal to an electrical load.

[0015] A specialist will recognize additional features and advantages upon reading the following detailed description and examining the attached drawings. Brief description of the drawings

[0016] The parts shown in the figures are not necessarily to scale; instead, the focus is on the principles of the invention. Furthermore, identical reference numbers in the figures denote corresponding parts. Fig. Figure 1 schematically illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. Figure 2 schematically illustrates a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. Figure 3 schematically illustrates a block diagram of a switching power device according to one or more embodiments; Fig. Figure 4 schematically illustrates a diagram of a power semiconductor device processing method according to one or more embodiments; Fig. Figure 5 schematically illustrates a diagram of a power semiconductor device processing method according to one or more embodiments; Fig. Figures 6-7 each schematically illustrate a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. Figure 8 schematically illustrates a section of a vertical cross-section of a trench of a power semiconductor device according to one or more embodiments; Fig. Figure 9 schematically illustrates ohmic resistances associated with a field electrode and a control electrode of a power semiconductor device according to one or more embodiments; Fig. Figure 10 schematically illustrates ohmic resistances associated with a control electrode of a power semiconductor device according to one or more embodiments; Fig. 11 schematically illustrates ohmic resistances associated with a field electrode and a control electrode of a power semiconductor device according to one or more embodiments; Fig. Figure 12 schematically illustrates ohmic resistances associated with a field electrode and a control electrode of a power semiconductor device according to one or more embodiments; and Fig. Figures 13-18 each schematically illustrate a section of a vertical cross-section of a power semiconductor device according to one or more embodiments. Detailed description

[0017] The following detailed description refers to the accompanying drawings, which show specific embodiments in which the invention can be practiced for illustrative purposes.

[0018] In this respect, directional terminology such as "above," "below," "below," "front," "back," "upstream," "downstream," "below," "above," etc., may be used with reference to the orientation of the figures being described. Because parts of embodiments may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention.

[0019] The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been labelled with the same references in the various drawings, unless otherwise stated.

[0020] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer or die. For instance, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, with the first lateral direction X and the second lateral direction Y potentially being perpendicular to each other.

[0021] The term "vertical," as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the semiconductor wafer's surface. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction Y and the second lateral direction Y.

[0022] In this description, n-doped materials are referred to as the "first conductivity type," while p-doped materials are referred to as the "second conductivity type." Alternatively, reverse doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0023] In the context of this description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, sections, zones, portions, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and a portion or part of a semiconductor device. Furthermore, the term "in contact" in the context of this description is intended to describe the existence of a direct physical connection between two elements of the respective semiconductor device; for example, a junction between two elements that are in contact with each other may not include any further intermediate element or the like.

[0024] Furthermore, in the context of this description, the term "electrical isolation" is used in its generally accepted sense, unless otherwise specified, and is intended to describe a situation where two or more components are positioned separately and there is no ohmic connection between them. However, components that are electrically isolated from each other may still be coupled, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. For example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled, e.g., by means of an insulating material such as a dielectric.

[0025] Specific embodiments described in this description apply, among others, to a power semiconductor device, such as a power semiconductor transistor, which can be used within a switching power device, e.g., within a power converter or a power supply. Accordingly, in one embodiment, the semiconductor device is configured to carry a load current, which is supplied to a load and / or provided by a power source.For example, the power semiconductor device can comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell and / or a monolithically integrated transistor cell and / or a monolithically integrated IGBT cell and / or a monolithically integrated RC-IGBT cell and / or a monolithically integrated MGD cell (MGD: MOS-Gated Diode) and / or a monolithically integrated MOSFET cell and / or derivatives thereof. Such diode cells and / or transistor cells can be integrated within a power semiconductor module. Several such cells can constitute a cell array integrated with an active region of the power semiconductor device.

[0026] The term “power semiconductor device,” as used in this description, is intended to describe a single-chip semiconductor device with high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is designed for high current, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltage, typically above 300 V, e.g., up to at least 400 V, e.g., higher than 1 kV or even higher than 3 kV. For example, the power semiconductor device described below may have a striped or cellular configuration and may be configured to be used as a power component in medium- and / or high-voltage applications. Occasionally, the power semiconductor device is also referred to simply as a “semiconductor device.”

[0027] Fig. Figure 1 schematically illustrates a section of a vertical cross-section of a power semiconductor device 1 according to one or more embodiments. The illustrated cross-section is parallel to a plane defined by the direction of extension Z and the first lateral direction X. Each of the components depicted therein can extend in the second lateral direction Y.

[0028] The in Fig. Figure 1, an illustrated embodiment of the semiconductor device 1, comprises a semiconductor body 10 configured to conduct a load current between a first load terminal 11 and a second load terminal 12 of the power semiconductor device 1. A source region 101, a channel region 102, and a drift volume 100 are each contained within the semiconductor body 10. The source region 101 can be electrically connected to the first load terminal 11, and the channel region 102, which can also be electrically connected to the first load terminal 11, can isolate the source region 101 from the drift volume 100.

[0029] A semiconductor zone 108, comprising, for example, a collector region or a drain region, can be contained within the semiconductor body 10 and can couple the drift volume 100 to the second load terminal 12. A first junction 1008 can be established between the semiconductor zone 108 and the drift volume 100. The first junction 1008 can be the lower end of a space charge region that is produced during a lock-out state of the semiconductor device 1 according to one embodiment. For example, the semiconductor zone 108 can be provided by means of a substrate material and / or by performing an implantation processing step, e.g., from a rear side of the semiconductor device 1. For example, at least one section of the semiconductor zone 108 exhibits a dopant concentration that is at least 10 times the dopant concentration of the drift volume 100. The factor can even be greater than 10; e.g.,The factor can be greater than 100 or even greater than 1000. Depending on the configuration of the power semiconductor device 1, the semiconductor zone 108 can comprise a drain region and / or a p-doped emitter (collector) region, which is, for example, in electrical contact with the second load terminal 12. To provide reverse load current capability, the semiconductor zone 108 can further comprise heavily doped regions, e.g., + The semiconductor zone 108 includes areas also referred to as "n-short circuits" that may be electrically connected to the second load terminal 12. Furthermore, the semiconductor zone 108 may also include a field-stop layer or a buffer layer. These exemplary and optional components of the semiconductor zone 108 are not illustrated in the drawings.

[0030] Furthermore, a control electrode 131, which is insulated from the semiconductor body 10 and the load terminals 11, 12, can be configured to control a path of the load current in the channel region 102. A trench 14, extending along the expansion direction Z into the drift volume 100, can contain a field electrode 141. In one embodiment, an ohmic resistor (compare, e.g., R) is used. FP in Fig. 9) of the field electrode 141 greater than an ohmic resistance (compare e.g. R) G in Fig. 9) of the control electrode 131. Furthermore, a distance D between the field electrode 141 and the first transition 1008 can be at least 70% of the total extent TED of the drift volume 100 in the expansion direction Z. This distance can even be greater than 70%, e.g. greater than 80%, greater than 90% or even greater than 95%.

[0031] Fig. Figure 2 schematically illustrates a section of a vertical cross-section of a power semiconductor device 1 according to one or more further embodiments. The illustrated cross-section is parallel to a plane defined by the direction of extension Z and the first lateral direction X. Each of the components depicted therein can extend in the second lateral direction Y.

[0032] The in Fig. Figure 2 illustrates an embodiment of the semiconductor device 1 comprising a semiconductor body 10 configured to conduct a load current between a first load terminal 11 and a second load terminal 12 of the power semiconductor device 1. A source region 101, a channel region 102, and a drift volume 100 are contained within the semiconductor body 10. The source region 101 can be electrically connected to the first load terminal 11, and the channel region 102, which can also be electrically connected to the first load terminal 11, can isolate the source region 101 from the drift volume 100. For example, at least one total extent TED of the drift volume 100 along the expansion direction Z defines a blocking voltage of the semiconductor device 1. Furthermore, a control electrode 131, which is isolated from the semiconductor body 10 and the load terminals 11, 12, can be configured to control a path of the load current in the channel region 102.A trench 14 extending along the direction of expansion Z into the drift volume 100 can contain a field electrode 141, which is insulated from the drift volume 100 by a field insulator 142. In one embodiment, an ohmic resistor (compare e.g. BR) is used. FP in Fig. 9) of the field electrode 141 greater than an ohmic resistance (compare e.g. R) G in Fig. 9) of the control electrode 131. Furthermore, a first thickness TX of the field insulator 142 along the first lateral direction X and / or a second thickness TZ of the field insulator 142 along the expansion direction Z is less than the blocking voltage multiplied by a factor of 2 nm / V.

[0033] According to the in Fig. 1 and Fig. In two schematically and exemplarily illustrated embodiments, the control electrode 131 can be arranged in a trench 17 and can be electrically isolated from both the semiconductor body 10 and the first load terminal 11 by an insulator 132. It is understood, however, that according to other embodiments, the control electrode 131 can have a flat configuration and can be arranged above the semiconductor body 10. As explained with reference to other drawings, the field electrode 141 and the control electrode 131 need not necessarily be arranged in separate trenches 14 and 17, but can also be arranged in a shared trench.

[0034] For example, according to one or more embodiments of the semiconductor device 1, the field electrode 141 can be located relatively far from the first junction 1008 compared to low-voltage FETs (FET: field-effect transistor). For example, the thickness of the field insulator 142 can be relatively small due to the relatively large distance D. In contrast, with respect to a low-voltage FET, a field electrode can essentially traverse the entire drift volume and may even extend into a substrate region. The inventor has recognized that, although the capacitance formed by the field electrode 141 and the second load terminal 12 may be relatively small, the damping effect of the field electrode 141 can be significant due to its ohmic configuration.

[0035] Fig. Figure 3 schematically illustrates a block diagram of a switching power device 3. The switching power device 3 can be configured to receive an input power signal that includes an input voltage U. IN and / or an input current I IN The switching power device 3 can comprise a circuit arrangement 31 which includes at least one power semiconductor device 1, e.g. a power semiconductor device 1 according to one of the in Fig. 1 and Fig. 2 schematically illustrated embodiments. The circuit arrangement 31, e.g. a switching power supply circuit or a switching driver circuit, can be configured to convert the input power signal into an output power signal that provides an output voltage U. OUT and / or an output current I OUTThe output power signal can differ from the input power signal; for example, it can differ in amplitude, frequency, phase, and / or shape. Furthermore, the switching power device 3 can be configured to deliver the output power signal to an electrical load 4. For example, the input power signal can be a DC voltage (DC: Direct Current), and the circuit arrangement 31 can be configured to convert the DC voltage to an AC voltage (AC: Alternating Current) to drive, for example, an electric motor. In other words, the load 4 can be an electric motor.In another embodiment, the load 4 can comprise a section of the electrical network, and the circuit arrangement 31 can be configured to receive an AC voltage and / or an AC current as the input power signal and can be configured to convert this AC input signal into an AC output signal. For this purpose, the circuit arrangement 31 can comprise several power semiconductor devices 1 arranged, for example, in a DC-DC, DC-AC, AC-DC, and / or AC-AC configuration. To give just a few examples, the circuit arrangement 31 can include a buck converter, a boost converter, a buck-boost converter, an LLC converter, a ZVS bridge (ZVS: Zero Voltage Switching), a PFC device (PFC: Power Factor Compensation), a rectifier, and / or a converter, etc. B. a converter in a bridge arrangement.

[0036] Fig. Figure 4 schematically and exemplarily illustrates a diagram of a method 2 for processing a power semiconductor device according to one or more embodiments. It also refers to the following. Fig. 1. For example, in step 20, a power semiconductor device 1 is provided, comprising a semiconductor body 10 configured to conduct a load current between a first load terminal 11 and a second load terminal 12 of the power semiconductor device 1. A source region 101, a channel region 102, and a drift volume 100 are each contained within the semiconductor body 10. Furthermore, the semiconductor device 1 can be provided such that the source region 101 is electrically connected to the first load terminal 11 and that the channel region 102 isolates the source region 101 from the drift volume 100. The provided semiconductor device 1 can include a semiconductor zone 108, which, for example, includes a collector region or a drain region, that can be integrated within the semiconductor body 10 and couple the drift volume 100 to the second load terminal 12.A first transition 1008 can be established between the semiconductor zone 108 and the drift volume 100. Furthermore, in step 22, a control electrode 131 can be provided, which is insulated from the semiconductor body 10 and the load terminals 11, 12. The control electrode 131 can be provided such that it is configured to control a path of the load current in the channel region 102. In step 24, a trench 14 can be provided, which extends along the expansion direction Z into the drift volume 100 and which includes a field electrode 141. In an embodiment of method 2, it is ensured in step 26 that an ohmic resistance (compare e.g. BR) FP in Fig. 9) of the field electrode 141 greater than an ohmic resistance (compare e.g. R) G in Fig. 9) of the control electrode 131. Furthermore, step 24 can be carried out such that a distance D between the field electrode 141 and the first transition 1008 is at least 70% of the total extent TED of the drift volume 100 in the expansion direction Z.

[0037] Fig. Figure 5 schematically and exemplarily illustrates a diagram of Method 2 for processing a power semiconductor device according to one or more embodiments. It also refers to the following: Fig. 2. For example, in step 20, a power semiconductor device 1 is provided, comprising a semiconductor body 10 configured to conduct a load current between a first load terminal 11 and a second load terminal 12 of the semiconductor device 1. A source region 101, a channel region 102, and a drift volume 100 may each be contained within the provided semiconductor body 10. Furthermore, the semiconductor device 1 may be provided such that the source region 101 is electrically connected to the first load terminal 11 and that the channel region 102 isolates the source region 101 from the drift volume 100. For example, at least one total extent TED of the drift volume 100 along the extent direction Z may define a blocking voltage of the semiconductor device 1. Furthermore, in step 22 a control electrode 131 can be provided which is insulated from the semiconductor body 10 and the load terminals 11, 12.The control electrode 131 can be provided such that it is configured to control a path of the load current in the channel area 102. In step 25, a trench 14 can be provided that extends along the expansion direction Z into the drift volume 100 and that includes a field electrode 141 which is insulated from the drift volume 100 by a field insulator 142. In one embodiment of method 2, it is ensured in step 26 that an ohmic resistance (compare e.g. BR) FP in Fig. 9) of the field electrode 141 greater than an ohmic resistance (compare e.g. R) G in Fig. 9) of the control electrode 131. Furthermore, step 25 can be carried out such that a first thickness TX of the field insulator 142 along the first lateral direction X and / or a second thickness TZ of the field insulator 142 along the expansion direction Z is less than the blocking voltage multiplied by a factor of 2 nm / V.

[0038] For example, the power semiconductor device 1 is e.g. according to the in Fig. 1 or in Fig. The embodiment illustrated in Figure 2 is configured for a blocking voltage of at least 300 V. The blocking voltage can be higher than 300 V, e.g., higher than 500 V, higher than 750 V, or even higher than 1 kV or more than 3 kV. To configure the semiconductor device to exhibit such a blocking voltage, the total extent TED of the drift volume 100 along the expansion direction Z can be selected accordingly, as explained above.

[0039] The following will describe features of further embodiments of the as described in Fig. 1 and Fig. 2 illustrated power semiconductor device 1 will be explained. Unless explicitly stated otherwise, each of the optional features listed below can be applied equally to the embodiments as described in each of Fig. 1 to Fig. 5 are illustrated, i.e. also apply to the embodiments of method 2 and to the embodiments of the switching power device 3.

[0040] In one embodiment, the distance D (compare Fig. 1) even greater than 70% of the total extent TED of the drift volume 100, e.g. greater than 75%, greater than 80% or even greater than 90%.

[0041] Furthermore, the first thickness TX of the field insulator 142 along the first lateral direction X and / or the second thickness TZ of the field insulator 142 along the expansion direction Z can even be less than the blocking voltage multiplied by a factor of 2 nm / V. For example, the factor can be 1 nm / V, 0.75 nm / V, or less than 0.5 nm / V. If, for example, the power semiconductor device 1, e.g., the total expansion TED of the drift volume 100, is designed for a blocking voltage of 500 volts, the first thickness TX and / or the second thickness TZ can, according to one embodiment, be less than 1000 nm or even less than 500 nm.

[0042] The ohmic field electrode resistance R FPIt can be configured to dampen ringing, for example, by reducing current and / or voltage oscillations with respect to amplitude and / or duration. Such oscillations can occur during switching procedures, such as during power-on and / or power-off. According to one embodiment, the ringing is reduced, for example, with respect to amplitude or duration, due to the presence of the ohmic field electrode resistance R. FP , which is greater than the ohmic control electrode resistance R G is muted.

[0043] For example, the ohmic field electrode resistance R FP at least 110% of the ohmic control electrode resistance R G This ratio can even be greater than 110%, e.g. greater than 150%, greater than 200% or even greater than 300%.

[0044] In one embodiment, the ohmic field electrode resistance R is FPat least 1 Ω, at least 2 Ω, at least 2.5 Ω or even more than 3 Ω.

[0045] The following are some exemplary ways to determine an ohmic field electrode resistance R FP to realize a resistance greater than an ohmic control electrode resistance R G This will be explained. Furthermore, the terms "ohmic field electrode resistance R" will be explained. FP “ and “ohmic control electrode resistance R G “, as they are used in this description, to be understood.

[0046] In relation to Fig. 6 and Fig. 7. The power semiconductor device 1 can initially comprise an active region 1-1 surrounded by a non-active border region 1-2. The non-active border region 1-2 can be closed off by a border 1-21, which may have been created, for example, by separating a die from a wafer along a sectioning line.

[0047] For example, several power cells 19, each of which can be configured to carry a portion of the load current between the first load terminal 11 and the second load terminal 12, can be arranged in the active area 1-1. As in Fig. As illustrated in Figure 6, the power cells 19 can, for example, have a striped configuration, with each striped cell being able to traverse at least a substantial part of the active area 1-1. In another example, as in Fig. As illustrated in Figure 7, the power cells 19 can have a cellular configuration, with the total lateral extent of each cellular cell being only a fraction of the lateral extent of the active area 1-1. Generally speaking, a person skilled in the art is familiar with the differences between a strip configuration and a cellular configuration (e.g., cells with a rectangular horizontal cross-section, a square cross-section, a hexagonal cross-section, or a circular / elliptical cross-section), and this general understanding of these terms is not deviated from within the present description. In the case of a cellular configuration (as in Figure 7), the power cells 19 can have a cellular configuration, where the total lateral extent of each cellular cell is only a fraction of the lateral extent of the active area 1-1. Fig. (Figure 7 illustrates) the control electrodes 131 can, for example, be formed by a continuous grid. The field electrodes 141, which can be arranged in the same trenches as the control electrodes 131, can also be formed by a continuous grid. Furthermore, it is understood that a power semiconductor chip, including the power semiconductor device 1 described herein, can comprise several active regions 1-1. Between such active regions 1-1, edge termination zones can be arranged, and, for example, a number of first contact runners for contacting the field electrodes 141 and / or a second number of contact runners for contacting the control electrodes 131 can be arranged on these. By means of these contact runners and the way in which they contact the control electrodes or the field electrodes 141, the ohmic resistances associated with the control electrodes 131 and / or the field electrodes 141 can be controlled according to one embodiment.

[0048] Regardless of the chosen configuration, each power cell 19 can comprise a section of the source area 101, a section of the channel area 102, and a section of the drift volume 100. Furthermore, each power cell 19 can be controlled by means of a respective control electrode 131. One or more trenches 14 may be arranged between two adjacent power cells 19, each trench containing the field electrode 141. These trenches 14 are arranged in Fig. 6 and Fig. 7 not illustrated. With reference to Fig. 6. The one or more trenches 14, each arranged between two adjacent power cells 19, can be, for example, a strip configuration with similar or identical lateral dimensions to the power cells 19 (compare, e.g., Fig. 12 or Fig. 13) exhibit. With reference to Fig. 7. The one or more trenches 14, which may be arranged between each pair of adjacent power cells 19, may also have a cellular configuration with similar or identical lateral dimensions to the power cells 19. Accordingly, the control electrodes 131 and the field electrodes may have a strip configuration or a cellular configuration.

[0049] Accordingly, it is understood that the term "ohmic field electrode resistance R" FP “In the event that the power semiconductor device 1 comprises more than one field electrode 141 and / or more than one control electrode 131, the ohmic field electrode resistance R FP all field electrodes 141 contained in the power semiconductor device 1 can refer to and that the term “ohmic control electrode resistance R” G “on the ohmic control electrode resistance R Gall control electrodes 131 contained in the power semiconductor device 1 can refer to. For example, several of the field electrodes 141 and several of the control electrodes 131 are arranged in the active region 1-1, wherein the ohmic resistance R FP of the several field electrodes 141 at least 110% of the ohmic resistance R G The number of multiple control electrodes is 131. This factor can be greater than 110%, as explained above.

[0050] For example, the electrical conductivity of the field electrode(s) 141 is lower compared to the electrical conductivity of the control electrode(s) 131. Regardless of the chosen spatial configuration of the control electrode 131 and the field electrode 141, the difference between the ohmic resistance of the control electrode R can G and the ohmic field electrode resistance R FPThis can be achieved by a difference in material. For example, the control electrode 131 can be made of a first material, and the field electrode 141 can be made of a second material. The second material can have an electrical conductivity that is lower than that of the first material. Both the first and second materials can be composite materials, e.g., stacks of materials. For example, the first material of the control electrode 131 can be a polydoped semiconductor material, and the second material of the field electrode 141 can also be a polydoped semiconductor material, with the dopant concentration present in the second material being lower compared to that present in the first material.

[0051] With reference to Fig. 8. The difference between the ohmic control electrode resistance R can now be determined. Gand the ohmic field electrode resistance R FPAlternatively or additionally, this can be achieved by a difference in geometry. For example, the cross-sectional area of ​​the field electrode 141 can be smaller than that of the control electrode 131, with each cross-sectional area being parallel to the plane defined by the first lateral direction X and the direction of extension Z. In one embodiment, the cross-sectional area of ​​the control electrode 131 is the cross-sectional area of ​​the field electrode multiplied by a factor greater than 1.1, greater than 1.5, or even greater than 2. Furthermore, the total extent TEF of the field electrode 141 can be smaller than the total extent TEG of the control electrode 131, with both the total extent TEF and TEG being parallel to the direction of extension Z.For example, the total extent TEG is the total extent TEF multiplied by a factor greater than 1.1, greater than 1.5, or even greater than 2. For example, another (not illustrated) electrode, e.g., a shielding electrode, may be arranged between the control electrode 131 and the field electrode 141, the additional electrode being electrically connected to the potential of the first load terminal 11, which may be a source potential.

[0052] As schematically in Fig. As illustrated in Figure 8, both the control electrode 131 and the field electrode 141 can be arranged in the same trench 14, with the field electrode 141 being located below the control electrode 131. This optional aspect is discussed with reference to Fig. Section 14 explains this in more detail. If the trench 14 contains both the control electrode 131 and the field electrode 141, both electrodes 131 and 141 can be insulated from the semiconductor body 10 by means of the field insulator 142. The field insulator 142 can comprise a field oxide and / or a gate oxide.

[0053] Each of the Fig. Figures 9 to 11 schematically illustrate ohmic resistances assigned to the field electrode 141 and / or the control electrode 131 of the power semiconductor device 1 according to one or more embodiments.

[0054] Regarding the embodiment according to Fig. 9 The semiconductor device 1 can comprise a first path 15 that electrically connects the field electrode 141 to either the first load terminal 11 or a control terminal 13 of the semiconductor device 1.

[0055] For example, the control terminal 13 is electrically isolated from both the first load terminal 11 and the second load terminal 12 and can be configured to receive a control signal from a driver unit 4, which may be located outside the semiconductor body 10. For this purpose, the control terminal 13 can include a control terminal contact pad (in Fig. 9 not illustrated, compare reference number 137 in Fig. 11).

[0056] For example, a series resistor 41 can be arranged between the driver unit 4 and the control terminal 13. This series resistor 41 can be located outside the semiconductor body 10 and can furthermore be designed, for example, with regard to its actual ohmic resistance value and / or its actual position, depending on the requirements of a given application. In one embodiment, the series resistor 41 does not contribute to the ohmic resistance of the control electrode R. G at.

[0057] Downstream of the control terminal 13, e.g., downstream of the control terminal contact pad, a second path 16 can be provided, connecting one or more control electrodes 131 to the control terminal 13. In one embodiment, the second path 16 is monolithically integrated with the power semiconductor device 1, for example, by means of a polysemier material that is insulated from the semiconductor body 10 by means of an insulator, e.g., an oxide, and is located, e.g., above the surface 10-1 (compare Fig. 11) of the semiconductor body 10 and / or within a trench extending into the semiconductor body 10. The second path 16 may include an ohmic resistor 133 and may have a resistance value R G,intexhibit. For example, the ohmic resistance 133 is a resistance that has been "explicitly" provided in the second path 16 to provide a specific resistance value between the control terminal 13 and the control electrodes 131, e.g., by means of a defined area filled with, for example, a polydoped semiconductor material, and / or by means of a discrete resistor device. Accordingly, the resistance 133, if present, may be geometrically identifiable. In another embodiment, the resistance 133 is not provided. As described in more detail below, in one embodiment, the resistance 133, or the control terminal 13, if the resistance 133 is not provided, may each be electrically connected to the control electrodes 131 by one or more contact runners. For example, the contact runners in Fig. 9 is illustrated by the vertical lines connecting the control electrodes 131. The resistance of these contact runners can be comparatively low or even negligible. This resistance R G,int The resistance of the second path 16, which may therefore depend strongly on the resistance of the optionally provided ohmic resistor 133, can be an internal resistance that may be effective between the control terminal 13 on one side and the control electrodes 131 and their contact runners on the other. As explained above, the control terminal 13 can provide an interface to an area outside the semiconductor device 1, thus enabling, for example, a connection to the driver unit 4, whereas the control electrodes 131 may be located within the semiconductor device 1, for example, buried in the trenches 14 and / or 17. In one embodiment, the internal resistance R G,intof the second path 16 not to the ohmic control electrode resistance R G Accordingly, the optionally provided resistor 133, for example, does not contribute to the ohmic control electrode resistance R. G However, according to one embodiment, the resistance of the contact runners connecting the control electrodes 131 can be adjusted to the ohmic resistance of the control electrodes R. G contribute.

[0058] The aspect discussed in the previous paragraph is also schematically represented in Fig. 10 illustrates. Accordingly, the one or more control electrodes 131, which are located in a respective trench 17 or 14 (the latter being in Fig. (10 is not illustrated) are buried, a distributed resistance R G,distexhibiting an internal ohmic resistance. The one or more control electrodes 131 can be electrically connected to the control terminal 13 via the second path 16. For example, the distributed resistance of the control electrode R G,dist essentially by that section of the control electrode 131 which controls the path of the load current, e.g. in the channel region 102, and the - although usually negligible - resistance of the (in Fig. 10 (not illustrated) contact runners are shown. In contrast, the second path 16, which represents the internal resistance R G,int exhibits, for example, the optionally provided resistor 133, is not configured to control the path of the load current in the channel area 102, and according to one embodiment does not contribute to the ohmic control electrode resistance R G at.

[0059] The distributed resistance of the control electrode R G,distThis does not necessarily have to be a "geometric" resistance, but can be the resistance that can be measured by performing an RC measurement. For example, with respect to an equivalent circuit, the resistance in Fig. The control electrode 131, illustrated in Figure 10, can be a network of several unit resistances connected to each other by unit capacitances. Accordingly, the distributed resistance of the control electrode R can be G,dist The effective ohmic resistance of the equivalent circuit may be defined as the equivalent circuit, where the equivalent circuit may include all of the control electrodes 131 that may be present in the semiconductor device 1. Such an effective ohmic resistance of the equivalent circuit may be smaller than the actual geometric resistance, e.g., by a factor of 1 / 3. This can be applied analogously to the distributed resistance of the field electrode R. FP,dist apply.

[0060] In one embodiment, only the distributed resistance R carries weight. G,dist the control electrodes 131 to the ohmic control electrode resistance R G As explained above, the contact runners that connect the control electrodes 131 to each other can also be added to the distributed resistance R. G,dist contribute. In contrast, the optionally provided ohmic resistor 133, which contributes at least part of R G,int forms, does not contribute to this. Accordingly, equation (1) with the definitions given above can hold according to one or more embodiments: RG=RG,dist

[0061] According to equation (1), the ohmic resistance of the control electrode is R. G only the distributed resistance R G,dist the control electrode(s) 131 and does not include the internal resistance R G,int of the second path 16.

[0062] Again with reference to Fig. 9. As explained above, the one or more field electrodes 141 can be electrically connected to the first load terminal 11 via the first path 15. However, it is understood that, according to another embodiment, the one or more field electrodes 141 can also be electrically connected to a different electrical potential, e.g., to the control terminal 13, via the first path 15. Like the control terminal 13, the first load terminal 11 can also provide an interface to an area outside the power semiconductor device 1, thus enabling, for example, the receiving and / or output of the load current. For example, the first load terminal 11 can have one or more first load terminal contact pads (in Fig. 9 not illustrated, compare reference number 117 in Fig. 11), which is / are configured to be contacted by load current transmission means, e.g., by one or more bond wires. In contrast, the one or more field electrodes 141 may be buried within the power semiconductor device 1, e.g., they may be contained in a respective trench 14 extending into the semiconductor body 10, as explained above. Like the control electrodes 131, the field electrodes 141 may also be interconnected by contact runners. For example, the contact runners are in Fig. Figure 9 illustrates this by means of the vertical lines connecting the field electrodes 141. The resistance of these contact runners can be comparatively low or even negligible.

[0063] The first path 15 can include an ohmic resistance 143 and can have a resistance R FP,intexhibit. For example, the ohmic resistance 143 is a resistance that has been "explicitly" arranged in the first path 15 to provide a specific resistance value between the first load terminal 11 (or another terminal whose electrical potential is to be supplied to the field electrodes 141) and the field electrodes 141, e.g., by means of a designated area filled with, for example, a polydoped semiconductor material, and / or by means of a discrete resistor device. Accordingly, the resistance 143, if present, may be geometrically identifiable. In another embodiment, the resistance 143 is not provided. As explained in more detail below, the resistance 143, or the terminal, e.g., the first load terminal 11, if the resistance 143 is not provided, may, according to one embodiment, be electrically connected to the field electrodes 141 by one or more contact runners.As explained above, for example, the contact runners are in . Fig. 9 illustrated by the vertical lines connecting the field electrodes 141. The resistance of these contact runners can be comparatively low or even negligible. In one embodiment, the first path 15 is monolithically integrated with the power semiconductor device 1, for example by means of a polysemier material insulated from the semiconductor body 10 by means of an insulator, e.g. an oxide, and is located, e.g., above the surface 10-1 (compare Fig. 11) of the semiconductor body 10 and / or within a trench extending into the semiconductor body 10. This resistor R FP,intThe second path 16 can be an internal resistance acting between the first load terminal 11 (or another terminal, e.g., the control terminal 13) on one side and the field electrodes 141 on the other. In one embodiment, this internal resistance R FP,int of the first path 15 to the ohmic field electrode resistance R FP For example, the distributed resistance of the field electrode R FP,dist by that section of the field electrode 141 which is arranged in the trench 14, and by the contact runner. In contrast, the first path 15, which represents the internal resistance R FP,int exhibits, which is represented, for example, at least also by the resistor 143, which is optionally provided, and according to one embodiment may be arranged outside the trench 14.

[0064] Accordingly, the one or more field electrodes 141, which may be buried in a respective trench 14, can contribute significantly to the distributed resistance R FP,dist contribute, which may be an internal ohmic resistance. The one or more field electrodes 141 can be connected via the first path 15, which has an internal resistance R. FP,int exhibits, electrically connected to the first load terminal 11. Accordingly, equation (2) with the definitions given above can apply according to one or more embodiments: RFP=RFP,dist+RFP,int

[0065] According to equation (2), the ohmic field electrode resistance R FP equal to the sum of the internal resistance R FP,int of the first path 15 and the distributed resistance of the field electrode(s) R FP,dist .

[0066] According to one or more embodiments, the feature according to which the ohmic resistance R FPThe resistance of the field electrode 141 is greater than the ohmic resistance R G the control electrode 131 is satisfied if the following equation (3) applies to the semiconductor device 1: RFP>RG,with RFP=RFP,dist+RFP,int and with RG=RG,dist.

[0067] This shows that there are many ways to implement the power semiconductor device 1 such that the ohmic resistance R FP The resistance of the field electrode 141 is greater than the ohmic resistance R G the control electrode 131, some of which has already been explained above and some of which will be explained in more detail below. First, the ohmic resistance R can be determined. FP the field electrode 141 (R FP,dist + R FP,int) even greater than the sum of the internal distributed resistance R FP,dist the control electrode 131 and its internal resistance R G,intbe such that equation (4) holds. Equation (4) also satisfies the condition as defined by equation (3). RFP=RFP,dist+RFP,int>RG,dist+RG,int.

[0068] For example, the first path 15 may have a meandering structure and / or a locally reduced cross-sectional area, so that a sufficiently high internal resistance R FP,int is provided.

[0069] According to the in Fig. 11 In the schematically illustrated embodiment, one or more of the contact runners 169, 159 mentioned above can be provided above a surface 10-1 of the semiconductor body 10. In the illustrated example, the resistors 133 and 143 mentioned above are not provided. The parts below the surface 10-1 are illustrated in a vertical cross-section along the ZY plane, e.g., along an extension of an exemplary strip trench (including the control electrode 131 and the field electrode 141) in the second lateral direction Y. For example, a first contact runner 159 is electrically connected to a first load terminal contact pad 117, and one or more contact runners 169 are electrically connected to a control terminal contact pad 137. For example, one or more contact runners 169, 159 can be formed by a respective metal conductor, such a metal conductor having an insignificant, i.e.,exhibits a negligible ohmic resistance. On the other hand, the first contact runner 159 can be electrically connected to the field electrode 141, e.g. by means of a first path section 152, and one or more second contact runners 169 can be electrically connected to the control electrode 131, e.g. by means of a second path section 162.

[0070] In one embodiment, the first contact runner 159 and the first path segment 151 form at least a part of the first path 15. Furthermore, one or more second contact runners 169 and the second path segments 162 can form at least a part of the second path 16. Furthermore, the ohmic resistance of the first contact runners 159 can be added to the distributed resistance R. FP,dist the field electrodes 141 contribute and the ohmic resistance of the second contact runner 169 can contribute to the distributed resistance R G,distthe control electrodes 131 contribute. For example, the first and / or second path sections 152, 162 can be implemented by a respective contact plug.

[0071] According to one embodiment, the number of first electrical contacts 151, which are made between the first path sections 152 and the first contact runner(s) 159, is lower compared to the number of second electrical contacts 161, which are made between the second path sections 162 and the one or more second contact runners 169. For example, the first electrical contacts 151 are made in a transition region 1-12 between the active region 1-1 and the inactive border region 1-2, and the second electrical contacts 161 are made in the active region 1-1, as shown in Fig. Figure 11 is illustrated by way of example. In another embodiment, the second electrical contacts 161 can also be additionally or alternatively made in such a transition region 1-12, e.g., between active regions. The first contacts 151 can also be made within the active region 1-1. Furthermore, if the control electrode 131 has a strip configuration, it can be electrically connected at some positions along the second lateral direction Y by respective second path sections 162, which are connected in parallel with each other, to one or more second contact runners 169.

[0072] For example, the distributed resistance R FP,dist the field electrode 141 is essentially proportional to a lateral distance between two first contacts 151 (compare Fig. 12) and the distributed resistance R G,distThe resistance of the control electrode 131 is essentially proportional to the lateral distance between two second contacts 161. For example, in one embodiment, the control electrode 131 and the field electrode 141 can have the same length-related ohmic resistances, whereby equation (3) or equation (4) can be satisfied at least also due to a non-contacted region (i.e., the region between two adjacent first contacts 151) of the field electrode 141, which has a larger lateral extent compared to a non-contacted region (i.e., the region between two adjacent contacts 161) of the control electrode 131. This optional aspect is also shown schematically in Fig. 12 illustrates this, and reference is now made to it.

[0073] According to the in Fig. In the schematically illustrated embodiment 12, each of the control electrodes 131 and the field electrodes 141 can have a strip configuration and can accordingly traverse at least a substantial part of the active area 1-1 along the second lateral direction Y. As illustrated, more than one field electrode 141, e.g., five field electrodes 141, can be arranged between two control electrodes 131 that are laterally adjacent to one another along the first lateral direction X. For example, each of the control electrodes 131 is electrically connected to the second contact runners 169 by means of a respective second path section 162, which establishes the second electrical contacts 161, e.g., at both lateral ends of a respective control electrode 131.In contrast, only a subset of the multiple field electrodes 141 arranged between two control electrodes 131 are electrically connected to the first contact runners 159. In the schematically illustrated example, two of the five field electrodes 141 are electrically connected to the first contact runners 159. For example, the remaining field electrodes 141 can be electrically connected to the subset of field electrodes 141 by means of first lateral sections 144. For example, the field electrodes 141 connected to each other by means of the lateral sections 144 can have a total length of at least 0.5 mm, at least 1 mm, or even more than 2 mm. Accordingly, in one embodiment, no first electrical contact 151 is provided along such a long lateral length of the connected field electrodes 141. Furthermore, the first electrical contacts 151 can be, as in . Fig. Figure 11 illustrates that the first electrical contacts 151 are made in the transition region 1-12. Additionally or alternatively, the first electrical contacts 151 can be made in the inactive border region 1-2. In other embodiments, the first electrical contacts 151 can be made in the active region 1-1, either additionally or alternatively. As shown in Fig. As illustrated in Figure 12, the first contact runner 151 can be laterally displaced relative to the second contact runner 169.

[0074] Some further embodiments of the semiconductor device 1 are disclosed below. In each of these embodiments, the ohmic resistance R can be FP the resistance of the field electrode(s) is greater than the ohmic resistance R Gthe control electrode(s) 131, wherein such a difference in ohmic resistance can be achieved in one or more ways as explained above. In at least some of the following embodiments, the distance D between the field electrode 141 and the first transition 1008 is at least 70% of the total extent TED of the drift volume 100 in the direction of expansion Z, as with reference to the example from Fig. 1 explained. In other embodiments, a first thickness TX of the field insulator 142 along a first lateral direction X and / or a second thickness TZ of the field insulator 142 along the extension direction Z is less than the blocking voltage of the semiconductor device multiplied by a factor of 2 nm / V, as explained with reference to the example from Fig. 2 was explained. In further embodiments as follows, each of the aforementioned features with regard to the distance D and the thicknesses TX and / or TY can be implemented.

[0075] According to the in Fig. In the schematically and exemplarily illustrated embodiment 13, the field electrode 141 and the control electrode 131, which may be arranged in separate trenches 14, 17, can have a common extent region CER in the extent direction Z in a vertical cross-section of the active region 1-1 of the power semiconductor device 1. For example, the source region 101, the channel region 102, and the drift volume 100, which includes the drift region 104, can also have at least a portion of this common extent region CER. For example, the common extent region CER is at least 200 nm, at least 500 nm, or at least 1 µm.

[0076] As illustrated in the example, more than one field electrode 141 can be arranged between two adjacent control electrodes 131. For example, three field electrodes 141 are arranged between the two adjacent control electrodes 131. Furthermore, each of the field electrodes 141 and the control electrodes 131 can have a strip configuration. The field electrodes 141 can extend further along the direction of extension Z relative to the control electrodes 131. For example, the field electrodes 141 are arranged in the trenches 14, and the control electrodes 131 are arranged in other trenches 17. Even if Fig. Figure 13 depicts the trenches 17 as containing only the control electrodes 131. It is understood that, according to another embodiment, the trenches 17 containing the control electrodes 131 may also contain a field electrode 141, which may, for example, be located below the control electrode 131. The trenches 14 and 17 may be adjacent to one another along the first lateral direction X and spatially separated from each other by a respective mesa zone 18. For example, each of the trenches 14 and 17 exhibits the same overall extent along the direction of expansion Z and was produced in one or more separate processing steps.

[0077] Now, with reference to the in Fig. In the schematically and exemplarily illustrated embodiment, the trench 14 can contain each of the control electrode 131 and the field electrode 141. For example, the field electrode 141 is arranged below the control electrode 131. The semiconductor device 1 can comprise several such trenches 14 arranged laterally adjacent to one another along the first lateral direction X. The mesa zones 18 can each have a width WM along the first lateral direction X. For example, the distance D between each field electrode 141 and the first junction 1008 is the mesa width WM multiplied by a factor greater than 2. For example, the mesa width WM lies within the range of 500 nm to 5 µm, within the range of 200 nm to 10 µm, or within the range of 10 nm to 20 µm.

[0078] As can be seen from the schematic representation in Fig. As can be seen from Figure 14, the mesa width WM can also be identical to the width of the section of the channel region 102 contained within the mesa 18. For example, the width of the trench 14 containing the field electrode 141, i.e., the total extent of the trench 14 in the first lateral direction X, can be adjusted with respect to the mesa width WM. For example, the mesa width WM divided by the width of the trench 14 is less than 10, less than 5, or even less than 1.0. For example, the trench 14 can even be wider than the mesa 18, e.g., wider than the channel region 102 contained within it.

[0079] According to the in Fig. In the schematically illustrated embodiment 15, the drift volume 100 can have a superjunction structure formed at least by the drift region 104 with dopants of the first conductivity type and an adjacent compensation region 105 with dopants of a second conductivity type. Generally speaking, a person skilled in the art is familiar with the principles of a superjunction structure (also referred to as a "compensation structure"), and this common understanding of the term is not deviated from within the present description.

[0080] The compensation area 105 can include dopants of the same conductivity type as the channel area 102, e.g. p-type dopants, and the compensation area 105 and the channel area 102 can form a contiguous semiconductor region doped with dopants of the second conductivity type.

[0081] For example, each of the trenches comprises 14 according to the schematic in Fig. Figure 15 illustrates both the control electrode 131 and the field electrode 141. Furthermore, according to one embodiment, the trenches 14 extend into the drift area 104, but not into the compensation area 105.

[0082] According to another in Fig. In the schematically illustrated embodiment shown in Figure 16, the field electrode 141 and the control electrode 131 can be arranged in separate trenches 14, 17, wherein the trench 14 encompassing the field electrode 141 can extend into the compensation area 105. For example, the compensation area 105 and the field electrode 141 can have a common extent along the direction of extension Z, as shown in Figure 16. Fig. Figure 16 illustrates this. In contrast, the trench 17, which contains the control electrode 131, does not extend into the compensation area 105, but into the drift area 104.

[0083] Now, with reference to Fig. 17. One, more, or all of the trenches 14 containing the field electrode 141 may extend into the compensation area 105. Furthermore, the field electrode 141 contained therein may be electrically connected to the (in Fig. (17 not illustrated) control port 13. Furthermore, the compensation area 105 can have a locally increased dopant concentration in an area 1055 adjacent to a trench bottom 146 of the trench 14. For example, the area 1055 is in contact with the trench bottom 146 and comprises only a fraction of the total cross-sectional area of ​​the compensation area 105. For example, the dopant concentration in the area 1055 is at least twice as high as the dopant concentration in the remaining part of the compensation area 105. This factor can even be greater than two, e.g., greater than five, greater than 10, greater than 100. In one embodiment, the area 1055 can be configured to reduce the risk of so-called hot charge carrier injection.

[0084] Regarding the embodiment according to Fig. 18 More than one trench 14 can extend into a given compensation area 105. For example, at least two trenches 14 extend into a compensation area 105. Furthermore, some of the field electrodes 141 can be electrically connected to the first load terminal 11, while other field electrodes 141 can instead be connected to the control terminal 13. If they are connected to the control terminal 13, the trenches 14 can be laterally flanked by a section of the source area 101, as shown in Fig. Figure 18 is schematically illustrated. For example, the field electrode 141 can also be configured to control part of the load current in the channel region 102. For this purpose, the field electrode 141 can be configured to induce an inversion channel in the channel region 102.

[0085] With respect to all embodiments described above, the source region 101 can comprise dopants of the first conductivity type. Furthermore, the source region 101 can be electrically connected to the first load terminal 11. The channel region 102 can comprise dopants of the second conductivity type complementary to the first conductivity type. The channel region 102 can also be electrically connected to the first load terminal 11 and can isolate the source region 101 from the drift volume 100. The drift volume 100 can comprise a drift region 104, which may contain dopants of the first conductivity type, for example, a dopant concentration that is significantly lower than the dopant concentration of the source region 101. A transition between the channel region 102 and the drift volume 100 can form a pn interface 1002.

[0086] The control electrode 131 can be operatively coupled to the channel region 102 and can be configured to induce an inversion channel in the channel region 102, thus enabling a load current to flow in the semiconductor body 10. For example, the control electrode 131 is arranged in a trench and an insulator contained in the trench 132 can be in contact with the source region 101 and the channel region 102 in the drift volume 100.

[0087] As already mentioned in reference to Fig. As explained in detail above, the semiconductor zone 108 can be electrically coupled to the second load terminal 12 and can couple the drift volume 100 to the second load terminal 12. For example, the semiconductor zone 108 is arranged between the drift volume 100 and the second load terminal 12. For example, at least one section of the semiconductor zone 108 exhibits a dopant concentration that is at least 10 times the dopant concentration of the drift volume 100. The factor can even be higher than 10; for example, the factor can be greater than 100 or greater than 1000. Depending on the configuration of the power semiconductor device 1, the semiconductor zone 108 can comprise a drain region and / or a p-doped emitter (collector) region, which is, for example, arranged in electrical contact with the second load terminal 12. To provide reverse current capability, semiconductor zone 108 can also include heavily doped regions, e.g. n +The semiconductor zone 108 includes regions, also referred to as "n-short circuits," which may be electrically connected to the second load terminal 12. Furthermore, the semiconductor zone 108 may also include a field-stop layer or a buffer layer. These exemplary and optional components of the semiconductor zone 108 are not illustrated in the drawings.

[0088] Furthermore, the control electrode 131 can be electrically isolated from the field electrode 141. For example, the control electrode 131 is electrically connected to the control terminal 13, as explained above. The field electrode 141 can, for example, be electrically connected to the first load terminal 11. In other embodiments, the field electrode 141 can be electrically connected to a different electrical potential. For example, the field electrode 141 is not electrically isolated from the control electrode 131, but is also electrically connected to the control terminal 13.

[0089] Furthermore, at least for some of the trenches 14 containing the field electrode 141, no source regions 102 adjacent to the trenches 14 are provided, thus ensuring strong robustness, whereas in other trenches 14 containing the field electrode 141, a source region 102 is provided, so that a precise capacitance value is set according to some embodiments. For example, according to the embodiments from Fig. 1, Fig. 2, Fig. 13, Fig. 15, and Fig. 16 No source areas adjacent to the trenches 14 were provided. According to the embodiments from Fig. 17 and Fig. 18 the source areas 102 adjacent to at least some of the ditches 14 are provided.

[0090] According to one embodiment, the overall extent of the field electrode 141 can be adjusted along the direction of expansion Z, so that, for example, the capacitance between the control electrode 131 and the second load terminal 12, e.g., the capacitance C, can be adjusted. GD , is controlled and / or avalanche effects are kept away from the control electrode 131. For example, increasing the overall extent of the field electrode 141 C GD reduce and can help keep avalanche effects away from the trenches 17.

[0091] These, for example, according to one or more of the in Fig. In the embodiments illustrated in Figures 1, 2, 6, 7, and 15 to 18, the power semiconductor device 1 described can be a MOSFET, e.g. an SJ MOSFET (SJ: Superjunction).

[0092] These, for example, according to one or more of the in Fig. 1, Fig. 2, Fig. 6, Fig. 7 and Fig.The power semiconductor device 1 described in the 14 illustrated embodiments can also be an IGBT, e.g. an RC-IGBT (RC: Reverse Conducting).

[0093] The above described embodiments applicable to power semiconductor device processing methods. For example, these semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, such as regions 10, 100, 101, 102, 104, 105, and 108 from exemplary embodiments, can be a monocrystalline Si region or layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0094] It is understood, however, that the semiconductor body 10 and components, e.g., the regions 10, 100, 101, 102, 104, 105 and 108, may be made of any semiconductor material suitable for the manufacture of a semiconductor device.Examples of such materials include elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGalnN), or indium gallium arsenide phosphide (InGaAsP); or binary or ternary II-VI semiconductor materials, such as cadmium telluride (CdTe) and mercury cadmium telluride. (HgCdTe), to name a few. The semiconductor materials mentioned above are also referred to as "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed.Examples of heterojunction semiconductor materials include, among others, aluminum gallium nitride (AlGaN)-aluminium gallium indium nitride (AlGalnN), indium gallium nitride (InGaN)-aluminium gallium indium nitride (AlGalnN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminium gallium nitride (AlGaN), silicon-silicon carbide (SixC. 1-x ) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently the most commonly used.

[0095] Spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, are used for the sake of simplicity to explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the respective device in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, areas, sections, etc., and are not intended to be restrictive. The same terms refer to the same elements throughout the description.

Claims

[1] Power semiconductor device (1) comprising the following: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) and a second load terminal (12) of the power semiconductor device (1); - a source region (101), a channel region (102) and a drift volume (100), each contained in the semiconductor body (10), wherein the source region (101) is electrically connected to the first load terminal (11) and wherein the channel region (102) isolates the source region (101) from the drift volume (100); - a semiconductor zone (108) contained in the semiconductor body (10) which couples the drift volume (100) to the second load terminal (12), whereby a first transition (1008) is established between the semiconductor zone (108) and the drift volume (100); - a control electrode (131) which is insulated from the semiconductor body (10) and the load terminals (11, 12) and is configured to control a path of the load current in the channel area (102); - a trench (14) extending along an expansion direction (Z) into the drift volume (100) and including a field electrode (141), wherein: - in a plane parallel to the direction of expansion (Z) the cross-sectional area of ​​the field electrode (141) is smaller than the cross-sectional area of ​​the control electrode (131); and - the drift volume (100) contains a superjunction structure formed by at least one drift region (104) with dopants of a first conductivity type and by an adjacent compensation region (105) with dopants of a second conductivity type; wherein the power semiconductor device (1) further comprises - a first path (15) that electrically connects the field electrode (141) to either the first load terminal (11) or a control terminal (13) of the power semiconductor device (1); and - a second path (16) that connects the control electrode (131) to the control terminal (13). [2] Power semiconductor device (1) according to claim 1, wherein - an ohmic resistance (R) FP ) of the field electrode (141) greater than an ohmic resistance (R) G ) the control electrode (131) is; and - a distance (D) between the field electrode (141) and the first transition (1008) is at least 70% of the total extent (TED) of the drift volume (100) in the direction of expansion (Z). [3] Power semiconductor device (1) according to claim 1 or 2, wherein: - the ohmic field electrode resistance (R FP ) equal to the sum of an internal resistance (R FP,int) of the first path (15) and a distributed resistance of the field electrode (R FP,dist ) is; and - the ohmic control electrode resistance (R G ) only a distributed resistance (R G,dist ) of the control electrode (131) and not an internal resistance (R G,int ) includes, which is represented by an ohmic resistance (133) provided in the second path (16). [4] Power semiconductor device (1) according to claim 3, wherein: - the distributed resistance of the field electrode (R FP , dist ) is represented at least by a section of the field electrode (141) which is arranged in the trench (14); - and the distributed resistance of the control electrode (R G,dist ) is represented by at least one section of the control electrode (131) which controls the path of the load current. [5] Power semiconductor device (1) according to any one of the preceding claims 2 to 4, wherein the ohmic field electrode resistance (R) FP ) is configured to dampen any transient response. [6] Power semiconductor device (1) according to one of the preceding claims, wherein the control electrode (131) is made of a first material and wherein the field electrode (141) is made of a second material, wherein the second material has an electrical conductivity that is lower than the electrical conductivity of the first material. [7] Power semiconductor device (1) according to any one of the preceding claims 2 to 6, wherein the ohmic field electrode resistance (R) FP ) is at least 1 Ω. [8] Power semiconductor device (1) according to any of the preceding claims, comprising: - an active area (1-1) with several cells (19), each cell (19) comprising a section of the source area (101), a section of the channel area (102) and a section of the drift volume (100); - several of the field electrodes (141) and several of the control electrodes (131), each arranged in the active region (1-1), wherein the ohmic resistance (R) FP ) of the several field electrodes (141) at least 110% of the ohmic resistance (R G ) of the multiple control electrodes (131). [9] Power semiconductor device (1) according to any of the preceding claims, comprising: - an active area (1-1) with several cells (19), each cell (19) comprising a section of the source area (101), a section of the channel area (102) and a section of the drift volume (100); - several of the field electrodes (141) and several of the control electrodes (131), each arranged in the active region (1-1), wherein only a subset of the several of the field electrodes (141) is electrically connected to the first load terminal (11) via a respective first path (15), wherein the remaining field electrodes (141) are electrically connected to each other and to the subset of field electrodes (141). [10] Power semiconductor device (1) according to claim 9, which further comprises a non-active border region (1-2), wherein the non-active border region (1-2) surrounds the active region (1-1), wherein an electrical connection between the field electrodes (141) is established only in the non-active region (1-2) and / or a transition region (1-12) between the active region (1-1) and the non-active region (1-2). [11] Power semiconductor device (1) according to one of the preceding claims, wherein the trench (14) includes each of the control electrode (131) and the field electrode (141). [12] Power semiconductor device (1) according to any of the preceding claims, wherein - at least one total extent (TED) of the drift volume (100) along an extent direction (Z) defines a blocking voltage of the semiconductor device (1); - the field electrode (141) is insulated from the drift volume (100) by a field insulator (142); - a first thickness (TX) of the field insulator (142) along a first lateral direction (X) and / or a second thickness (TZ) of the field insulator (142) along the direction of expansion (Z) is less than the blocking voltage multiplied by a factor of 2 nm / V. [13] Power semiconductor device (1) according to claim 11 or 12, further comprising: - several trenches (14) each containing a control electrode (131) and a field electrode (141), wherein the trenches (14) are adjacent to each other along a first lateral direction (X) and spatially separated from each other by a respective mesa zone (18) having a width (WM) along the first lateral direction (X), and wherein a distance (D) between each field electrode (141) and the first transition (1008) is the mesa width (WM) multiplied by a factor of at least 2. [14] Power semiconductor device (1) according to one of the preceding claims, wherein the trench (14) or trenches (14) extend into the compensation area (105). [15] Power semiconductor device (1) according to claim 14, wherein the compensation area (105) has a locally increased doping concentration in a region (1055) adjacent to a trench bottom (146) of the respective trench (14). [16] Power semiconductor device (1) according to one of the preceding claims, wherein the channel region (102) and the compensation region (105) form a contiguous region doped with dopants of the second conductivity type. [17] Power semiconductor device (1) according to any of the preceding claims, wherein the power semiconductor device (1) is a MOSFET. [18] Power semiconductor device (1) according to one of the preceding claims, wherein the field electrode (141) and the control electrode (131) have a common extension area (CER) in a vertical cross-section of an active region (1-1) of the power semiconductor device (1) in the extension direction (Z). [19] Power semiconductor device (1) according to any of the preceding claims, wherein: - the source area (101) contains dopants of the first conductivity type; - the canal area (102) contains doping materials of the second conductivity type; - both the source area (101) and the canal area (102) are electrically connected to the first load connection (11); and - a transition from the channel area (102) to the drift volume (100) forms a pn boundary layer (1002) configured to block a blocking voltage applied between the first load terminal (11) and the second load terminal (12). [20] Power semiconductor device (1) according to one of the preceding claims, wherein the power semiconductor device (1) is configured for a blocking voltage of at least 300 V. [21] Switching power device (3) configured to receive an input power signal that includes an input voltage (U IN ) and / or an input current (I IN ) includes, where: - the switching power device (3) comprises a circuit arrangement (31) including at least one power semiconductor device (1) according to one of the preceding claims; - the circuit arrangement (31) is configured to convert the input power signal into an output power signal that provides an output voltage (U OUT ) and / or an output current (I OUT ) includes, where the output power signal is different from the input power signal; and - the switching power device (3) is configured to deliver the output power signal to an electrical load (4).

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