Voltage converter for power management

Abstract

Voltage converter (10, 10a, 20, 600, 730) which has the following features: a converter circuit (60, 100, 100a, 610, 732) comprising an inductor connected to a switching node, a first switching device (61, 120, 611) connected between the switching node and a common voltage, and a second switching device (63, 130, 612) connected between the switching node and an output node, wherein the first switching device (61, 120, 611) is configured to charge an input power supply voltage into the inductor and is configured to discharge the inductor in response to a driver control signal; and a switching control circuit (160, 515, 625, 731) configured to generate the driver control signal by performing pulse width modulation (PWM) and pulse frequency modulation (PFM) based on a first sample signal, a second sample signal, and a feedback voltage, wherein the first sample signal and the second sample signal are based on a sampled current flowing through the first switching device (61, 120, 611), and wherein the feedback voltage is obtained by dividing an output voltage at the output node. wherein the switching control circuit (160, 515, 625, 731) is configured to adjust a charging time of the inductor on a time basis based on at least the input voltage when the switching control circuit (160, 515, 625, 731) performs the PFM, wherein the switching control circuit (160, 515, 625, 731) has the following: an on-time controller (300, 530, 640) configured to generate an on-time control pulse that adjusts the charging time of the inductor based on the input power supply voltage and a reference voltage; a pulse generation circuit (200, 525, 630) configured to generate a first pulse signal by performing PWM, and configured to generate a second pulse signal by performing PFM based on the reference voltage, the first sample signal, the second sample signal, the feedback voltage and the on-time control pulse, configured to generate a mode signal indicating a difference between the reference voltage and the feedback voltage, wherein the first sample signal indicates a level of the sampled current, and the second sample signal indicates an essentially zero level of the sampled current; a mode controller (400, 540, 650) configured to select one of the first pulse signals and the second pulse signal as an output pulse signal according to the mode signal and an operating mode based on the on-time control pulse; and a driver controller (470, 550, 660) which is configured to generate the driver control signal based on the output pulse signal, wherein the mode controller (400, 540, 650) is configured to select one of the first pulse signal and the second pulse signal as the output pulse signal based on a comparison of a first on-time and a second on-time, and where the first on-time corresponds to a first activation interval of the first pulse signal, and the second on-time corresponds to a second activation interval of the second pulse signal.

Description

TECHNICAL AREA

[0001] Exemplary embodiments generally refer to power supply devices and more specifically to voltage converters and power management devices that incorporate the same. DISCUSSION OF THE STATE OF THE TECHNOLOGY

[0002] Power supply devices are generally used to provide voltage for the operation of electronic devices. One type of power supply device is a voltage converter, such as a DC-DC converter. DC-DC converters are used in various types of electronic devices to efficiently provide a stable power supply voltage according to an output load.

[0003] US 2015 / 0091544A1 discloses: A control circuit in a PFM / PWM boost controller includes a timed PFM output control circuit configured to receive an initial control signal for controlling a main circuit breaker, a zero-crossing signal indicating that an inductor current has reached zero, and a timer reference signal indicating a timer threshold duration. The timed PFM output control circuit evaluates an inductor current idle time based on the initial control signal and the zero-crossing signal, where the idle time is the duration during which the inductor current is at zero.The time-controlled PFM output control circuit activates the PFM output signal in response to the idle time being equal to or less than the timer threshold duration, and the boost controller switches from PFM mode to PWM mode in response to the activation of the PFM output signal.

[0004] DE 11 2009 000 505 T5 discloses: DC-DC converter circuit, comprising: a circuit arrangement for generating a PWM waveform signal at a phase node of the DC-DC converter in response to an input voltage and a monitored output voltage, wherein the circuit arrangement further comprises a high-voltage switching transistor connected between the input voltage node and the phase node and a low-voltage switching transistor connected between the phase node and ground; an output filter connected to the circuit arrangement for generating the PWM waveform signal, wherein the output filter includes an inductor having a first side connected to the phase node and a second side connected to the output voltage node;and a detection circuit arrangement for detecting zero-current crossings in the inductor in response to a voltage at the high-voltage-side switching transistor and a voltage at the low-voltage-side switching transistor. SUMMARY

[0005] The present inventive concept provides for a voltage converter set out in the accompanying claims, which is capable of increasing power transmission efficiency and performing stable mode switching, as well as a power management device set out in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become obvious to those skilled in the art by a detailed description of exemplary embodiments of the present inventive concept with reference to the accompanying drawings. Fig. Figure 1 is a block diagram illustrating a voltage converter according to an exemplary embodiment. Fig. Figure 2 is a block diagram illustrating a voltage converter according to an exemplary embodiment. Fig. 3A and Fig. Figure 3B illustrates one operation of the converter circuit in the voltage converter of the Fig. 1 or the Fig. 2. Fig. 4 is a block diagram showing the current sensing circuit in Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment. Fig. 5 is a block diagram showing the pulse generation circuit in Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment. Fig. Figure 6 is a timing diagram showing different signals in the first pulse generator in Fig. 5 illustrates. Fig. Figure 7 is a block diagram showing the on-time controller in Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment. Fig. Figure 8 is a circuit diagram showing the on-time controller in Fig. 1 illustrated according to an exemplary embodiment. Fig. 9A is a time-lapse diagram showing the operation of the on-time controller of the Fig. 8 illustrates. Fig. 9B is a time-course diagram showing the operation of the second pulse generator in the pulse generation circuit of the Fig. 5 illustrates. Fig. 10 is a block diagram showing the mode controller in the voltage converter of the Fig. 1 or the Fig. 2 illustrated according to an exemplary embodiment. Fig. Figure 11 illustrates that the voltage converter of the Fig. 1 or Fig. 2 adjusts an on-time in PFM mode. Fig. Figure 12 illustrates a mode change according to a latch in the voltage converter of the Fig. 1 or Fig. 2. Fig. Figure 13 illustrates a power transfer efficiency of the voltage converter of the Fig. 1 or Fig. 2. Fig. Figure 14 is a block diagram illustrating a voltage converter according to an exemplary embodiment. Fig. 15A and Fig. Figure 15B illustrates one operation of the converter circuit in the voltage converter of the Fig. 14. Fig. Figure 16 is a graph which shows the operation of the voltage converter of the Fig. 14 explained, and Fig. 17 is a graph which represents a section of the Fig. 16 enlarged. Fig. Figure 18 is a block diagram illustrating a voltage converter according to an exemplary embodiment. Fig. Figure 19 is a block diagram illustrating a power management device according to an exemplary embodiment. Fig. Figure 20 is a block diagram illustrating a power management system according to an exemplary embodiment. Fig. Figure 21 is a block diagram illustrating a power management system according to an exemplary embodiment. Fig. Figure 22 is a block diagram illustrating an electronic device which includes the voltage converter according to an exemplary embodiment. Fig. Figure 23 is a block diagram illustrating a mobile system that houses the power management device of the Fig. 19 according to an exemplary embodiment. Fig. 24 is a block diagram which represents a calculation system which is the power management device of the Fig. 19 according to an exemplary embodiment, illustrates. DETAILED DESCRIPTION

[0007] Exemplary embodiments of the present inventive concept provide a voltage converter with high transmission efficiency over a wide range of load currents, which performs stable mode switching by switching between modes, such as pulse-width modulation and pulse-frequency modulation, based on accurate measurements of the current flow through an energy storage device and / or a switching device during a time window. Embodiments include a switching-mode power supply with feedforward control, feedback, and current sampling, which can stably switch between power transmission operating modes (e.g., PWM, PFM, boost, buck, hybrid) based on pulse-on times and the current. The present inventive concept will be described in more detail with reference to the accompanying drawings, which show exemplary embodiments.However, the present inventive concept can be implemented in many different forms and should not be considered limited to the embodiments described herein.

[0008] Rather, these embodiments are provided so that this disclosure will be conscientious and complete and will fully convey to those skilled in the art the scope of the present inventive concept. The same reference numerals may refer to the same elements throughout this application.

[0009] It will be understood that, although the terms first / first / first, second / second / second, or the like may be used herein to describe different elements, these elements should not be considered limited by these terms. These terms are used to distinguish one element from another. For example, a first element might be called a second element, and similarly, a second element might be called a first element, without departing from the scope of the present revelation. If an element is called a third element, for example, a second element need not be present. When used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0010] It will be understood that when an element is referred to as "connected" or "coupled" with another element, it may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" with another element, no intervening elements are present. Other words used to describe the relationship between elements should be interpreted in the same way, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," and so on.

[0011] The terminology used herein is for the purpose of describing certain embodiments and is not intended to be limiting to the present disclosure. When used herein, the singular forms "one" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it shall be understood that the terms "indicates," "indicating," "comprises," and / or "including," when used herein, specify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more others.

[0012] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as generally understood by those skilled in the art within the field to which this disclosure relates. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an overly idealized or overly formal sense unless expressly defined herein.

[0013] Exemplary embodiments of the present inventive concept are described in detail below with reference to the accompanying drawings. Identical reference numerals may be assigned to identical elements, and details thereof may be omitted to avoid redundancy.

[0014] Fig. Figure 1 is a block diagram illustrating a voltage converter according to an exemplary embodiment.

[0015] Referring to Fig. Figure 1 comprises a voltage converter 10 of an exemplary embodiment, comprising a converter circuit 100 connected between an input node and an output node, a capacitor C1 connected between the output node and a common node, a feedback unit 40 connected between the output node and the common node, a reference voltage generator 70 generating a reference signal, a current sampling circuit 150 generating sampling signals, and a switching control circuit 160 receiving the reference and sampling signals. A load 50 is conveniently provided in Fig. Figure 1 illustrates that the voltage converter 10 does not necessarily have to have the load 50. The voltage converter 10 can be referred to as a switching mode power supply (SMPS) or a power converter.

[0016] The converter circuit 100 comprises an energy storage device, such as an inductor or coil L, a first switching device 120, a second switching device D, and a third switching device 110. The first switching device 120 can include an n-channel power switch connected between a switching node SN and a common voltage node, and the second switching device D can include a diode. The third switching device 110 can be connected between an input power supply voltage Vin node and the inductor L, and can transfer the input power supply voltage Vin to the inductor L in response to a boost control signal BSTEN provided externally. The second switching device D can be connected between switching node SN and an output node NO.

[0017] The smoothing capacitor C1 can be connected between the output node NO and the common voltage node. The feedback unit 40 is connected in parallel with capacitor C1 between the output node NO and the common voltage node and includes resistors R1 and R2, which are connected to a feedback node FN. This FN divides an output voltage Vout at the output node NO to provide a feedback voltage VFB. A load current ILOAD flows into the load 50 from the output node NO. The inductor L and capacitor C1 can act as a low-pass filter, removing ripple in the output voltage Vout. Alternatively, equivalent circuits can be substituted using primarily inductors and / or primarily capacitors as the energy storage devices.

[0018] The first switching device 120 charges the inductor L with the input power supply voltage Vin in response to a driver control signal GP with a first logic level and transmits the voltage charged into the inductor L to the output node NO in response to the driver control signal GP with a second logic level. The first switching device 120 has an n-channel power switch which has a drain coupled to switching node SN, a source coupled to the common voltage node, and a gate that receives the driver control signal GP.

[0019] The second switching device D may include a diode which essentially prevents current from flowing to the output node NO from the switching node SN.

[0020] The current sampling circuit 150 generates a first sampling signal CS, which indicates a non-zero peak or limit level of a sampled current ISEN flowing through the first switching device 120, and generates a second sampling signal ZCS, which indicates an essentially zero level of the sampled current ISEN based on the sampled current ISEN. The reference voltage generator 70 generates a reference voltage VREF.

[0021] As in the Fig. 1 and Fig. As shown in Figure 12, the switching control circuit 160 generates the driver control signal GP by performing pulse frequency modulation (PFM) and pulse width modulation (PWM) based on the feedback voltage VFB, the reference voltage VREF, the first sample signal CS, and the second sample signal ZCS. The switching control circuit 160 can adjust the charging time of the inductor L on a time basis based on at least the input power supply voltage Vin when the switching control circuit 160 performs the PFM. The switching control circuit 160 can adjust the activation interval of the driver control signal GP on a time basis based on at least the input power supply voltage Vin.

[0022] The reference voltage generator 70 generates the reference voltage VREF and provides the reference voltage VREF for the switching control circuit 160.

[0023] The switching control circuit 160 includes a pulse generation circuit 200, an on-time controller 300, a mode controller 400 and a driver controller 470.

[0024] The On-Time Controller 300 of the Fig. 1, Fig. 7 and Fig. 8 generates an on-time control pulse VON, which limits or adjusts the charging time of the inductor L based on the input power supply voltage Vin and the reference voltage VREF. The pulse generation circuit 200 of the Fig. 1 and Fig. 5 receives the VON signal and generates a first pulse signal PWMO by performing PWM, and / or generates a second pulse signal PFMO by performing PFM based on the reference voltage VREF, the first sample signal CS, the second sample signal ZCS, the feedback voltage VFB, and the on-time control pulse VON, and generates a mode signal MD based on a difference between the reference voltage VREF and the feedback voltage VFB. The on-time controller 300 can be activated in response to an external controller activation signal OTCEN. The on-time controller 300 can also receive a calibration code CCD.

[0025] The Mode Controller 400 selects either the first pulse signal PWMO or the second pulse signal PFM as an output pulse signal PLO according to an operating mode based on the mode signal MD and the on-time control pulse VON. Alternatively, the Mode Controller 400 selects either the first pulse signal PWMO or the second pulse signal PFMO as the output pulse signal PLO based on a comparison of a first on-time and a second on-time. The first on-time can represent a first activation interval of the first pulse signal PWMO, and the second on-time can represent a second activation interval of the second pulse signal PFMO. Alternatively, the first and second on-times can represent different activation intervals of the first pulse signal, or they can represent different activation intervals of the second pulse signal.

[0026] The driver controller 470 outputs the driver control signal GP based on the output pulse signal PLO. Accordingly, the switching control circuit 160 causes the voltage converter 10 to operate in a PWM mode, which can be more efficient for higher electrical loads if the load generally remains above a limit, and causes it to operate in a PFM mode, which can be more efficient for low electrical loads if the load generally remains below a limit.

[0027] Fig. Figure 2 is a block diagram illustrating a voltage converter according to an exemplary embodiment.

[0028] Referring to Fig. 2 is a voltage converter 10a similar to the voltage converter 10 of the Fig. 1, so that a duplicate description can be omitted. The voltage converter 10a comprises a converter circuit 100a, a capacitor or capacitance C1, a feedback unit 40, a reference voltage generator 70, a current sampling circuit 150 and a switching control circuit 160.

[0029] The converter circuit 100a comprises an inductor or coil L, a switching device 120, a second switching device 130, and a third switching device 110. The first switching device 120 can have an n-channel power switch connected between a switching node SN and a common voltage, and the second switching device 130 can have a p-channel power switch connected between the switching node SN and an output node NO. The third switching device 110 can be connected between an input power supply voltage Vin and the inductor L and can transfer the input power supply voltage Vin to the inductor L in response to a boost control signal BSTEN provided externally.The second switching device 130 can be a p-channel power switch which has a source which is coupled to the switching node SN, a drain which is coupled to the output node NO, and a gate which receives the driver control signal GP.

[0030] Accordingly, the voltage converter 10 of the Fig. 1 an asynchronous boost converter or step-up converter, and the voltage converter 10a of the Fig. 2 can be a synchronous boost converter. In either case, the switching control circuit 160 causes the voltage converter 10 or 10a to operate in a PFM mode, which is more efficient for lower current loads when the load current remains below a limit, and causes it to operate in a PWM mode, which is more efficient for higher current loads when the load current remains above a limit. In the synchronous configuration of the voltage converter 10a, the second switching device is a complementary transistor with a lower drain-to-source resistance to further reduce losses and improve overall converter efficiency, with the first and second transistors not being switched on at the same time.

[0031] Fig. 3A and Fig. Figure 3B illustrates one operation of the converter circuit in the voltage converter of the Fig. 1 or Fig. 2.

[0032] Referring to the Fig. 1, Fig. 2 and Fig. 3A, when the first switching device 120 is switched on in response to the driver control signal GP with a first logic level, the converter circuits 100 and 100a charge the input power supply voltage Vin into the inductor L by performing a current build-up operation. When the converter circuits 100 and 100a perform the current build-up operation, a first current path IPATH1 is formed in the converter circuits 100 and 100a. Additionally, when the converter circuits 100 and 100a perform the current build-up operation, an inductance current IL of the inductor L is essentially the same as the sampled current ISEN.

[0033] Referring to the Fig. 1, Fig. 2 and Fig. 3B, when the first switching device 120 is switched off and the second switching device 130 is switched on, in response to the driver control signal GP with a second logic level, the converter circuits 100 and 100a transfer the energy stored in the inductor L to the output node NO by performing a current transfer operation. When the converter circuits 100 and 100a perform the current transfer operation, a second current path IPATH2 is formed in the converter circuits 100 and 100a, and the load current ILOAD is provided for the load 50.

[0034] Fig. 4 is a block diagram showing the current sensing circuit in Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment.

[0035] Referring to Fig. Figure 4 of the current sensing circuit 150 comprises a current sensor 151 and a zero-current sensor 153. The current sensor 151 samples a non-zero peak or limit level of the sampled current ISEN to output the first sampling signal CS. The zero-current sensor 153 samples an essentially zero level of the sampled current ISEN to output the second sampling signal ZCS. The first sampling signal CS and the second sampling signal ZCS can be voltage signals that are essentially independent of each other, for example, due to different limit values.

[0036] Fig. 5 is a block diagram showing the pulse generation circuit in Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment.

[0037] Referring to Fig. 5 The pulse generation circuit 200 has a first pulse generator 210 and a second pulse generator 230.

[0038] The first pulse generator 210 generates the first pulse signal PWMO based on the reference voltage VREF, the feedback voltage VFB, the first sampling signal CS, and a clock signal CLK. The second pulse generator 230 generates the second pulse signal PFMO based on the reference voltage VREF, the feedback voltage VFB, the second sampling signal ZCS, and the on-time control signal VON.

[0039] The first pulse generator 210 comprises an error amplifier 211, a hysteresis comparator 213, and an RS flip-flop 215. The error amplifier 211 amplifies the difference between the differential voltage VREF and the feedback voltage VFB to output an error voltage VER. The hysteresis comparator 213 compares the first sampled signal CS and the error voltage VER to output a PWM signal PWMS, which indicates the difference between the first sampled signal CS and the error voltage VER. The RS flip-flop 215 has a setting terminal S, which receives a clock signal CSK with a predetermined frequency, a reset terminal R, which receives the PWM signal PWMS, and an output terminal Q, which provides the first pulse signal PWMO. Accordingly, the first pulse signal PWMO is set in response to a rising edge of the clock signal CLK and is reset in response to a rising edge of the PWM signal PWMS.

[0040] The second pulse generator 230 has a first hysteresis comparator 231, a second hysteresis comparator 233, a first OR gate 235, a second OR gate 237 and an RS flip-flop 239.

[0041] The first hysteresis comparator 231 compares the feedback voltage VFB and the reference voltage VREF to output a PFM signal PFMS, which corresponds to the difference between the feedback voltage VFB and the reference voltage VREF. The first hysteresis comparator 231 can have a variable hysteresis window. The second hysteresis comparator 233 compares the reference voltage VREF and the feedback voltage VFB to output the mode signal MD, which corresponds to the difference between the reference voltage VREF and the feedback voltage VFB. The first OR gate 235 performs an OR operation on the PFM signal PFMS and the second sample signal ZCS. The second OR gate 237 performs an OR operation on the mode signal MD and the on-time control pulse VON.The RS flip-flop 239 has a setting terminal S, which receives an output from the first OR gate 235, a reset terminal R, which receives an output from the second OR gate 237, and an output terminal Q, which provides the second pulse signal PFMO. Accordingly, the second pulse signal PFMO is set in response to a rising edge of the second sample signal ZCS or a rising edge of the PFM signal PFMS, and is reset in response to a rising edge of the mode signal MD or a rising edge of the on-time control pulse VON.

[0042] Fig. Figure 6 is a time-course diagram showing different signals in the first pulse generator of the Fig. 5 illustrates.

[0043] In Fig. 6 represents VREF' an electrical potential of the output voltage Vout in a case where the feedback voltage VFB is the same as the reference voltage VREF.

[0044] While the output voltage Vout is lower than VREF', which corresponds to the reference voltage VREF, specifically during time T1, the error voltage VER is at a low level. During time T1, the first pulse signal PWMO is also at a low level.

[0045] As a result, the output voltage Vout gradually decreases, and consequently, the feedback node FN decreases during time T1. When the output voltage Vout becomes equal to or less than VREF', the error voltage VER changes from a low level to a high level. Since the level of the first sample signal CS is lower than the level of the error voltage VER between times t1 and t2, the hysteresis comparator 213 outputs the PWM signal PWMS at a low level. Since the level of the first sample signal CS is higher than the level of the error voltage VER between times t2 and t3, the hysteresis comparator 213 outputs the PWM signal PWMS at a high level, and the clock signal CLK changes to a high level at time t3.Accordingly, the first pulse signal PWMO is set in response to a rising edge of the clock signal CLK at time t1, is reset in response to a rising edge of the PWM signal PWMS at time t2, and is set in response to a rising edge of the clock signal CLK at time t3.

[0046] Fig. Figure 7 is a block diagram showing the on-time controller in Fig. 1 or Fig. 2 shows an exemplary embodiment.

[0047] Fig. Figure 8 is a circuit diagram showing the on-time controller in Fig. 1 shows an exemplary embodiment.

[0048] Referring to the Fig. 7 and Fig. The on-time controller 300 comprises an activation signal generator 310, a current mirror circuit 330, and an on-time pulse generator 350. Additionally, the on-time controller 300 may also include a reference current generator 320. The reference current generator 320 can generate a reference current IBGR for the current mirror circuit 330.

[0049] The activation signal generator 310 generates a first activation signal EN and a second activation signal ENB based on control signals CLEN and OTCEN and a reference pulse signal PLON. The control signals CLEN and OTCEN can be supplied externally. The first activation signal EN and the second activation signal ENB can be complementary to each other. The current mirror circuit 330 generates a charging current ICH by mirroring the reference current IBGR based on the first activation signal EN. The on-time pulse generator 350 generates the on-time control pulse VON based on the first activation signal EN, the second activation signal ENB, the charging current ICH, the reference voltage VREF, and the input power supply voltage Vin.

[0050] The activation signal generator 310 comprises a first AND gate 311, a second AND gate 313, and an inverter 315. The first AND gate 311 performs an AND operation on the calibration activation signal CLEN and the reference pulse signal PLON. The second AND gate 313 performs an AND operation on an output of the first AND gate 311 and the controller activation signal OTCEN, ordering activation of the on-time controller to output the first activation signal EN. The inverter 315 inverts the first activation signal EN to output the second activation signal ENB.

[0051] The current mirror circuit 330 features n-channel metal oxide semiconductor (NMOS=n-Channel Metal-Oxide Semiconductor=n-Channel Metal-Oxide Semiconductor) transistors 331, 332 and 333 and p-channel metal oxide semiconductor (PMOS=p-Channel Metal-Oxide Semiconductor=p-Channel Metal-Oxide Semiconductor) transistors 334 and 335.

[0052] The NMOS transistor 331 has a drain that receives the reference current IBGR, a gate that receives the first activation signal EN, and a source that is coupled to node N1. The NMOS transistor 332 has a drain that is coupled to node N1, a gate that is coupled to node N1, and a source that is coupled to the common voltage. The NMOS transistor 333 has a drain that is coupled to node N2, a gate that is coupled to node N1, and a source that is coupled to the common voltage.

[0053] The PMOS transistor 334 has a source coupled to a power supply voltage VDD, a gate coupled to node N2, and a drain coupled to node N2. The PMOS transistor 335 has a source coupled to the power supply voltage VDD, a gate coupled to node N2, and a drain that provides the charging current ICH. The drain of the PMOS transistor 335 is coupled to the on-time pulse generator 350 at node N3.

[0054] The NMOS transistors 331, 332, and 333 can form a first current mirror, and the NMOS transistor 333 and the PMOS transistors 334 and 335 can form a second current mirror. Therefore, the charging current ICH provided at node N3 can be of the same magnitude or order of magnitude as the reference current ICH, or it can be larger than the reference current ICH, based on the parameters of the NMOS transistors 331, 332, and 333, and the PMOS transistors 334 and 335.

[0055] The on-time pulse generator 350 has a first switch 351, a capacitor 352, a second switch 353, a second capacitor 354, a comparator 355 and an RS flip-flop 356.

[0056] The first switch 351 is connected between node N3 and the common voltage, and the first switch 351 discharges voltage stored in the first and second capacitors 352 and 354, or reduces a current remaining in the current mirror circuit 330, in response to the second activation signal ENB. The first capacitor 352 is connected in parallel with the first switch 351 between node N3 and the common voltage, and the first capacitor 352 stores a voltage corresponding to the charging current ICH. The second switch 353 and the second capacitor 354 are connected in series between node N3 and the common voltage.A plurality of the second switch 353 and the second capacitor 354 can be connected between node N3 and the common voltage, the second capacitor 354 can store one of the input power supply voltage Vin and a voltage corresponding to the calibration code CCD, and the second switch 354 provides the voltage stored in the second capacitor 354 to node N3 in response to a switching control signal SCS provided from outside.

[0057] The comparator 355 is activated in response to the first activation signal EN, compares a ramp voltage VRMP at node N3 with the reference voltage VREF, and provides an output signal CMPO corresponding to the difference between the ramp voltage VRMP and the reference voltage VREF. Thus, the level of the ramp voltage VRMP increases according to the levels of the voltages stored in the first and second capacitors 352 and 354, and the output signal CMPO arrives at the reference voltage VREF more quickly as the level of the ramp voltage VRMP increases. Furthermore, since the level of the ramp voltage VRMP is at least related to the level of the input power supply voltage Vin, the rate at which the output signal CMPO arrives at the reference voltage VREF is also related to at least the level of the input power supply voltage Vin.

[0058] The RS flip-flop 356 has a setting terminal S, which receives the first activation signal EN, a reset terminal R, which receives the output CMPO of the comparator 355, and an output terminal Q, which provides the on-time control pulse VON. Thus, the on-time control pulse VON is set in response to a rising edge of the first activation signal EN and is reset in response to a rising edge of the output signal CMPO. Since the speed at which the output signal CMPO arrives at the reference voltage VREF is related to at least the level of the input power supply voltage Vin, the on-time, the activation interval of the on-time control pulse VON, is associated with the input power supply voltage Vin. Therefore, the on-time controller 300 can, in feedforward control, adjust the charging time of the inductor L based on the input power supply voltage Vin on a time basis.

[0059] Fig. 9A is a time-lapse diagram showing the operation of the On-Time Controller 300. Fig. 8 illustrates.

[0060] Referring to the Fig. 8 and Fig. 9, since the controller activation signal OTCEN and the calibration activation signal CLEN are activated between times t21 ~ t28, and the reference pulse signal PLON is activated between times t21 ~ t22, t24 ~ t25 and t27 ~ t28 respectively, the activation intervals of the first activation signal EN are the same as those of the reference pulse signal PLON.

[0061] Since the level of the ramp voltage VRMP is essentially the same as the level of the reference voltage VREF at times t23, t26, and t28, the output signal CMPO is activated for a short interval at each of these times. When the calibration code CCD is applied, the level of the ramp voltage VRMP gradually increases from times t21, t24, and t27. Therefore, the on-time control pulse VON is set or activated in response to a rising edge of the first activation signal EN and is reset or deactivated in response to a rising edge of the output signal CMPO.

[0062] Fig. 9B is a time-course diagram showing the operation of the second pulse generator 230 in the pulse generation circuit of the Fig. 5 illustrates.

[0063] Referring to the Fig. 5, Fig. 9A and Fig. 9B, the level of the feedback voltage VFB increases between times t31 ~ t34, t35 ~ t38, and t39 ~ t42, and the level of the feedback voltage VFB decreases between times t34 ~ t35, t38 ~ t39, and t42 ~ t43. Since the level of the inductance current IL is essentially zero at times t35 and t39, the second sampling signal ZCS is activated during short intervals between times t35 ~ t36 and between times t39 ~ t40. The PFM signal PFMS, which is the output of the first hysteresis comparator 231 of the Fig. 5 is activated between time points t31 ~ t34, t35 ~ t38 and t39 ~ t42, and the mode signal MD, which is the output of the second hysteresis comparator 233 of the Fig. 5 is activated between times t32 ~ t33, t36 ~ t37 and t40 ~ t41 based on a difference between the feedback voltage VFB and the differential voltage VREF.

[0064] The on-time control pulse VON is activated between times t34 ~ t35, t38 ~ t39, and t42 ~ t43. Therefore, the output S of the first OR gate 135 is activated between times t31 ~ t34, t35 ~ t38, and t39 ~ t42, and the output R of the second OR gate 237, 235 is activated between times t32 ~ t33, t34 ~ t35, t36 ~ t37, t38 ~ t39, t40 ~ t41, and t42 ~ t43. Therefore, the second pulse signal PFMO is activated in response to a rising edge of the output of the first OR gate 235 and is deactivated in response to a rising edge of the output of the second OR gate 237. This means that the second pulse signal PFMO is activated between time points t31 ~ t32, t35 ~ t36, and t39 ~ t40.

[0065] Fig. 10 is a block diagram showing the mode controller in the voltage converter of the Fig. 1 or Fig. 2 illustrated according to an exemplary embodiment.

[0066] Referring to Fig. 10 The mode controller 400 has a time comparator 410, a counter 420, a signal generator 430 and a selection circuit 440.

[0067] The time comparator 410 compares a first on-time, corresponding to the first activation interval of the first pulse signal PWMO, and a second on-time, corresponding to the second activation interval of the on-time control pulse VON, to output a time comparison signal TOUT. The time comparator 410 outputs the time comparison signal TOUT at a first logic level if the first on-time is less than the second on-time. When the time comparison signal TOUT has a first logic level, the counter 420 counts the time comparison signal TOUT and outputs a count output signal COUT. The counter 420 outputs the count output signal COUT at a first logic level if the time comparison signal TOUT has a first logic level consecutively for a reference number of times, such as during a short-term event.

[0068] Signal generator 430 generates a reset signal RST and a selection signal SS based on the count output signal COUT and the mode signal MD. Signal generator 430 provides the reset signal RST to the counter and the selection signal SS to the selection circuit 440. Signal generator 430 outputs the selection signal SS at a first logic level when the mode signal MD and the count output signal COUT both have a first logic level. Signal generator 430 outputs the reset signal RST to the counter 420 to reset the counter 420 to a logic level in response to the count output signal COUT.

[0069] The selection circuit 440 selects one of the first pulse signal PWMO and the second pulse signal PFMO as the output pulse signal PLO in response to the selection signal SS. The selection circuit 440 selects the second pulse signal PFMO as the output pulse signal PLO if the mode signal MD has a first logic level and the count output signal COUT has a first logic level.

[0070] Fig. Figure 11 illustrates that the voltage converter of the Fig. 1 or Fig. 2 adjusts an on-time in PFM mode.

[0071] Referring to Fig. 11 can the on-time controller 300 of the Fig. 1, Fig. 2, Fig. 7 or Fig. 8. Adaptively, the on-time of the driver control signal GP in PFM mode is adjusted according to the peak level IPEAK of the inductance current IL based on the input power supply voltage Vin. The on-time controller 300 adjusts the on-time of the driver control signal GP to an on-time TON1 when the peak level of the inductance current IL is high, and adjusts the on-time of the driver control signal GP to an on-time TON2 when the peak level of the inductance current IL is low.

[0072] According to an exemplary embodiment of the present inventive concept, the charging time for the inductance current is adjusted on a time basis using a feedforward control configuration.

[0073] Fig. Figure 12 illustrates a mode change according to a reduced load in the voltage converter of the Fig. 1 or Fig. 2.

[0074] Referring to Fig. 12 the voltage converter 10 of the Fig. 1 or Fig. 10a of the Fig. 2 operates in PWM mode during a first interval INT11 and a second interval INT12, and in PFM mode during a third interval INT13. During the first interval, the on-time of the driver control signal GP is greater than the on-time of the on-time control signal VON. During the second interval INT12, the on-time of the driver control signal GP is less than the on-time of the on-time control signal VON.

[0075] The counter 420 of the mode controller 400 of the Fig. Voltage converter 10 counts the number of times the on-time of the driver control signal GP is less than the on-time of the on-time control signal VON, and outputs the count signal COUT at a first logic level when the counted number of times reaches or exceeds the reference number of times. Fig. 1 or Fig. 10a of the Fig. 2 operates in a PFM mode, as during the third interval INT13, when the count output signal COUT has a first logic level and the mode signal MD has a first logic level.

[0076] Fig. Figure 13 illustrates a power transmission efficiency of the Fig. 1 and / or Fig. 2.

[0077] In Fig. 13. During interval INT21, the load current ILOAD supplied to load 50 is very small; during interval INT22, the load current ILOAD supplied to load 50 is small; and during interval INT23, the load current ILOAD supplied to load 50 is large. Additionally, reference 451 represents a case where the input power supply voltage Vin is boosted to the output voltage of 3.3 V without the full benefit of exemplary embodiments; reference 453 represents a case where the input power supply voltage Vin is boosted to the output voltage of 3.3 V while an exemplary embodiment is used; and reference 455 represents a case where the input power supply voltage Vin is boosted to the output voltage of 5.5 V while an exemplary embodiment is used.Additionally, reference numbers 456, 457 and 458 indicate mode changes from PFM mode to PWM mode in the voltage converter when the load current ILOAD increases.

[0078] Referring to Fig. 13 It is noted that a power transfer efficiency in both the PFM mode and the PWM mode in the voltage converter 10 of the Fig. 1 or Fig. 10a of the Fig. 2 is improved.

[0079] Fig. Figure 14 is a block diagram illustrating a voltage converter according to an exemplary embodiment.

[0080] Referring to Fig. A voltage converter 20 comprises a converter circuit 60, a capacitor C1, a feedback unit 40, a reference voltage generator 560, a current sampling circuit 510, and a switching control circuit 515. A load 50 is conveniently located in Fig. Figure 14 illustrates that the voltage converter 20 does not need to have the load 50. The voltage converter 20 can also be referred to as a switching mode power supply (SMPS) or a power converter.

[0081] The converter circuit 60 comprises a first switching device 61, a second switching device 63, and an inductor L. The inductor L is connected between the switching node SN and an output node NO. The first switching device 61 is connected between the input power supply voltage Vin and the switching node SN and charges the input power supply voltage Vin into the inductor L in response to a first driver control signal GP1. The second switching device 63 is connected between the switching node SN and the common voltage and discharges the inductor L in response to a second driver control signal GP2.

[0082] The first switching device 61 can comprise a PMOS transistor having a source coupled to the input power supply voltage Vin, a gate receiving the first driver control signal GP1, and a drain coupled to the switching node SN. The second switching device 63 can comprise an NMOS transistor having a drain coupled to the switching node SN, a gate receiving the second driver control signal GP2, and a source coupled to the common voltage. The first and second driver control signals GP1 and GP2 have the same logic level.

[0083] The smoothing capacitor C1 is connected between the output node NO and the common voltage. The feedback unit 40 is connected in parallel with capacitor C1 between the output node NO and the common voltage, has resistors R1 and R2 connected at a feedback node FN, and splits an output voltage Vout1 at the output node NO to provide a feedback voltage VFB1. A load current ILOAD flows into the load 50 from the output node NO. The inductor L and capacitor C1 act as a low-pass filter, removing ripples in the output voltage Vout1.

[0084] The current sampling circuit 510 generates a first sampling signal CS1, which indicates the level of a sampled current ISEN1 flowing through the inductor L, and generates a second sampling signal ZCS1, which indicates a zero level of the sampled current ISEN1 based on the sampled current ISEN1. The reference voltage generator 560 generates a reference voltage VREF.

[0085] The switching control circuit 515 generates the first and second driver control signals GP1 and GP2 by performing a PFM and a PWM based on the feedback voltage VFB1, the reference voltage VREF, the first sample signal CS1, and the second sample signal ZCS1. The switching control circuit 515 can adjust the charging time of the inductor L on a time basis based on at least the input power supply voltage Vin when the switching control circuit 515 performs the PFM. The switching control circuit 515 can adjust a low-on interval of the first driver control signal GP1 on a time basis based on at least the input power supply voltage Vin.

[0086] The switching control circuit 515 includes a pulse generation circuit 525, an on-time controller 530, a mode controller 540 and a driver controller 550.

[0087] The on-time controller 530 generates an on-time control pulse VON1, which adjusts (or limits) the charging time of the inductor L based on the input power supply voltage Vin and the reference voltage VREF. The pulse generation circuit 520 generates a first pulse signal PWMO1 by performing PWM, generates a second pulse signal PFMO1 by performing PFM based on the reference voltage VREF, the first sample signal CS1, the second sample signal ZCS1, the feedback voltage VFB1, and the on-time control pulse VON1, and generates a mode signal MD1, which indicates a difference between the differential voltage VREF and the feedback voltage VFB1. The on-time controller 530 can be activated in response to an external controller activation signal OTCEN. The on-time controller 530 can receive a calibration code CCD.

[0088] The mode controller 540 selects one of the first pulse signals PWMO1 and the second pulse signal PFMO1 as an output pulse signal PLO1 according to an operating mode based on the mode signal MD1 and the on-time control pulse VON1. The mode controller 540 selects one of the first pulse signals PWMO1 and the second pulse signal PFMO1 as the output pulse signal PLO1 based on a comparison of a first on-time and a second on-time. The first on-time can represent a first activation interval of the first pulse signal PWMO1, and the second on-time can represent a second activation interval of the second pulse signal PFMO1.

[0089] The driver controller 550 outputs the first and second driver control signals GP1 and GP2 respectively to the first switching device 61 and the second switching device 63 based on the output pulse signal PLO1.

[0090] The Fig. 15A and Fig. Figure 15B illustrates one operation of the converter circuit in the voltage converter of the Fig. 14.

[0091] Referring to the Fig. 14 and Fig. When the first switching device 61 is switched on in response to the first driver control signal GP1 with a second logic level, and the second switching device 63 is switched off in response to the second driver control signal GP2 with a second logic level, the converter circuit 60 charges the input power supply voltage Vin into the inductor L by performing a current build-up operation. When the converter circuit 60 performs the current build-up operation, a first current path IPATH21 is formed in the converter circuit 60.

[0092] Referring to the Fig. 14 and Fig. 15B can, when the first switching device 61 is switched off in response to the first driver control signal GP1 with a first logic level, and the second switching device 63 is switched on in response to the second driver control signal GP2 with a first logic level, transfer the energy stored in the inductor L to the output node NO by performing a current transfer operation. When the converter circuit 60 performs the current transfer operation, a second current path IPATH22 is formed in the converter circuit 60 and the load current ILOAD is provided for the load 50.

[0093] The voltage converter 20 of the Fig. 14 converts the input power supply voltage Vin to the output voltage Vout, and the level of the output voltage Vout is lower than the level of the input power supply voltage Vin. Therefore, the voltage converter 20 can Fig. 14 be a downward-moving type.

[0094] The operation of the voltage converter 20 of the Fig. 14 is similar to the operation of the voltage converters 10a and 10b of the Fig. 1 and Fig. 2 with reference to the Fig. 1 to 13, a detailed description of the operation of the voltage converter 20 of the Fig. Number 14 will be skipped.

[0095] Fig. Figure 16 is a graph which shows the operation of the voltage converter of the Fig. 14 explained, and Fig. 17 is a graph which represents a section of the Fig. 16 enlarged.

[0096] Referring to the Fig. 16 and Fig. 17 operates because the level of the load current ILOAD is lower than the reference level in an initial stage of operation of the voltage converter 20, i.e., the level of the output voltage Vout1 is higher than the reference level, the voltage converter 20 in PFM mode. In PFM mode, before time t1'', ​​the voltage converter 20 can increase the efficiency of the power transferred to the load 50 in PFM mode by adjusting the charging time of the inductor L in the switching control circuit 515 in feedforward control based on at least the input power supply voltage Vin on a time basis.

[0097] When the load current ILOAD begins to increase and the level of the load current ILOAD reaches the reference level between times t1'' ~ t2'', the operating mode of the voltage converter 20 changes from PFM mode to PWM mode.

[0098] The level of the load current ILOAD is greater than the reference level between times t1'' ~ t2'', and the voltage converter 20 operates in PWM mode after time t2''. It is noted that the power is transferred to the load 50 with higher efficiency than when the inductance current IL reaches its zero value, since an average value of the inductance current IL to the load 50 in a mode change interval of 491 in Fig. 17 will be transferred.

[0099] Fig. Figure 18 is a block diagram illustrating a voltage converter according to an exemplary embodiment.

[0100] Referring to Fig. A voltage converter 600 comprises a converter circuit 610, a capacitor C1, a feedback unit 40, a reference voltage generator 670, a current sampling circuit 620, and a switching control circuit 625. A load 50 is conveniently located in Fig. Figure 18 illustrates that the voltage converter 600 does not necessarily have to have the load 50. The voltage converter 600 can be referred to as a switching mode power supply (SMPS) or a power converter.

[0101] The converter circuit 610 comprises a first inductor L, a first switching device 611, a second switching device 612, a third switching device 613, and a fourth switching device 614. The inductor L is connected between the first switching node SW1 and a second switching node SW2. The first switching device 611 is connected between the input power supply voltage Vin and the first switching node SW1 and charges the input power supply voltage Vin into the inductor L in response to a first driver control signal GP21 in a buck mode. The second switching device 612 is connected between the first switching node SW1 and the common voltage and discharges the inductor L in response to a second driver control signal GP22 in the buck mode.

[0102] The third switching device 613 is connected between the second switching node SW2 and the common voltage and charges the input power supply voltage Vin into the inductor IL in response to a third driver control signal GP23 in a boost mode. The fourth switching device 614 is connected between the second switching node SW2 and the output node NO and discharges the inductor L in response to a fourth driver control signal GP24 in the boost mode.

[0103] The first switching device 611 can comprise a PMOS transistor having a source coupled to the input power supply voltage Vin, a gate receiving the first driver control signal GP21, and a drain coupled to the first switching node SW1. The second switching device 612 can comprise an NMOS transistor having a drain coupled to the first switching node SW1, a gate receiving the second driver control signal GP22, and a source coupled to the common voltage. The third switching device 613 can comprise an NMOS transistor having a drain coupled to the second switching node SW2, a gate receiving the third driver control signal GP23, and a source coupled to the common voltage.The fourth switching device 614 can have a PMOS transistor which has a source which is coupled to the second switching node SW2, a gate which receives the fourth driver control signal GP24, and a drain which is coupled to the output node NO.

[0104] The smoothing capacitor C1 is connected between the output node NO and the common voltage. The feedback unit 40 is connected in parallel with capacitor C1 between the output node NO and the common voltage, has resistors R1 and R2 connected to a feedback node FN, and divides an output voltage Vout2 at the output node NO to provide a feedback voltage VFB2. A load current ILOAD flows into the load 50 from the output node NO. The inductor L and capacitor C1 act as a low-pass filter, removing ripple in the output voltage Vout2.

[0105] The converter circuit 610 generates the output voltage Vout2 by lowering the input power supply voltage Vin in the buck mode, 610 generates the output voltage Vout2 by raising the input power supply voltage Vin in the boost mode, and generates the output voltage Vout2 by lowering or raising the input power supply voltage Vin in the buck-boost mode.

[0106] The output voltage level Vout2 is lower than the input power supply voltage level Vin in the buck mode, the output voltage level Vout2 is higher than the input power supply voltage level Vin in the boost mode, and the output voltage level Vout2 can generally be similar to the input power supply voltage level Vin in the buck-boost mode.

[0107] The fourth switching device 614 is switched on, the third switching device 613 is switched off, and the first and second switching devices 611 and 612 are switched on alternately in the low-shift mode. The first and third switching devices 611 and 613 are switched on alternately, and the second and fourth switching devices 612 and 614 are switched on alternately in the low-shift-up mode. The first switching device 611 is switched on, the second switching device 612 is switched off, and the third and fourth switching devices 613 and 614 are switched on alternately in the up-shift mode.

[0108] The current sampling circuit 620 generates a first sampling signal CS21, which indicates a peak or non-zero level of a first sampled current ISEN21 flowing through the inductor L, generates a second sampling signal ZCS21, which indicates an essentially zero level of the first sampled current ISEN21 based on the sampled current ISEN21, generates a third sampling signal CS22, which indicates a peak or non-zero level of a second sampled current ISEN22 flowing through the third switching device 613, and generates a fourth sampling signal ZCS22, which indicates an essentially zero level of the second sampled current ISEN22 based on the second sampled current ISEN22.

[0109] The switching control circuit 625 generates the first to fourth driver control signals GP21 ~ GP24 by performing PFM and PWM based on the feedback voltage VFB2, the reference voltage VREF, and the first to fourth sample signals CS21, ZCS21, CS22, and ZCS22. The switching control circuit 625 can adjust the charging time of the inductor L on a time basis based on at least the input power supply voltage Vin when the switching control circuit 625 performs the PFM. The switching control circuit 625 can adjust a low-level activation interval of the first driver control signal GP21 on a time basis in buck mode and can adjust an activation interval of the third driver control signal GP23 on a time basis in boost mode based on at least the input power supply voltage Vin.

[0110] The switching control circuit 625 includes a pulse generation circuit 630, an on-time controller 640, a mode controller 650 and a driver controller 660.

[0111] The 640 on-time controller generates on-time control pulses VON21 and VON22, which adjust (or limit) the charging time of the inductor L based on the input power supply voltage Vin and the reference voltage VREF. The 630 pulse generation circuit generates a first pulse signal PWMO2 by performing PWM, a second pulse signal PFMO2 by performing PFM based on the reference voltage VREF, the first sample signal CS21, the second sample signal ZCS21, the third sample signal CS22, the fourth sample signal ZCS22, the feedback voltage VFB2, and the on-time control pulses VON21 and VON22, and generates a mode signal MD2, which indicates a difference between the reference voltage VREF and the feedback voltage VFB2. The 640 on-time controller can receive a calibration code CCD.

[0112] The Mode Controller 650 selects one of the first pulse signals PWMO1 and the second pulse signal PFMO1 as the output pulse signal PLO1 according to an operating mode based on the mode signal MD1 and the on-time control pulses VON1 and VON2. The Mode Controller 650 selects one of the first pulse signals PWMO2 and the second pulse signal PFMO2 as the output pulse signal PLO2 based on a comparison of the first on-time of an activation interval of the first pulse signal PWMO2 and the second on-time of an activation interval of the on-time control pulse VON21 in the down-shift mode. The Mode Controller 650 selects one of the first pulse signals PWMO2 and the second pulse signal PFMO2 as the output pulse signal PLO2 based on a comparison of the first on-time of the activation interval of the first pulse signal PWMO2 and the second on-time of an activation interval of the on-time control pulse VON22 in the up-shift mode.

[0113] The driver controller 660 outputs the first to fourth driver control signal GP21 ~ GP24 to the first four switching devices 611 ~ 614 according to an operating mode based on the output pulse signal PLO2.

[0114] The operation of the voltage converter 600 in boost mode is similar to the operation of the voltage converters 10 and 10a with reference to the Fig. 1 to 13 and the operation of the voltage transformer 600 in the buck-shift mode is similar to the operation of the voltage transformer 20 with reference to the Fig. 14 to 17.

[0115] Fig. Figure 19 is a block diagram illustrating a power management device according to an exemplary embodiment.

[0116] Referring to Fig. Figure 19 includes a power management device 700 comprising a reference voltage generator 710, a reset signal generator 720, and a voltage transformer 730. The reference voltage generator 710 generates a reference voltage VREF based on a power activation signal PEN. Although in Fig. Not illustrated in Figure 19, the reference voltage generator 710 can be implemented with resistors that act as a voltage divider to generate the first reference voltage VREF. If a more stable reference voltage is desired, the reference voltage generator 710 can be implemented with a bandgap reference voltage circuit. The bandgap reference voltage circuit can provide a stable reference voltage that is insensitive to temperature variations. The bandgap reference voltage circuit can include a startup circuit, at least one transistor, at least one resistor, or the like.

[0117] The 720 reset signal generator produces a reset signal RST based on the power activation signal PEN and the reference voltage VREF. Although in Fig. Not illustrated in Figure 19, the reset signal generator 720 can include a reset activation unit, a reset deactivation unit, and a latch unit. The reset activation unit generates a reset activation signal based on the power activation signal PEN. The reset deactivation unit generates a reset deactivation signal based on the first reference voltage VREF and the reset activation signal. The latch unit generates the reset signal RST based on the reset activation signal and the reset deactivation signal.

[0118] The voltage converter 730 can replace one of the voltage converters 10. Fig. 1, of the voltage converter 10a of the Fig. 2, of the voltage converter 20 of the Fig. 14 and the voltage converter 600 of the Fig. Insert 18.

[0119] The voltage converter 730 comprises a switching control circuit 731, a converter circuit 732, and an output circuit 733. The switching control circuit 731 generates at least one driver control signal GP, which drives the converter circuit 732, and the converter circuit 732 converts an input power supply voltage Vin into an output voltage Vout in response to the at least one driver control signal GP. The output circuit 733 can control the capacitor C1 and the feedback unit 40 of the Fig. The switching control circuit 731 exhibits a load current based on the output voltage Vout and can provide a load current for a load. Accordingly, the switching control circuit 731 generates at least one driver control signal GP by performing PWM and PFM based on an inductance current flowing through an inductor in the converter circuit 732 and the feedback voltage VFB. In feedforward control, it adjusts the charging time of the inductor based on the input power supply voltage Vin on a time basis when the switching control circuit 731 performs the PFM, and it performs a mode change based on an on-time control pulse. Therefore, the voltage converter 730 can increase stability by reliably performing the mode change and can improve power transfer efficiency.

[0120] Fig. Figure 20 is a block diagram illustrating a power management system according to an exemplary embodiment.

[0121] Referring to Fig. 20 comprises a power management system 800, a power management device 820, and several integrated circuits 830a, 830b,... 830n. The power management device 820 and the several integrated circuits 830a, 830b,... 830n can be formed on a printed circuit board (PCB) 810.

[0122] The performance management device 820 can, for example, be the performance management device 700, which is in Fig. Figure 19 shows that the power management device 820 generates an output voltage Vout based on the input power supply voltage Vin and generates a reset signal RST based on a power activation signal PEN.

[0123] The voltage converter can be one of the voltage converter 10 of the Fig. 1, of the voltage converter 10a of the Fig. 2, of the voltage converter 20 of the Fig. 14 and the voltage converter 600 of the Fig. Insert 18.

[0124] Accordingly, the voltage converter generates at least one driver control signal by performing PWM and PFM based on the inductance current flowing through an inductor and the feedback voltage. During PFM, it adjusts the inductor's charging time based on the input power supply voltage Vin on a time-based basis and performs a mode change based on a time-based control pulse. Therefore, the voltage converter can increase stability through stable mode changes and improve power transfer efficiency.

[0125] The integrated circuits 830a, 830b,... 830n maintain a reset state based on the reset signal RST until the output power supply voltage Vout reaches a stable state. Once the output voltage Vout reaches the stable state, the integrated circuits 830a, 830b,... 830n are ready to operate and are powered based on the output voltage Vout.

[0126] Fig. Figure 21 is a block diagram illustrating a power management system according to an exemplary embodiment.

[0127] Referring to Fig. 21 includes a power management system 900, a system-on-a-chip (SoC) 910, and a filter 940. The SoC 910 includes a power management device 920 and a functional block 930.

[0128] The performance management device 920 can, for example, the performance management device 700 of the Fig. 19. The power management device 920 generates an output current based on the input power supply voltage Vin and generates a reset signal RST based on a power activation signal PEN. The voltage converter contained in the power management device 920, as described in the Fig. As described in Figure 1-18, the power management device 820 generates at least one driver control signal by performing PWM and PFM based on an inductor current flowing through an inductor and the feedback voltage. In feedforward mode, it adjusts the charging time of the inductor based on the input power supply voltage Vin on a time basis when performing the PFM, and it performs a mode change based on an on-time control pulse. Therefore, the power management device 820 can increase stability by reliably performing the mode change and can improve power transfer efficiency.

[0129] The filter 940 can be implemented as a low-pass filter which has an inductor LS and a capacitor CS.

[0130] Functional block 930 maintains a reset state based on the reset signal RST until the output power supply voltage Vout reaches a stable state. Once the output voltage Vout reaches the stable state, functional block 930 is ready to operate and is powered based on the output voltage Vout.

[0131] Although Fig. 21 An example of the performance management system 900, which has the filter 940 located outside the SoC 910, illustrates that the filter 940 can alternatively be contained within the SoC 910.

[0132] Fig. Figure 22 is a block diagram illustrating an example of an electronic device which includes the voltage converter according to an exemplary embodiment.

[0133] Referring to Fig. 22. An electronic device 1000 can be implemented as a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player. The electronic device 1000 includes a power management IC 1050 and a battery 1060.

[0134] The power management IC 1050 is powered by the battery 1060 and can manage the power of a processor 1010, an image sensor 1020, a memory 1040, or a display 1030. The power management IC 1050 can control one of the voltage converters 10 of the Fig. 1, of the voltage converter 10a of the Fig. 2, of the voltage converter 20 of the Fig. 14 and the voltage converter 600 of the Fig. 18. Accordingly, the performance management IC 1050 generates, as with reference to the Fig. As described in sections 1 to 18, at least one driver control signal is generated by performing PWM and PFM based on an inductor current flowing through an inductor and the feedback voltage. During PFM, the inductor's charging time is adjusted in pre-feedback mode based on the input power supply voltage Vin on a time basis. A mode change is then performed based on an on-time control pulse. Consequently, the 1050 power management IC can increase stability by ensuring stable mode changes and can improve power transfer efficiency.

[0135] The image sensor 1020 of the electronic device 1000 can convert an optical signal into a digital signal. The converted digital signal can be stored in the memory 1040 or displayed by the display 1030 under the control of the processor 1010. Likewise, the digital signal stored in the memory 1040 can be displayed by the display 1030 under the control of the processor 1010.

[0136] Fig. Figure 23 is a block diagram illustrating a mobile system that houses the power management device of the Fig. 19 according to an exemplary embodiment.

[0137] Referring to Fig. 23 A mobile system 1100 comprises an application processor 1110, a connectivity unit 1120, a volatile storage device 1130, a non-volatile storage device 1140, a user interface 1150, and a power supply 1160. According to various embodiments, the mobile system 1100 can be any mobile system, such as a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation system, or the like.

[0138] The application processor 1110 can run applications such as a web browser, a game application, a video player, or the like. The application processor 1110 can include a power management device 1111. The power management device 1111 can control one of the voltage converters 10 of the Fig. 1, of the voltage converter 10a of the Fig. 2, of the voltage converter 20 of the Fig. 14 and the voltage converter 600 of the Fig. 18. The voltage converter generates at least one driver control signal by performing PWM and PFM based on an inductance current flowing through an inductor and the feedback voltage. In feedforward control, it adjusts the charging time of the inductor based on the input power supply voltage on a time basis when performing PFM, and it performs a mode change based on an on-time control pulse. Therefore, the power management device 1111 can increase stability by ensuring stable mode changes and can improve power transfer efficiency.

[0139] The Connectivity Unit 1120 can perform wired or wireless communications with an external device. For example, the Connectivity Unit 1120 can perform Ethernet communication, Near Field Communication (NFC), Radio Frequency Identification (RFID), mobile telecommunications, memory card communication, Universal Serial Bus (USB) communication, or similar. In some embodiments, the Connectivity Unit 1120 may include a baseband chipset that supports communications such as Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Wideband Code Division Multiple Access (WCDMA), High-Speed ​​Downlink / Uplink Packet Access (HSxPA), or similar.

[0140] The volatile memory device 1130 can store data that is processed by the application processor 1110, or it can function as main memory. For example, the volatile memory device 1130 can be a dynamic random-access memory such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, or the like, or it can be any volatile memory device that requires a refresh operation.

[0141] The non-volatile storage device 1140 can store a boot image for booting the mobile system 1100.For example, the non-volatile memory device 1140 can be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nanofloating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), or the like.

[0142] The user interface 1150 can comprise at least one input device, such as a keypad, a touchscreen, or the like, and at least one output device, such as a loudspeaker, a display device, or the like. The power supply 1160 can supply a power supply voltage to the mobile system 1100. In some embodiments, the mobile system 1100 can further comprise a camera image processor (CIS) and / or a storage device, such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0143] In some embodiments, the mobile system 1100 and / or components of the mobile system 1100 can be enclosed in various forms such as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), a plastic leded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline IC (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi chip package (MCP), a wafer-level fabricated package (WFP), or a wafer-level processed stack package (WSP).

[0144] Fig. 24 is a block diagram illustrating a computer system that is the power management device of the Fig. 19 according to an exemplary embodiment.

[0145] Referring to Fig. 24 A computer system 1200 comprises a processor 1210, an input / output hub (IOH) 1220, an input / output controller hub (ICH) 1230, at least one memory module 1240, and a graphics card 1250. In some embodiments, the computer system 1200 may be a personal computer (PC), a server computer, a workstation, a laptop computer, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, or the like.

[0146] The processor 1210 can perform various computational functions, such as executing specific software to carry out specific calculations or tasks. For example, the processor 1210 can be a microprocessor, a central processing unit (CPU), a digital signal processor, or the like. The processor 1210 can include a power management device 1211. The power management device 1211 can control one of the voltage converters 10. Fig. 1, of the voltage converter 10a of the Fig. 2, of the voltage converter 20 of the Fig. 14 and the voltage converter 600 of the Fig. 18. Accordingly, the voltage converter generates at least one driver control signal by performing a PWM and a PFM based on an inductance current flowing through an inductor and the feedback voltage, adjusts the charging time of the inductor in feedforward control based on the input power supply voltage on a time basis when it performs the PFM, and performs a mode change based on an on-time control pulse.

[0147] In some embodiments, the 1210 processor may have a single core or multiple cores. For example, the 1210 processor may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, or the like. Although Fig. Figure 24 illustrates that the computer system 1200 includes a processor 1210; in some embodiments, the computer system 1200 may include a plurality of processors. The processor 1210 may include an internal or external cache memory.

[0148] The processor 1210 can include a memory controller for controlling operations of the memory module 1240. The memory controller included in the processor 1210 can be referred to as an integrated memory controller (IMC). The memory controller can have a structure and / or perform the procedures of one or more of the embodiments described herein. A memory interface between the memory controller and the memory module 1240 can be implemented with a single channel having a plurality of signal lines, or it can be implemented with multiple channels. At least one memory module 1240 can be coupled to each of the multiple channels.In some embodiments, the memory controller can be placed within the input / output hub 1220, which can be referred to as a memory controller hub (MCH=Memory Controller Hub=Speichercontroller-Hub).

[0149] The Input / Output Hub 1220 can manage data transfer between the Processor 1210 and devices such as the Graphics Card 1250. The Input / Output Hub 1220 can be connected to the Processor 1210 via various interfaces. For example, the interface between the Processor 1210 and the Input / Output Hub 1220 can be a Frontside Bus (FSB), a System Bus, HyperTransport, Lightning Data Transport (LDT), QuickPath Interconnect (QPI), a Common System Interface (CSI), or similar. Fig.Figure 24 illustrates that the computer system 1200 has an input / output hub 1220. In some embodiments, the computer system 1200 may have multiple input / output hubs. The input / output hub 1220 may provide various interfaces with the devices. For example, the input / output hub 1220 may have an accelerated graphics port (AGP), a peripheral component interface (PCIe), a communications streaming architecture (CSA) interface, or the like.

[0150] The graphics card 1250 can be connected to the input / output hub 1220 via the AGP interface or PCIe. The graphics card 1250 can control a display device (not shown) for displaying an image. The graphics card 1250 can include an internal processor for processing image data and an internal memory device. In some embodiments, the input / output hub 1220 can include an internal graphics device together with or instead of the graphics card 1250, which is located outside the input / output hub 1220. The graphics device contained in the input / output hub 1220 can be referred to as integrated graphics. Furthermore, the input / output hub 1220, which includes the internal memory controller and the internal graphics device, can be referred to as a graphics and memory controller hub (GMCH).

[0151] The I / O Controller Hub 1230 can perform data buffering and interface arbitration to efficiently operate various system interfaces. The I / O Controller Hub 1230 can be coupled to the I / O Hub 1220 via an internal bus, such as a Direct Media Interface (DMI), a hub interface, an Enterprise Southbridge Interface (ESI), PCIe, or similar interfaces. The I / O Controller Hub 1230 can provide various interfaces with peripheral devices. For example, the I / O Controller Hub 1230 can feature a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a General Purpose Input / Output (GPIO) port, a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI), PCI, PCIe, or similar interfaces.

[0152] In some embodiments, the processor 1210, the input / output hub 1220, and the input / output controller hub 1230 can be implemented as separate chipsets or separate integrated circuits. In other embodiments, at least two of them can be implemented as a single chipset: the processor 1210, the input / output hub 1220, and the input / output controller hub 1230.

[0153] The use of the term "voltage converter" is not considered in order to limit the current converter capabilities of exemplary embodiments. Accordingly, a power converter may comprise a converter circuit connected to an input node and having a switching node, an energy storage device connected to the switching node, and a plurality of switching devices connected to the switching node; and a switching control circuit connected to control inputs of the plurality of switching devices to control the plurality of switching devices by means of one of a plurality of power transfer modes at a time based on at least one feedback signal, at least one feedforward signal, and at least one sampling signal, and by controlling switching between the plurality of power transfer modes based on a short-term current.which essentially flows through an output node, wherein the at least one feedback signal is based on an output potential at the output node, wherein the at least one feedforward signal is based on an input potential at the input node, and the at least one sampling signal is based on a sampled current which essentially flows through at least one of the plurality of switching devices, and a first of the plurality of switching devices is connected between the switching node and a common node.

[0154] As mentioned above, according to an exemplary embodiment of the voltage converter, the inductance current is increased by switching on the first driver device and switching off the second driver device using the off-time control voltage in the switching control circuit before the second sampling signal is activated. Thus, the voltage converter can increase the efficiency of power transferred to the load in PFM mode. Additionally, the voltage converter stably performs the mode change based on the first and second sampling signals during a mode change interval.

Claims

[1] Voltage transformer (10, 10a, 20, 600, 730) comprising the following: a converter circuit (60, 100, 100a, 610, 732) comprising an inductor connected to a switching node, a first switching device (61, 120, 611) connected between the switching node and a common voltage, and a second switching device (63, 130, 612) connected between the switching node and an output node, wherein the first switching device (61, 120, 611) is configured to charge an input power supply voltage into the inductor and is configured to discharge the inductor in response to a driver control signal; and a switching control circuit (160, 515, 625, 731) configured to generate the driver control signal by performing pulse width modulation (PWM) and pulse frequency modulation (PFM) based on a first sample signal, a second sample signal, and a feedback voltage, wherein the first sample signal and the second sample signal are based on a sampled current flowing through the first switching device (61, 120, 611), and wherein the feedback voltage is obtained by dividing an output voltage at the output node. wherein the switching control circuit (160, 515, 625, 731) is configured to adjust a charging time of the inductor on a time basis based on at least the input voltage when the switching control circuit (160, 515, 625, 731) performs the PFM, wherein the switching control circuit (160, 515, 625, 731) has the following: an on-time controller (300, 530, 640) configured to generate an on-time control pulse that adjusts the charging time of the inductor based on the input power supply voltage and a reference voltage; a pulse generation circuit (200, 525, 630) configured to generate a first pulse signal by performing PWM, and configured to generate a second pulse signal by performing PFM based on the reference voltage, the first sample signal, the second sample signal, the feedback voltage and the on-time control pulse, configured to generate a mode signal indicating a difference between the reference voltage and the feedback voltage, wherein the first sample signal indicates a level of the sampled current, and the second sample signal indicates an essentially zero level of the sampled current; a mode controller (400, 540, 650) configured to select one of the first pulse signals and the second pulse signal as an output pulse signal according to the mode signal and an operating mode based on the on-time control pulse; and a driver controller (470, 550, 660) which is configured to generate the driver control signal based on the output pulse signal, wherein the mode controller (400, 540, 650) is configured to select one of the first pulse signal and the second pulse signal as the output pulse signal based on a comparison of a first on-time and a second on-time, and where the first on-time corresponds to a first activation interval of the first pulse signal, and the second on-time corresponds to a second activation interval of the second pulse signal. [2] Voltage converter (10, 10a, 20, 600, 730) according to claim 1, wherein the mode controller (400, 540, 650) is configured to change the operating mode from a PWM mode to a PFM mode when the first on-time is less than the second on-time by at least one reference number. [3] Voltage converter (10, 10a, 20, 600, 730) according to claim 1, wherein the on-time controller (300, 530, 640) comprises: an activation signal generator (310) which is configured to generate a first activation signal and a second activation signal based on control signals from outside and a reference pulse signal; a current mirror circuit (330) configured to generate a charging current by mirroring a reference current in response to the first activation signal; and an on-time pulse generator (350) which is configured to generate the on-time control pulse based on the first activation signal, the second activation signal, the charging current and reference voltage and the input power supply voltage. [4] Voltage converter (10, 10a, 20, 600, 730) according to claim 3, wherein the on-time pulse generator (350) comprises: a first capacitor (352) which is connected between a first node which is coupled to the current mirror circuit (330) and the common voltage, wherein the first capacitor (352) stores the charging current; a first switch (351) which is connected in parallel with the first capacitor (352) between the first node and the common voltage, wherein the first switch (351) is switched in response to the second activation signal; at least one second switch (353) and at least one second capacitor (354) connected in series between the first node and the common voltage; a comparator (213, 355) configured to compare a ramp voltage at the first node and the reference voltage; and a flip-flop (215, 356) which has a setting terminal which receives the first activation signal, a reset terminal which receives an output from the comparator (213, 355), and an output terminal which provides the on-time control pulse. [5] Voltage converter (10, 10a, 20, 600, 730) according to claim 4, wherein an on-time of the on-time control pulse is varied according to a level of the ramp voltage. [6] Voltage converter (10, 10a, 20, 600, 730) according to claim 1, wherein the pulse generation circuit (200, 525, 630) comprises: a first pulse generator (210) configured to generate the first pulse signal based on the reference voltage, the feedback voltage, and the first sampling signal; and a second pulse generator (230) which is configured to generate the second pulse signal based on the reference voltage, the feedback voltage, the second sampling signal and the on-time control pulse. [7] Voltage converter (10, 10a, 20, 600, 730) according to claim 6, wherein the second pulse generator (230) comprises: a first hysteresis comparator (231) configured to generate a PFM signal corresponding to a difference between the feedback voltage and the reference voltage, wherein the first hysteresis comparator (231) has a variable hysteresis window; a second hysteresis comparator (233) which is configured to generate the mode signal which corresponds to a difference between the reference voltage and the feedback voltage; a first OR gate (235) which performs an OR operation on the PFM signal and the second sample signal; a second OR gate (237) which performs an OR operation on the mode signal and the on-time control pulse; and a flip-flop (215, 356) which has a setting terminal which receives an output from the first OR gate (235), a reset terminal which receives an output from the second OR gate (237) and an output terminal which provides the second pulse signal. [8] Voltage converter (10, 10a, 20, 600, 730) according to claim 1, wherein the mode controller (400, 540, 650) comprises: a time comparator (410) configured to compare a first on-time corresponding to a first activation interval of the first pulse signal and a second on-time corresponding to a second activation interval of the second pulse signal in order to output a time comparison signal; a counter (420) which is configured to count the time comparison signal which has a first logic level in order to output a count output signal; a signal generator (430) configured to generate a reset signal and a selection signal based on the count output signal and the mode signal; and a selection circuit (440) which is configured to select one of the first pulse signal and the second pulse signal as the output pulse signal in response to the selection signal. [9] Voltage converter (10, 10a, 20, 600, 730) according to claim 8, wherein the counter (420) is configured to output the count output signal as a first logic level when the time comparator (410) successively outputs the time comparison signal as a first logic level for a reference number of times. [10] Voltage converter (10, 10a, 20, 600, 730) according to claim 1, wherein the converter circuit (60, 100, 100a, 610, 732) further comprises: a third switching device (110, 613) which is connected between the input power supply voltage and the inductor, wherein the third switching device (110, 613) switches the input power supply voltage to the inductor in response to a boost control signal; wherein the third switching device (110, 613) comprises a p-channel circuit breaker. [11] Voltage transformer (10, 10a, 20, 600, 730) comprising the following: a converter circuit (60, 100, 100a, 610, 732) comprising an inductor connected to a first switching node, a first switching device (61, 120, 611) connected to the switching node, and a second switching device (63, 130, 612) connected between the switching node and an output node, wherein the first switching device (61, 120, 611) is configured to charge an input power supply voltage into the inductor in response to a first driver control signal, and the second switching device (63, 130, 612) is configured to discharge the inductor in response to a second driver control signal; and a switching control circuit (160, 515, 625, 731) configured to generate the first driver control signal and the second driver control signal by performing pulse width modulation (PWM) and pulse frequency modulation (PFM) based on a first sample signal, a second sample signal and a feedback signal, wherein the first sample signal and the second sample signal are based on an inductor current flowing through the inductor, and wherein the feedback voltage is obtained by dividing an output voltage at the output node. wherein the switching control circuit (160, 515, 625, 731) is configured to adjust a charging time of the inductor on a time basis, based on at least the input voltage, when the switching control circuit (160, 515, 625, 731) performs the PFM, wherein the switching control circuit (160, 515, 625, 731) has the following: an on-time controller (300, 530, 640) configured to generate an on-time control pulse that adjusts the charging time of the inductor based on the input power supply voltage and a reference voltage; a pulse generation circuit (200, 525, 630) configured to generate a first pulse signal by performing PWM, configured to generate a second pulse signal by performing PFM based on the reference voltage, the first sample signal, the second sample signal, the feedback voltage and the on-time control pulse, and configured to generate a mode signal indicating a difference between the reference voltage and the feedback voltage, wherein the first sample signal indicates a non-zero level of the inductance current, and the second sample signal indicates a substantially zero level of the inductance current; a mode controller (400, 540, 650) configured to select one of the first pulse signals and the second pulse signal as an output pulse signal according to the mode signal and an operating mode based on the on-time control pulse; and a driver controller (470, 550, 660) which is configured to generate the first driver control signal and the second driver control signal based on the output pulse signal, where the output voltage level is lower than the input power supply voltage level, wherein the mode controller (400, 540, 650) is configured to select one of the first pulse signal and the second pulse signal as the output pulse signal based on a comparison of a first on-time and a second on-time, and where the first on-time corresponds to a first activation interval of the first pulse signal, and the second on-time corresponds to a second activation interval of the second pulse signal. [12] Power converter which features the following: a converter circuit (60, 100, 100a, 610, 732) which is connected to an input node and has a switching node, an energy storage device which is connected to the switching node, and a plurality of switching devices which are connected to the switching node; and a switching control circuit (160, 515, 625, 731) which is connected to control inputs of the plurality of switching devices in order to control the plurality of switching devices by means of a following one of a plurality of power transmission operating modes at a time based on at least one feedback signal, at least one feedforward signal and at least one sampling signal and switching between the plurality of power transmission operating modes based on a current which essentially flows through an output node, wherein the at least one feedback signal is based on an output potential at the output node, the at least one feedforward signal is based on an input potential at the input node, and the at least one sampling signal is based on a sampled current which flows substantially through at least one of the plurality of switching devices, and a first of the plurality of switching devices is connected between the switching node and a common node, wherein the switching control circuit (160, 515, 625, 731) has the following: an on-time controller (300, 530, 640) configured to generate an on-time control pulse that adjusts the charging time of the inductor based on the input power supply voltage and a reference voltage; a pulse generation circuit (200, 525, 630) configured to generate a first pulse signal by performing PWM, and configured to generate a second pulse signal by performing PFM based on the reference voltage, the first sample signal, the second sample signal, the feedback voltage and the on-time control pulse, configured to generate a mode signal indicating a difference between the reference voltage and the feedback voltage, wherein the first sample signal indicates a level of the sampled current, and the second sample signal indicates an essentially zero level of the sampled current; a mode controller (400, 540, 650) configured to select one of the first pulse signals and the second pulse signal as an output pulse signal according to the mode signal and an operating mode based on the on-time control pulse; and a driver controller (470, 550, 660) which is configured to generate the driver control signal based on the output pulse signal, wherein the mode controller (400, 540, 650) is configured to select one of the first pulse signal and the second pulse signal as the output pulse signal based on a comparison of a first on-time and a second on-time, and where the first on-time corresponds to a first activation interval of the first pulse signal, and the second on-time corresponds to a second activation interval of the second pulse signal. [13] Power converter according to claim 12, wherein each of the plurality of switching devices is controlled by a corresponding one of a plurality of control signals, and at least one of the plurality of control signals is based on a sampled current flow through at least one of the first switching device or the energy storage device. [14] Power converter according to claim 13, wherein: the switching control circuit (160, 515, 625, 731) is configured to generate at least one of the plurality of control signals for controlling at least one of the plurality of switching devices by performing pulse width modulation (PWM) and pulse frequency modulation (PFM) based on a first sampling signal, a second sampling signal and a feedback signal, wherein the first sampling signal and the second sampling signal are each based on a sampled current which flows through at least one of the first switching device (61, 120, 611) or the energy storage device, the feedback signal is based on an output voltage potential at the output node, and at least one of the plurality of switching devices is configured to discharge the energy storage device in response to at least one control signal. [15] Power converter according to claim 12, configured to provide a low output current when the switching control circuit (160, 515, 625, 731) performs pulse frequency modulation (PFM) as one of the plurality of power transfer operating modes, wherein the switching control circuit (160, 515, 625, 731) is configured to match a charging time of the energy storage device based on at least one power supply voltage potential at the input node. [16] Power converter according to claim 14, wherein the first sampling signal and the second sampling signal are based on the sampled current flowing through the first switching device (61, 120, 611); the first of the majority of switching devices is configured to discharge the inductance in response to a first of at least one control signal, a second of the plurality of switching devices is connected between the switching node and the output node, and is configured to essentially pass an output voltage potential to the output node in response to a second of the at least one control signal, and a third of the plurality of switching devices is connected between the switching node and the input node, and is configured to charge the inductor with an input power supply voltage in response to a third of the at least one control signal. [17] Power converter according to claim 16, wherein: the energy storage device is an inductor, and the switching control circuit (160, 515, 625, 731) is configured to adjust an inductor charging time based on at least one voltage potential at the input node when the switching control circuit (160, 515, 625, 731) performs PFM as one of the majority of power transfer operating modes.

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