Verification of gate driver protection logic

Abstract

Gate driver that features: a gate signal module (6) configured to output a gate signal from the gate driver (4) to control a gate terminal of a semiconductor device (14; 14A; 14B); a test module (10; 10A; 10B) configured to generate a simulated fault condition on the semiconductor device during a test of a monitoring and protection feature of the gate driver (4); and a monitoring module (8; 8A; 8B) which is configured to output a message about the simulated fault condition in response to the detection of the simulated fault condition at the semiconductor device (14).

Description

[0001] Some systems rely on semiconductor modules composed of one or more insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or other types of transistor-based devices. Some systems will drive the device gate(s) of a semiconductor module using a specialized gate driver IC (integrated circuit) that includes fault condition monitoring and / or protection features to prevent damage to the module during a fault condition (e.g., accidental short circuit, over-temperature condition, over-voltage condition, over-current condition, or other fault conditions).

[0002] For example, a high-performance automotive powertrain typically contains one or more semiconductor modules that act as power switches to control the flow of electrical power to and from a motor. The gate drivers of the powertrain's semiconductor modules may include desaturation protection features, overcurrent protection features, or other types of fault-monitoring features that remain continuously active. If the monitoring features identify a fault condition, a motor controller can take action (such as opening or closing a switch) to prevent the fault condition from damaging the semiconductor module.

[0003] To ensure compliance with safety requirements (e.g., according to ISO standard 26262), some systems may occasionally (e.g., when starting a motor vehicle) intentionally introduce actual system-level disturbances. Introducing actual system-level disturbances provides a way for some systems to exercise and verify the functionality of fault monitoring and protection features in the event of unintended disturbances. For example, some systems include additional hardware (e.g., at the circuit board level) that, at the risk of damaging the system, injects currents in the impermissible range to occasionally trigger overcurrent monitoring and protection features. Additional hardware like this can increase the size, cost, and / or complexity of a system and also risk damaging the system if the protection features fail.

[0004] US 2013 / 0181729 A1 describes a method for testing the existing protection mechanisms of a power converter. The system simulates the generation of a voltage level by the voltage converter below an undervoltage threshold; a short circuit in the power converter that pulls an input bus down; and a short circuit in the power converter that pulls an output bus down. The system compares the system responses with those of a correctly functioning system and determines whether the power converter's protection mechanisms are functioning correctly.

[0005] US 2008 / 0062602A1 describes a driver circuit for an electronic switch, which has a first input for receiving a first control signal and a second input for receiving a signal from a current sensor. The driver circuit also includes a circuit that controls the switch so that current flow is interrupted in the event of a fault.

[0006] DE 10 2007 039 820 B4 describes a FET monitoring and protection arrangement. The monitoring and protection arrangement comprises a FET switching device with a FET, a logic module electrically coupled to the FET and generating a feedback status signal, and a feedback status output. The FET monitoring and protection arrangement also includes a counter that is incremented only when the FET device is in a short-circuit state; a memory for permanently storing the counter value; and a control unit electrically coupled to the feedback status output, wherein the control unit enables or disables the activation of the FET depending on the feedback status signal and the counter value.

[0007] In general, circuits and techniques are described to enable a gate driver to test the performance of internal fault monitoring features without requiring system-level excitation from an external, fault-triggering circuit. An example gate driver includes a fault monitoring module (e.g., an overcurrent monitoring module, a desaturation monitoring module, or another module or feature that provides fault monitoring). Instead of relying on specialized hardware to introduce actual fault conditions into the system, the example gate driver includes a test module trained to simulate fault conditions which, if detected by the fault monitoring module, can verify the module's functionality.In this way, a system can verify that a gate driver's fault monitoring module is working without relying on special hardware to introduce actual fault conditions into the system and without risking damage to the system if the fault monitoring and protection features fail.

[0008] In one example, the disclosure relates to a gate driver comprising: a gate signal module configured to output a gate signal from the gate driver to drive a gate terminal of a semiconductor device, a test module configured to generate a simulated fault condition on a semiconductor device during a test of a monitoring and protection feature of the gate driver, and a monitoring module configured to output a message of the simulated fault condition in response to the detection of the simulated fault condition on the semiconductor device.

[0009] In another example, the disclosure relates to a method for testing a monitoring and protection feature of a gate driver. The method includes triggering a test of the gate driver's monitoring and protection feature by a control module, during which the gate driver simulates a fault condition associated with a semiconductor device, and, in response to receiving a fault message issued by the gate driver in response to the simulated fault condition, measuring a time interval for the gate driver to output the fault message after the test has been triggered.The procedure may further include the control module comparing the measured time interval with an expected time threshold; and, in response to determining that the measured time interval does not meet the expected time threshold, determining that a fault in the monitoring and protection feature of the gate driver has occurred.

[0010] In another example, the disclosure relates to a computer-readable storage medium comprising instructions which, when executed, configure at least one processor of a control module to test a monitoring and protection feature of a gate driver by triggering at least one test of the gate driver's monitoring and protection feature, during which the gate driver simulates a fault condition associated with a semiconductor device, and, in response to receiving a fault message issued by the gate driver in response to the simulated fault condition, to measure a time interval for the gate driver to issue the fault message after the test has been triggered.The instructions further configure, when executed, the at least one processor of the control module to test the monitoring and protection feature of the gate driver, at least by comparing the measured time interval with an expected time threshold, and in response to determining that the measured time interval does not meet the expected time threshold, to determine that a fault in the monitoring and protection feature of the gate driver has occurred.

[0011] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, functions, and advantages of the disclosure will become apparent from the description, the drawings, and the claims. Fig. Figure 1 is a conceptual diagram illustrating a system that includes an exemplary gate driver trained to test the internal protection logic of the gate driver according to one or more aspects of the present disclosure. Fig. Figure 2 is a flowchart illustrating exemplary operations of an exemplary control module for testing the internal monitoring and protection logic of an exemplary gate driver according to one or more aspects of the present disclosure. Fig. Figure 3 is a conceptual diagram illustrating an exemplary gate driver trained to test the desaturation monitoring and protection logic of an exemplary gate driver according to one or more aspects of the present disclosure. Fig. Figure 4 is a vibration curve diagram showing exemplary temporal and electrical characteristics of the exemplary gate driver. Fig. 3 illustrated according to one or more aspects of the present disclosure, while an exemplary control module tests the desaturation monitoring and protection logic of an exemplary gate driver. Fig. Figure 5 is a conceptual diagram illustrating an exemplary gate driver trained to test the overcurrent monitoring and protection logic of an exemplary gate driver according to one or more aspects of the present disclosure. Fig. Figure 6 is a vibration curve diagram showing exemplary temporal and electrical characteristics of the exemplary gate driver. Fig. 5 illustrated according to one or more aspects of the present disclosure, while an exemplary control module tests the overcurrent monitoring and protection logic of an exemplary gate driver.

[0012] Fig. Figure 1 is a conceptual diagram illustrating a system 1 containing the gate driver 4, which is configured to test the internal protection logic of the driver 4 according to one or more aspects of the present disclosure. In addition to the driver 4, the system 1 includes the control module 12 and the component 14.

[0013] System 1 represents any exemplary system containing one or more semiconductor modules or “devices” controlled by gate drivers that incorporate monitoring and / or protection features to prevent damage to the semiconductor modules during a fault condition (e.g., accidental short circuit, over-temperature condition, over-voltage condition, over-current condition, or other fault conditions). For example, System 1 could be an automotive system (e.g., a lighting system, powertrain system, or other automotive system), an electrical power and distribution system, a computer system, a power conversion system, or any other system containing one or more semiconductor components vulnerable to fault conditions and drivers designed to protect the semiconductor components from the fault conditions.

[0014] Device 14 is a semiconductor module driven by a gate driver, such as driver 4. Device 14 may comprise one or more insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or other types of transistor-based devices having gates configured to receive a gate signal from a driver. In some examples, device 14 is a power switch configured to conduct current through a forward-conducting channel when device 14 is driven "on." Device 14 may be configured to refrain from conducting current through the forward-conducting channel when device 14 is driven "off."

[0015] Device 14 can receive a gate signal via junction 18, which drives a gate terminal of one or more transistor-based components of device 14. Device 14 can output feedback information via junction 20, which driver 4 and / or control module 12 can use to determine whether device 14 is functioning correctly. For example, device 14 can output a voltage level or a current level via junction 20 in response to receiving a gate signal via junction 18. Driver 4 and / or control module 12 can compare the voltage level or current level at junction 20 with an expected voltage or current level (e.g., a threshold) to determine whether device 14 is functioning correctly and / or whether there is a fault condition at device 14. In some examples, as in Fig. As shown in Figure 1, the component 14 is electrically coupled to the driver 4 at a ground or common termination.

[0016] The control module 12 exchanges command and control signals with the driver 4 to cause the component 14 to perform an operation. For example, the control module 12 can output a gate control signal via junction 16B, which in turn causes the driver 4 to output a gate signal at junction 18 (e.g., to control the component 14 to "on" or "off"). The control module 12 can receive a fault feedback signal via junction 16A in response to the monitoring and protection features of the driver 4 reporting the detection of a fault condition related to the driver 4 and / or the component 14. In some examples, the control module 12 can output a gate control signal via the link 16B, which signals the driver 4 to switch the component 14 from "off" (and e.g. not conducting through a conducting channel) to "on" (and e.g. forward conducting) or vice versa.

[0017] The control module 12 may comprise any suitable arrangement of hardware, software, firmware, or any combination thereof to perform the techniques attributed herein to the control module 12. For example, the control module 12 may include one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuits, as well as any combination of such components. If the control module 12 includes software or firmware, it shall also include all necessary hardware for storing and executing the software or firmware, such as one or more processors or processing units.

[0018] In general, a processing unit can contain one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, as well as any combination of such components. Although this in Fig. Unless otherwise shown in Figure 1, the control module 12 may contain memory configured to store data. This memory may include any volatile or non-volatile media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically erasable PROM (EEPROM), flash memory, and the like. In some examples, the memory may be located outside the control module 12; for example, it may be located outside a package in which the control module 12 is housed.

[0019] In some examples, the control module 12 can output a test signal to the driver 4 via link 16C, triggering the driver 4 to test its monitoring and protection features. For example, to verify that the driver 4 adequately monitors itself and / or component 14 for potential disturbances in system 1 and correctly reports all fault conditions back to system 1, the control module 12 can output a test signal via link 16C, signaling the driver 4 to perform a verification test of its monitoring and protection features. In response to the test signal, the control module 12 can receive one or more feedback signals from the driver 4 via link 16A, indicating whether the monitoring module 8 has detected a disturbance condition in response to the test.

[0020] Driver 4 is an exemplary driver designed to test the performance of the internal fault monitoring features without requiring system-level electrical excitation. Driver 4 includes the gate signal module 6, the output buffer 7, the monitoring module 8, and the test module 10. The gate signal module 6 contains the fade-out counter 9. Driver 4 can use additional or fewer modules and components than those shown. Fig. Included in Figure 1. In some examples, the driver 4 and the component 14 are a single unit. In other examples, as in Figure 1, they are... Fig. As shown in Figure 1, the driver 4 and the component 14 are separate, distinct modules linked by links 18, 20 and a common GND.

[0021] Modules 6-10 may comprise any suitable arrangement of hardware, software, firmware, or any combination thereof, to perform the techniques attributed to Modules 6-10 herein. For example, Modules 6-10 may contain one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, as well as any combination of such components. If Modules 6-10 contain software or firmware, they shall also contain all necessary hardware for storing and executing the software or firmware, such as one or more processors or processing units.

[0022] As is the case with a processing unit of control module 12, a processing unit of any of modules 6-10 can contain one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, as well as any combinations of such components. Although this in Fig. Unless otherwise shown in Figure 1, modules 6-10 may contain memory configured to store data. This memory may include any volatile or non-volatile media, such as RAM, ROM, NVRAM, EEPROM, flash memory, and the like. In some examples, the memory may reside outside of modules 6-10 and / or driver 4; for example, it may reside outside of a package that houses modules 6-10 and / or driver 4.

[0023] The gate signal module 6 (simply referred to as GSM 6) is configured to cause the driver 4 to output a gate signal to the component 14 via the output buffer 7 and the interconnect 18, based on information received from the control module 12. For example, the GSM 6 can receive a gate control signal from the control module 12 and cause the driver 4 to output a corresponding gate signal to the interconnect 18.

[0024] The gate signal module 6 can also be configured to transmit fault information to the control module 12 via link 16A, reporting whether the monitoring features of the driver 4 have detected any potential fault conditions related to the driver 4, the component 14, and / or the system 1. For example, the GSM 6 can receive information from the monitoring module 8 when the monitoring module 8 detects an overcurrent condition, a desaturation condition, or any other fault condition at link 20. The GSM 6 can provide a fault signal to the control module 12 in response to the monitoring module 8's detection of the fault condition. Based on the fault signal received from the driver 4, the control module 12 can take action to prevent the fault condition from damaging the component 14 and / or the driver 4.Instead of outputting the fault signal to the control module 12, the driver 4 itself can react to the fault condition in some examples. For instance, the gate signal module 6 can configure the driver 4 to operate in a "safe state" or "safe mode" to protect the component 14 from damage due to the fault condition.

[0025] As described below with reference to the additional figures, in some examples, when test module 10 is disabled, the gate signal output by GSM 6 can follow signal path 5B, which runs from GSM 6 via link 17 directly to buffer 7 and outwards via link 18 to component 14. However, in other examples, when test module 10 is enabled, the gate signal output by GSM 6 can follow path 5A, exiting GSM module 6 and passing through test module 10 before continuing to buffer 7 and outwards to component 14 via link 18.

[0026] In addition to outputting a gate signal via link 17, the GSM module 6 includes the blanking counter 9. Although they are consistently described as “counters” in this disclosure, the blanking counter 9 and the other counters described herein can be “classic” digital counters, or they can be other equivalent analog delay lines (e.g., designed with some external resistive / capacitive elements). The purpose of the blanking counter 9 is to provide the monitoring module 8 with a sufficient amount of time (i.e., a blanking period) to determine whether the device 14 is experiencing a fault condition before the GSM module 6 analyzes the information received from the monitoring module 8 for any detected faults.In other words, the filter counter 9 prevents errors from being falsely received by the GSM module 6 during a transition phase of the gate control signal at link 16B, when the monitoring module 8 cannot necessarily detect fault conditions accurately.

[0027] In some examples, the blanking counter 9 can reset (e.g., restore its initial count and restart counting) after the gate control signal from control module 12 changes from "off" to "on" or vice versa. When the blanking counter expires (e.g., counting down to zero or up to a maximum count), the GSM module 6 can analyze the information received from the monitoring module 8 and report externally via link 16A whether the driver 4 has detected any fault conditions. However, before the blanking counter expires, the GSM module 6 can disregard the information received from the monitoring module 8 and report externally that no fault conditions have been detected.In other words, the masking counter 9 can provide the GSM module 6 with a defined masking window, which would otherwise mask any anomalies in the faults detected by the monitoring module 8 during the transition phase of a gate control signal received by the control module 12.

[0028] The monitoring module 8 of the driver 4 is a component that provides the driver 4 with fault condition monitoring features. In some examples, the monitoring module 8 is a desaturation detection module. In other examples, the monitoring module 8 is an overcurrent detection module. In each case, the monitoring module 8 receives information via the link 20 about the operating states associated with the component 14 (e.g., voltage levels or current levels). Based on the operating states associated with the component 14, the monitoring module 8 outputs a fault or feedback signal to the GSM module 6. The GSM module 6 analyzes the information received from the monitoring module 8 to determine whether a reportable fault condition has occurred or is about to occur at the component 14.

[0029] The test module 10 tests the performance of the monitoring module 8 without requiring the control module 12 to trigger an electrical excitation of the driver 4 and / or the component 14 at the system level (e.g., by an external fault-triggering circuit). In other words, instead of relying on special hardware to introduce actual fault conditions into the system 1, the driver 4 includes the test module 10, which is designed to simulate fault conditions that, if detected by the monitoring module 8, verify that the monitoring module 8 is functioning correctly. In this way, the driver 4 and the system 1 can verify that the fault monitoring and protection features of the driver 4 are working without relying on special hardware to introduce actual fault conditions into the system 1 and without risking damage to the system 1 should the fault monitoring and protection features of the driver 4 fail.

[0030] Test module 8 can be activated by control module 12. Control module 12 can send information via link 16C that causes test module 10 to trigger a test of monitoring module 8. In response to the information from control module 12, test module 10 can simulate a fault condition at link 20. For example, in some cases, test module 10 can force the gate signal output by GSM module 6 at link 17 to take signal path 5A through test module 10, allowing test module 10 to modify the gate signal before outputting it to buffer 7 to perform the test. In other cases, test module 10 can perform a test of monitoring module 8 by coupling link 20 to GND or VCC to simulate a fault condition at component 14.

[0031] In any case, by simulating a fault condition at component 14, test module 10 can activate control module 12 to determine whether monitoring module 8 and driver 4 are correctly reporting a fault condition. In some examples, after simulating a fault condition at link 20, monitoring module 8 can detect a fault condition and output an error message to GSM module 6. GSM module 6 can then report the fault condition externally to control module 12 via link 16A. After activating test module 10, control module 12 can validate the functionality of driver 4's monitoring and protection features depending on whether or not control module 12 receives a fault condition message.

[0032] In this way, System 1 can ensure compliance with safety requirements (e.g., according to ISO standard 26262) without having to apply the interference protection features of Driver 4 and Component 14 to actual fault conditions. Instead, Control Module 12 can simply test the monitoring and protection features of System 1 by activating Test Module 10 to simulate a fault condition on Driver 4 and Component 14 and to perform a test. Thus, System 1 does not require any special hardware (e.g., at the board level) designed to inject currents outside the permissible range or otherwise introduce fault conditions intended to trigger the interference monitoring and protection features of Driver 4.As a result of the absence of additional hardware for injecting disturbances into System 1, System 1 can cost less, be smaller, and / or be less complex than other systems. By conducting tests using a simulated disturbance condition instead of an actual disturbance condition (e.g., an injected overcurrent), System 1 does not risk damaging Driver 4 and / or Component 14 if the monitoring and protection features (e.g., Monitoring Module 8) of Driver 4 fail.

[0033] Fig. Figure 2 is a flowchart illustrating exemplary operations of the control module 12 for testing the internal monitoring and protection logic of the driver 4 according to one or more aspects of the present disclosure. Fig. 2 is referred to below in the context of system 1. Fig. 1 described.

[0034] To test the monitoring and protection features of driver 4, at least one processor of control module 12 can be configured to perform operations 102-116. For example, control module 12 can contain non-volatile memory containing instructions which, when executed, configure at least one processor of control module 12 to perform operations 102-116.

[0035] During operation, the control module 12 can initially configure the test logic of driver 4 (102) to trigger driver 4 to perform tests of its monitoring and protection features. In some examples, driver 4 configuration can occur before each test. In some examples, driver 4 configuration can occur in a factory or manufacturing facility for driver 4. In some examples, driver 4 configuration can occur during the installation of driver 4 and / or system 1 in a larger system. In some examples, driver 4 configuration can occur each time system 1 is powered on (e.g., each time system 1 transitions from an idle or low-power state to full-power or other operating state).

[0036] In some examples, when configuring the test logic of driver 4, control module 12 can establish a defined delay window associated with driver 4. This defined delay window can specify a time that GSM module 6 must wait before reporting whether a fault condition has occurred at link 20. In other words, the defined delay time can correspond to an initial or maximum count value associated with the delay counter 9 of GSM module 6. Again, one purpose of the delay counter 9 is to provide monitoring module 8 with sufficient time to determine whether component 14 is experiencing a fault condition before GSM module 6 analyzes the information received from monitoring module 8 for any detected faults.In other words, the filter counter 9 prevents errors from being falsely received by the GSM module 6 during a transition phase of the gate control signal at link 16B, when the monitoring module 8 cannot necessarily detect fault conditions accurately.

[0037] In some examples, when configuring the test logic of driver 4, control module 12 can set a defined test threshold voltage associated with driver 4. This defined test voltage threshold can be used, for example, by desaturation monitoring features of driver 4 to determine whether desaturation has occurred at junction 20. For instance, during normal operation (not during a test of monitoring module 8), the desaturation monitoring features of monitoring module 8 can compare the voltage at junction 20 to the defined voltage threshold to determine if desaturation has occurred. During test operations (during a test of monitoring module 8), the desaturation monitoring features of monitoring module 8 can flag a desaturation fault if the voltage at junction 20 exceeds a lower voltage threshold.

[0038] In any case, after setting up the test logic of driver 4, control module 12 can trigger a test of driver 4 and start a timer used to measure the duration of the test (104). For example, control module 12 can send a signal to test module 10 via link 16C, causing test module 10 to simulate a fault condition at link 20. Control module 12 can trigger the test of driver 4 occasionally, for example, before starting system 1 (e.g., before it sends electrical power to a motor in a motor vehicle). In some examples, link 16C is a "static" or dedicated line for transmitting a test message / activation signal from control module 12.

[0039] The fade-out counter 9 is independent of the test signal at junction 16C. Fade-out counter 9 is triggered or reset as soon as the control signal at junction 16B transitions from off to on. If fade-out counter 9 is reset during the off / on transition of the gate control signal, the test of driver 4 begins.

[0040] When the fade-out counter reaches 9, the control module 12 can wait for a fault to be detected (106 / 108). For example, the control module 12 can query link 16A until the GSM module 6 of driver 4 reports a fault condition in response to the simulated fault condition caused by test module 10. If a fault is reported at link 16A by driver 4, the control module 12 can stop the timer used to measure the test duration (110). If no fault is reported at link 16A, the control module 12 can otherwise continue waiting for the fault to be reported at link 16A.

[0041] The control module 12 can stop (110) the timer used to measure the test duration and use the measured test duration to determine whether the fault monitoring and protection features of the driver 4 are functioning correctly. The control module 12 can compare the measured time with an expected time (112). For example, the expected time could be an average time or an average range of times that the driver 4 typically needs to report a simulated fault condition.

[0042] The control module 12 can determine that if the measured time does not exceed the expected time, the monitoring and protection features of the driver 4 are performing satisfactorily (114). However, in response to determining that the measured time exceeds the expected time (e.g., by a threshold), the control module 12 can then determine that a fault in the monitoring and protection feature of the driver 4 has occurred (118). After failing a test, the control module 12 can report a fault in the system 1 (e.g., by illuminating an engine warning light on the dashboard of a motor vehicle). In this way, the fault monitoring and protection features of the driver 4 can be triggered occasionally (e.g.,before electrical power is sent to component 14 and / or other components of system 1 (in other words, before a motor vehicle engine is running) and without risking damage to system 1 by unnecessarily injecting a disturbance condition (e.g., overcurrent or overvoltage) into system 1.

[0043] Fig. Figure 3 is a conceptual diagram illustrating driver 4A, which is trained to test the desaturation monitoring and protection logic of driver 4A according to one or more aspects of the present disclosure. Driver 4A is an example of driver 4 of system 1 and is referred to below in the context of system 1. Fig. 1 described. The driver 4A contains the gate signal module 6, the buffer 7, the test module 10A, the monitoring module 8A, the switch 32 and the element 30.

[0044] Driver 4A is coupled to component 14A, which in this case is an IGBT power module. The gate of component 14A is coupled to the output of driver 4A at junction 18. The desaturation pin of driver 4A is coupled via resistor-diode circuit 39 to the collector terminal or input of component 14A at junction 20. The emitter terminal or output of component 14A is coupled to the GND terminal of driver 4A.

[0045] The monitoring module 8A provides desaturation monitoring for the component 14A at the junction 20. The monitoring module 8A contains the comparator 24, the programmable threshold 26, and the pull-up resistor 22.

[0046] One input of comparator 24 can be connected to the programmable threshold 26 (e.g., a digital-to-analog input, a register, or another element for storing a voltage threshold). The other input of comparator 24 of monitoring module 8A can be connected to circuit 20 and pull-up resistor 22. Pull-up resistor 22 is connected to VCC. During testing of monitoring module 8A, circuit 20 is momentarily connected to GND via switch 32 (e.g., a clamping transistor). The output of comparator 24 provides information to GSM module 6 about whether the voltage at the desaturation pin of driver 4A is saturated or not.

[0047] Switch 32 can be a clamping transistor in some examples. Switch 32 may not require a special test mode for activation. In other words, switch 32 can be activated during normal operation: whenever information at link 16B reports that component 4 is OFF, or during a test, whenever the fade-out counter is incrementing. When activated, switch 32 connects the desaturation pin of driver 4A to link 20 and GND.

[0048] The programmable threshold 26 represents a reference voltage for determining whether the monitoring module 8 is operating correctly. In some examples, the value of the programmable threshold 26 can correspond to the expected voltage level at the desaturation pin of driver 4A. This expected voltage level corresponds to the voltage level at the desaturation pin of driver 4A at a predefined time after the link 20 has been disconnected from GND (e.g., by opening or disabling switch 32) and has been allowed to rise with the pull-up resistor 22. In some examples, the control module 12 can vary the value of the programmable threshold 26 to perform consistency checks of the monitoring module 8A to determine whether the monitoring module 8A correctly reports desaturation errors externally at changing, predefined times during a test after the link 20 has been decoupled from GND (e.g.with the opening or deactivation of switch 32) and with the pull-up resistor 22. In other words, the control module 12 can vary the value of the programmable voltage threshold 26 to perform consistency checks against the comparator 24 to determine whether the rise time associated with the desaturation pin of driver 4A changes accordingly.

[0049] The 4A driver also contains the 10A test module. The 10A test module contains element 30 and element 28.

[0050] Element 30 is shown as containing an OR gate where one input is connected to the output of the GSM 6's fade counter 9, and the other input is inverted and connected to link 16B. Other variations of element 30 exist. The purpose of element 30 is to enable or "close" switch 32 during normal and test operations, and also to connect the desaturation pin of driver 4A to link 20 at GND during the "fade-out period." That is, element 30 connects link 20 to GND during the period after fade counter 9 is initialized and until fade counter 9 reaches a maximum count (i.e., counts down to zero or up to a maximum). Element 30 also causes switch 32 to couple the desaturation pin of driver 4A at link 20 to GND whenever the gate control signal at link 16B is low (e.g., "OFF").After the fade-out period is over, or when the gate control signal at link 16B is high (e.g., "ON"), element 30 disables or "opens" terminal element 32, so that the desaturation pin of driver 4A at link 20 is not coupled to GND; instead, the desaturation pin is coupled to the input of component 14A for performing normal desaturation monitoring and protection operations.

[0051] Driver 4A also contains element 28, which is responsible for keeping driver 4A off and preventing any gate signal from link 17 to buffer 7 whenever test module 10A is performing a test. In this way, operations of component 14A controlled by gate signals from driver 4A are blocked during a test of monitoring module 8A (e.g., for safety reasons). In the example in Fig. Element 28 contains an AND gate and a D flip-flop. One input of the AND gate in element 28 is connected to junction 17, and the other input of the AND gate is connected to an output of the D flip-flop. The enable input of the D flip-flop in element 28 is connected to junction 16C. When element 28 is enabled by a signal at junction 16C and configured to test monitoring module 8A, element 28 prevents the generation of signal path 5A. When element 28 is disabled by a signal at junction 16C and configured to refrain from testing monitoring module 8A, element 28 allows the generation of signal path 5A, so that a gate signal output by GSM 6 can pass through junction 17 and element 28 and out to buffer 7.Element 28 prevents driver 4A from outputting a gate signal during a test of driver 4A's desaturation monitoring and protection feature.

[0052] The monitoring module 8A provides desaturation monitoring and protection by monitoring the voltage across the collector and emitter (V CEThe monitoring module 6 provides a signal to the GSM module 6 if the voltage deviates from the nominal value. For example, the monitoring module can determine whether component 14A, when switched to an ON state, will be able to pull its collector down to a level close to GND. If a fault condition occurs (e.g., a short circuit with a power supply causes excessive current), the fault condition can cause the collector of component 14A to remain high and not be pulled down to a level close to GND. If the output of component 14A remains high, the desaturation pin of driver 4A at junction 20 will also remain high (e.g., not pulled down by diode 39), and therefore comparator 24 will output a fault signal.

[0053] Instead of injecting an overcurrent at the input of component 14A to test whether the desaturation monitoring and protection feature provided by monitoring module 8A is working, test module 10A can simulate a fault condition at link 20 to trick monitoring module 8A into detecting a desaturation state, assuming monitoring module 8A is functioning correctly. If, in response to the simulated fault condition, monitoring module 8A correctly reports the desaturation state to GSM module 6 and control module 12, control module 12 can validate that monitoring module 8A is functioning correctly.

[0054] Fig. Figure 4 is a vibration curve diagram showing exemplary temporal and electrical characteristics of the driver 4A. Fig. 3 illustrated according to one or more aspects of the present disclosure, while the control module 12 tests the desaturation monitoring and protection logic of the driver 4A. Fig. 4 is discussed below in the context of Fig. 1 - 3 described.

[0055] Fig. Figure 4 illustrates the oscillation waveforms 202-210 between times t0 and t5. Oscillation waveform 202 corresponds to the gate control signal at junction 16B. Oscillation waveform 204 corresponds to the count value at the fade-out counter 9 when the fade-out counter 9 counts down from a maximum count value to zero. Oscillation waveform 206 represents the output of element 30, and oscillation waveform 208 represents the voltage at the desaturation pin of driver 4A at junction 20. Finally, oscillation waveform 210 represents the output of monitoring module 8A and / or the error signal at junction 16A.

[0056] At time t0, the gate control signal at junction 16B can be low, causing element 30 to activate switch 32, which in turn causes the voltage at the desaturation pin of driver 4A to be zero volts. At time t0, the fade-out counter 9 has not been initialized, and driver 4A is not outputting an error signal at junction 16A.

[0057] Sometime after time t0, control module 12 can trigger a test of the desaturation monitoring and protection features of driver 4A. Test module 10A can receive a signal from control module 12 via link 16C to trigger a test of monitoring module 8A. The signal received via link 16C can activate element 28 of test module 10A and prevent the signal path 5A from forming between GSM 6 and buffer 7 (e.g., to prevent a faulty gate signal at the gate terminal of component 14A during the test).

[0058] At time t1, when the gate control signal at junction 16B transitions from low (e.g., off) to high (e.g., on), the transition can cause the fade-out counter 9 to be initialized from a count of zero to a non-zero count. At time t2, the fade-out counter 9 can begin counting down the fade-out period. The duration D1 represents the fade-out period during which switch 32 connects the desaturation pin of driver 4A to GND.

[0059] At time t3, the fade-out counter 9 reaches a count of zero, and element 30 deactivates switch 32. Once deactivated, the voltage level at the desaturation pin of driver 4A begins to rise from GND for a duration D2 with a known RC time constant, otherwise referred to as the "rise time" associated with the desaturation pin of driver 4A. In other words, the "rise time" is the time it takes for the voltage level at the desaturation pin of driver 4A to rise from GND to the value of the programmable threshold 26, due to the pull-up resistor 22.

[0060] At time t4, the control module 12 can analyze the output from driver 4A at junction 16A to determine whether GSM module 6 and comparator 24 of monitoring module 8A are correctly reporting a desaturation fault in response to the test. At time t5, the control module 12 can first identify the desaturation fault reported at junction 16A. The time between times t4 and t5 corresponds to duration D3 and is referred to as the "reporting time." The reporting time is the time required by driver 4A to warn the control module 12 of a detected desaturation fault at junction 20.

[0061] To determine whether the desaturation monitoring and protection logic of driver 4A is functioning correctly, control module 12 can determine whether the desaturation fault reported at time t5 was reported in a timely manner. That is, if it causes driver 4A to perform a test of monitoring module 8A, control module 12 can expect a fault at link 16A to appear with a sufficient delay (e.g., in the area D1 + D2 + D3). However, if the fault at 16A appears too early, too late, or not at all, then something may be wrong with driver 4A, and control module 12 can take action to prevent system 1 from using driver 4A and / or component 14A.

[0062] The control module 12 can determine the difference between the measured total test time from t1 to t5 and an expected test time. By comparing the measured fault signaling delay with the expected delay value, the entire desaturation monitoring and protection feature (including the functionality of the fade-out counter 9) can be verified. In some examples, the control module 12 can vary the value of the programmable voltage threshold 26 to perform consistency checks for the comparator 24 to determine whether the rise time (duration D2) changes accordingly. In this way, a test of the desaturation monitoring and protection features of the driver 4A can be performed without having to turn on the device 14A. The functionality of the driver 4A can be verified and guaranteed before the device 14A is turned on.

[0063] Fig. Figure 5 is a conceptual diagram illustrating driver 4B, which is configured to test the overcurrent monitoring and protection logic of driver 4B according to one or more aspects of this disclosure. Driver 4B is an example of driver 4 of System 1 and is subsequently referred to in the context of System 1. Fig. 1 described.

[0064] Driver 4B is coupled to component 14B, which in this case is a dual-output or emitter IGBT power module. The gate of component 14B is coupled to the output of driver 4B at junction 18. The first output pin of component 14B is connected to the GND pin of driver 4B. The second output pin of component 14B is coupled via resistors 50B and 50C to the overcurrent protection pins of driver 4B at junctions 20A and 20B. In some examples, junction 20B is connected to GND at the board level. That is, the overcurrent protection pin of driver 4B is coupled to the second output of component 14B via resistor 50B at junction 20A. The overcurrent protection ground pin of driver 4B is coupled to the second output of component 14B via resistor 50C at junction 20B. Although Fig. 5. The comparator 48 of component 4B is shown to receive both the overcurrent protection pin and the overcurrent protection GND pin input to enable the sampling of small voltages. In some examples, the comparator 48 is a ground-referenced comparator that compares the overcurrent protection pin to GND; in this case, the overcurrent protection GND pin can be omitted.

[0065] Driver 4B contains monitoring module 8B, which provides overcurrent monitoring for component 14B at connections 20A and 20B. Monitoring module 8B provides overcurrent monitoring and protection by monitoring the current from the emitter of component 14B and outputs an error signal to GSM module 6 if the current reaches a maximum. Monitoring module 8B contains comparator 48.

[0066] As stated above, in the case where comparator 48 is a differential comparator, as stated in Fig. As shown in Figure 5, one input of comparator 48 is connected to the overcurrent protection ground pin of driver 4B at junction 20B. The other input of comparator 48 is connected to the overcurrent protection pin of driver 4B at junction 20A and also to the pull-up resistor 44 of test module 10B when switch 46 of test module 10B is open or closed. If comparator 48 is a ground-referenced comparator, its input is connected to the overcurrent protection pin of driver 4B at junction 20A. The output of comparator 48 provides information to GSM module 6 about whether an overcurrent condition exists at component 14B.

[0067] This means that the monitoring module 8B relies on the comparator 48 to monitor the current level through component 14B and output an error signal when the current reaches a maximum level. Resistor 50C is a shunt or sampling resistor with a resistance value selected according to the maximum current that component 14B can handle. When the current from component 14B indicates an overcurrent condition, the voltage difference between the two inputs of comparator 48 increases above a defined threshold, triggering comparator 48 to flag the high current as a fault condition. After a delay period, GSM module 6 can output the fault condition to control module 12 at link 16A. The delay period can mask any overcurrent faults that might be falsely reported during the transition phase after component 14B is switched on.

[0068] The driver 4A also contains the test module 10B. In addition to the switch 46, which, when activated, couples the overcurrent protection pin of the driver 4B to the link 20A with the pull-up resistor 44, the test module 10B contains the element 40 and the element 42.

[0069] Element 42 is used in the example in Fig. Element 42 is shown as a so-called "D flip-flop," although there are other examples. Element 42 is responsible for sending a test message signal to junction 19 for output buffer 7 (which in the example is shown in Fig. 5 (representing a dual-input buffer) whenever test module 10B performs a test of the overcurrent monitoring and protection features of driver 4B. The test message signal at junction 19 can prevent output buffer 7 from fully turning device 14B ON, even if a gate signal appears at junction 17. In other words, the test message signal at junction 19 can cause driver 4B to perform a "weak" ON turn on device 14B, or it can cause device 14B to remain OFF during a test. By providing an output at junction 19, element 42 can cause buffer 7 to ignore junction 17 during a test (e.g., path 5B is disabled).

[0070] For example, to perform a test of the overcurrent monitoring and protection features of driver 4B, driver 4B can excite component 14B to perform a "weak" ON switching. Component 14B will not switch ON strongly enough to provide a signal carrying sufficient current to generate an output at junctions 20A and 20B. To cause output buffer 7 to provide a weak ON signal at junction 18, control module 12 provides an enable signal at junction 16C whenever control module 12 triggers a test. Component 42 samples junction 16C and activates the test mode by enabling a signal at junction 19. In this way, during a test of monitoring module 8B, driver 4B outputs only a weak ON signal (i.e., a signal that is only slightly active).(less than full strength, or alternatively with less current than the current of an actual gate signal), but not an actual full-strength gate signal, to prevent a large current through device 14B. In some examples, the output buffer 7 may alternatively keep device 14B completely OFF during the test. The term "weak on or off" gate signal, as used here, may carry less current than a nominal gate signal used by a driver to keep a semiconductor device in an on or off state at times other than during a test.

[0071] Element 40 is shown as containing an AND gate where a first input is connected to the output of the GSM 6's fade-out counter 9, a second input is connected to link 16B, and a third input is connected to the output of element 42. Other variants of element 40 exist. The purpose of element 40 is to activate or "close" switch 46 and to connect the overcurrent protection pin of driver 4B at link 20A to pull-up resistor 44 after the "fade-out period" of a test of monitoring module 8B. That is, element 40 couples link 20A to pull-up resistor 44 after the fade-out counter 9 reaches a final count value (e.g., a maximum count value when counting up, or a minimum count value when counting down) and element 42 is activated, and whenever the gate control signal at link 16B is high (e.g., "ON").The test message signal at link 19 forces buffer 7 to send a weak ON signal or a completely OFF signal to 14B.

[0072] Instead of driving component 14B into an overcurrent state to test whether the overcurrent monitoring and protection feature provided by monitoring module 8B is working, test module 10B can simulate a fault condition at links 20A and 20B to trick monitoring module 8B into detecting an overcurrent condition if it is functioning correctly. Test module 10A can inject a simulated overcurrent condition at the overcurrent protection pin of driver 4B when switch 46 is closed. If, in response to the simulated fault condition, monitoring module 8B correctly reports the overcurrent condition to GSM module 6 and control module 12, control module 12 can validate that monitoring module 8B is functioning correctly.

[0073] Fig. Figure 6 is a vibration curve diagram showing exemplary temporal and electrical characteristics of the driver 4B. Fig. 5 is illustrated according to one or more aspects of the present disclosure, while the control module 12 tests the overcurrent monitoring and protection logic of the driver 4B. Fig. 6 is discussed below in the context of Fig. 1, Fig. 2 and Fig. 4 described.

[0074] Fig.Figure 6 illustrates the waveforms 302-310 between times t0 and t5. Waveform 302 corresponds to the gate control signal at junction 16B. Waveform 304 corresponds to the count value at the blanking counter 9 when the blanking counter 9 counts down from a maximum count value to zero. Waveform 306 represents the output of element 40, and waveform 308 represents the voltage at the overcurrent protection pin of driver 4B at junction 20A. Finally, waveform 310 represents the output of monitoring module 8B and / or the fault signal at junction 16A.

[0075] At time t0, the gate control signal at junction 16B may be low, causing element 40 to disable switch 46. This causes the voltage at the overcurrent protection pin of driver 4B to fluctuate near or around zero volts or GND, because 50C pulls to GND during normal and test mode operations (e.g., at junction 20B). At time t0, the fade-out counter 9 has not been initialized, and driver 4B does not output an error signal at junction 16A.

[0076] Sometime after time t0, control module 12 can trigger a test of the overcurrent monitoring and protection features of driver 4B. Test module 10B can receive a signal from control module 12 via junction 16C to trigger a test of monitoring module 8B. The signal received via junction 16C can activate element 42 of test module 10B to output a test message signal at junction 19. The test message signal can cause buffer 7 to send a weak ON signal or a completely OFF signal to the gate of device 14B at junction 18.

[0077] At time t1, when the gate control signal at junction 16B transitions from low (e.g., off) to high (e.g., on), the transition can cause the fade-out counter 9 to be initialized from a count of zero to a non-zero count. At time t2, the fade-out counter 9 can begin counting down the fade-out period. The duration D1 represents the fade-out period during which switch 46 refrains from coupling the overcurrent protection pin of driver 4B to pull-up resistor 44.

[0078] At time t2, the blanking counter 9 reaches a final count (e.g., zero). The outputs of blanking counter 9, element 42, and junction 16B cause element 40 to activate switch 46 at time t3. Once activated, a small current from junction 20A enters pull-up resistor 44, and the voltage level at the overcurrent protection pin of driver 4B at junction 20A begins to rise from GND over a duration D2 with a known RC time constant, otherwise referred to as the "rise time" associated with the overcurrent protection pin of driver 4B. In other words, the "rise time" is the time it takes for the voltage level at the overcurrent protection pin of driver 4B to rise from GND to a voltage threshold associated with test module 10B.

[0079] At time t4, the control module 12 can analyze the output from driver 4B at link 16A to determine whether GSM module 6 and comparator 48 of monitoring module 8B are correctly reporting an overcurrent fault in response to the test. At time t5, the control module 12 can first identify the overcurrent fault reported at link 16A. The time between times t4 and t5 corresponds to duration D3 and is referred to as the "reporting time." The reporting time is the time required by driver 4B to warn the control module 12 of a detected overcurrent fault at link 20A.

[0080] To determine whether the overcurrent monitoring and protection logic of driver 4B is functioning correctly, control module 12 can determine whether the overcurrent fault reported at time t5 was reported in a timely manner. That is, if it causes driver 4B to perform a test of monitoring module 8B, control module 12 can expect a fault at link 16A to appear with a sufficient delay (within the range of D1 + D2 + D3). However, if the fault at 16A appears too early, too late, or not at all, then something may be wrong with driver 4B, and control module 12 can take action to prevent system 1 from using driver 4B and / or component 14B.

[0081] The control module 12 can determine the difference between the measured total test time from t1 to t5 and an expected test time. By comparing the measured fault signaling delay with the expected delay value, the entire overcurrent monitoring and protection feature (including the functionality of the blanking counter 9) can be verified. In this way, the overcurrent monitoring and protection features of the driver 4B can be tested without having to turn on the component 14B, which would potentially cause high currents and compromise safety. The functionality of the driver 4B can be verified and guaranteed before the component 14B is turned on.

[0082] Clause 1. Gate driver comprising: a gate signal module configured to output a gate signal from the gate driver to drive a gate terminal of a semiconductor device; a test module configured to generate a simulated fault condition on a semiconductor device during testing of a monitoring and protection feature of the gate driver; and a monitoring module configured to output a message of the simulated fault condition in response to the detection of the simulated fault condition on the semiconductor device.

[0083] Clause 2. Gate driver according to Clause 1, further comprising: a fade-out counter configured to delay the output of the message of the simulated fault state for at least one transition phase of a gate control signal received from a control module by the gate signal module.

[0084] Clause 3. Gate driver according to one of Clauses 1 - 2, wherein the monitoring module is a monitoring and protection feature of the desaturation-type gate driver and is further configured to output a message of a desaturation state associated with the semiconductor device, which the monitoring module detects at a desaturation pin of the gate driver.

[0085] Clause 4. Gate driver according to Clause 3, further comprising a switch, wherein the test module is configured to generate the simulated fault condition at least by: closing the switch to clamp the desaturation pin of the gate driver to ground level during a fade-out period of the gate driver monitoring and protection feature test; and opening the switch after the fade-out period of the gate driver monitoring and protection feature test.

[0086] Clause 5. Gate driver according to Clause 4, wherein the monitoring module includes a pull-up resistor coupled to the desaturation pin of the gate driver and configured to increase a voltage at the desaturation pin from ground to a voltage threshold after the test module opens the switch following the fade-out period of the test of the monitoring and protection feature of the gate driver.

[0087] Clause 6. Gate driver according to one of Clauses 3 - 5, wherein the test module is further configured to generate the simulated fault condition at least by preventing the gate driver from outputting a gate signal to the semiconductor device during the test of the monitoring and protection feature of the gate driver.

[0088] Clause 7. Gate driver according to any of Clauses 1 - 2, wherein the monitoring module is a monitoring and protection feature of the overcurrent type gate driver and is further configured to output a message of an overcurrent condition associated with the semiconductor device which the monitoring module detects at an overcurrent protection pin of the gate driver.

[0089] Clause 8. Gate driver according to Clause 7, further comprising a switch, wherein the test module is configured to generate the simulated fault condition at least by: generating a weak on or off signal for output to the semiconductor device during the test of the gate driver's monitoring and protection feature, wherein the weak on or off gate signal carries less current than a nominal gate signal that holds the semiconductor device in an on state or an off state outside of the test; opening the switch before and during a fade-out period of the gate driver's monitoring and protection feature test to hold the gate driver's overcurrent protection pin at a ground level; closing the switch to clamp the gate driver's overcurrent protection pin at a voltage threshold after the fade-out period of the monitoring and protection feature test.

[0090] Clause 9. Gate driver according to Clause 8, wherein the test module includes a pull-up resistor coupled to VCC, wherein closing the switch to clamp the overcurrent protection pin of the gate driver to the voltage threshold after the fade-out period of the monitoring and protection feature test includes coupling the overcurrent protection pin to the pull-up resistor via the switch.

[0091] Clause 10. Gate driver according to any of Clauses 1 - 9, wherein the semiconductor device is a power switch comprising at least one metal-oxide-semiconductor field-effect transistor device or a bipolar transistor device with an insulated gate electrode.

[0092] Clause 11. Gate driver according to any of Clauses 1 - 10, wherein the monitoring module is further configured to output a message of an actual fault condition not attributed to the test module in response to the detection of the actual fault condition on the semiconductor device.

[0093] Clause 12. Gate driver according to any of Clauses 1 - 11, wherein the gate signal module is further configured to output the gate signal based on a control signal received by the gate driver from a control unit.

[0094] Clause 13. Method for testing a monitoring and protection feature of a gate driver, the method comprising: triggering a test of the gate driver's monitoring and protection feature by a control module, during which the gate driver simulates a fault condition associated with a semiconductor device; in response to receiving a fault message issued by the gate driver in response to the simulated fault condition, the control module measuring a time interval for the gate driver to issue the fault message after the test has been triggered; the control module comparing the measured time interval with an expected time threshold; and in response to determining that the measured time interval does not meet the expected time threshold, determining that a fault of the gate driver's monitoring and protection feature has occurred.

[0095] Clause 14. Procedure according to Clause 13, wherein the expected time threshold is based at least partly on a gate driver-related blocking period that prevents anomalies detected during the test from being output by the gate driver.

[0096] Clause 15. Procedure according to Clause 14, which further comprises: outputting a gate control signal to the gate driver by the control module, wherein the fade-out period occurs after a transition phase of the gate control signal.

[0097] Clause 16. Method according to any of Clauses 13 - 15, wherein the monitoring and protection feature of the gate driver comprises an overcurrent type gate driver monitoring and protection feature.

[0098] Clause 17. Method according to Clause 16, wherein the expected time threshold is based at least in part on a rise time associated with a voltage level at an overcurrent protection pin of the gate driver, wherein the rise time is an expected time period for the voltage level to rise from ground level to a voltage threshold attributable to a pull-up resistor associated with the gate driver after the overcurrent protection pin is pulled to the voltage threshold following the triggering of the test.

[0099] Clause 18. Method according to any of Clauses 13 - 17, wherein the monitoring and protection feature of the gate driver comprises a monitoring and protection feature of the gate driver of the desaturation type.

[0100] Clause 19. Method according to Clause 18, wherein the expected time threshold is based at least in part on a rise time associated with a voltage level at a desaturation pin of the gate driver, wherein the rise time is an expected time period for the voltage level to rise from ground level to a voltage threshold attributable to a pull-up resistor associated with the gate driver after the desaturation pin is subsequently pulled to ground following the triggering of the test.

[0101] Clause 20.A computer-readable storage medium comprising instructions which, when executed, configure at least one processor of a control module to test a monitoring and protection feature of a gate driver by at least the following: triggering a test of the gate driver's monitoring and protection feature during which the gate driver simulates a fault condition associated with a semiconductor device; in response to receiving a fault message issued by the gate driver in response to the simulated fault condition, measuring a time interval for the gate driver to issue the fault message after the test was triggered; comparing the measured time interval with an expected time threshold; and in response to determining that the measured time interval does not meet the expected time threshold, determining that a fault of the gate driver's monitoring and protection feature has occurred.

[0102] Clause 21. System comprising at least one processor and at least one module capable of being operated by the at least one processor to perform any of the procedures of Clauses 13 - 19.

[0103] Clause 22. System comprising means for carrying out any of the procedures of Clauses 13 - 19.

[0104] In one or more examples, the described operations can be implemented in hardware, processors, software, firmware, or any combination thereof. If implemented as software, the operations can be stored as one or more instructions or code on or transmitted via a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media can include computer-readable storage media that correspond to a physical medium, such as data storage media or transmission media, including any medium that enables the transfer of a computer program from one location to another, for example, according to a communication protocol.Computer-readable media can thus generally correspond to (1) physical, computer-readable storage media that are non-volatile, or (2) a communication medium, such as a signal or a carrier wave. Data storage media can be any available media that can be accessed by one or more computers or by one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. A computer program product can include a computer-readable medium.

[0105] As an example, and not limited to this: such computer-readable storage media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium used to store desired program code in the form of instructions or data structures and accessible by a computer. Likewise, any connection is correctly called a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL (Digital Subscriber Line), or wireless technologies such as infrared, radio, and microwaves, then the definition of the medium includes the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves.It is understood, however, that computer-readable storage media and data storage media do not contain connections, carrier waves, signals, or other transient media, but instead refer to non-transient, physical storage media. The terms "disk" and "disc," as used here, include CDs (Compact Discs), LaserDiscs, optical discs, DVDs (Digital Versatile Discs), floppy disks, and Blu-ray discs, whereby disks typically reproduce data magnetically, while discs reproduce data optically using a laser. Combinations of the above should also be included in the category of computer-readable media.

[0106] Instructions can be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FGPAs, or other equivalent integrated or discrete logic circuits. Accordingly, the term "processor," as used here, can refer to any of the aforementioned structures or to any other structure capable of implementing the techniques described herein. Additionally, some aspects of the functionality described herein can be provided in dedicated hardware and / or software modules. The techniques could also be implemented entirely in one or more circuits or logic elements.

[0107] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including a wireless handheld device, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices designed to perform the disclosed techniques, but which do not necessarily require implementation by different hardware units. Rather, as described above, different units can be combined in a single hardware unit or provided as a collection of cooperating hardware units, including one or more processors in conjunction with suitable software and / or firmware, as described above.

Claims

[1] Gate driver which features: a gate signal module (6) configured to output a gate signal from the gate driver (4) to control a gate terminal of a semiconductor device (14; 14A; 14B); a test module (10; 10A; 10B) configured to generate a simulated fault condition on the semiconductor device during a test of a monitoring and protection feature of the gate driver (4); and a monitoring module (8; 8A; 8B) which is configured to output a message about the simulated fault condition in response to the detection of the simulated fault condition at the semiconductor device (14). [2] Gate driver according to claim 1, further comprising: a blanking counter (9) which is configured to delay the output of the message about the simulated fault state at least for a transition phase of a gate control signal received by a control module through the gate signal module (6). [3] Gate driver according to claim 1 or 2, wherein the monitoring module (8; 8A; 8B) is a desaturation-type monitoring and protection feature of the gate driver (4) and is further configured to output a message about a desaturation state associated with the semiconductor device, which the monitoring module (8; 8A; 8B) detects at a desaturation pin (20) of the gate driver (4). [4] Gate driver according to claim 3, further comprising a switch (32), wherein the test module (10) is configured to generate the simulated fault condition at least by: Closing the switch (32) to clamp the desaturation pin (20) of the gate driver (4) to a ground level during a fade-out period of the test of the monitoring and protection feature of the gate driver (4); and Opening the switch (32) after the fade-out period of the test of the monitoring and protection feature of the gate driver (4). [5] Gate driver according to claim 4, wherein the monitoring module (8A) has a pull-up resistor (22) coupled to the desaturation pin (20) of the gate driver (4) and configured to increase a voltage at the desaturation pin (20) from ground to a voltage threshold after the test module (10A) opens the switch (32) after the fade-out period of the test of the monitoring and protection feature of the gate driver (4). [6] Gate driver according to claim 3, wherein the test module (10; 10A; 10B) is further configured to generate the simulated fault condition at least by preventing the gate driver (4) from outputting a gate signal to the semiconductor device (14; 14A; 14B) during the test of the monitoring and protection feature of the gate driver (4). [7] Gate driver according to any of the preceding claims, wherein the monitoring module (8B) is an overcurrent type monitoring and protection feature of the gate driver (4) and is further configured to output a message about an overcurrent condition associated with the semiconductor device (14B) which the monitoring module (8B) detects at an overcurrent protection pin (20A) of the gate driver (4). [8] Gate driver according to claim 7, further comprising a further switch (46), wherein the test module is configured to generate the simulated fault condition at least by: Generating a weak on or off gate signal for output to the semiconductor device (14B) during testing of the monitoring and protection feature of the gate driver (4), wherein the weak on or off gate signal carries less current than a nominal gate signal that holds the semiconductor device (14B) in an on state or an off state outside of testing; Opening the additional switch (46) before and during a fade-out period of the test of the monitoring and protection feature of the gate driver (4) in order to keep the overcurrent protection pin of the gate driver (4) at a ground level; Closing the further switch (46) to clamp the overcurrent protection pin (20A) of the gate driver (4) to a voltage threshold after the masking period of the monitoring and protection feature test. [9] Gate driver according to claim 8, wherein the test module (10B) comprises a pull-up resistor (44) coupled to VCC, wherein the closing of the further switch (46) to clamp the overcurrent protection pin of the gate driver (4) to the voltage threshold after the fade-out period of the test of the monitoring and protection feature comprises coupling the overcurrent protection pin (20A) to the pull-up resistor (44) via the further switch (46). [10] Gate driver according to any of the preceding claims, wherein the semiconductor device (14; 14A; 14B) is a power switch comprising at least one metal oxide semiconductor field-effect transistor device or a bipolar transistor device with an insulated gate electrode. [11] Gate driver according to any of the preceding claims, wherein the monitoring module (8; 8A; 8B) is further configured to output a message about an actual fault condition not attributed to the test module (10; 10A; 10B) in response to the detection of the actual fault condition at the semiconductor device (14; 14A; 14B). [12] Gate driver according to one of the preceding claims, wherein the gate signal module (6) is further configured to output the gate signal on the basis of a control signal received by the gate driver (4) from a control module (12). [13] Method for testing a monitoring and protection feature of a gate driver (4), wherein the method comprises: Triggering a test of the monitoring and protection feature of the gate driver (4) by a control module (12), during which the gate driver (4) simulates a fault condition associated with a semiconductor device (14; 14A; 14B); in response to receiving a message about an error, which is output by the gate driver (4) in response to the simulated fault condition, measuring a time interval required by the control module (12) for the gate driver (4) to output the error message after the test has been triggered; Comparing the measured time interval with an expected time threshold by the control module (12); and in response to the determination that the measured time interval does not meet the expected time threshold, the determination that a disturbance of the monitoring and protection feature of the gate driver (4) has occurred. [14] Method according to claim 13, wherein the expected time threshold is based at least partly on a blocking period associated with the gate driver (4) which prevents anomalies detected during the test from being output by the gate driver (4). [15] The method of claim 14, further comprising: Output of a gate control signal to the gate driver (4) by the control module (12), wherein the fade-out period occurs after a transition phase of the gate control signal. [16] Method according to any one of claims 13 to 15, wherein the monitoring and protection feature of the gate driver (4) comprises an overcurrent type monitoring and protection feature of the gate driver (4). [17] Method according to claim 16, wherein the expected time threshold is based at least partly on a rise time associated with a voltage level at an overcurrent protection pin (20A) of the gate driver (4), wherein the rise time is an expected time period for the voltage level to rise from ground level to a voltage threshold attributable to a pull-up resistor (44) associated with the gate driver (4) after the overcurrent protection pin is pulled to the voltage threshold following the triggering of the test. [18] Method according to any one of claims 13 to 17, wherein the monitoring and protection feature of the gate driver (4) comprises a desaturation-type monitoring and protection feature of the gate driver (4). [19] Method according to claim 18, wherein the expected time threshold is based at least partly on a rise time associated with a voltage level at a desaturation pin (20) of the gate driver (4), wherein the rise time is an expected time period for the voltage level to rise from ground level to a voltage threshold attributable to a pull-up resistor (22) associated with the gate driver (4) after the desaturation pin (20) is subsequently pulled to ground following the triggering of the test. [20] Computer-readable storage medium containing instructions which, when executed, configure at least one processor of a control module to test a monitoring and protection feature of a gate driver by at least the following: Triggering a test of the monitoring and protection feature of the gate driver (4) during which the gate driver (4) simulates a fault condition associated with a semiconductor device (14; 14A; 14B); in response to receiving a message of an error issued by the gate driver (4) in response to the simulated fault condition, measuring a time interval required by the gate driver to issue the error message after the test has been triggered; Comparing the measured time period with an expected time threshold; and in response to the determination that the measured time interval does not meet the expected time threshold, the determination that a disturbance of the monitoring and protection feature of the gate driver (4) has occurred.

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