Semiconductor package with integrated output inductance on a printed circuit board

Abstract

Semiconductor package comprising: a semiconductor chip (310) having a control transistor (152) and a sync transistor (154); an integrated output inductor (158; 358) having a winding around a core (222) coupled to the semiconductor chip (310); wherein the winding has several conductive clips (224) located over a printed circuit board (PCB) (270) and several conductive segments (226) in the PCB, wherein the conductive clips (224) are connected to the conductive segments (226).

Description

The present disclosure relates to a semiconductor package having an integrated output inductor on a printed circuit board (PCB).Power converters, such as voltage regulators, are used in numerous electronic circuits and systems. For example, integrated circuit (IC) applications may require conversion of a DC input voltage to a lower or higher DC output voltage. As an example, a buck converter may be implemented as a voltage regulator to convert a higher voltage DC input to a lower voltage DC output for use in low voltage applications. Semiconductor packaging solutions for power converters may be configured to accommodate power transistors and an output inductor.In conventional semiconductor packages, the output inductance used in the power converter is placed side by side with the power transistors and mounted over a top surface of a printed circuit board or substrate. The lateral placement of the output inductor with the other components increases the overall size of the semiconductor package. Also, in the conventional semiconductor packages, the output inductance is a preformed inductance having a relatively large form factor and poor thermal performance. Integrating the preformed inductance with the power transistors may further increase the overall form factor of the semiconductor package and degrade thermal performance.A further conventional semiconductor package is described in US 2013 / 0 056 847 A1. In this semiconductor package, a winding is disposed above a printed circuit board (PCB) and connected to the PCB via solder balls.US 2011 / 0 284 989 A1 describes a semiconductor package having an inductance and a semiconductor chip arranged on the inductance, which has connections which are connected to the inductance.US 2008 / 0 122 418 A1 describes a buck converter which is realized with switches based on a III-nitride semiconductor material.US 2009 / 0 167 477 A1 describes a power electronics package having a substrate and a power inductance arranged thereon. The inductor includes a core forming a closed loop. In the substrate, electrically conductive elements are arranged which form a lower part of a coil and which are connected to further electrically conductive elements which are arranged above the substrate and which form an upper part of the coil.DE 11 2012 002 725 T5 describes an integrated circuit which is manufactured with a number of layers. The integrated circuit includes a carrier and a transformer having a first winding, a second winding, and a magnetic core. The first winding and the second winding surround the magnetic core. The transformer is disposed above a first side of the carrier. A flux conductor is arranged on a second side of the carrier opposite the first side.The object on which the invention is based is to provide semiconductor packages with an integrated output inductance on a printed circuit board, with a reduced form factor, with improved thermal power loss and which are space-saving. This object is achieved by a semiconductor package according to any of claims 1 and 11.The present disclosure relates to a semiconductor package having an integrated output inductor on a printed circuit board (PCB).An example relates to a semiconductor package including a semiconductor die having a control transistor and a sync transistor and an integrated output inductor having a winding around a core and coupled to the semiconductor die. The winding includes a plurality of conductive clips located over a printed circuit board (PCB) and a plurality of conductive segments in the PCB, the conductive clips being connected to the conductive segments.Another example relates to a semiconductor package including an output integrated inductor having a winding around a core and a power stage stacked over the output integrated inductor. The power stage includes a control transistor and a sync transistor connected in a half bridge. The winding includes a plurality of conductive clips located over a printed circuit board (PCB) and a plurality of conductive segments in the PCB, the conductive clips being connected to the conductive segments.Hereinafter, examples will be explained with reference to the drawings. FIG. 1 shows a diagram of an example circuit suitable for use as a power converter, according to an implementation of the present disclosure. FIG. 2 shows a top view of an integrated output inductor according to an implementation of the present disclosure. FIG. 3A shows a top view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure. FIG. 3B illustrates a cross-sectional view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure. FIG. 3C illustrates a cross-sectional view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure.The following description contains specific information related to implementations in the present disclosure. The drawings in the present application and their accompanying detailed description relate to merely exemplary implementations. Unless otherwise indicated, the same or corresponding elements may be denoted by the same or corresponding reference numerals throughout the figures. Further, the drawings and illustrations in the present application are generally not to scale and are not intended to correspond to actual relative dimensions.Referring to FIG. 1, FIG. 1 shows an illustration of an example circuit suitable for use as a power converter, according to an implementation of the present disclosure. A power converter circuit 100 includes a power converter package 102 and an output capacitor 160. A power converter package 102 includes a power stage 110 and an output inductor 158. As shown in FIG. 1, the power stage 110 includes a high side or control transistor 152 (Q 1), which is coupled to a low side or sync transistor (synchronous rectifier transistor) 154 (Q 2) at the switched node 156, as well as a pulse width modulation (PWM) control and driver unit 150 coupled to the control transistor 152 and sync transistor 154. It is noted that the PWM control and driving unit 150 may be implemented as a PWM and control driver IC and is configured to provide driving signals to the corresponding gates of the control transistor 152 and the sync transistor 154. As further illustrated in FIG. 1, power converter circuit 100 is configured to receive an input voltage V IN, and provide a converted voltage, e.g., a rectified and / or stepped down voltage, as V AUS at output node 162.In the present implementation, the control transistor 152 and sync transistor 154 of the power stage 110 may take the form of metal oxide semiconductor field effect transistors (MOSFETs) configured as a half bridge, for example. That is, control transistor 152 may be coupled at switched node 156 to sync transistor 154, which in turn may be coupled through output inductor 158 to an output node 162. In some implementations, control transistor 152 and sync transistor 154 may be implemented as group IV-based power transistors, such as silicon power MOSFETs with a vertical or lateral design. In other implementations, the control transistor 152 and sync transistor 154 may be implemented as field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or high electron mobility transistors (HEMTs), for example. Generally, the control transistor 152 and sync transistor 154 may be implemented as group IV power transistors, such as silicon power transistors, or group III-V power transistors, such as gallium nitride (GaN) power transistors. In some implementations, it may be advantageous or desirable for at least one of the control transistor 152 and the sync transistor 154 to be implemented as a group III-V power transistor, such as a GaN power transistor. Power converter circuit 100 may be advantageously used, for example, as a buck converter in a variety of automotive, industrial, appliance, and lighting applications.It is noted that, in the interest of a simple and predictive description, the present inventive principles are described in some cases with reference to specific implementations of a buck converter that includes one or more silicon-based power FETs. However, it is emphasized that such implementations are exemplary only and the inventive principles disclosed herein find general application in a wide range of applications, including buck and boost converters implemented using power transistors based on another group IV material or based on a group III-V semiconductor.It is further noted that, as used herein, the phrase "group III-V" refers to a compound semiconductor that includes at least one group III element and at least one group V element. For example, a Group III-V semiconductor may take the form of a Group III nitride semiconductor containing nitrogen and at least one Group III element. For example, a III-nitride power transistor may be fabricated using gallium nitride (GaN), where the Group III element or elements may contain some or a substantial amount of gallium, but may also contain other Group III elements in addition to gallium.Referring to the drawings of the present application, it should be noted that the implementations of the present disclosure are described with respect to a power stage and an output inductance within a power semiconductor package, such as a semiconductor chip 310 of FIGS. 3A, 3B, and 3C on which a power stage is monolithically formed and an output inductance 358 integrated in the power semiconductor package 302. Each semiconductor die 310 in FIGS. 3A, 3B, and 3C may correspond to the power stage 110 of FIG. 1, and each integrated output inductor 358 may correspond to the output inductor 158 of FIG. 1. In some implementations, the semiconductor die 310 corresponding to the power stage 110 and the output integrated inductor 358 corresponding to the output inductor 158 may be electrically coupled together in a manner illustrated in the power converter circuit 100 of FIG. 1.As electronic devices and systems move toward increasingly smaller form factors, the large circuit board area still required to accommodate an output inductance, such as output inductance 158 in FIG. 1, becomes increasingly expensive. As such, the present application discloses a packaging solution that uses a stacked architecture that enables fabrication of a power semiconductor package that includes an output integrated inductor, but does not require substantially a larger area than a package that encloses only the power transistors and the driver circuit alone. Further, according to implementations of the present disclosure, conductive clips having unetched portions and partially etched portions and conductive segments in a PCB are used to form a continuous wire winding and embed a core in an interior space formed by the partially etched portions of the conductive clips, thereby further reducing the height or thickness of the package.Referring now to FIG. 2, FIG. 2 shows a top view of an integrated output inductor on a PCB, according to an implementation of the present disclosure. As shown in FIG. 2, the integrated output inductor 258 includes a core 222, conductive clamps 224 a, 224 b, 224 c, 224 d, 224 e, 224 f, and 224 g(collectively referred to as "conductive clamps 224"), conductive segments 226 a, 226 b, 226 c, 226 d, 226 e, 226 f, 226 g, and 226 h(collectively referred to as "conductive segments 226"), and the PCB 270. As shown in FIG. 2, conductive clips 224 are over PCB 270, while conductive segments 226 are formed in one or more metal layers (e.g., the top metal layer) in PCB 270, where conductive clips 224 are connected to conductive segments 226 to form a continuous winding of wire wrapped around and substantially embedding core 222.In the present implementation, the integrated output inductance 258 may correspond to the output inductance 158 in FIG. 1. As shown in FIG. 2, one end of the integrated output inductor 258 is coupled to the switched node pad 256 corresponding to the switched node 156 in FIG. 1, while the other end of the integrated output inductor 258 is coupled to the output node pad 262 corresponding to the output node 162 in FIG. 1.As shown in FIG. 2, conductive clips 224 a, 224 b, 224 c, 224 d, 224 e, 224 f, and 224 gare substantially parallel to and spaced apart from each other over PCB 270, while conductive segments 226 a, 226 b, 226 c, 226 d, 226 e, 226 f, 226 g, and 226 hare substantially parallel to and spaced apart from each other in PCB 270. As further shown in FIG. 2, the conductive brackets 224a, 224b, 224c, 224d, 224e, 224f, and 224g are disposed at a slightly oblique angle to the conductive segments 226a, 226b, 226c, 226d, 226e, 226f, 226g, and 226h. As a result of this arrangement, conductive clip 224a connects conductive segment 226a to conductive segment 226b. Conductive clip 224b connects conductive segment 226b to conductive segment 226c. Conductive clip 224c connects conductive segment 226c to conductive segment 226d. Conductive clip 224d connects conductive segment 226d to conductive segment 226e. Conductive clip 224e connects conductive segment 226e to conductive segment 226f. Conductive clip 224f connects conductive segment 226f to conductive segment 226g. Conductive clip 224g connects conductive segment 226g to conductive segment 226h.In the present implementation, the core 222 includes a ferrite core. In other implementations, the core 222 may include another suitable material, such as plastic, ferromagnetic, or ceramic material. In the present implementation, the conductive clips 224 a, 224 b, 224 c, 224 d, 224 e, 224 f, and 224 gmay each include a partially etched portion and at least one unetched portion, which are not expressly shown in FIG. 2.As shown in FIG. 2, I / O pads 230 are formed around the perimeter of the output integrated inductor 258 for electrical terminals for a power converter package, as described in detail below with reference to FIGS. 3A, 3B, and 3C. In some implementations, the conductive clips 224 a, 224 b, 224 c, 224 d, 224 e, 224 fand 224 g, conductive segments 226 a, 226 b, 226 c, 226 d, 226 e, 226 f, 226 gand 226 h, and I / O pads 230 may each include a conductive material having a high current carrying capacity and a suitably low electrical resistance. For example, the conductive clips 224, conductive segments 226, and I / O pads 230 may each include copper, aluminum, or a metallic alloy. The thickness, length, and depth of the integrated output inductor 258 may vary to meet the requirements of a particular application.Referring now to FIG. 3A, FIG. 3A shows a top view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure. As shown in FIG. 3A, semiconductor package 302 includes semiconductor die 310 stacked over output integrated inductor 358, where output integrated inductor 358 includes core 322, conductive clips 324 a, 324 b, 324 c, 324 d, 324 e, 324 f, and 324 g(collectively referred to as "conductive clips 324"), conductive segments 326 a, 326 b, 326 c, 326 d, 326 e, 326 f, 326 g, and 326 h(collectively referred to as "conductive segments 326"), and PCB 370. The semiconductor die 310 is stacked over and coupled to the output integrated inductor 358 by a die attach material (not explicitly shown in FIG. 3A ).In the present implementation, the semiconductor die 310 may include a power stage (not explicitly shown in FIG. 3A ) that may correspond to the power stage 110 in FIG. 1 monolithically integrated thereon. The semiconductor die 310 may include a high-side or control transistor (e.g., control transistor 152 in FIG. 1 ) coupled to a low-side or sync transistor (e.g., sync transistor 154 in FIG. 1 ) at a switched node (e.g., switched node 156 in FIG. 1 ). The semiconductor die 310 may also include a PWM control and driver unit (e.g., PWM control and driver unit 150 in FIG. 1 ) coupled to the control transistor and the sync transistor. In one implementation, the PWM control and driver unit may be implemented as a PWM and control driver IC and is configured to provide drive signals to the corresponding gates of the control transistor and the sync transistor. In an implementation, the power stage comprising the control transistor and the sync transistor is monolithically integrated on the semiconductor chip 310. It is noted that the PWM control and driver unit, the control transistor and the sync transistor are not explicitly shown in FIG. 3A, but may be monolithically integrated on the semiconductor chip 310 in any suitable method and / or any manner known in the art.In the present implementation, the semiconductor chip 310 may include a Group IV material such as silicon. In another implementation, the semiconductor chip 310 may include a group III-V material, such as gallium nitride (GaN). In some implementations, it may be advantageous or desirable for at least one of the control transistor and the sync transistor to be implemented as a group III-V power transistor, such as a GaN power transistor.In the present implementation, the output integrated inductance 358 may correspond to the output integrated inductance 258 in FIG. 2, which may correspond to the output inductance 158 in FIG. 1. Integrated output inductor 358 includes a switched node pad 356 and output node pad 362, which may correspond to switched node 156 and output node 162, respectively, in FIG. 1. As shown in FIG. 3A, the switched node pad 356 is coupled to the conductive segment 326 aat one end of the output integrated inductor 358, and the output node pad 362 is coupled to the conductive segment 326 hat the other end of the output integrated inductor 358. In one implementation, the conductive clips 324 and conductive segments 326 may each include a conductive material having a high current carrying capacity and a suitably low electrical resistance. For example, the conductive clips 324 and conductive segments 326 may each include copper, aluminum, or a metallic alloy. The thickness, length, and depth of the integrated output inductor 358 may vary to meet the requirements of a particular application.As shown in FIG. 3A, the conductive clips 324a, 324b, 324c, 324d, 324e, 324f, and 324g are substantially parallel to and spaced apart from each other over the PCB 370, while the conductive segments 326a, 326b, 326c, 326d, 326e, 326f, 326g, and 326h are substantially parallel to and spaced apart from each other within the PCB 370. As further illustrated in FIG. 3A, the conductive brackets 324a, 324b, 324c, 324d, 324e, 324f, and 324g are disposed at a slightly oblique angle to the conductive segments 326a, 326b, 326c, 326d, 326e, 326f, 326g, and 326h. As a result of this arrangement, conductive clip 324a connects conductive segment 326a to conductive segment 326b. Conductive clip 324b connects conductive segment 326b to conductive segment 326c. Conductive clip 324c connects conductive segment 326c to conductive segment 326d. Conductive clip 324d connects conductive segment 326d to conductive segment 326e. Conductive clip 324e connects conductive segment 326e to conductive segment 326f. Conductive clip 324f connects conductive segment 326f to conductive segment 326g. Conductive clip 324g connects conductive segment 326g to conductive segment 326h. As a result, the conductive clips 324 and conductive segments 326 are connected to form a continuous winding of wire around the core 322.The number of turns of the wire winding formed by the conductive brackets 324 a, 324 b, 324 c, 324 d, 324 e, 324 f, and 324 gand conductive segments 326 a, 326 b, 326 c, 326 d, 326 e, 326 f, 326 g, and 326 hmay range from several to several hundreds of turns. The conductive clips 324 a, 324 b, 324 c, 324 d, 324 e, 324 f, and 324 gare connected to the conductive segments 326 a, 326 b, 326 c, 326 d, 326 e, 326 f, 326 g, and 326 hby electrical connectors (not explicitly shown in FIG. 3A ). The electrical connectors may include solder bodies such as solder paste. In other implementations, the electrical connectors may take the form of an electrically conductive chip mounting material. For example, electrically conductive die attach materials may include conductive epoxies, conductive sintered materials, or diffusion bonded materials. For example, electrically conductive die attach materials may include conductive epoxies, conductive sintered materials, or diffusion bonded materials.In the present implementation, the core 322 includes a ferrite core. In other implementations, the core 322 may include another suitable material, such as plastic, ferromagnetic, or ceramic material. In the present implementation, the conductive clips 324 a, 324 b, 324 c, 324 d, 324 e, 324 f, and 324 gmay each include a conductive clip having a partially etched portion and at least one unetched portion, which are not expressly shown in FIG. 3A. The conductive segments 326 a, 326 b, 326 c, 326 d, 326 e, 326 f, 326 g, and 326 hmay be located below a top surface of the PCB 370 and each have a substantially uniform thickness. In one implementation, the conductive segments 326 a, 326 b, 326 c, 326 d, 326 e, 326 f, 326 g, and 326 hmay be segments of one or more metal layers (e.g., the top metal layer) in the PCB 370.The semiconductor package 302 also includes I / O pads 330 around the perimeter of the output integrated inductor 358, where the I / O pads 330 are electrically coupled to the semiconductor die 310, for example, by wire bonds 328. As shown in FIG. 3A, the wire bonds 328 are configured to electrically couple various terminals (not explicitly shown in FIG. 3A ) at a top surface of the semiconductor die 310 to corresponding I / O pads 330. Similarly, one or more wire bonds 328 are configured to electrically couple a switched node (e.g., switched node 156 in FIG. 1 ) of semiconductor die 310 to switched node pad 356 on conductive segment 326 a. In some implementations, wire bonds 328 may each include, for example, copper, gold, or other suitable conductive material. In other implementations, the wire bonds 328 may be replaced with conductive tapes or other connectors that include conductive materials such as aluminum, copper, gold, and / or other metals or composites.A package (not explicitly shown in FIG. 3A ) is configured to encapsulate the semiconductor die 310, the die attach material 312, the output integrated inductor 358, the wire bonds 328, and the I / O pads 330 to form an enclosed package. The package 334 may include any suitable substance, such as an encapsulant and / or potting compound, to provide mechanical and / or environmental protection for the semiconductor package 302. In some implementations, the semiconductor package 302 may be a quad flat no leads (QFN) package, such as a power QFN (PQFN) package.Referring now to FIG. 3B, FIG. 3B shows a cross-sectional view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure. In particular, FIG. 3B shows a cross-sectional view of a semiconductor package 302 along a line 380- 380 in FIG. 3A. While like reference numerals represent like features as in FIG. 3A, the semiconductor package 302 in FIG. 3B includes a semiconductor die 310 stacked over and attached to the output integrated inductor 358 by a die attach material 312. Integrated output inductor 358 includes, in part, a core 322 and a winding having a conductive clip 324c over PCB 370 and is connected to conductive segment 326d in PCB 370. As shown in FIG. 3B, semiconductor package 302 also includes I / O pads 330 on the periphery of output integrated inductor 358 and coupled to semiconductor chip 310 by wire bonds 328. A package 334 is configured to encapsulate the semiconductor die 310, the die attach material 312, the conductive clip 324c, and the core 222 of the output integrated inductor 358, the wire bonds 328, and the top pads 331 of the I / O pads 330.As shown in FIG. 3B, the conductive clip 324c includes unetched portions 323a and 323c and a partially etched portion 323b. The unetched portions 323 aand 323 ctentain a full thickness of the conductive clip 324 c, while the partially etched portion 323 bhas a thickness that is a fraction (e.g., half) of the full thickness of the conductive clip 324 c. In the present implementation, the unetched portions 323 aand 323 chave a substantially uniform thickness, which is the full thickness of the conductive clip 324 c. The partially etched portion 323b also has a substantially uniform thickness which is a fraction of the full thickness of the conductive clip 324c. The conductive segment 326d includes a conductive body having a substantially uniform thickness in the PCB 370.As shown in FIG. 3B, the conductive clip 324 cand the conductive segment 326 dform a winding around the core 322, with the unetched portion 323 aof the conductive clip 324 con one end (e.g., on the left side) of the integrated output inductor 358 electrically and mechanically coupled to the conductive segment 326 dusing an electrical connector 372, such as solder paste. The partially etched portion 323b of the conductive clip 324c forms a recess in the conductive clip 324c to provide an interior space for receiving or embedding the core 322. As shown in FIG. 3B, the core 322 has a lower surface that does not extend below a lower surface of each of the unetched portions 323 aand 323 cof the conductive bracket 324 c.It is noted that in the cross-sectional view shown in FIG. 3B, the conductive clip 324 cand the conductive segment 326 dare connected only at one end (e.g., on the left side) of the output integrated inductor 358. This is because the conductive clip 324c is over and disposed at a slightly oblique angle to the conductive segment 326d (as shown in Figure 3A). As a result of this arrangement, conductive segment 326 dis connected to an unetched portion (e.g., unetched portion 327 cin FIG. 3C ) of conductive clip 324 d(not expressly shown in FIG. 3B ), while unetched portion 323 cof conductive clip 324 cis connected to conductive segment 326 c(not expressly shown in FIG. 3B ). Thus, the conductive clips 324 and conductive segments 326 are connected to form a continuous winding of wire around the core 322 as shown in FIG. 3A.As shown in FIG. 3B, the wire bonds 328 are configured to electrically couple various terminals (not explicitly shown in FIG. 3B ) at a top surface of the semiconductor die 310 to corresponding I / O pads 330. In the present implementation, the I / O pads 330 each include an upper pad 331 connected to a lower pad 332 by an electrical connector 372, such as solder paste. In the present implementation, the top pad 331 of each I / O pad 330 includes an unetched portion and a partially etched portion, as shown in FIG. 3B. The bottom pad 332 of each I / O pad 330 is formed in the PCB 370 and has a substantially uniform thickness. In the present implementation, the conductive segment 326d and the bottom pads 332 of the I / O pads 330 may be formed in a single processing operation, while the conductive clip 324c and top pads 331 of the I / O pads 330 may be formed in a single processing operation. In the present implementation, conductive clip 324c, conductive segment 326d, and I / O pads 330 may each include any conductive material having high current carrying capacity and a suitably low electrical resistance, such as copper, aluminum, or a metallic alloy.As shown in FIG. 3B, in the present implementation, a package 334 encapsulates the semiconductor die 310, the die attach material 312, the conductive clip 324 cand the core 322 of the output integrated inductor 358, the wire bonds 328, and the top pads 331 of the I / O pads 330. The package 334 may include any suitable substance, such as an encapsulant and / or potting compound, to provide mechanical and / or environmental protection for the semiconductor package 302As shown in FIG. 3B, the conductive clip 324 cand the core 322 of the integrated output inductor 358 are over the PCB 370 and separated therefrom by a gap 336, such as an air gap. The gap 336 may provide sufficient clearance to allow for improved thermal dissipation by, for example, radiating heat directly to ambient air. In another implementation, the gap 336 may be eliminated from the semiconductor package 302 such that the conductive clip 324 cand the core 322 of the output integrated inductor 358, as well as the top pads 331 of the I / O pads 330, are above and in contact with the PCB 370.Referring now to FIG. 3C, FIG. 3C shows a cross-sectional view of a semiconductor package with an integrated output inductor, according to an implementation of the present disclosure. In particular, FIG. 3C shows a cross-section of a semiconductor package 302 along a line 390- 390 in FIG. 3A. While like reference numerals represent like features as in FIG. 3A, the semiconductor package 302 in FIG. 3C includes a semiconductor die 310 stacked over the output integrated inductor 358 and attached thereto by a die attach material 312. Integrated output inductor 358 includes, in part, a core 322 and a winding having a conductive clip 324d over PCB 370 and is connected to conductive segment 326d in PCB 370. As shown in FIG. 3C, semiconductor package 302 also includes I / O pads 330 on the periphery of output integrated inductor 358. The package 334 is configured to encapsulate the semiconductor die 310, the die attach material 312, the conductive clip 324d and the core 222 of the output integrated inductor 358, the wire bonds 328, and the top pads 331 of the I / O pads 330.As shown in FIG. 3C, conductive clip 324d, similar to conductive clip 324c in FIG. 3B, includes unetched portions 327a and 327c and a partially etched portion 327b. The unetched portions 327 aand 327 ctentain a full thickness of the conductive clip 324 d, while the partially etched portion 327 bhas a thickness that is a fraction (e.g., one-half) of the full thickness of the conductive clip 324 d. In the present implementation, the unetched portions 327 aand 327 chave a substantially uniform thickness, which is the full thickness of the conductive clip 324 d. The partially etched portion 327b also has a substantially uniform thickness which is a fraction of the full thickness of the conductive clip 324d. The conductive segment 326d includes a conductive body having a substantially uniform thickness in the PCB 370.As shown in FIG. 3C, the conductive clip 324d and the conductive segment 326d form a winding around the core 322, with the unetched portion 327c of the conductive clip 324d at one end (e.g., on the right side) of the integrated output inductor 358 electrically and mechanically coupled to the unetched portion 325c of the conductive segment 326d by an electrical connector 372, such as solder paste. The partially etched portion 327 bof the conductive bracket 324 dconstitutes a recess in the conductive bracket 324 dto provide an interior space for receiving or embedding the core 322. As shown in FIG. 3C, the bottom surface of the core 322 does not extend below a bottom surface of each unetched portion 327 aand 327 cof the conductive bracket 324 d.It is noted that in the cross-sectional view shown in FIG. 3C, the conductive clip 324d and the conductive segment 326d are connected only at one end (e.g., on the right side) of the output integrated inductor 358. This is because the conductive clip 324d is over and at a slightly oblique angle to the conductive segment 326d (as shown in Figure 3A). As a result of this arrangement, conductive segment 326d is connected to an unetched portion (e.g., unetched portion 323a in FIG. 3B) of conductive clip 324c (not expressly shown in FIG. 3C), while unetched portion 327a of conductive clip 324d is connected to conductive segment 326e (not expressly shown in FIG. 3C). Thus, the conductive clips 324 and conductive segments 326 are connected to form a continuous winding of wire around the core 322 as shown in FIG. 3A.As shown in FIG. 3C, the I / O pads 330 each include an upper pad 331 connected to a lower pad 332 by an electrical connector 372, such as solder paste. The top pad 331 of each I / O pad 330 may include an unetched portion and a partially etched portion, as shown in FIG. 3C. The bottom pad 332 of each I / O pad 330 is formed in the PCB 370 and has a substantially uniform thickness. In the present implementation, the conductive segment 326d and the bottom pads 332 of the I / O pads 330 may be formed in a single processing operation, while the conductive clip 324d and the top pads 331 of the I / O pads 330 may be formed in a single processing operation. In the present implementation, conductive clip 324d, conductive segment 326d, and I / O pads 330 may each include any conductive material having high current carrying capacity and a suitably low electrical resistance, such as copper, aluminum, or a metallic alloy.As shown in FIG. 3C, in the present implementation, the package 334 encapsulates the semiconductor die 310, the die attach material 312, the conductive clip 324d and the core 322 of the output integrated inductor 358, and the top pads 331 of the I / O pads 330. The package 334 may include any suitable substance, such as an encapsulant and / or potting compound, to provide mechanical and / or environmental protection for the semiconductor package 302.As shown in FIG. 3C, the conductive clip 324d and the core 322 of the integrated output inductor 358 are over the PCB 370 and are separated therefrom by a gap 336, such as an air gap. The gap 336 may provide sufficient clearance to allow for improved thermal dissipation by, for example, radiating heat directly to ambient air. In another implementation, the gap 336 may be eliminated from the semiconductor package 302 such that the conductive clip 324d and the core 322 of the output integrated inductor 358, as well as the top pads 331 of the I / O pads 330, are over and in contact with the PCB 370.As shown in FIGS. 3A, 3B, and 3C, since the core 322 of the output integrated inductor 358 is embedded in the interior space formed by the partially etched portions of the conductive clips 324, the overall height of the output integrated inductor 358 may be significantly reduced, which in turn reduces the form factor of the semiconductor package 302. Since the semiconductor die 310 is over the integrated output inductor 358, unlike conventional power semiconductor packages having individual semiconductor dies disposed side by side with output inductors over a top surface of a PCB, according to the present implementation, the semiconductor package 302 may advantageously have a reduced footprint, thereby further reducing the form factor of the semiconductor package 302. Further, because the conductive segments 326 in the PCB 370 are used to connect to the conductive clips 324 over the PCB 370 to form a continuous winding around the core 322, a portion of the integrated output inductor 358 is formed in the PCB 370, further reducing the overall height of the integrated output inductor 358.Likewise, by using conductive clips 324 and conductive segments 326 to form a continuous winding of wire around the core 322, with a space between each adjacent pair of conductive clips 324, the housing 334 can occupy the recesses formed by the partially etched portions of the conductive clips 324 around the core 322 to provide mechanical support and hold the core 322 in position. Similarly, the package 334 may encapsulate the semiconductor die 310 and the integrated output inductor 358 in a single processing operation, thereby saving manufacturing time and cost. The package 334 may have excellent thermal conductivity to conduct heat away from the semiconductor die 310 and the integrated output inductor 358. Additionally, because the core 322 is exposed at the bottom surface, the semiconductor package 302 may provide improved thermal dissipation by radiating heat directly to ambient air, for example.

Claims

A semiconductor package comprising: a semiconductor die (310) comprising a control transistor (152) and a sync transistor (154); an integrated output inductor (158; 358) comprising a winding around a core (222) and coupled to the semiconductor die (310); wherein the winding comprises a plurality of conductive clips (224) located over a printed circuit board (PCB) (270) and a plurality of conductive segments (226) in the PCB, wherein the conductive clips (224) are connected to the conductive segments (226).The semiconductor package of claim 1, wherein the control transistor (152) and the sync transistor (154) are configured as a half bridge.The semiconductor package of claim 2, wherein the integrated output inductor (158) is coupled to a switched node (156) of the half bridge.The semiconductor package of any preceding claim, wherein at least one of the plurality of conductive clips (224) includes a partially etched portion and an unetched portion.The semiconductor package of any preceding claim, wherein the semiconductor die (310) further comprises a driver integrated circuit (150) coupled to the control transistor (152) and the sync transistor (154).The semiconductor package of any preceding claim, wherein at least one of the control transistor (512) and the sync transistor (154) comprises a group III-V transistor.The semiconductor package of any preceding claim, wherein at least one of the control transistor (152) and the sync transistor (154) comprises a group IV transistor.The semiconductor package of any preceding claim, wherein the core (222) is a ferrite core.The semiconductor package of any preceding claim, wherein the semiconductor die (310) is over the integrated output inductor (358) and is attached thereto by a die attach material.The semiconductor package of any preceding claim, wherein the semiconductor die (310) and the integrated output inductor (358) are encapsulated in a potting compound.A semiconductor package comprising: an integrated output inductor (158; 358) comprising a winding around a core (222); a power stage (110) stacked over the integrated output inductor (158; 358), the power stage (110) comprising a control transistor (152) and a sync transistor (154) connected in a half bridge; wherein the winding comprises a plurality of conductive clips (224) located over a printed circuit board (PCB) (270) and a plurality of conductive segments (226) in the PCB, wherein the conductive clips (224) are connected to the conductive segments (226).The semiconductor package of claim 11, wherein at least one of the plurality of conductive clips (224) includes a partially etched portion and an unetched portion.The semiconductor package of claim 11 or 12, wherein the integrated output inductor (158) is coupled to a switched node (156) of the half bridge.The semiconductor package of any of claims 11 to 13, wherein the power stage (110) further comprises a driver integrated circuit (150) coupled to the control transistor (152) and the sync transistor (154).The semiconductor package of any of claims 11 to 14, wherein the core (222) is a ferrite core.The semiconductor package of any of claims 11 to 15, wherein at least one of the control transistor (152) and the sync transistor (154) comprises a group III-V transistor.The semiconductor package of any of claims 11 to 16, wherein at least one of the control transistor (152) and the sync transistor (154) comprises a group IV transistor.The semiconductor package of any of claims 11 to 17, wherein the control transistor (152) and the sync transistor (154) are monolithically integrated on a semiconductor die (310).The semiconductor package of claim 18, wherein the semiconductor chip (310) is attached to the integrated output inductor by a chip attach material.The semiconductor package of any of claims 11 to 19, wherein the power stage (110) and the integrated output inductor (358) are encapsulated in a potting compound.

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