Serial capacity tuner

Abstract

Impedance matching network (104, 204, 400, 500), comprising: a first signal terminal (212, 302, 402, 502) configured to receive a signal from a source circuit (102, 202); a second signal terminal (214, 304, 404, 504) configured to provide the signal to a load circuit (106, 206); a series branch comprising a variable capacitive component (208, 300, 350, 401, 501) between the first signal terminal (212, 302, 402, 502) and the second signal terminal (214, 304, 404, 504), wherein the variable capacitive component (208, 300, 350, 401, 501) comprises a plurality of series-connected capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508), wherein at least one of the capacitive sections comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N), and a control component (210, 426, 526) configured to control a capacitance of the variable capacitive component (208, 300, 350, 401, 501) by controlling at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) based on a predetermined algorithm, wherein the at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprises a first capacitive section comprising a first switching element comprising a stack of series-connected transistors, and a second capacitive section comprising a second switching element comprising a stack of series-connected transistors, wherein the control component (210, 426, 526) is configured to switch the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520) on or off in series in steps of one in a predetermined direction according to the predetermined algorithm in order to avoid voltage overload.

Description

Technical area

[0001] The present invention relates to impedance tuning systems and, more particularly, to a capacitor tuner for adjusting antenna impedance and a related method. background

[0002] In electrical or electronic systems, optimal power transfer between an electrical power source and an electrical load is achieved when the load impedance is equal to the source impedance. Current radio frequency (RF) or radio frequency (HF) front-end systems, such as a mobile communications network, typically include a transceiver, a power amplifier, a harmonic filter, an antenna switch, an antenna matching network, and an antenna. The antenna matching network is designed to improve power transfer between the transceiver and the antenna by matching the impedance of the transceiver to the impedance of the antenna feedline.

[0003] With advances in mobile communication technology, the frequency spectrum of mobile communication frequencies is becoming increasingly broader, and the antenna itself also requires different impedance matching settings for different environmental conditions. The impedance matching network must therefore be selected taking into account the various possible operating frequencies and impedances. Furthermore, the advanced design requirements of mobile communication systems impose size constraints on the impedance matching network.

[0004] US 2014 / 009248 A1 discloses an impedance network with multiple capacitors, each of which can be bridged by a switch. The switches can be implemented as transistors, in particular as stacked transistors with a common control.

[0005] US 2013 / 258 535 A1 and DE 10 2013 220 362 A1 also disclose adjustable impedance networks in which stacked transistors are used as switches.

[0006] It is therefore a task to provide improved possibilities for impedance matching. Summary

[0007] An impedance matching network according to claim 1, a capacitance tuner device according to claim 13 and a method according to claim 23 are provided. The subclaims define further embodiments. Short description of the drawings

[0008] In the following, the disclosure is further explained and described by means of specific embodiments with reference to the accompanying drawings. Fig. 1 illustrates a block diagram of a mobile communication network having an impedance matching network according to an embodiment of the disclosure; Fig. 2 illustrates another block diagram of a mobile communication network having an impedance matching network according to another embodiment of the disclosure; Fig. 3A illustrates a schematic diagram of a variable capacitive element according to an embodiment of the disclosure; Fig. 3B illustrates a schematic diagram of a switching element comprising a stack of series-connected transistors, according to an embodiment of the disclosure; Fig. 4 illustrates a schematic diagram of an impedance matching network with a variable capacitive element according to an embodiment of the present disclosure; Fig. 5 illustrates a schematic diagram of an impedance matching network with a bridging element according to another embodiment of the present disclosure; and Fig. 6 illustrates a flowchart of a method for adjusting an impedance according to an embodiment of the present disclosure. Detailed description

[0009] In one embodiment of the disclosure, an impedance matching network includes a first signal terminal configured to receive a signal from a source circuit, a second signal terminal configured to provide the signal to a load circuit, and a series branch comprising a variable capacitive component between the first signal terminal and the second signal terminal. The variable capacitive component element includes a plurality of series-connected capacitive portions, wherein at least one of the capacitive portions includes a switching element comprising a stack of series-connected transistors. The impedance matching network further includes a control component configured to control a capacitance of the variable capacitive component by controlling the at least one of the capacitive portions comprising the switching element based on a predetermined algorithm.

[0010] In another embodiment of the disclosure, a capacitance tuner device comprises a variable capacitive component comprising a plurality of capacitive elements in series. At least one of the plurality of capacitive elements comprises a switching element comprising a stack of series-connected transistors, and a combination of the blocking capacitances of the transistors provides a capacitance of the capacitive element comprising the switching element. The capacitance tuner device further comprises a control unit configured to generate a total capacitance of the variable capacitive component by switching the at least one capacitive element comprising the switching element on and off based on a predetermined algorithm.

[0011] In another embodiment of the disclosure, a method for adjusting an impedance comprises determining or estimating a source impedance of a signal source and determining or estimating a drain impedance of a signal sink. The method further comprises adjusting an impedance matching network based on the source impedance and the drain impedance by adjusting a variable capacitive component that is part of the impedance matching network, wherein the variable capacitive component comprises a plurality of series-connected capacitive elements, wherein at least one of the capacitive elements comprises a switch element that comprises a stack of series-connected transistors.

[0012] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As used herein, the terms "component," "system," "interface," "element," and the like are intended to refer to a computer-related entity, hardware, software (e.g., executing), and / or firmware. For example, a component may be a process, a process executing on a processor, a controller, an object, an executable program, a storage device, and / or a computer having a processing device. Illustratively, an application executing on a server and the server may also be a component.One or more components may be located within a process, and a component may be located on a single computer and / or distributed between two or more computers. A set of elements or a set of other components may be described herein, where the term "set" may be interpreted as "one or more."

[0013] As another example, a component may be a device with specific functionality provided by mechanical parts operated by electrical or electronic circuitry, where the electrical or electronic circuitry may be operated by a software application or a firmware application executed by one or more processors. The one or more processors may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component may be a device that provides specific functionality through electronic components without mechanical parts; the electronic components may include one or more processors therein to execute software and / or firmware that provides, at least in part, the functionality of the electronic components.

[0014] The use of the word "exemplary" is intended to introduce concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied under each of the foregoing. Additionally, the articles "a," "an," and their declensions, as used in this application and the appended claims, should generally be construed to mean "one or more" unless otherwise stated or it is clear from the context that the singular form is referred to.Furthermore, to the extent that the terms “including,” “includes,” “having,” “comprising,” “with,” or variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

[0015] In the following description, numerous details are set forth to provide a more detailed explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure. Additionally, features of the various embodiments described below may be combined with one another unless expressly noted otherwise.

[0016] This disclosure is directed to a serial capacitance tuner for adjusting an impedance and a method for operating the serial capacitance tuner. In wireless communication systems for the radio frequency (RF), high frequency (HF), or other frequency ranges, a so-called front-end system may be provided. Such a front-end system may be part of a mobile station (e.g., a mobile phone, smartphone, tablet computer, USB modem) or a base station (e.g., a base transceiver station BTS) of a mobile communication network. The front-end system may typically include a transceiver, a power amplifier, a harmonic filter, an antenna switch, an impedance matching network, and an antenna.The impedance matching network is typically connected between a radio transmitter or receiver and its antenna to improve power transfer between them by matching the transceiver's impedance to the antenna's feedline. In some implementations, the impedance matching network operates to convert the antenna impedance, thereby matching the antenna impedance to the transceiver's impedance. Typically, an RF or HF front-end system can be configured to support multiple transmit frequencies and / or multiple mobile communication standards.

[0017] Since the RF front-end system can be configured to support multiple frequencies, mobile communication standards, and / or other parameters associated with transmitting or receiving radio signals, the impedance matching network can be selected to account for the various possible use cases, frequencies, and operating modes, as well as their respective probabilities, to provide a weighted optimum. This task becomes increasingly difficult as the frequency spectrum of mobile communication frequencies becomes increasingly broader and the antenna itself also requires different impedance matching settings for different environmental conditions.

[0018] To cover a wide range of possible impedances, adjustable impedance matching networks are typically used. The impedance matching network can be implemented as a basic LC network comprising a serial inductor and an adjustable capacitor, connected in parallel to an output of the impedance matching network. In conventional systems, the adjustable capacitance is typically implemented using expensive radio frequency microelectromechanical systems (RF MEMS) capacitors or barium strontium titanate (BST) capacitors, or simple RF switches with external components. In one implementation, the adjustable capacitor comprises three parallel branches, each branch comprising a capacitor element connected in series with a switch element.The use of external components provides design flexibility, but incurs significant losses, and the space requirement is proportional to the number of states used. To provide a less expensive and less lossy alternative, the present disclosure presents a serial capacitive tuner comprising a series capacitor topology. In some implementations, the serial capacitor tuner comprises a plurality of capacitive sections integrated into a single chip, thereby avoiding the use of external components and reducing size.

[0019] Fig. 1 shows an example front-end system 100, for example, a mobile communications network, according to the present disclosure, comprising a source circuit 102, a load circuit 106, and an impedance matching network 104 between the source circuit 102 and the load circuit 106. The source circuit 102 is configured to provide a signal 103 to be transmitted to the load circuit 106 via the impedance matching network 104. The source circuit 102 may, for example, comprise a transceiver, a power amplifier, a harmonic filter, and an antenna switch. When functioning in a transmitter mode of operation, in one implementation, the transceiver may provide a transmit signal (e.g., signal 103) to the power amplifier at its output. An amplified transmit signal provided by the power amplifier is connected to the harmonic filter, which reduces frequency components of the amplified transmit signal outside an intended transmit frequency range.An output of the harmonic filter is connected to one of the plurality of inputs of the antenna switch. The antenna switch may be configured to connect the inputs to the antenna switch output. The antenna switch output may be connected to an input of the impedance matching network 104.

[0020] The impedance matching network 104 may, for example, comprise an LC network configured to convert the impedance of the load circuit 106 to match the impedance of the source circuit 102. In one embodiment, the LC network may comprise a series combination of an inductor and an adjustable capacitor. The adjustable capacitor may comprise a variable capacitive element comprising a plurality of capacitive elements, and the variable capacitive element may be configured to operate in different adjustable states, each of which provides a different capacitor value.For example, in a first adjustable state, a first set of capacitive elements is activated to provide a first capacitance value, and in a second adjustable state, a second set of capacitive elements is activated to provide a second capacitance value, wherein the first capacitance value and the second capacitance value are different from each other. The different adjustable states of the variable capacitive element can be configured based on control signals from a control unit. One or more of the plurality of capacitive elements in the variable capacitive element can be implemented as switches, each of which can be turned on or off based on the control signals from the control unit. Each of the switches can comprise a stack of series-connected transistors, and the blocking capacitance of each of these transistors contributes to the capacitance of the switches.Additionally, in some implementations, capacitance from metal-insulator-metal (MIM) and / or metal-metal capacitors also contributes to the capacitance of the switches. Furthermore, in some implementations, each of the transistors in the stack is designed to have a high transistor width, thus achieving a low R. on (on resistance of the transistors) and thereby reduce the loss.

[0021] The load circuit 106 may include an antenna and is configured to receive a signal 105 to be transmitted from the impedance matching network 104. The load circuit 106 may be operated to provide different input impedance values ​​under different environmental conditions. Based on the input impedance of the load circuit 106, the impedance matching network 104 is operated to provide an impedance that converts the input impedance of the load circuit to match the impedance of the source circuit 102. By matching the impedance of the load circuit 106 to the impedance of the source circuit 102, the impedance matching network 104 provides maximum power transfer between the source circuit 102 and the load circuit 106.

[0022] Fig. Figure 2 illustrates another embodiment of a mobile communications network 200 according to the present embodiment. The mobile communications network 200 includes a source circuit 202 configured to provide a signal 203 to be transmitted to a load circuit 206. The mobile communications network 200 further includes an impedance matching network 204 configured to convert the impedance of the load circuit 206 to match the impedance of the source circuit 202. The impedance matching network 204 includes a first signal terminal 212 configured to receive the signal 203 from the source circuit 202 and a second signal terminal 214 configured to provide a signal 205 to the load circuit 206. The impedance matching network 204 further includes a series branch comprising a coil 207 and a variable capacitive element 208 connecting the first signal terminal 212 and the second signal terminal 214.

[0023] In a particular embodiment, the variable capacitive element 208 may comprise a plurality of series-connected capacitive sections. At least one of the capacitive sections may be implemented as a switching element comprising a transistor. In some implementations, the capacitive sections implemented as switching elements may comprise a stack of series-connected transistors, and a combination of the blocking capacitances of all the series-connected transistors in the stack contributes to the capacitance of the capacitive sections. Furthermore, MIM capacitors and / or metal-to-metal capacitors in parallel with the stack of transistors in the switching elements may also contribute to the capacitance of the capacitive sections implemented as switching elements.Additionally, the variable capacitive element 208 may comprise capacitive sections, with the capacitance being contributed by the MIM capacitance or the metal-to-metal capacitance alone.

[0024] The impedance matching network 204 further includes a control circuit 210 configured to provide control signals to control the capacitive sections implemented as switching elements. In one embodiment, the capacitive sections implemented as switching elements are switched on and off by the control circuit 210 based on a predetermined algorithm, thereby controlling the capacitance of the variable capacitive element 208. The predetermined algorithm may include switching the capacitive sections implemented as switching elements in a predetermined direction to avoid voltage overload. In some implementations, the control circuit 210 includes a thermometer code decoder. In other implementations, the control circuit 210 may include other control algorithms that differ from the thermometer code.

[0025] Fig. Figure 3a illustrates a variable capacitive element 300 according to an embodiment of the disclosure. The variable capacitive element 300 includes a series branch comprising a plurality of capacitive sections C1 306, C2 308, C3 310, C4 312, and C5 314 between a first signal terminal 302 and a second signal terminal 304. The capacitive sections C2 308, C3 310, and C4 312 each include switching elements S1 316, S2 318, and S3 320, and are configured to be turned on or off based on control signals from a control unit. Each of the first, second and third switching elements S1 316, S2 318 and S3 320 comprises a stack of series-connected transistors, and they advantageously utilize the blocking capacitance of a transistor, in particular a field-effect transistor, although the blocking capacitance C offtypically considered a parasitic undesirable phenomenon of field-effect transistors. A combination of the blocking capacitances of the stack of series-connected transistors and the MIM capacitance and / or metal-to-metal capacitances contribute to the total capacitance of the first, second, and third switching elements S1 316, S2 318, and S3 320, respectively. In one embodiment, the capacitive portions C2 308, C3 310, and C4 312 are configured to provide equal capacitance values, and in other embodiments, the capacitance values ​​may be different.

[0026] In one embodiment, the switching elements S1 316, S2 318, and S3 320 are switched in one-step in a predetermined direction based on the control signals from the control unit. For example, in one implementation, the first switching element S1 316 is turned off first, followed by the second switching element S2 318, and then the third switching element S3 320. The number of transistors in the first, second, and third switching elements S1 316, S2 318, and S3 320 may vary and is derived based on the expected voltage across the switching element at the stage in which the corresponding switching element is turned off. For example, in one embodiment, the number of transistors in S1 316 is greater than the number of transistors in S2 318, and the number of transistors in S2 318 is greater than the number of transistors in S3 320.

[0027] Furthermore, the variable capacitive element 300 includes two capacitive sections C1 306 and C5 314 implemented as MIM capacitors and / or metal-to-metal capacitors, which provide fixed capacitance values. The capacitive sections C1 306 and C5 314 may also include a plurality of series-connected MIM capacitors and / or metal-to-metal capacitors, and the number of MIM capacitors and / or metal-to-metal capacitors in the capacitive sections C1 306 and C5 314 is derived based on the anticipated voltage across the capacitive sections C1 306 and C5 314 when the first, second, and third switching elements S1 316, S2 318, and S3 320 are turned on.In addition, the variable capacitive element 300 comprises a first sub-branch comprising a first electrostatic discharge (ESD) protection element ESD1 322 between the first signal terminal 302 and a reference potential terminal 326, and a second sub-branch comprising a second electrostatic discharge (ESD) protection element ESD2 324 between the second signal terminal 304 and the reference potential terminal 326.

[0028] Fig. 3b illustrates a switching element 350 comprising a stack of series-connected transistors. In one embodiment, the switching element 350 may be similar to the switching element S1 316 of Fig. 3a. The switching element 350 comprises a plurality of series-connected transistors 352a, 352b up to 352N, where N can be any integer. The number of transistors N is derived based on the expected voltage across the switching element 350 in the stage in which the corresponding switching element is turned off. When the transistors are turned off, a blocking capacitance, for example, 354, and the blocking capacitances of each of the series-connected transistors contribute to the capacitance of the switching element 350. In addition, the MIM capacitance and / or the metal-to-metal capacitance also contribute to the total capacitance of the switching element 350.

[0029] Fig. 4 illustrates a schematic diagram of an impedance matching network 400 showing some possible implementation details for the variable capacitive element 401. The variable capacitive element 401 comprises a plurality of capacitive sections C1 406, C2 408, C3 410, C4 412 and C5 414 between a first signal terminal 402 and a second signal terminal 404. The first capacitive section C1 406 and the fifth capacitive section C5 414 comprise MIM capacitors and / or metal-to-metal capacitors, and the second capacitive section C2 408, the third capacitive section C3 410 and the fourth capacitive section C4 412 comprise switching elements S1 416, S2 418 and S3 420, respectively. The switching elements S1 416, S2 418 and S3 420 each comprise a stack of series-connected transistors.Each of the switching elements S1 416, S2 418 and S3 420 is controlled by the control circuit 426, which is configured to provide control signals A, B and C for the corresponding switching elements S1 416, S2 418 and S3 420, for example, based on a predetermined algorithm.

[0030] In the embodiment of Fig. 4, four different capacitance values ​​can be obtained by individually rendering the first switching element S1 416, the second switching element S2 418, and the third switching element S3 420 non-conductive, and therefore the variable capacitive element 401 can be operated to provide a 4-stage capacitance tuner. A transistor (in particular, a field-effect transistor) that is in a conductive state can be used as a resistor R on can be viewed, with R onis the on-resistance of the transistor. In a non-conductive state, the transistor can be considered a capacitor with a capacitance C off be viewed, with C off is the blocking capacitance of the transistor. The control signals A, B, and C are configured to turn the switching elements S1 416, S2 418, and S3 420 on or off in one-step in a predetermined direction to avoid voltage overload.

[0031] In an example implementation, a uniform capacitance equal to 6 pF is selected to be switched in series in steps of one based on the control signals A, B, and C, thereby implementing a series capacitor tuner from 1.5 pF to 6 pF. For this purpose, the switching elements S1 416, S2 418, and S3 420 are Fig. 4 are selected to each have a capacitance value of 6 pF, and the MIM capacitors C1 406 and C5 414 are selected to each have a capacitance value of 12 pF. For example, assume initially that the first switching element S1 416, the second switching element S2 418, and the third switching element S3 420 are turned on (i.e., conductive). Therefore, in stage one, the total capacitance of the variable capacitive element 401 is equal to 6 pF (from the series combination of the MIM capacitors C1 406 (12 pF) and C5 414 (12 pF)). In stage two, the first switching element S1 416 is turned off, introducing a capacitance value of 6 pF in series with the two MIM capacitors C1 406 and C5 414, and therefore the total capacitance of the variable capacitive element 401 becomes 3 pF.In stage three, the second switching element S2 418 is turned off, introducing a capacitance value of 6 pF in series, and therefore the total capacitance of the variable capacitive element 401 becomes 2 pF. In stage four, the third switching element S2 420 is turned off, introducing a capacitance value of 6 pF in series, and therefore the total capacitance of the variable capacitive element 401 becomes 1.5 pF. Thus, the variable capacitive element is operated to provide four different capacitance values ​​(1.5 pF, 2 pF, 3 pF, and 6 pF) based on the control signals from the control circuit 426. In other implementations, non-uniform capacitance values ​​may be switched in each stage to implement the series capacitor tuner. Furthermore, in other implementations, the number of switching elements may be varied, thereby implementing an N-stage tuner.

[0032] The number of transistors in the stack in each of the switching elements S1 416, S2 418, and S3 420 may be different, and in one embodiment, an optimal number of transistors in the stack is derived based on the voltage that is expected to occur at the switching elements in the stage in which the corresponding switching element is turned off. In an example implementation, a maximum voltage classification of the variable capacitive element 401 in Fig. 4 is assumed to be 40 V, the maximum voltage rating of each of the transistors in the stack is assumed to be 1.5 V, and the maximum voltage rating of the MIM capacitors is assumed to be 10 V. For example, in stage one, when the first switching element S1 416, the second switching element S2 418, and the third switching element S3 420 are turned on, the total 40 V is divided equally between the two MMI capacitors C1 406 and C5 414 (i.e., 20 V across C1 406 and 20 V across C5 414). Since the maximum voltage rating of the MMI capacitors is assumed to be 10 V, a total of two MIM capacitors are grouped together to form C1 406 and C5 414, respectively, to withstand 20 V. In stage two, when the first switching element S1 416 is turned off, 20 V (i.e. half of 40 V) appears at the first switching element S1 416.Since the maximum voltage rating of each of the transistors in the stack is assumed to be 1.5 V, a total of 14 transistors must be grouped together in series to form the first switching element S1 416 to withstand 20 V. Further, in stage three, when the second switching element S2 418 is turned off, 13.33 V (i.e., one-third of 40 V) appears at the second switching element S2 418. Therefore, to withstand 13.33 V, a total of at least 9 transistors must be grouped in series to form the second switching element S2 418. Further, in stage four, when the third switching element S3 420 is turned off, 10 V (i.e., one-quarter of 40 V) appears at the third switching element S3 420. In order to withstand 10 V, a total of at least 7 transistors must be grouped in series to form the third switching element S3 420.In other implementations, the number of transistors in the stack may vary based on a number of factors, such as the number of switching elements or the number of adjustable states used, the maximum voltage rating of the device, and the voltage rating of the transistors. The control circuit 426 is operated to switch the first switching element S1 416, the second switching element S2 418, and the third switching element S3 420 according to the predetermined algorithm (or a predetermined direction), where the predetermined algorithm includes first turning off the switching element with the highest number of transistors to withstand the voltage stress. For example, in the variable capacitive element 401 of FIG. Fig. 4 the first switching element S1 416 with a stack of at least 14 series-connected transistors is switched off first, followed by the second switching element S2 418 with a stack of at least 9 series-connected transistors and then by the third switching element S3 420 with a stack of at least 7 series-connected transistors.

[0033] The impedance matching network 400 further includes two ESD protection elements ESD1 422 and ESD2 424 configured to provide electrostatic discharge (ESD) protection on both sides, i.e., against the voltage surges arriving at the first signal terminal 402 and the voltage surges arriving at the second signal terminal 404. The ESD protection elements ESD1 422 and ESD2 424 conduct a high voltage surge as a moderate electrical current to ground potential at a reference potential terminal 426, thereby protecting the variable capacitive element 401. In some embodiments, the variable capacitive element 401 is implemented as a slave device in which the second signal terminal is grounded. Therefore, in such implementations, the capacitance C5 414 and the ESD2 424 may be removed, and C5 414 may be combined with C1 406 to save chip size.

[0034] Furthermore, the variable capacitive element 401 comprises resistors R1, R2 and R3, which are operated to define the switching functionality of the switching elements S1 416, S2 418 and S3 420 by maintaining their source and drain at the same potential. In some embodiments, each of the resistors R1, R2 and R3 further comprises a plurality of resistors, wherein there is a resistor between the source and drain of each of the transistors comprising the stack of series-connected transistors in the switching elements S1 416, S2 418 and S3 420. In addition, a resistor R4 is provided to set the potential value, which, for example, in Fig. 4 is fixed to ground potential. Typically, resistors R1, R2, and R3 range in resistance from 20 kOhm to 100 kOhm, and resistor R4 has a high resistance such as 1 MOhm. Resistor R4 forces the source-drain potential of the switching elements S1 416, S2 418, and S3 420 to ground, and thereby a positive potential at the gate of the S1 / S2 / S3 switches turns them on, and a negative potential at the gate of the S1 / S2 / S3 switches turns them off. Furthermore, high resistances are required to enable device grouping. For example, in off-RF switching mode, the blocking capacitances force the RF voltage to spread across the transistors. A low resistance would cause Q-factor losses and also disturb the voltage distribution across the transistors.

[0035] Fig. 5 illustrates the schematic diagram of the impedance matching network 500 according to another embodiment in which the variable capacitive element 501 is configured to be selectively bypassed by a bypass element. The bypass functionality is provided by a switch element S4 528 comprising a field-effect transistor. In some implementations, the switch element S4 528 comprises a stack of series-connected transistors. The switch element S4 528 is connected in parallel with the variable capacitive element 501. During normal operation of the impedance matching network 500, the switch element S4 528 is off (i.e., non-conducting), and thus the blocking capacitances of the transistors in the switch element 528 can contribute to the total capacitance of the variable capacitive element 501. During bypass mode, the switch element S4 528 is enabled, or on, which then shorts the impedance matching network 500.

[0036] Fig.6 shows a flowchart illustrating a method 600 for adjusting an impedance according to an embodiment of the disclosure. In 602, a source impedance associated with a signal source is determined. In 604, a drain impedance associated with a signal sink is determined. In 606, an impedance matching network is adjusted based on the determined source impedance and the drain impedance to adjust the drain impedance and the source impedance. Adjusting the impedance matching network in 606 further includes adjusting a variable capacitive element that is part of the impedance matching network, wherein the variable capacitive element comprises a plurality of series-connected capacitive elements, wherein at least one of the capacitive elements comprises a switch element implemented as a stack of series-connected transistors.In some embodiments, the source and sink impedances are determined using directional couplers that detect forward and reflected power levels. In other embodiments, the source and sink impedances are determined using a lookup table. By checking the phone using the gyroscope, the display brightness sensor, etc., one can approximate the current handling and determine the impedance to be set.

[0037] Adjusting the variable capacitive component comprises turning on or off the at least one capacitive component comprising the switching element, resulting in the corresponding capacitive element being connected or disconnected to a signal path of the impedance matching network. Furthermore, adjusting the variable capacitive element comprises turning on or off the capacitive elements comprising the switching element in series in one-step in a predetermined direction.

[0038] Although the methods are illustrated and described above as a series of acts or events, it will be appreciated that the illustrated order of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and / or concurrently with other acts or events apart from those illustrated and described herein. In addition, not all of the illustrated acts may be required to implement one or more aspects or embodiments of the invention herein. Moreover, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0039] As highlighted above, the impedance matching network comprising a series capacitor topology has many advantages. The integrated approach using the RF transistor itself as the capacitance contributor eliminates the need for external RF switches and other discrete components. The elimination of external components reduces the cost of the device and further reduces the chip size. Additional tuning states can be added without significantly increasing the chip size. In addition, higher Q factors can be achieved due to the elimination of RF switches. In the series capacitor topology, Ron of the switch is not fixed and can be scaled according to the capacitors used. For example, the Q factor per stage is Q=Im(Z)Re(Z)=1ωCNRON,N=12πf∗CN∑1N−1NTr∗RonmmW_N where Ron is the total on-resistance of the transistors. In the series capacitor topology, the Q factor increases with each additional state (i.e., turning off the switching elements in steps of one), as the total Ron drops drastically to almost zero. Furthermore, the use of optimized stacking makes the design suitable for higher RF voltages with low power loss. In addition, it allows the use of transistors with a wide transistor width to lower R on also to reduce the power loss.

Claims

[1] Impedance matching network (104, 204, 400, 500), comprising: a first signal terminal (212, 302, 402, 502) configured to receive a signal from a source circuit (102, 202); a second signal terminal (214, 304, 404, 504) configured to provide the signal to a load circuit (106, 206); a series branch comprising a variable capacitive component (208, 300, 350, 401, 501) between the first signal terminal (212, 302, 402, 502) and the second signal terminal (214, 304, 404, 504), wherein the variable capacitive component (208, 300, 350, 401, 501) comprises a plurality of series-connected capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508), wherein at least one of the capacitive sections comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N), and a control component (210, 426, 526) configured to control a capacitance of the variable capacitive component (208, 300, 350, 401, 501) by controlling at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) based on a predetermined algorithm, wherein the at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprises a first capacitive section comprising a first switching element comprising a stack of series-connected transistors, and a second capacitive section comprising a second switching element comprising a stack of series-connected transistors, wherein the control component (210, 426, 526) is configured to switch the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520) on or off in series in steps of one in a predetermined direction according to the predetermined algorithm in order to avoid voltage overload. [2] The impedance matching network (104, 204, 400, 500) of claim 1, wherein the first capacitive portion comprising the first switching element and the second capacitive portion comprising the second switching element are connected in series. [3] Impedance matching network (104, 204, 400, 500) according to claim 1 or 2, wherein a voltage at the capacitive section (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) in the stage in which the corresponding capacitive section (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) is switched off, a number of transistors (352a...352N) in the corresponding capacitive section (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520). [4] The impedance matching network (104, 204, 400, 500) of any of claims 1-3, wherein a number of transistors in the first capacitive portion comprising the first switching element is higher than a number of transistors in the second capacitive portion comprising the second switching element. [5] The impedance matching network (104, 204, 400, 500) of claim 4, wherein the predetermined algorithm comprises turning off the first capacitive portion having a higher number of transistors first, followed by turning off the second capacitive portion. [6] The impedance matching network (104, 204, 400, 500) of any one of claims 1-5, wherein the variable capacitive component further comprises one or more capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising metal-insulator-metal capacitors and / or metal-metal capacitors. [7] The impedance matching network (104, 204, 400, 500) of claim 6, wherein a voltage across the capacitive portions (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising metal-insulator-metal capacitors and / or metal-metal capacitors determines a number of the metal-insulator-metal capacitors and / or metal-metal capacitors. [8] The impedance matching network (104, 204, 400, 500) of any one of claims 1-7, wherein the capacitive portions (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) further comprise metal-insulator-metal capacitance and / or metal-metal capacitors connected in parallel with the assembly of series-connected transistors (352a...352N). [9] Impedance matching network (104, 204, 400, 500) according to one of claims 1-8, further comprising a reference potential terminal, a first sub-branch between the first signal terminal and the reference potential terminal, the first sub-branch comprising a first electrostatic discharge protection element, and a second sub-branch between the second signal terminal and the reference potential terminal, the second sub-branch comprising a second electrostatic discharge protection element. [10] The impedance matching network (104, 204, 400, 500) of any one of claims 1-9, further comprising a bypass switch (528) in parallel with the variable capacitive component (208, 300, 350, 401, 501) configured to bypass the variable capacitive component (208, 300, 350, 401, 501) in a signal path between the first signal terminal and the second signal terminal and thus exclude it from the signal path when the bypass switch (528) is turned on. [11] The impedance matching network (104, 204, 400, 500) of claim 10, wherein the bypass switch (528) comprises a stack of series-connected transistors. [12] The impedance matching network (104, 204, 400, 500) of any of claims 1-11, wherein the variable capacitive component is integrated on a single chip. [13] A capacity tuner device comprising: a variable capacitive component (208, 300, 350, 401, 501) comprising a plurality of capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) in series; wherein at least one of the plurality of capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N); wherein a combination of blocking capacitances of the transistors (352a...352N) provides a capacitance of the capacitive element comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520); and a controller (210, 426, 526) configured to generate a total capacitance of the variable capacitive component (208, 300, 350, 401, 501) by switching on or off the at least one of the plurality of capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) based on a predetermined algorithm, wherein the controller (210, 426, 526) is configured to switch the capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520), according to the predetermined algorithm, in series in steps of one in a predetermined direction to avoid voltage overload. [14] The device of claim 13, wherein the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) further comprises a metal-insulator-metal capacitance and / or metal-metal capacitance connected in parallel to the stack of series-connected transistors (352a...352N), and wherein a combination of the blocking capacitances of the transistors (352a...352N) and the metal-insulator-metal capacitance and / or the metal-metal capacitance provides the capacitance of the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520). [15] The device of claim 13, wherein the at least one of the plurality of capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprises a first capacitive element comprising a first switching element comprising a stack of series-connected transistors, and a second capacitive element comprising a second switching element comprising a stack of series-connected transistors. [16] The device of claim 15, wherein the first capacitive element and the second capacitive element are connected in series. [17] The device according to claim 15 or 16, wherein a number of transistors in the first capacitive element comprising the first switching element is higher than a number of transistors in the second capacitive element comprising the second switching element. [18] The apparatus of claim 17, wherein the predetermined algorithm comprises turning off the first capacitive element having a higher number of transistors first, followed by turning off the second capacitive element. [19] The device of any of claims 13-18, wherein the variable capacitive component (208, 300, 350, 401, 501) further comprises one or more capacitive elements implemented as metal-insulator-metal capacitors and / or metal-metal capacitors. [20] Device according to one of claims 13-19, wherein the variable capacitive component (208, 300, 350, 401, 501) is arranged to generate N different capacitance values ​​based on control signals from the controller (210, 426, 526), ​​where N is a real, in particular natural, number and is greater than or equal to 2. [21] The device of any of claims 13-20, wherein a number of capacitance values ​​to be generated by the variable capacitive component (208, 300, 350, 401, 501) determines a number of capacitive elements comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520) in the variable capacitive component (208, 300, 350, 401, 501). [22] The device of any of claims 13-21, wherein a voltage across the capacitive element comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) in the stage in which the corresponding capacitive element comprising the switching element is turned off determines a number of transistors (352a...352N) in the corresponding capacitive element comprising the switching element. [23] A method for adjusting an impedance, the method comprising: Determining or estimating a source impedance of a signal source; Determining or estimating a sink impedance of a signal sink; and Setting an impedance matching network based on the source impedance and the sink impedance by setting a variable capacitive component (208, 300, 350, 401, 501) which is part of the impedance matching network, wherein the variable capacitive component (208, 300, 350, 401, 501) comprises a plurality of series-connected capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508), wherein at least one of the capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N) includes wherein adjusting the variable capacitive component (208, 300, 350, 401, 501) further comprises switching the capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element on or off according to a predetermined algorithm in series in steps of one in a predetermined direction to avoid voltage overload. [24] The method of claim 23, wherein adjusting the variable capacitive component (208, 300, 350, 401, 501) comprises turning on or off the at least one of the capacitive elements (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element, resulting in the corresponding capacitive element (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) being connected or not to a signal path of the impedance matching network.

Images