Semiconductor devices with multiple gate structures and methods for manufacturing such devices

Abstract

Semiconductor device comprising: a substrate (101) having a first region (I) and a second region (II); a plurality of first gate structures (140) in the first region (I), wherein the first gate structures (140) are spaced apart from one another by a first distance (SG1); a plurality of second gate structures (240) in the second region (II), wherein the second gate structures (240) are spaced apart from one another by a second distance (SG2); a plurality of first spacers (150a; 150a') directly on sidewalls of the respective first gate structures (140); a dielectric layer (154a) directly on outer sidewalls of the respective first spacers (150a; 150a'); a plurality of second spacers (250a; 250a') directly on sidewalls of the respective second gate structures (240); a plurality of third spacers (254a) on outer side walls of the respective second spacers (250a; 250a'); a plurality of first embedded source / drain regions (110; 110') on opposite sides of the first gate structures (140); a plurality of second embedded source / drain regions (210; 210') on opposite sides of the second gate structures (240); an insulating intermediate layer (162, 262) over the first and second embedded source / drain regions (110; 110'; 210; 210'), wherein the dielectric layer (154a) covers upper surfaces of the first embedded source / drain regions (110; 110'), wherein the plurality of third spacers (254a) do not cover upper surfaces of the second embedded source / drain regions (210; 210'), wherein a sum of a first thickness (X1) of a first of the first spacers (150a; 150a') and a second thickness (X2) of the dielectric layer (154a) formed on a sidewall of a first of the first gate structures (140) is substantially equal to a sum of a third thickness (X3) of a first of the second spacers (250a; 250a') and a fourth thickness (X4) of a first of the third spacers (254a) formed on a sidewall of a first of the second gate structures (240), and wherein the first spacers (150a; 150a') and the second spacers (250a; 250a') have an L-shaped cross section.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the inventive concepts relate to semiconductor devices having a plurality of gate structures and to methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices are becoming more highly integrated in response to the demand for smaller, lower-power electronic devices. Fin field-effect transistors (FinFETs) with a three-dimensional channel structure have been developed that can reduce short-channel effects, which increase with increasing device integration. Additionally, research is currently underway into techniques for increasing charge carrier mobility.

[0003] A semiconductor device with source-drain stressors is known from patent application US 2013 / 320 457 A1. The semiconductor device comprises a gate structure with a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be arranged on sidewalls of the gate structure, and a stressor pattern containing an impurity region is arranged on one side of the gate structure. The stressor pattern comprises a protruding portion with an upper surface that is higher than a lower surface of the gate structure, and a facet in the protruding portion. The facet is inclined at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers.An insulating barrier layer may extend conformally on the stressor pattern and the gate spacers, and an insulating wing pattern is arranged in the concave portion on the insulating barrier layer.

[0004] From patent application US 2013 / 285 146 A1, a semiconductor component is known, comprising: a substrate, a first gate structure and a second gate structure positioned on the substrate, a first source / drain region formed in the substrate on two sides of the first gate structure, and a second source / drain region formed in the substrate on two sides of the second gate structure. The first gate structure and the second gate structure have the same conductivity type. The first source / drain region and the second source / drain region are different.

[0005] From patent application US 2015 / 044831 A1, a semiconductor process is known which comprises the following steps: A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer adjacent to the first gate, but retains the first stress layer covering the second gate. A first epitaxial layer is formed adjacent to the first spacer. The first stress layer and the first spacer are completely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer adjacent to the second gate, but retains the second stress layer covering the first gate.A second epitaxial layer is formed next to the second spacer. The second stress layer and the second spacer are completely removed. SUMMARY

[0006] The object of the present invention is to provide an improved semiconductor device.

[0007] This object is achieved by a semiconductor device according to claims 1 and 12. Further developments and preferred embodiments are the subject of the subclaims.

[0008] In some example embodiments, the first embedded source / drain regions may include an n-doped impurity region.

[0009] In some example embodiments, an upper portion of the first embedded source / drain regions may comprise undoped silicon.

[0010] In some exemplary embodiments, the first spacers may include substantially the same material as the second spacers.

[0011] In some example embodiments, the dielectric layer may include substantially the same material as the third spacers.

[0012] A method of manufacturing a semiconductor device not covered by the following set of claims includes forming a plurality of first active fins and a plurality of first sacrificial gate structures in a first region of a substrate, forming a plurality of second active fins and a plurality of second sacrificial gate structures in a second region of the substrate, forming a first preliminary spacer on sidewalls of the respective first sacrificial gate structures, the first preliminary spacer including a first spacer and a first sacrificial spacer, etching upper portions of the first active fins using the first preliminary spacers as an etch mask to form first recess regions on opposite sides of the first sacrificial gate structures, removing the first sacrificial spacers,epitaxially growing first embedded source / drain regions in the first recess regions; forming second preliminary spacers on sidewalls of the respective second sacrificial gate structures, the second preliminary spacers including a second spacer, a third spacer, and a second sacrificial spacer; etching upper portions of the second active fins using the second preliminary spacers as an etch mask to form second recess regions on opposite sides of the second sacrificial gate structures; removing the second sacrificial spacers; and epitaxially growing second embedded source / drain regions in the second recess regions.

[0013] In some example embodiments, forming the first preliminary spacers may include forming a first insulating layer on the first sacrificial gate structures and on the second sacrificial gate structures, forming a second insulating layer on the first insulating layer, the second insulating layer having etch selectivity with respect to the first insulating layer, performing an etch-back process on the second insulating layer to form the first sacrificial spacers, and performing an etch-back process on the first insulating layer to form the first spacers.

[0014] In some exemplary embodiments, the first spacers may have L-shaped cross sections.

[0015] In some exemplary embodiments, removal of the first sacrificial spacers may be performed by a wet etching process using at least one solution selected from a dilute HF solution and a buffered oxide etch (BOE) solution.

[0016] In some exemplary embodiments, removal of the first sacrificial spacers may be performed by a dry etching process using at least one gas selected from NH 3 and NF 3 .

[0017] In some example embodiments, the second insulating layer is removed in the second region during removal of the first sacrificial spacers, and the first insulating layer of the second region may not be removed during removal of the first sacrificial spacers.

[0018] In some example embodiments, forming the second preliminary spacers may include forming a third insulating layer on the substrate, forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having etch selectivity with respect to the third insulating layer, performing an etch-back process on the fourth insulating layer in the second region to form the second sacrificial spacers, and performing an etch-back process on the third and first insulating layers in the second region to form the third and second spacers, respectively.

[0019] In some exemplary embodiments, the second and third spacers may have L-shaped cross sections.

[0020] In some exemplary embodiments, removal of the second sacrificial spacers may be performed by a wet etching process using at least one solution selected from a dilute HF solution and a buffered oxide etch (BOE) solution.

[0021] In some exemplary embodiments, removal of the second sacrificial spacers may be performed by a dry etching process using at least one gas selected from NH 3 and NF 3 .

[0022] In some example embodiments, the fourth insulating layer in the first region may be removed during removal of the second sacrificial spacers, and the third insulating layer in the first region may not be removed during removal of the second sacrificial spacers.

[0023] In some exemplary embodiments, the method may further include forming an etch stop layer on the substrate after forming the second embedded source / drain regions, forming an interlayer dielectric layer on the etch stop layer, planarizing the interlayer dielectric layer to expose upper surfaces of the first and second sacrificial gate structures, removing the first sacrificial gate structures and the second sacrificial gate structures to form a third recess region and a fourth recess region, respectively, and forming a first gate structure and a second gate structure in the third recess region and in the fourth recess region, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above aspects and features of the inventive concepts will become more apparent by describing detailed exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a plan view illustrating first and second regions of a semiconductor device according to an exemplary embodiment of the inventive concepts; Fig. 2 a cross-sectional view along lines AA' and BB' of Fig. 1 is; Fig. 3 to 13 are perspective views and cross-sectional views showing a method of manufacturing the semiconductor device from the Fig. 1 and Fig. 2 represent; Fig. 14 and Fig. 15 are cross-sectional views illustrating a semiconductor device according to an alternative exemplary embodiment of the inventive concepts; Fig. 16 is a circuit diagram illustrating an inverter with a semiconductor device according to an exemplary embodiment of the inventive concepts; Fig. 17 is a circuit diagram illustrating a NAND gate cell including a semiconductor device according to an exemplary embodiment of the inventive concepts; Fig. 18 is a circuit diagram illustrating an SRAM (Static Random Access Memory) unit cell according to an exemplary embodiment of the inventive concepts; Fig. 19 is a block diagram illustrating a memory device including a semiconductor device according to an exemplary embodiment of the inventive concepts; Fig. 20 is a block diagram illustrating an electronic device including a semiconductor device according to an exemplary embodiment of the inventive concepts; and Fig. 21 is a block diagram illustrating a system including a semiconductor device according to an exemplary embodiment of the inventive concepts. DETAILED DESCRIPTION

[0025] Example embodiments of the inventive concepts will now be described in more detail with reference to the accompanying drawings. It will be understood that when an element is described as being "on," "connected to," or "coupled to" another element, it may be directly on, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element is described as being "touching" another element, or as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Other words used to describe the relationship between elements or layers are intended to be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "beneath" versus "directly beneath," etc.).).

[0026] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, components, regions, and / or layers, these elements, components, regions, and / or layers are not limited by these terms. Unless the context indicates otherwise, these terms are used only to distinguish one element, component, region, or layer from another element, component, region, or layer. Thus, a first element, component, region, or layer discussed below could be referred to as a second element, component, region, or layer without departing from the teachings of the exemplary embodiments.

[0027] In the figures, the dimensions of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout the drawings and description.

[0028] Spatially relative terms, e.g., "beneath," "under," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass various orientations of the devices in use or operation in addition to the orientation illustrated in the figures. For example, if the device in the figures is turned over, then elements described as "below" or "below" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" can include both an above and below orientation.The device may be oriented differently (rotated by 90° or in other orientations) and the spatially relative descriptors used here can be interpreted accordingly.

[0029] As used herein, the singular forms "a" and "an" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprising," "including," and variations thereof, when used in this material, indicate the presence of the specified features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more additional features, steps, operations, elements, components, and / or groups thereof.

[0030] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0031] Example embodiments are described with reference to cross-sectional views and plan views. The profile of an example view may be modified, for example, according to manufacturing techniques and / or tolerances. Accordingly, the example embodiments should not be construed as limiting the particular shapes of regions illustrated herein. For example, a region illustrated as a rectangle may have rounded or curved features at its edges due to manufacturing techniques and / or tolerances. Thus, the regions shown in the drawings are illustrated in a schematic form, and the exact shapes of the regions represent example shapes.

[0032] When terms such as "same," "identical," "planar," or "coplanar" are used, unless otherwise specified, they mean a nearly identical orientation, layout, location, shape, size, quantity, or other nearly identical dimension, within acceptable variations that may occur, e.g., due to manufacturing processes. The term "substantially" may be used here to reflect this meaning.

[0033] Although corresponding top and / or perspective views of some cross-sectional views may not be shown, the cross-sectional views of device structures illustrated herein support a plurality of device structures extending along two directions as would be illustrated in a top view and / or in three directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction, which may be orthogonal to the two different directions. The plurality of device structures may be integrated into a same electronic device. For example, if a device structure (e.g.While a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures) as they would be illustrated in a plan view of the electronic device. The plurality of device structures may be arranged in a matrix and / or in a two-dimensional pattern. Hereinafter, exemplary embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings.

[0034] Fig. 1 is a plan view illustrating a first region I and a second region II of a semiconductor device 100 according to an exemplary embodiment of the inventive concepts. Fig. 2 is a pair of cross-sectional views along lines AA' and BB', respectively, of Fig. 1. To simplify the drawings, Fig. 1 some elements, such as first, second and third spacers 150a, 250a and 254a and a first insulating intermediate layer 162, which in Fig. 2 are omitted.

[0035] Referring to Fig. 1 and Fig. 2, the semiconductor device 100 may include a substrate 101 having the first region I and the second region II, a plurality of first transistors 100A formed in the first region I, and a plurality of second transistors 100B formed in the second region II.

[0036] The first region I may include a plurality of first active fins 105, a plurality of first gate structures 140, a plurality of first spacers 150a, a dielectric layer 154a, and a plurality of first embedded source / drain regions 110. The second region II may include a plurality of second active fins 205, a plurality of second gate structures 240, a plurality of second spacers 250a, a plurality of third spacers 254a, and a plurality of second embedded source / drain regions 210. The semiconductor device 100 may further include a first etch stop layer 158, a second etch stop layer 258, a first insulating interlayer 162, and a second insulating interlayer 262.

[0037] A plurality of n-type fin field-effect transistors (FinFETs) may be formed in the first region II. A plurality of p-type fin field-effect transistors (FinFETs) may be formed in the second region II. In some example embodiments, the first transistors 100A may be n-type FinFETs, and the second transistors 100B may be p-type FinFETs.

[0038] The substrate 101 may have a top surface extending in the X-direction and the Y-direction. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In some example embodiments, the substrate 101 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some example embodiments, the substrate 101 may be an SOI (silicon-on-insulator) substrate or a GeOI (germanium-on-insulator) substrate.

[0039] The first and second active fins 105 and 205 may be formed on the substrate 101 and may extend in a first direction, e.g., the Y-direction. The first and second active fins 105 and 205 may protrude upward from the substrate 101. In some example embodiments, the first and second active fins 105 and 205 may be formed by etching the substrate 101 or by forming recesses in the substrate 101 using, e.g., a dry etching process. In further example embodiments, the first and second active fins 105 and 205 may include an epitaxial layer(s) grown from the substrate 101. For example, the first active fins 105 may include a silicon layer containing a p-type impurity, and the second active fins 205 may include a silicon layer containing an n-type impurity.The first and second active fins 105 and 205 may extend in the same direction.

[0040] A device isolation region may be disposed between each of the first active fins 105 and between each of the second active fins 205, respectively. The device isolation regions may be formed by a trench isolation (STI) process. The device isolation regions may be formed of an insulating material, e.g., silicon oxide, silicon nitride, a low-k dielectric material, or a mixture thereof. The low-k dielectric material may be BPSG (borophosphosilicate glass), TOSZ (tonene silazane), USG (undoped silicate glass), SOG (spin-on glass), FOX (flowable oxide), TEOS (tetraethyl orthosilicate), or HDP-CVD (high density plasma chemical vapor deposition) oxide.

[0041] The first and second gate structures 140 and 240 may be formed on the first and second active fins 105 and 205, respectively. The first gate structures 140 may cross over the first active fins 105 and may extend in a second direction, e.g., the X-direction. The second gate structures 240 may cross over the second active fins 205 and may also extend in the second direction. The first and second gate structures 140 and 240 may surround top surfaces and sidewalls of the first and second active fins 105 and 205, respectively. A first channel region and a second channel region may be formed in the top portions and sidewalls of the first and second active fins 105 and 205 at locations where the first and second gate structures 140 and 240 cross over the respective first and second active fins 105 and 205.The first gate structures 140 may be spaced apart by a first distance SG1, and the second gate structures 240 may be spaced apart by a second distance SG2. The first distance SG1 may be substantially equal to the second distance SG2. As used herein, the term "substantially equal" means a deviation of less than 10%. Throughout the materials, when a value A is stated to be substantially equal to a value B, then the deviation of the value A from the value B is less than 10% of the value A.

[0042] In some example embodiments, the first gate structures 140 and the second gate structures 240 may or may not extend parallel to each other.

[0043] Each of the first gate structures 140 may include a first gate dielectric layer 142, a first lower gate electrode 145, and a first upper gate electrode 147. The first gate dielectric layer 142 may be disposed between the first active fins 105 and the first lower gate electrode 145. The first gate dielectric layer 142 may also include portions extending along sidewalls of the first spacers 150a. The first upper gate electrodes 147 may be formed on the respective first lower gate electrodes 145.

[0044] Each of the second gate structures 240 includes a second gate dielectric layer 242, a second lower gate electrode 245, and a second upper gate electrode 247. The second gate dielectric layer 242 may be disposed between the second active fins 205 and the second lower gate electrode 245. Some portions of the second gate dielectric layer 242 may extend upward along sidewalls of the second spacers 250a. The second upper gate electrodes 247 may be formed on the respective second lower gate electrodes 245.

[0045] The first and second gate dielectric layers 142 and 242 may include silicon oxide, silicon nitride, or a high-k dielectric material. The high-k dielectric material may have a dielectric constant greater than that of silicon dioxide (SiO 2 ) layer. For example, the high-k dielectric material can be aluminum oxide (Al 2 O 3), Tantalum oxide (Ta 2 YOU ARE 3 ), Titanium Oxide (TiO 2 ), Yttrium Oxide (Y 2 YOU ARE 3 ), Zirconium oxide (ZrO 2 ), Zirconium silicon oxide (ZrSi x YOU ARE y ), Hafnium Oxide (HfO 2 ), Hafniumsilicon oxide (HfSi x YOU ARE y ), Lanthanum oxide (La 2 YOU ARE 3 ), Lanthanum oxide (LaAl x YOU ARE y ), Lanthanum oxide (LaHf x YOU ARE y ), Hafniumalumnium oxide (HfAl x YOU ARE y ) and / or Praseodymoxide (Pr 2 YOU ARE 3 ).

[0046] The first and second lower gate electrodes 145 and 245 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), tantalum carbide (TaC), and / or titanium carbide (TiC). The first and second upper gate electrodes 147 and 247 may include, for example, aluminum (Al), tungsten (W), molybdenum (Mo), and / or other metals. In some example embodiments, the first and second upper gate electrodes 147 and 247 may include one or more semiconductor materials, such as doped polysilicon.

[0047] First spacers 150a may be arranged on opposite sides of each of the first gate electrodes 140. The first spacers 150 may extend along the respective sidewalls of the first gate electrodes 140 and on a top surface of the first active fins 105. The first spacers 150a may have L-shaped cross-sections. The dielectric layer 154a may be formed along a top surface of the first spacers 150a (e.g., on the top surface of the lower portion of the L-shaped cross-section) and on sidewalls of the first spacers 150a. The dielectric layer 154a may also extend on top surfaces of the first embedded source / drain regions 110 arranged on opposite sides of the first gate structures 140.The dielectric layer 154a may be conformally formed on the first spacers 150a and on the first embedded source / drain regions 110 with a uniform thickness. Portions of the first spacers 150a formed along the top surface of the first active fins 105 have a first length Xa in the Y direction. The length Xa may be substantially equal to the sum of a first thickness X1 of a corresponding one of the first spacers 150a that is on the sidewall of the first gate structure 140 and a second thickness X2 of the dielectric layer 154a that is on the sidewall of the first spacer 150a, as shown in the first enlarged portion in FIG. Fig. 2 shown.

[0048] Second spacers 250a may be arranged on opposite sides of each of the second gate structures 240. The second spacers 250a may extend along the respective sidewalls of the second gate structures 240 and on a top surface of the second active fins 205. The second spacers 250a may have L-shaped cross-sections. The third spacers 254a may be formed along top surfaces of the respective second spacers 250a (e.g., on the top surface of the lower portion of the L-shaped cross-section) and on sidewalls of the respective second spacers 250a. The third spacers 254a may also have L-shaped cross-sections. Portions of the second spacers 250a formed along the top surface of the second active fins 205 may have a third length Xc in the Y direction.The third length Xc may be greater than a sum of a third thickness X3 of a corresponding one of the second spacers 250a provided on the sidewall of the second gate structures 240 and the fourth thickness X4 of a corresponding one of the third spacers 254a provided on a sidewall of the second spacers 250a, as shown in the enlarged portion in FIG. Fig. 2 is shown.

[0049] A sum of the first thickness X1 of one of the first spacers 150a and the second thickness X2 of the dielectric layer 154a may be substantially equal to the sum of the third thickness X3 of one of the second spacers 250a and the fourth thickness X4 of one of the third spacers 254a. Here, the thicknesses of the first spacers 150a, the dielectric layer 154a, the second spacers 250a, and the third spacers 254a refer to the thickness in a direction parallel to the top surface of the substrate 101 and perpendicular to the direction in which the corresponding gate structure 140 or 240 extends (i.e., to the Y-direction in Fig. 1 and Fig. 2). In some exemplary embodiments, the first thickness X1 of each of the first spacers 150a may be substantially equal to the third thickness X3 of each of the second spacers 250a, and the second thickness X2 of the dielectric layer 154a may be substantially equal to the fourth thickness X4 of each of the third spacers 254a.

[0050] In some example embodiments, the first distance SG1 between adjacent first gate structures 140 may be substantially equal to the second distance SG2 between adjacent second gate structures 240. In some example embodiments, a distance S1' between portions of the dielectric layer 154a that oppose each other on sidewalls of adjacent ones of the first gate structures 140 may be substantially equal to a distance S2' between the third spacers 254a that oppose each other on sidewalls of adjacent ones of the second gate structures 240.

[0051] The first spacers 150a, the dielectric layer 154a, the second spacers 250a, and the third spacers 254a may include silicon oxide, silicon nitride, and / or silicon oxynitride. The first spacers 150a may be formed from substantially the same material as the second spacers 250a. The dielectric layer 154a may be formed from substantially the same material as the third spacers 254a. The first spacers 150a may be formed from a different material having a different dielectric constant than that of the dielectric layer 154a or the third spacers 254a. The second spacers 250a may be formed from a different material having a different dielectric constant than the dielectric layer 154a or the third spacers 254a.In some example embodiments, the first spacers 150a have a dielectric constant lower than that of the dielectric layer 154a, and the second spacers 250a may have a dielectric constant lower than that of the third spacers 254a. In some example embodiments, the first spacers 150a and the second spacers 250a may include silicon oxide, and the dielectric layer 154a and the third spacers 254a may include silicon nitride. In some example embodiments, the first spacers 150a and the second spacers 250a may include silicon oxynitride having a lower nitrogen concentration. The dielectric layer 154a and the third spacers 254a may include silicon oxynitride having a relatively higher nitrogen concentration than the first spacers 150a and the second spacers 250a.

[0052] The first embedded source / drain regions 110 may be formed on the first active fins 105 arranged on opposite sides of the first gate structures 140. The first embedded source / drain regions 110 may be source / drain regions of the first transistors 100A. In some example embodiments, each of the first active fins 105 may have recessed regions, and the first embedded source / drain regions 110 may be formed in the respective recessed regions. In some example embodiments, each of the first embedded source / drain regions 110 may have raised upper surfaces that are higher above the upper surface of the substrate 101 than the upper surfaces of the first active fins 105. Some of the first embedded source / drain regions 110 may have a joined structure such that they touch each other on the first active fins 105.The first embedded source / drain regions 110 may be formed using a selective epitaxial growth (SEG) process. In some example embodiments, the first embedded source / drain regions 110 may include silicon (Si) or silicon carbide (SiC) highly doped with an n-type impurity. A top portion of each of the first embedded source / drain regions 110 may include undoped silicon.

[0053] The second embedded source / drain regions 210 may be formed on the second active fins 205 arranged on opposite sides of the second gate structures 240. The second embedded source / drain regions 210 may be source / drain regions of the second transistors 100B. Upper surfaces of the second embedded source / drain regions 210 may have a height above the upper surface of the substrate 110 that is substantially equal to the height of the bottom surfaces of the second gate structures 250 above the upper surface of the substrate 101. In further example embodiments, the second embedded source / drain regions 210 may have a raised structure such that the upper surfaces of the second embedded source / drain regions 210 are higher above the upper surface of the substrate 101 than the bottom surfaces of the second gate structures 240.Some of the second embedded source / drain regions 210 may have a combined structure such that they touch each other on the second active fins 205. In some example embodiments, the second embedded source / drain regions 210 may be formed by a selective epitaxial growth (SEG) process. In some example embodiments, the second embedded source / drain regions 210 may comprise silicon germanium (SiGe) highly doped with a p-type impurity. The second embedded source / drain regions 210 containing silicon germanium (SiGe) may exert compressive stress on the second active fins 205 formed of silicon (Si). This may increase the mobility of holes in the channel region of the second active fins 205.The second embedded source / drain regions 210 may be multiple regions with different germanium (Ge) concentrations.

[0054] A first etch stop layer 158 having a uniform thickness may be conformally formed on the dielectric layer 154a in the first region I. A second etch stop layer 258 may be conformally formed in the second region II. The second etch stop layer 258 may have a substantially uniform thickness on the third spacers 254a and the second embedded source / drain regions 210. The first and second etch stop layers 158 and 258 may include silicon nitride, silicon oxynitride, or a mixture thereof. The thickness of the first etch stop layer 158 may be substantially equal to the thickness of the second etch stop layer 258.

[0055] In some example embodiments, the first distance SG1 between the first gate structures 140 may be substantially equal to the second distance SG2 between the second gate structures 240. A first gap S1 between portions of the first etch stop layer 158 that oppose each other on sidewalls of adjacent ones of the first gate structures 140 may be substantially equal to a second gap S2 between portions of the second etch stop layer 258 that oppose each other on sidewalls of adjacent ones of the second gate structures 240.

[0056] First and second insulating interlayers 162 and 262 may be formed on the respective first and second etch stop layers 158 and 258. The first and second insulating interlayers 162 and 262 may be BPSG (borophosphosilicate glass), TOSZ (tonene silazane), USG (undoped silicate glass), SOG (spin-on glass), FOX (flowable oxide), TEOS (tetraethyl orthosilicate), or HDP-CVD (high plasma density CVD) oxide.

[0057] Fig. 3 to 13 are cross-sectional views showing a method of manufacturing the semiconductor device 1 of Fig. 1 and Fig. 2 represent. Fig. 3 to 13 are cross-sectional views along lines AA' and BB' of Fig. 1.

[0058] Referring to Fig. 3, the substrate 101 includes the first region I and the second region II. A plurality of first active fins 105 are formed in the first region I, and a plurality of first sacrificial gate structures are formed on the first active fins 105. The first sacrificial gate structures may include a first sacrificial gate dielectric layer 132, a first sacrificial gate 135, and a first sacrificial gate mask pattern 136, which are stacked in sequence. The first sacrificial gate structures may be spaced from each other by the first distance SG1. A plurality of second active fins 205 are formed in the second region II, and a plurality of second sacrificial gate structures are formed on the second active fins 205. The second sacrificial gate structures may include a second sacrificial gate dielectric layer 232, a second sacrificial gate 235, and a second gate mask pattern 236, which are stacked in sequence.The second sacrificial gate structures may be spaced apart by the second distance SG2. The first distance SG1 may be substantially equal to the second distance SG2.

[0059] The first and second active fins 105 and 205 may be formed in the first region I and the second region II, respectively, by etching the substrate 101 using a mask pattern as an etching mask. A plurality of trenches may be formed in the first active fins 105 and the second active fins 205, respectively. A device isolation region may be formed in the trenches. Upper portions of the first and second active fins 105 and 205 may protrude from an upper surface of the device isolation region.

[0060] In some example embodiments, the first and second sacrificial gate dielectric layers 132 and 232 may include silicon oxide, and the first and second sacrificial gates 135 and 235 may include polysilicon.

[0061] Referring to Fig. 4, first insulating layers 150 and 250 may be formed on the first active fins 105 and on the second active fins 205, respectively. Second insulating layers 152 and 252 may be formed on the first insulating layers 150 and 250, respectively. The second insulating layers 152 and 252 may have etch selectivity with respect to the first insulating layers 150 and 250. In some example embodiments, the first insulating layers 150 and 250 may include silicon nitride or silicon oxynitride, and the second insulating layers 152 and 252 may include silicon oxide. The first and second insulating layers 150, 250, 152, and 252 may be formed by atomic layer deposition (ALD).

[0062] Referring to Fig. 5, first preliminary spacers may be formed on opposite sides of the first sacrificial gate structures. The first preliminary spacers may be double-layered structures, each including a first spacer 150 and a first sacrificial spacer 152a.

[0063] The first sacrificial spacers 152a may be formed on the first insulating layer 150 by performing an etch-back process on the second insulating layer 152 after forming a mask pattern 273 covering the second region. The mask pattern 273 may be a photoresist pattern. The first spacers 150a may be formed on opposite sides of each first sacrificial gate structure by performing an etch-back process on the first insulating layer 150. Each first spacer 150a may have an L-shaped cross-section and may be formed along a top surface of one of the first active fins 105 and along a sidewall of one of the first sacrificial gate structures. First preliminary spacers may be formed on opposite sides of each of the sacrificial gate structures. A length of the first spacers 150a along the top surface of the first active fins 105 (i.e.in the Y direction) may be a sum of the thicknesses of the first sacrificial spacers 152a and the first insulating layer 150 in the Y direction.

[0064] The mask pattern 273 covering the second region II may be removed after the preliminary spacers are formed. The first insulating layer 250 and the second insulating layer 252 formed in the second region II may remain after the mask pattern 273 is removed.

[0065] Referring to Fig. 6, first recess regions R1 may be formed in the first region I by removing upper portions of the first active fins 105 arranged on opposite sides of the first sacrificial gate structures using an anisotropic etching process. In some exemplary embodiments, an additional isotropic etching process may be performed to extend the first recess regions R1 laterally below the first spacers 150a.

[0066] Referring to Fig. 7, a plurality of first embedded source / drain regions 110 may be formed on opposite sides of each of the first sacrificial gate structures in the first region I.

[0067] A pre-cleaning process may first be performed on the first recessed areas R1. The pre-cleaning process may be performed using a wet cleaning process and / or a dry cleaning process. The wet cleaning process may be an isotropic etching process using a dilute hydrofluoride (HF) solution or a buffered oxide etchant (BOE). The dry cleaning process may be a dry etching process, e.g., Siconi ® using an ammonia (NH 3 ) gas and / or nitrogen trifluoride (NF 3) gas. The second insulating layer 252 and the first sacrificial spacers 152a may be removed by the pre-cleaning process. Removing the first sacrificial spacers 152a may expose sidewalls of the first spacers 150a in the first region I. The first insulating layer 250 may remain on the second sacrificial gate structures and the second active fins 205 in the second region II.

[0068] The first embedded source / drain regions 110 may be formed using a selective epitaxial growth (SEG) process such that they fill the first recessed regions R1. The first insulating layer 250 formed on the second region II may act as a blocking layer during the selective epitaxial growth (SEG) process. A top surface of the first embedded source / drain regions 110 may be provided at a higher level above the top surface of the substrate 101 than the top surfaces of the first active fins 105. In some example embodiments, the first embedded source / drain regions 110 may comprise silicon (Si). The first embedded source / drain regions 110 may be doped in-situ with an n-type impurity, such as phosphorus (P), during the SEG process.An upper portion of the first embedded source / drain regions 110 may comprise undoped silicon (Si). The undoped silicon may be formed by stopping the supply of the n-type dopant during a final step of the SEG process. Some of the first embedded source / drain regions 110 may be connected to at least adjacent ones of the first embedded source / drain regions 110. In further example embodiments, the first embedded source / drain regions 110 may be formed using a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, or an ultra-high vacuum chemical vapor deposition (UHV CVD) process.

[0069] Referring to Fig. 8, third insulating layers 154 and 254 may be formed on the substrate 101 such that they cover the first spacers 150a and the first insulating layer 250, respectively. Fourth insulating layers 156 and 256 may be formed on the third insulating layers 154 and 254, respectively. The fourth insulating layers 156 and 256 may have etch selectivity with respect to the third insulating layers 154 and 254. For example, the third insulating layers 154 and 254 may include silicon nitride, and the fourth insulating layers 156 and 256 may include silicon oxide. The third and fourth insulating layers 154, 254, 156, and 256 may be formed, for example, using an atomic layer deposition (ALD) method.

[0070] Referring to Fig. 9, second preliminary spacers may be formed on opposite sides of the second sacrificial gate structures in the second region II. The second preliminary spacers may be three-layer structures, each including a second spacer 250a, a third spacer 254a, and a second sacrificial spacer 256a.

[0071] The second sacrificial spacers 256a may be formed on the third insulating layer 254 by performing an etch-back process on the fourth insulating layer 256 after forming a mask pattern 173 in the first region I. The mask pattern 173 may be a photoresist pattern. The second spacers 250a and the third spacers 254a may be formed on opposite sides of each of the second sacrificial gate structures by performing an etch-back process on the third insulating layer 254 and on the first insulating layer 250. The second spacers 250a may have L-shaped cross-sections and may extend along respective top surfaces of the second active fin 205 and along respective sidewalls of the second sacrificial gate structures. The third spacers 254a may have L-shaped cross-sections and may extend along top surfaces and sidewalls of the second spacers 250a.The second preliminary spacers, including the second spacers 250a, the third spacers 254a, and the second sacrificial spacers 256a, may be formed on opposite sides of each of the second sacrificial gate structures. A length of each second spacer 250a in the Y direction along the top surface of the second active fin 205 may be a sum of the thicknesses of the second spacers 250a, the third spacers 254a, and the second sacrificial spacer 256a. In other words, a length of the second spacers 250a formed along the top surface of the second active fin 205 may be determined by a sum of the thicknesses of the first insulating layer 250, the third insulating layer 254, and the fourth insulating layer 256.

[0072] The mask pattern 173 covering the first region I may be removed. The third insulating layer 154 and the fourth insulating layer 156 formed in the first region I may remain after the removal of the mask pattern 173.

[0073] Referring to Fig. 10, second recess regions R2 may be formed in the second region II by removing upper portions of the second active fins 205 on opposite sides of the second sacrificial gate structures using an anisotropic etching process. In some exemplary embodiments, an isotropic etching process may be performed to extend the second recess regions R2 laterally below the second spacers 250a.

[0074] Referring to Fig. 11, a plurality of second embedded source / drain regions 210 may be formed on opposite sides of the second sacrificial gate structures in the second region II.

[0075] A pre-cleaning process may be performed on the second recess region R2. The pre-cleaning process may be performed using a wet cleaning process and / or a dry cleaning process. The wet cleaning process may be an isotropic etching process using a dilute hydrofluoride (HF) solution or a buffered oxide etchant (BOE). The dry cleaning process may be a dry etching process, e.g., Siconi ® , using an ammonia (NH 3 ) gas and / or nitrogen trifluoride (NF 3) gas. The fourth insulating layer 156 and the second sacrificial spacers 256a may be removed by the pre-cleaning process. The second spacers 250a and the third spacers 254a may remain on opposite sides of the second sacrificial gate structures in the second region II, and the first spacers 150a and the third insulating layer 154 may remain on opposite sides of the first sacrificial gate structures. The third insulating layer 154 may also cover upper surfaces of the first embedded source / drain regions 110 in the first region I. The third insulating layer 154 may act as a blocking layer that may prevent the growth of an epitaxial layer on the first embedded source / drain regions 110 during a selective epitaxial growth (SEG) process performed to grow second embedded source / drain regions 210 in the second recess region II.The first spacers 150a may extend a first length Xa along the top surface of the first active fins 105 (i.e., in the Y direction). The first length Xa may be substantially equal to the sum of the first thickness X1 of one of the first spacers 150a and the second thickness X2 of one of the third insulating layers 154. The second spacers 250a may extend a third length Xc along the top surface of the second active fins 205 (i.e., the Y direction). The third length Xc may be greater than the sum of the third thickness X3 of one of the second spacers 250a and the fourth thickness X4 of one of the third spacers 254a.

[0076] A sum of the first thickness X1 of one of the first spacers 150a and the second thickness X2 of the third insulating layer 154 may be substantially equal to the sum of the third thickness X3 of one of the second spacers 250a and the fourth thickness X4 of one of the third spacers 254a. In some example embodiments, the first thickness X1 of the first spacers 150a may be substantially equal to the third thickness X3 of the second spacers 250a, and the second thickness of the third insulating layer 154 may be substantially equal to the fourth thickness X4 of the third spacers 254a. In some example embodiments, the first distance SG1 between sidewalls of adjacent ones of the first gate structures 140 that face each other may be substantially equal to the second distance SG2 between sidewalls of adjacent ones of the second gate structures 240 that face each other.A distance S1' between portions of the third insulating layer 154 that are on sidewalls of adjacent ones of the first gate structures 140 may be substantially equal to a distance S2' between the third spacers 254a that are on sidewalls of adjacent ones of the second gate structures 240.

[0077] The second embedded source / drain regions 210 may be formed using a selective epitaxial growth (SEG) method to grow an epitaxial layer in the second recess region R2. The upper surfaces of the second embedded source / drain regions 210 may be coplanar with the upper surfaces of the second active fins 205. For example, in further example embodiments, upper surfaces of the second embedded source / drain regions 210 may be positioned above the upper surfaces of the second active fins 205.

[0078] The second embedded source / drain regions 210 may comprise silicon germanium (SiGe). The second embedded source / drain regions 210 may be in-situ doped with a p-type impurity, such as boron (B), during the SEG process. An upper portion of the second embedded source / drain regions 210 may have a higher germanium (Ge) concentration than a lower portion of the second embedded source / drain regions 210 by controlling an inlet amount of germanium (Ge) during the SEG process. Some of the second embedded source / drain regions 210 may be connected to adjacent ones of the second embedded source / drain regions 210.In further exemplary embodiments, the second embedded source / drain region 210 may be formed using a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process.

[0079] Referring to Fig. 12, first and second etch stop layers 158 and 258 may be formed on the respective first and second regions I and II to cover the upper surfaces of the dielectric layer 154a and the third spacers 254a, respectively. A first insulating interlayer 162 and a second insulating interlayer 262 may be formed on the respective first and second etch stop layers 158 and 258.

[0080] The first etch stop layer 158 may be conformally formed on the third insulating layer 154 and may have a uniform thickness. The second etch stop layer 258 may be conformally formed on upper surfaces of the third spacers 254a, the second sacrificial gate structures, and the second embedded source / drain regions 210. The first and second etch stop layers 158 and 258 may include silicon nitride, silicon oxynitride, or a mixture thereof. The thickness of the first etch stop layer 158 may be substantially equal to the thickness of the second etch stop layer 258. The first and second etch stop layers 158 and 258 may be formed using, for example, an atomic layer deposition (ALD) method.

[0081] A planarization process may be performed on the first and second interlayer insulating layers 162 and 262, as well as on the first and second etch stop layers 158 and 258 to expose upper surfaces of the first and second sacrificial gate structures. Upper portions of the first and second gate mask patterns 136 and 236 may be removed during the planarization process. In some example embodiments, the first and second gate mask patterns 136 and 236 may be completely removed during the planarization process. The third insulating layer 154 may be partially removed by the planarization process to form the dielectric layer 154a.

[0082] The first and second insulating interlayers 162 and 262 may include BPSG (borophosphosilicate glass), TOSZ (tonene silazane), USG (undoped silicate glass), SOG (spin-on glass), FOX (flowable oxide), TEOS (tetraethyl orthosilicate), or an HDP-CVD (high-density plasma CVD) oxide. The first and second insulating interlayers 162 and 262 may be formed using a chemical vapor deposition process, a plasma-enhanced CVD (PE-CVD), a spin coating process, or an ALD process.

[0083] Referring to Fig. 3, the first and second gate mask patterns 136 and 236, the first and second sacrificial gates 135 and 235, and the first and second sacrificial gate dielectric layers 132 and 232 may be removed to form a plurality of openings exposing upper surfaces of the first and second active fins 105 and 205. The openings may be formed using a dry etching process and / or a wet etching process.

[0084] Referring again to Fig. 2, the first and second gate dielectric layers 142 and 242 may be formed on the first and second active fins 105 and 205, which are respectively exposed through the openings. The first and second lower gate electrodes 145 and 245 may be formed on the first and second gate dielectric layers 142 and 242, respectively. The first and second upper gate electrodes 147 and 247 may be formed on the first and second lower gate electrodes 145 and 245, respectively. First gate structures 140, each including a first gate dielectric layer 142, a first lower gate electrode 145, and a first upper gate electrode 147, may be formed in the first region I after performing a planarization process.Second gate structures 240, each including a second gate dielectric layer 242, a second lower gate electrode 245, and a second upper gate electrode 247, may also be formed in the second region II after performing the planarization process. In some exemplary embodiments, the first lower gate electrodes 145 may include a conductive material different from that of the second lower gate electrodes 245.

[0085] Fig. 14 and Fig. 15 are cross-sectional views illustrating a semiconductor device according to another exemplary embodiment of the inventive concepts. In particular, Fig. 14 and Fig. 15 enlarged views of areas M and N in Fig. 2, each of which represents the modified embodiment.

[0086] Referring to Fig. 14, a second length Xb of the first spacers 150a' formed along the upper surface of the first active fin 105 may be greater than the first length Xa of the first spacers 150a' formed in Fig. 2. The second length Xb of the first spacers 150a' may be greater than the sum of the first thickness X1 of the first spacers 150a' and the second thickness X2 of the dielectric layer 154a on the sidewall of the first gate structures 140. This result may occur if the Fig. 5, the first sacrificial spacer 152 is thicker.

[0087] The structure of the Fig. The first spacer 150a' shown in Figure 14 may reduce parasitic capacitance between the first gate structure 140 and the first embedded source / drain regions 110' protruding from the top surfaces of the first active fins 105. Some portions of the first embedded source / drain regions 110' may be formed below the first spacers 150a' to increase the amount of current.

[0088] Referring to Fig. 15, a fourth length Xd of the second spacers 250a' formed along the upper surfaces of the second active fins 205 may be greater than the third length Xc of the second spacers 250a' formed along the upper surfaces of the second active fins 205 Fig. 2. This result can occur if the second spacer 250a shown in Fig. 9 are formed thicker. In some exemplary embodiments, the second embedded source / drain regions 210' may protrude from the upper surfaces of the second active fins 205. The structure of the second sacrificial spacers 256a shown in Fig. The second spacer 250a' shown in Figure 15 may reduce parasitic capacitance between the second gate structure 240 and the second embedded source / drain regions 210' protruding from the top surface of the second active fins 205. Some portions of the second embedded source / drain regions 210' may be formed below the second spacers 250a' to increase the amount of current.

[0089] Fig. 16 is a circuit diagram illustrating an inverter circuit including a semiconductor device according to an exemplary embodiment of the inventive concepts. Fig. The semiconductor device shown in Figure 16 may be a CMOS (complementary metal oxide semiconductor) inverter.

[0090] Referring to Fig. 16, the CMOS inverter may include a PMOS transistor P1 and an NMOS transistor N1. The PMOS transistor P1 and the NMOS transistor N1 may be connected in series between a drive voltage Vdd and a ground voltage Vss. An input signal IN may be commonly input to gate electrodes of the PMOS transistor P1 and the NMOS transistor N1. An output signal may be commonly output from the drain terminals of the PMOS transistor P1 and the NMOS transistor N1. The drive voltage Vdd may be supplied to the source terminal of the PMOS transistor P1, and the ground voltage Vss may be applied to the source terminal of the NMOS transistor N1. The CMOS inverter may output the output signal inverted from the input signal. In particular, when the level of the input signal is high, the output of the CMOS inverter should be low, and when the level of the input signal is low, the output of the CMOS inverter should be high.The PMOS transistor P1 and the NMOS transistor N1 can be manufactured according to various exemplary embodiments of the inventive concepts as described above.

[0091] Fig. 17 is a circuit diagram illustrating a NAND gate cell including a semiconductor device according to an exemplary embodiment of the inventive concepts.

[0092] Referring to Fig. 17, the NAND gate cell can receive two input signals M and N and can output an output signal Q. The NAND gate cell can include a first PMOS transistor TP1, a second PMOS transistor TP2, a first NMOS transistor TN1, and a second NMOS transistor TN2. The first PMOS transistor TP1 can transmit a logic value "high" to the output signal Q when the input signal M = "low." The first and second NMOS transistors TN1 and TN2 can transmit a logic value "low" to the output signal Q when the input signals M and N are both "high." The second PMOS transistor TP2 can transmit a logic value "high" to the output signal Q when the input signal N = "low."

[0093] The Fig. The NAND gate shown in Figure 17 may operate as follows. The first and second PMOS transistors TP1 and TP2 may be turned off, and the first and second NMOS transistors TN1 and TN2 may be turned on when both of the input signals M and N have a logic value of "high." In this case, the output signal Q may be a logic value of "low." The first and second PMOS transistors TP1 and TP2 may be turned on, and the first and second NMOS transistors TN1 and TN2 may be turned off when both of the input signals M and N have a logic value of "low." In this case, the output signal Q may be a logic value of "high." The first and second PMOS transistors TP1 and TP2, and the first and second NMOS transistors TN1 and TN2 may be configured as described above, according to example embodiments of the inventive concepts.

[0094] Fig. 18 is a circuit diagram illustrating an SRAM (Static Random Access Memory) cell according to an example embodiment of the inventive concepts.

[0095] Referring to Fig. 18, the SRAM cell may have a first inverter and a second inverter formed between a power supply node Vdd and a ground node Vss. The first inverter may include a first pull-up transistor TP1 and a first pull-down transistor TN1. The second inverter may include a second pull-up transistor TP2 and a second pull-down transistor TN2. An input node of the first inverter may be connected to a source / drain region of a second pass transistor TN4 and to the output node of the second inverter. The input node of the second inverter may be connected to a source / drain region of a first pass transistor TN3 and to the output node of the first inverter. Gate electrodes of the first and second pass transistors TN3 and TN4 may be connected to a word line WL. A bit line BL may be connected to a source / drain region of the first pass transistor TN3.A bit line rail / BL may be connected to a source / drain region of the second pass transistor TN4. The first and second pull-up transistors TP1 and TP2 may be PMOS transistors. The first and second pull-down transistors TN1 and TN2, and the first and second pass transistors TN3 and TN4 may be NMOS transistors. The first and second pull-up transistors TP1 and TP2 may be configured according to an exemplary embodiment of the inventive concepts.

[0096] Fig. 19 is a block diagram of a memory device including a semiconductor device according to an exemplary embodiment of the inventive concepts.

[0097] Referring to Fig. 19, a storage device 1000 according to the exemplary embodiment of the inventive concepts may include a controller 1010 communicating with a host, and memories 1020-1, 1020-2, and 1020-3 that store data. The respective memories 1020-1, 1020-2, and 1020-3 may include semiconductor devices according to various embodiments of the inventive concepts described above with reference to Fig. 1 to 15 were described.

[0098] The host may be, for example, an electronic device on which the storage device 1000 is mounted. The host may be, for example, a smartphone, a digital camera, a desktop computer, a laptop computer, a portable media player, or the like. The controller 1010 may receive a request from the host to store data in the memories 1020-1, 1020-2, and 1020-3 or a request to retrieve data stored in the memories 1020-1, 1020-2, and 1020-3, and may generate an appropriate read or write command in response.

[0099] As in Fig. 19, at least one or more memories 1020-1, 1020-2, and 1020-3 may be connected to the controller 1010. The memories 1020-1, 1020-2, and 1020-3 may be connected to the controller 1010 in parallel to provide a high-capacity storage device 1000, such as a solid-state drive.

[0100] Fig. 20 is a block diagram of an electronic device 2000 including a semiconductor device according to an exemplary embodiment of the present inventive concepts.

[0101] Referring to Fig. 20, the electronic device 2000 may include a communication unit 2010, an input unit 2020, an output unit 2030, a memory 2040, and a processor 2050. The communication unit 2010 may include a wired or wireless communication module, a wireless internet module, a local area network communication module, a Global Positioning System (GPS) module, a cellular communication module, and the like. The wired or wireless communication module included in the communication unit 2010 may be connected to external communication networks according to various communication standards for transmitting and receiving data.

[0102] Input unit 2020 may control the operation of electronic device 2000 in response to commands received from a user and may include one or more mechanical switches, a touchscreen, a voice recognition module, or the like. Additionally, input unit 2020 may include a mouse operating according to a trackball or laser pointer method, or a finger mouse device. Additionally, input unit 2020 may further include various sensor modules that allow a user to input data therein.

[0103] The output unit 2030 may output information processed in the electronic device 2000 in the form of sound or image, and the memory 2040 may store programs for processing and controlling the processor 2050. The memory 2040 may contain at least one semiconductor device according to various exemplary embodiments of the inventive concepts as described above with reference to Fig. 1 to 15. The processor 2050 may transmit an instruction to the memory 2040 according to a required operation to thereby store or retrieve data.

[0104] The memory 2040 may be embedded in the electronic device 2000 for communicating with the processor 2050 or for communicating with the processor 2050 via a separate interface. In a case where the memory 2040 communicates with the processor 2050 via a separate interface, the processor 2050 may store or retrieve data via various interface standards, such as SD, SDHC, SDXC, MICRO-SD, USB standards, or the like.

[0105] The processor 2050 can control the operation of the respective components included in the electronic device 2000. The processor 2050 can perform control and processing related to voice communication, video telephony, data communication, and the like, or can perform control and processing for multimedia playback and management. In addition, the processor 2050 can process information input by a user through the input unit 2020 and output the results thereof through the output unit 2030. In addition, the processor 2050 can store data required to control the operation of the electronic device 2000 in the memory 2040 as described above or retrieve data from the memory 2040.

[0106] Fig. 21 is a block diagram of a system 3000 including a semiconductor device according to an exemplary embodiment of the inventive concepts.

[0107] Referring to Fig. 21, system 3000 may include a controller 3100, an input / output device 3200, a memory 3300, and an interface 3400. System 3000 may be a mobile system. Examples of mobile systems may include PDAs, portable computers, web tablets, wireless telephones, cellular phones, digital music players, and memory cards.

[0108] The controller 3100 may execute a program and control the system 3000. The controller 3100 may be a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0109] Input / output device 3200 may be used to input or output data to or from system 3000. System 3000 may be connected to an external device, such as a personal computer or network, and may exchange data with the external device. Input / output device 3200 may be a keyboard, keypad, or display device.

[0110] Memory 3300 may store code and / or data for operating controller 3100 and / or store data processed by controller 3100. Memory 3300 may include semiconductor devices according to any of the exemplary embodiments of the inventive concepts.

[0111] Interface 3400 may be a data transmission path between system 3000 and an external device. Controller 3100, input / output device 3200, memory 3300, and interface 3400 may communicate with each other via bus 3500.

[0112] At least one of the controller 3100 or the memory 3300 may perform at least one of the functions described above with respect to Fig. 1 to 15 described semiconductor devices.

Claims

[1] Semiconductor device comprising: a substrate (101) having a first region (I) and a second region (II); a plurality of first gate structures (140) in the first region (I), wherein the first gate structures (140) are spaced apart from one another by a first distance (SG1); a plurality of second gate structures (240) in the second region (II), wherein the second gate structures (240) are spaced apart from one another by a second distance (SG2); a plurality of first spacers (150a; 150a') directly on sidewalls of the respective first gate structures (140); a dielectric layer (154a) directly on outer sidewalls of the respective first spacers (150a; 150a'); a plurality of second spacers (250a; 250a') directly on sidewalls of the respective second gate structures (240); a plurality of third spacers (254a) on outer side walls of the respective second spacers (250a; 250a'); a plurality of first embedded source / drain regions (110; 110') on opposite sides of the first gate structures (140); a plurality of second embedded source / drain regions (210; 210') on opposite sides of the second gate structures (240); an insulating intermediate layer (162, 262) over the first and second embedded source / drain regions (110; 110'; 210; 210'), wherein the dielectric layer (154a) covers upper surfaces of the first embedded source / drain regions (110; 110'), wherein the plurality of third spacers (254a) do not cover upper surfaces of the second embedded source / drain regions (210; 210'), wherein a sum of a first thickness (X1) of a first of the first spacers (150a; 150a') and a second thickness (X2) of the dielectric layer (154a) formed on a sidewall of a first of the first gate structures (140) is substantially equal to a sum of a third thickness (X3) of a first of the second spacers (250a; 250a') and a fourth thickness (X4) of a first of the third spacers (254a) formed on a sidewall of a first of the second gate structures (240), and wherein the first spacers (150a; 150a') and the second spacers (250a; 250a') have an L-shaped cross section. [2] The semiconductor device according to claim 1, wherein the first thickness (X1) of the first of the first spacers (150a; 150a') is substantially equal to the third thickness (X3) of the first of the second spacers (250a; 250a'); and wherein the second thickness (X2) of the dielectric layer (154a) is substantially equal to the fourth thickness (X4) of the first of the third spacers (254a). [3] The semiconductor device according to claim 1 or 2, wherein the first distance (SG1) is substantially equal to the second distance (SG2); and wherein a first gap (S1') formed between portions of the dielectric layer (154a) formed on opposing sidewalls of an adjacent pair of the first gate structures (140) is substantially equal to a second gap (S2') between the third spacers (254a) formed on opposing sidewalls of an adjacent pair of the second gate structures (240). [4] The semiconductor device according to any one of claims 1 to 3, further comprising an etch stop layer (158, 258) on sidewalls of the dielectric layer (154a) and the third spacers (254a), wherein a third gap (S1) between portions (158) of the etch stop layer (158, 258) formed on opposing sidewalls of the adjacent pair of first gate structures (140) is substantially equal to a fourth gap (S2) between portions (258) of the etch stop layer (158, 258) formed on opposing sidewalls of the adjacent pair of second gate structures (240). [5] A semiconductor device according to any one of claims 1 to 4, further comprising at least one active fin (105) extending in a first direction in the first region (I) such that it traverses below the first gate structures (140). [6] The semiconductor device according to any one of claims 1 to 5, wherein the first of the first spacers (150a; 150a') has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate (101), a length (Xa; Xb) of the parallel portion in the first direction being substantially equal to or greater than the sum of the first thickness (X1) and the second thickness (X2). [7] A semiconductor device according to any one of claims 1 to 6, further comprising at least one second active fin (205) extending in the first direction in the second region (II) such that it traverses below the second gate structures (240). [8] The semiconductor device according to any one of claims 1 to 7, wherein the first of the second spacers (250a') has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate (101), a length (Xd) of the parallel portion in the first direction being greater than the sum of the third thickness (X3) and the fourth thickness (X4). [9] A semiconductor device according to any one of claims 1 to 8, wherein the third spacers (254a) have an L-shaped cross section. [10] A semiconductor device according to any one of claims 1 to 9, wherein the second embedded source / drain regions (210; 210') comprise silicon germanium (SiGe) doped with a p-type impurity. [11] The semiconductor device according to claim 10, wherein the second embedded source / drain regions (210; 210') include a plurality of regions having mutually different germanium (Ge) concentrations. [12] Semiconductor device comprising: a substrate (101) having a top surface extending in a first direction and in a second direction perpendicular to the first direction; a first active fin (105) extending in the first direction in a first region (I) of the substrate (101); a first gate structure (140) traversing over the first active fin (105) in the first region (I) of the substrate (101); a first embedded source / drain region (110; 110') on a first side of the first gate structure (140); a pair of first spacers (150a) having respective inner sidewalls formed directly on respective opposite sidewalls of the first gate structure (140), each of the first spacers (150a) including a first portion extending in the first direction and a second portion extending in a third direction perpendicular to both the first and second directions; a dielectric layer (154a) comprising a material different from a material of the first spacers (150a), directly on outer sidewalls of the respective first spacers (150a); a second active fin (205) extending in the first direction in a second region (II) of the substrate (101); a second gate structure (240) traversing over the second active fin (205) in the second region (II) of the substrate (101); a second embedded source / drain region (210; 210') on a first side of the second gate structure (240); an insulating interlayer (162, 262) over the first and second embedded source / drain regions (110; 110'; 210; 210'); a pair of second spacers (250a; 250a') having respective inner sidewalls formed directly on respective opposite sidewalls of the second gate structure (240), each of the second spacers (250; 250') including a first portion extending in the first direction and a second portion extending in the third direction; a pair of third spacers (254a) comprising a material different from a material of the second spacers (250a; 250a'), directly on outer side walls of the respective second spacers (250a; 250a'); wherein the dielectric layer (154a) extends across an upper surface of the first embedded source / drain region (110; 110'), while the third spacer (254a) does not extend across an upper surface of the second embedded source / drain region (210; 210'), wherein each of the first spacers (150a) has a first thickness (X1), the dielectric layer (154a) has a second thickness (X2), each of the second spacers (250a; 250a') has a third thickness (X3), and each of the third spacers (254a) has a fourth thickness (X4), and wherein a sum of the first thickness (X1) and the second thickness (X2) is substantially equal to a sum of the third thickness (X3) and the fourth thickness (X4). [13] The semiconductor device according to claim 12, wherein the first thickness (X1) is substantially equal to the third thickness (X3), and the second thickness (X2) is substantially equal to the fourth thickness (X4). [14] The semiconductor device according to any one of claims 12 to 13, further comprising an etch stop layer (158, 258), wherein the etch stop layer (158, 258) directly contacts a top surface of the second embedded source / drain region (210; 210') and directly contacts a portion of the dielectric layer (154a) formed on a top surface of the first embedded source / drain region (110; 110'). [15] A semiconductor device according to any one of claims 12 to 14, wherein the first embedded source / drain region (110) has a top surface that is above the top surface of the substrate (101), and the second embedded source / drain region (210) is coplanar with the top surface of the substrate (101). [16] A semiconductor device according to any one of claims 12 to 15, wherein the third spacers (254a) each have a first portion extending in the first direction and a second portion extending in the third direction.

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