Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device comprising: a transistor cell arrangement comprising transistor cells (102) in a semiconductor body (104); a planar gate electrode structure (106) on the semiconductor body (104) at a first side (108), wherein the gate electrode structure (106) has a plurality of strip-shaped and parallel extending gate electrodes; Field electrode trenches (110) extending from the first side (108) into the semiconductor body (104), each of the field electrode trenches (110) having a field electrode structure (112); and wherein a depth d of the field electrode trenches (110) is greater than a maximum lateral dimension wmax of the field electrode trenches (110) along any arbitrary lateral direction on the first side (108), and a contact structure (120) which is electrically connected to the field electrodes (1122), extends into the semiconductor body (104) on the first side (108), and wherein a source region (114) of the transistor cells (102) is electrically connected to a side wall of the contact structure (120) in the semiconductor body (104).

Description

BACKGROUND

[0001] In semiconductor devices such as insulated-gate power semiconductor field-effect transistors (IGFETs), e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), static and dynamic losses affect the device's performance. While drain-to-source on-resistance (Rdson), drain-source leakage currents (IDSS), and gate-source leakage currents (IGSS) typically contribute to static losses, input and output capacitances, determined by specific capacitances such as gate-to-drain capacitance (C), also contribute to dynamic losses. GD ), Gate-to-source capacity (CGS) and drain-to-source capacity (C DS) are determined, as well as a gate resistance, which typically contribute to the dynamic losses. For example, reference is made to the disclosure content in the publications US 2014 / 0264433A1, US 2013 / 0137230A1, US 2012 / 0061720A1, US 2005 / 0032291A1, US 2003 / 0047768A1, US 2007 / 0108511A1, and the subsequently published publication DE 102014109859A1.

[0002] It is desirable to improve both the static and dynamic losses of a semiconductor device. SUMMARY

[0003] The problem is solved by the teaching of independent patent claims. Further developments are the subject of dependent patent claims.

[0004] The expert will recognize additional features and advantages upon reading the following detailed description and examining the accompanying illustrations. BRIEF DESCRIPTION OF THE IMAGES Fig. Figure 1A is a schematic cross-sectional view of a semiconductor device with field electrode trenches and a planar gate structure. Fig. Figure 1B is a schematic top view illustrating embodiments of field electrode trench shapes on a first side of a semiconductor body. Fig. 2A is a schematic top view showing parts of a transistor cell arrangement and an edge termination region of a semiconductor device with a continuous gate electrode surrounding field electrode trench contacts. Fig. Figure 2B shows an embodiment of a cross-sectional view of the semiconductor device of Fig. 2A along line A-A'. Fig. Figure 2C shows another embodiment of a cross-sectional view of the semiconductor device of Fig. 2A along line A-A'. Fig. Figure 3A is a schematic top view showing parts of a transistor cell arrangement and an edge termination region of a semiconductor device with separate gate electrode parts between field electrode trenches. Fig. Figure 3B shows an embodiment of a cross-sectional view of the semiconductor device of Fig. 3A along a line B-B'. Fig. 3C and Fig. 3D images show embodiments of cross-sectional views of the separated gate electrode parts between field electrode trenches. Fig. Figure 4A is a schematic top view showing a transistor cell arrangement and an edge termination region of a semiconductor device with strip-shaped gate electrode parts between field electrode trenches. Fig. Figure 4B shows an embodiment of a cross-sectional view of the semiconductor device of Fig. 4A along a line C-C'. Fig. Figure 5 is a flowchart of an embodiment of a method for manufacturing a semiconductor device with field electrode trenches and a planar gate structure. Fig. Figures 6 to 18 show cross-sectional views of a semiconductor body to illustrate process features of embodiments for manufacturing a semiconductor device with field electrode trenches and a planar gate structure. DETAILED DESCRIPTION

[0005] The terms “have”, “contain”, “comprise”, “exhibit” and similar terms are open terms, and these terms indicate the presence of the identified structures, elements or features, but do not exclude the presence of additional elements or features.

[0006] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements designed for signal transmission may be present between the electrically coupled elements, for example, elements that provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0007] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping concentration "n" or "p". For example, "n" means -“a doping concentration that is lower than the doping concentration of an “n” doping range, while an “n + A doping area with a relative concentration has a higher doping concentration than an n-type doping area. Doping areas with the same relative concentration doping do not necessarily have the same absolute concentration. For example, two different n-type doping areas can have the same or different absolute concentrations of doping.

[0008] The terms "wafer," "substrate," or "semiconductor wafer," as used in the following description, can encompass any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood as including silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor substrate, and other semiconductor structures. The semiconductor need not be silicon-based; it could just as easily be silicon-germanium, germanium, or gallium arsenide. According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) can form the semiconductor substrate material.

[0009] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a first or main surface of a semiconductor substrate or body. This could be, for example, the surface of the wafer, a die, or a chip.

[0010] The term “vertical”, as used in the present description, is intended to describe an orientation that is essentially perpendicular to the first surface of the semiconductor substrate or semiconductor body.

[0011] In this description, a second surface of a semiconductor substrate or semiconductor body is considered to be formed by the lower or backside surface, while the first surface is considered to be formed by the upper, front, or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, are therefore intended to describe the relative position of one structural feature to another.

[0012] In this description, n-doped refers to a first conductivity type, while p-doped refers to a second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type n-doped.

[0013] The semiconductor device can have contact points, such as contact pads (or electrodes), that allow electrical contact with the integrated circuits or a separate semiconductor device contained within the semiconductor body. The electrodes can comprise one or more electrode metal layers applied to the semiconductor material of the semiconductor chips. The electrode metal layers can be manufactured with any desired geometric shape and material composition. For example, the electrode metal layers can be in the form of a layer covering an area. Any desired metal, such as Cu, Ni, Sn, Au, Ag, Pt, Pd, and an alloy of one or more of these metals, can be used as the material. The electrode metal layer, orThe electrode metal layers do not need to be homogeneously made from a single material, allowing for different compositions and concentrations of the materials contained within them. For example, the electrode layers can be large enough to be bonded or connected to a wire.

[0014] In the embodiments disclosed herein, one or more conductive layers are applied. It should be emphasized that terms such as "formed" or "applied" are to be understood as encompassing all types and techniques of layer application. In particular, they mean that they include techniques in which layers are applied all at once, for example, as a whole, such as lamination techniques, as well as techniques in which layers are applied sequentially, such as by sputtering, plating, molding, CVD (chemical vapor deposition), PVD (physical vapor deposition), evaporation, hybrid physicochemical vapor deposition (HPCVD), and so on.

[0015] The applied conductive layer can comprise, among other things, one or more layers of metal, such as copper or tin, or an alloy thereof, a layer of conductive paste, and a layer of bonding material. The metal layer can be a homogeneous layer. The conductive paste can comprise metal particles dispersed in a vaporizable or curable polymer material, and the paste can be fluid, viscous, or waxy. The bonding material can electrically and mechanically secure or connect the semiconductor chip, for example, to a substrate or a contact clip. A soft solder material, or in particular a solder material capable of forming diffusion solder bonds, can be used, for example, a solder material comprising one or more components of tin, tin ag, tin-auger, tin-cubic copper, inferred oxide, inferred oxide, inferred oxide, inferred oxide, inferred oxide, inferred oxide, and inferred oxide.A singulation process can be used to divide the wafer into individual chips. Any division technique can be applied, such as knife cutting (sawing), laser cutting, etching, and so on.

[0016] An embodiment of a semiconductor device is shown in the schematic cross-sectional view 100 of Fig. Shown in 1A.

[0017] The semiconductor device comprises a transistor cell arrangement with transistor cells 102 in a semiconductor body 104. The semiconductor device 100 also includes a planar gate structure 106 on the semiconductor body 104 at a first side 108. Field electrode trenches 110 extend into the semiconductor body 104 from the first side 108. Each of the field electrode trenches 110 has a field electrode structure 112. A depth d of the field electrode trenches 110 is greater than a maximum lateral dimension wmax of the field electrode trenches 110 at the first side 108.

[0018] The planar gate structure 106 comprises a gate dielectric 1061 and a gate electrode 1062. The gate dielectric 1061 can comprise one or more insulating layers such as oxide(s), e.g., SiO2, nitride(s), e.g., Si3N4, high-k dielectric(s), and low-k dielectric(s). The gate electrode 1062 can comprise one or more conductive layers such as metal(s) and highly doped semiconductors, e.g., highly doped polycrystalline silicon. In the Fig. In the embodiment shown in Figure 1A, the gate electrode 1062 is continuous between adjacent field electrode trenches 110 along a lateral direction x. In some other embodiments, the gate electrode 1062 of the gate electrode structure 106 is separated and has first and second gate electrode parts that are spaced apart from each other along the lateral direction x between two adjacent field electrode trenches 110.

[0019] The field electrode structure 112 comprises a field dielectric 1121 and a field electrode 1122. The field dielectric 1121 can have one or more insulating layers such as oxide(s), e.g., SiO2, nitride(s), e.g., Si3N4, high-k dielectric(s), and low-k dielectric(s). The field electrode can have one or more conductive materials such as metal(s) and highly doped semiconductors, e.g., highly doped polycrystalline silicon. Typically, the thickness d1 of the field dielectric 1121 is greater than the thickness d2 of the gate dielectric 1121. In the Fig. In the embodiment shown in Figure 1A, the field electrode 1122 is a single field electrode. In some other embodiments, the field electrode 1022 can have more than one, for example, two, three, four, or even more field electrode parts arranged successively along a vertical direction y perpendicular to the first side 108. In some embodiments, the thickness of the field dielectric 1121 varies along the vertical direction. In some embodiments comprising multiple field electrode parts, each field electrode part can have a different thickness of the field dielectric 1121 inserted between the respective field electrode part and the semiconductor body 104. In some embodiments, the field electrode parts are electrically insulated from one another. The field electrode parts can be coupled to different voltages, for example, via a voltage divider.The voltage divider may, for example, include a resistor(s) and / or a diode(s), which may be located inside and / or outside the semiconductor body.

[0020] Source and body regions 114, 116 of opposite conductivity type are formed in the semiconductor body 104 on the first side 108. In a channel region 118 of the body region 116, which borders the gate dielectric 1061 on the first side 108, a conductive channel can be switched on and off by varying a voltage applied to the gate electrode 1062.

[0021] In the Fig. In the embodiment shown in Figure 1A, a contact structure 120, which is electrically connected to the field electrodes 1122, extends into the semiconductor body 104 on the first side 108. The source regions 114 and the body regions 116 of the transistor cells 102 are electrically connected to side walls of the contact structure 120 in the semiconductor body 104.

[0022] Embodiments of the shapes of the field electrode trenches 110 on the first page 108 are shown in the schematic top views of Fig. Figure 1B shows that in some embodiments, the field electrode trenches 110 on the first side 108 assume at least one of the shapes round, elliptical, and polygonal. The maximum lateral dimension of the field electrode trenches 110 in the figures shown in Figure 108 is... Fig. The various embodiments shown in 1D are denoted by wmax.

[0023] The field electrode trenches 110 offer a technical advantage by providing an enlarged mesa area for current flow while maintaining lateral charge compensation. This contributes to a further reduction of resistance in a current path between drain and source, and thus to a further reduction of Rdson. The planar gate structure 106 not only enables a simplified manufacturing process and layout, but also a lateral channel that allows for a low gate-to-drain capacitance C. GD which is advantageous.

[0024] A gate resistor can be adapted to application requirements with regard to flexibility in selecting the thickness of the gate electrode 1062, the layout, and the material composition. Since the gate electrode 1062 is located on the top of a mesa region 122 and the gate electrode can also be divided into sections, the gate-to-drain capacitance C can be GD will be further reduced.

[0025] Furthermore, the body and source regions 116, 114 can be formed by self-adjusted ion implantations with respect to the gate electrode 1062, which is advantageous with regard to narrowing the gate-to-source threshold voltage distribution. A dopant concentration profile of the mesa region 122 as well as of the semiconductor body 104 below the field electrode trenches 110 can be adapted to compensate for, for example, segregation effects or JFET effects. A field stop layer with a higher dopant concentration than the drift zone, which borders a bottom surface of the body region 116, can be arranged between the drift zone and a second side of the semiconductor body 104 opposite the first side.The semiconductor body 104 can also have several epitaxial layers on a semiconductor substrate, wherein the dopant concentration of the epitaxial layers gradually increases from an outermost layer of the epitaxial layers towards the semiconductor substrate. Furthermore, lifetime-controlled semiconductor regions can be formed in the semiconductor body 104 for the purpose of reducing reverse recovery charge (Qrr). In some embodiments, the lifetime-controlled semiconductor regions comprise platinum (Pt). In some embodiments, a net dopant concentration in the mesa region 122 is reduced in a first part between the gate dielectric 1061 and a reference level above or below a bottom surface of the body regions 116, for example by counter-doping the first part, while a second part of the mesa region 122 below the first part remains unchanged.Counter-doping in the case of an n-doped mesa region can be achieved by introducing p-type dopants into the first part, for example by ion implantation and / or diffusion, in an amount that allows the n-type dopants in the first part to partially compensate. A reduction in the net dopant concentration in the first or upper part of the mesa region 122 and adjacent to the gate dielectric 1061 offers the technical advantage of reducing the gate-to-drain capacitance C. DGIn some embodiments, the net dopant concentration of the mesa region 122 is increased in the first part between the gate dielectric 1061 and the reference level above or below the bottom of the body regions 116. Increasing the net dopant concentration in the first or upper part of the mesa region 122 adjacent to the gate dielectric 1061 offers the technical advantage of reducing the JFET effect caused by space charge regions extending from opposite body regions 116 within a mesa region. This also reduces the negative impact on the drain-to-source on-resistance (Rdson) due to the planar channel structure.

[0026] The field dielectric 1121 can also have a tapered profile, for example by having a lower field dielectric segment with a thickness d1 and an upper field dielectric segment with a thickness d 11exhibits. A dashed line in the schematic cross-sectional view of Fig. Figure 1A shows an interface between the field dielectric 1121 and the field electrode 1122 in an upper part of the field electrode trench 1110. In some embodiments, the upper and lower parts of the field electrode 1122 can also have an intermediate layer with high resistance or insulation, so that the lower part of the field plate 1122 has a high resistance or capacitive coupling to the source, which can be advantageous with regard to damping an overshoot during turn-off.

[0027] Fig. Figure 2A shows a top view of some embodiments of a semiconductor device with a continuous gate electrode 1062 between adjacent field electrode trenches 110 in a transistor cell arrangement 124. A boundary termination region 125 surrounds the transistor cell arrangement 124.

[0028] Initial contacts extend through initial openings 130 in the gate electrode 1062 and are electrically connected to the field electrodes 1122 in the field electrode trenches 110 as well as to the body and source areas 116, 114. In the Fig. In the embodiment shown in Figure 1A, the gate electrode 162 is formed in a continuous manner in the transistor cell arrangement 124 and, apart from the first openings 130, is free of further openings in the transistor cell arrangement 124.

[0029] A gate wiring 132 made of one or a plurality of conductive materials electrically connects the gate electrode 1062 to a gate runner 134 which runs around the transistor cell arrangement 124 to provide a plurality of gate electrodes between connection points 136.

[0030] In the edge termination region 125, transition termination structures are arranged to reduce an electric field peak in the vicinity of the transistor cell arrangement 124. In the Fig. In the embodiment shown in Figure 2A, the transition termination structures can have a plurality of transition termination trenches 138, wherein the transition termination trenches comprise transition termination trench electrodes 139 that are electrically insulated from a surrounding part of the semiconductor body 104 by transition termination trench dielectrics 140. Fig. 2A runs a row of termination trenches 138 around the transistor cell arrangement 124. In other embodiments, for example, more than one row of termination trenches 138, such as two, three, four or even more rows of termination trenches 138, can run around the transistor cell arrangement 124. In the Fig. In the embodiment shown in Figure 2A, one shape of the transition termination trenches 138 corresponds to a shape of the field electrode trenches 110 on the first side 108. In some other embodiments, the shape of the transition termination trenches 138 differs from the shape of the field electrode trenches 110 on the first side 108. In some other embodiments, additional or alternative structural elements of transition termination structures may be arranged in the edge termination area 125. Typical structural elements of additional or alternative transition termination structures include one or more field plate elements, ring structures such as floating or potential-free guard rings or ring segments, Junction Termination Extension (JTE) structures, and Variation of Lateral Doping (VLD) structures.

[0031] An optional boundary trench 142 can be arranged in the edge termination region 125 and run around the transistor cell arrangement 124. A boundary trench electrode 143 in the boundary trench 142 can be electrically insulated from a surrounding part of the semiconductor body 104 by a boundary trench dielectric 144. At intermediate connection points 145, the boundary trench electrode 143 can be electrically connected to a contact layer or an electrode, for example, to a source electrode in a wiring region above the semiconductor body 104.

[0032] An embodiment of a cross-sectional view of the semiconductor body 104 along line AA' of Fig. 2A is in Fig. Figure 2B shows the gate electrode 1062, which comprises a single gate electrode portion between two adjacent field electrode trenches 110. The gate dielectric 1061 and a field insulation layer 146 merge at a boundary between the transistor cell arrangement 124 and the edge termination region 125. The thickness of the field insulation layer 146 is greater than the thickness of the gate dielectric 1061. An intermediate dielectric 148 is arranged on the gate electrode 1062 and on the field insulation layer 146 for electrical insulation of the wiring of the semiconductor body 104.

[0033] The first contacts 128 provide an electrical connection between the field electrodes 1122 and the source and body regions 114, 116 on one side, and a source electrode 150 on the other. The source electrode 150 can be part of a structured wiring layer, for example, part of a structured metallization layer. The source electrode 150 is also electrically connected to the transition trench electrode 139 via a contact 1201.

[0034] Another embodiment of a cross-sectional view of the semiconductor body 104 along line AA' of Fig. 2A is in Fig. 2C is shown. A doped auxiliary region 119 is arranged in a first part of the mesa region 122 between the gate dielectric 1061 and a reference level above or below a bottom surface of the body regions 116. In the Fig. In the embodiment shown in Figure 2C, the reference level lies below the underside of the body regions 116. In some embodiments, the net dopant concentration in the doped auxiliary region 119 is lower than in a portion of the mesa region 122 below the doped auxiliary region 119. The doped auxiliary region 119 can be formed, for example, by counter-doping the mesa region 122. Counter-doping in the case of an n-doped mesa region can be achieved by introducing p-type dopants into the doped auxiliary region 119, for example, by ion implantation and / or diffusion, in an amount sufficient to partially compensate for the n-type dopants in the doped auxiliary region 119. A reduction of the net dopant concentration in the doped auxiliary area 119 or in an upper part of the mesa area 122 adjacent to the gate dielectric 1061 enables the technical advantage of reducing the gate-to-drain capacitance C. GDIn some embodiments, the net dopant concentration in the doped auxiliary region 119 is greater than in a portion of the mesa region 122 below the doped auxiliary region 119. Increasing the net dopant concentration in the doped auxiliary region 119 of the mesa region 122 offers the technical advantage of reducing a JFET effect caused by space charge regions extending from opposite body regions 116 of a mesa region, and leading to a reduction in the negative influence on the drain-to-source turn-on resistance (Rdson) due to the planar channel structure.

[0035] Fig. Figure 3A shows a top view of another embodiment of a semiconductor device with separate gate electrode parts. The gate electrode 1062 has first sections 1063, each of which is arranged around an associated contact of the first contacts 128, and second sections 1064, each of which is arranged to connect two or more of the first sections 1063.

[0036] The in Fig. The schematic cross-sectional view shown in 3B is an embodiment of a cross-section along a line BB' of Fig. 3A. The gate electrode 1062 comprises first and second gate electrode parts 1063, which are spaced apart from each other along the lateral direction x between two adjacent field electrode trenches 110. Dividing the gate electrode 1062 into the first and second gate electrode parts 1063 allows for a further reduction of the gate-to-drain capacitance C. GD . In the in Fig. In the embodiment shown in 3B, the spaced-apart first and second gate electrode parts 1063 are connected to the Fig. 3A shows the Gaterunner 134 electrically connected.

[0037] Other embodiments of the connection of the first and second gate electrode parts 1063 are shown in the schematic cross-sectional views of Fig. 3C and Fig. Shown in 3D. Fig. 3C allows one of the first and second gate electrode parts 1063 to be electrically connected to the gaterunner 134, and the other of the first two gate electrode parts 1063 can be connected to the source electrode 150. This connection scheme is advantageous, for example, for high-speed switching applications.

[0038] As shown in the schematic cross-sectional view of Fig. As shown in 3D, the thickness t1 of the gate dielectric 1061 of one of the first and second gate electrode parts 1063, which is electrically connected to the gate runner 134, is greater than the thickness t2 of the gate dielectric of the other of the first and second gate electrode parts 1063, which is connected to the source electrode 150. The other of the first and second gate electrode parts 1063, which is connected to the source electrode 150, acts as a metal-oxide-semiconductor (MOS) controlled diode, which provides a small forward voltage VF at a reference current.

[0039] Fig. Figure 4A is a top view of some embodiments of a semiconductor device with strip-shaped gate electrode parts 1063 between field electrode trenches 110. A second contact 1065 to the source and body regions 114, 116 is positioned between the first and second gate electrode parts 1063.

[0040] An embodiment of a cross-sectional view of the semiconductor body 104 along a line CC' of Fig. 4A is in Fig. 4B shown.

[0041] Unlike the ones in Fig. In the embodiment shown in Figure 2B, the source and body regions 114, 116 are electrically connected to the source electrode 150 via a second contact 1065, which extends from the first side 108 into the semiconductor body 104. The source and body regions 114, 116 are arranged between the first and second gate electrode parts 1063 along the lateral direction x.

[0042] In some embodiments, the semiconductor device is a vertical field-effect transistor with an insulated gate, comprising a first load electrode, for example the source electrode 150, on the first side 108 and a second load electrode L2 on a second side 109 opposite the first side 108.

[0043] Fig. Figure 5 is a schematic flowchart illustrating a process 500 for the manufacture of a semiconductor device.

[0044] While Method 500 is presented and described as a sequence of operations or events, the presented sequence of such operations or events is not to be understood as restrictive. For example, some operations may occur in a different order and / or concurrently with other operations or events, in addition to those presented and / or described herein. Furthermore, not all presented operations need include one or more aspects of embodiments of this disclosure. Likewise, one or more of the operations described herein may be carried out in one or more separate operations and / or phases.

[0045] The process feature S100 includes the formation of field electrode trenches extending from a first side into a semiconductor body, wherein a depth d of the field electrode trenches is greater than a maximum lateral dimension wmax of the field electrode trenches at the first side.

[0046] The process feature S110 includes the formation of a field electrode structure in the field electrode trenches.

[0047] The process feature S120 includes the formation of a planar gate electrode on the semiconductor body on the first side.

[0048] The process feature S130 includes the formation of a source region in the semiconductor body by ion implantation of dopants self-aligned to the gate electrode and to the field electrode structure, wherein the gate electrode and the field electrode structure form an implantation mask.

[0049] In some embodiments, a contact trench is formed in the semiconductor body by removing an upper portion of the field dielectric of the field electrode structure within the field electrode trenches. The contact trench can be filled with a conductive material that is electrically connected to the source region via a side wall of the contact trench.

[0050] In some embodiments, a body region in the semiconductor body can be self-aligned to the gate electrode and the field electrode structure by ion implantation of dopants, wherein the gate electrode and the field electrode structure form an ion implantation mask.

[0051] The schematic cross-sectional views of the semiconductor body 104 in the Fig. Figures 6 to 18 show process features according to embodiments for the manufacture of a semiconductor device.

[0052] With reference to the schematic cross-sectional view of Fig. In this embodiment, trenches 610 are formed in the semiconductor body by an etching process using an etch mask pattern on the first side 108. After forming a first dielectric material 612 on the semiconductor body 104, the first dielectric material 612 lines the side walls and a bottom of the trenches 610 as well as a top of the semiconductor body 104. The first dielectric material 612 can be produced by a conformal deposition process, for example, by low-pressure chemical vapor deposition (LPCVD) of silicon oxide or by thermal oxidation. A first conductive material 614 is formed on the first side 108 in the trenches 610 as well as on the dielectric material 612. In some embodiments, the first conductive material 614 is a highly doped polycrystalline silicon deposited by CVD and / or a metallic material, for example, Ti / TiN / W.Each material consisting of the first dielectric material 612 and the first conductive material 614 can, for example, be formed from a layer or from a stack of layers.

[0053] Fig. Figure 7 is a schematic cross-sectional view of the [structure]. Fig. Figure 6 shows the semiconductor body 104 after removal of the first conductive material 614 down to the first dielectric material 612. In some embodiments, the first conductive material 614 is removed by a chemical-mechanical polishing process (CMP process). Additionally or alternatively, the first conductive material 614 can be removed by etching down to the first dielectric material 612.

[0054] In the schematic cross-sectional view of Fig. 8 A first mask 616 is formed on a portion of the first dielectric material 612 at the first side 108. In some embodiments, the first mask 616 is absent in areas where the transistor cell arrangement is to be formed and is present in areas where transition termination trench structures are to be formed.

[0055] After the formation of the first mask 616, the fabrication of the semiconductor device can be continued as shown in the schematic cross-sectional view from Fig. Figure 14 shows the alternative. Alternatively, a tapered field electrode, such as in Figure 14, can be used. Fig. 1A shown by dashed lines, are produced by processes that are shown in the schematic cross-sectional views of Fig. 8 to 13 are shown, specifically before continuing with the sections in the Fig. 15 to 18 processes shown.

[0056] After training the first Mask 616 in Fig. 8 The first conductive material 614 is partially removed from the trenches 610, for example by an etching process.

[0057] In the schematic cross-sectional view of Fig. 9 The dielectric material 612 is at least partially removed from the first side 108. Instead of partially removing the first dielectric material 612 in unmasked parts of the semiconductor body 104, the first dielectric material 612 can also be completely removed from the unmasked parts of the semiconductor body 104 and reformed using a suitable process such as a deposition and / or growth process.

[0058] In some embodiments, a dielectric is formed on the uncovered parts of the regenerated first conductive material 614 in the trenches 610 to provide electrical insulation between upper and lower field electrodes to be formed in the trenches 610.

[0059] In the schematic cross-sectional view of Fig. In 10, a second conductive material 618 is formed in the grooves 610 that are not covered on the first side, as well as on the dielectric material 612. In some embodiments, the first and second conductive materials 614, 618 are identical. In some embodiments, the first and second conductive materials 614, 618 consist of highly doped polycrystalline silicon and / or a metal layer, for example Ti / TiN / W.

[0060] Regarding the schematic cross-sectional view of Fig. 11. The second conductive material 618 is removed from the first side 108 to the first dielectric material 612, for example by CMP and / or etching. The second conductive material 618 can serve as the upper field electrode portion in an upper part of the trenches 610, and the first conductive material 614 can serve as the lower field electrode portion of a tapered field electrode in a transistor cell arrangement to be formed in a lower part of the trenches 610. Trenches 610 that contain the first conductive material 614 up to the first side 108 can serve as transition termination trenches in an edge termination region of a semiconductor device to be formed.

[0061] With reference to the schematic cross-sectional view of Fig. In step 12, a second mask 620 is formed on a portion of the first dielectric material 612 on the first side. Then, the first dielectric material 612 on the first side 108 is removed from unmasked portions of the semiconductor body 104. In some embodiments, the second mask 620 is absent in areas where a transistor cell field is to be formed and is present in areas where junction termination structures are to be formed.

[0062] In the schematic cross-sectional view of Fig. 13 the second mask 620 is removed from the first side 108.

[0063] As an alternative to the formation of the first and second conductive materials 614, 618 in some of the trenches 610, as exemplified in Fig. Figures 8 to 13 show the provision of a tapered electrode in trenches 610 (Option I). Alternatively, a non-tapered or only slightly tapered electrode (due to trench etching) can be used in trenches 610, as shown in the schematic cross-sectional view of Figure 8. Fig. 7 (Option II) shows that the semiconductor body 104 undergoes further processing. The schematic cross-sectional view of Fig. The semiconductor bodies 104 shown in Figure 14 result from the processing of the semiconductor body 104, as shown in Figure 14. Fig. 7 shown, after removal of parts of the first dielectric material 612 and partial exposure of the semiconductor body 104 on the first side 108.

[0064] Although the in the Fig. Since the process characteristics shown in points 15 to 18 are based on Option I, the process characteristics shown apply equally to Option II.

[0065] In the schematic cross-sectional view of Fig. 15. A second dielectric material 622, serving as a gate dielectric in a transistor cell arrangement, is formed on the semiconductor body 104, for example, by a thermal oxidation process. Then, a third conductive material 624 is formed on the second dielectric material 622 and structured by lithography, e.g., for the purpose of providing a planar gate electrode in a transistor cell arrangement and for providing connecting leads in the vicinity of the transistor cell arrangement. In some embodiments, the third conductive material 624 comprises or consists of polycrystalline silicon and / or a metallic layer.

[0066] In the schematic cross-sectional view of Fig. 16 Ion implantation processes are carried out in a self-adjusting manner with respect to the third conductive material 624 and the first dielectric material 612. First semiconductor regions 626 are formed by ion implantation of dopants of a first conductivity type for the purpose of providing body regions in a transistor cell arrangement to be formed. Second semiconductor regions 628 are formed by implantation of dopants of a second conductivity type for the purpose of providing source regions in a transistor cell arrangement to be formed. Examples of p-type dopants in silicon include boron (B), gallium (Ga), aluminum (Al), etc. Examples of n-type dopants in silicon include phosphorus (P), arsenic (As), antimony (Sb), etc.

[0067] In the schematic cross-sectional view of Fig. 17. A third dielectric material 630 is formed on the third conductive material 624 and on the first and second dielectric materials 612, 622 for the purpose of providing an interlayer dielectric in a transistor cell arrangement to be formed. Openings are formed through the third dielectric material 630. Some of the openings extend further through the first dielectric material 612 and into the semiconductor body 104. A fourth conductive material 634 is formed on the third dielectric material 630 and in the openings to establish an electrical contact with the first conductive material 614 and the first and second semiconductor regions 626, 628.

[0068] In the schematic cross-sectional view of Fig. 18 A fifth conductive material 636 is formed on the fourth conductive material 636, for example, a power metallization layer such as a copper layer and / or a copper alloy such as AlCu. In some embodiments, the formation of the fifth conductive material 636 can also be omitted. The fourth and fifth conductive materials 634, 636 are structured to provide different electrodes, for example, source and gate electrodes.

[0069] Further processes can follow on the first side 108 and / or on a second side opposite the first side, for example the formation of a drain contact on the second side to enable front-end-of-line (FEOL) processing as described in Fig. to complete the semiconductor device shown in 1.

[0070] The second side of the semiconductor body 104 can be attached to a substrate, for example, by gluing, soldering, or sintering. If the semiconductor device is attached by soldering, soft soldering or diffusion soldering, for example, can be used to attach the semiconductor device. The semiconductor body 104 can, for example, be attached to the substrate with its second side facing the substrate. The substrate can be, for example, a leadframe, a ceramic substrate such as a DCB (direct copper bonded) ceramic substrate, or a printed circuit board (PCB).

Claims

[1] Semiconductor device comprising: a transistor cell arrangement comprising transistor cells (102) in a semiconductor body (104); a planar gate electrode structure (106) on the semiconductor body (104) at a first side (108), wherein the gate electrode structure (106) has a plurality of strip-shaped and parallel extending gate electrodes; Field electrode trenches (110) extending from the first side (108) into the semiconductor body (104), each of the field electrode trenches (110) having a field electrode structure (112); and wherein a depth d of the field electrode trenches (110) is greater than a maximum lateral dimension wmax of the field electrode trenches (110) along any arbitrary lateral direction on the first side (108), and a contact structure (120) which is electrically connected to the field electrodes (1122) extends into the semiconductor body (104) on the first side (108), and wherein a source region (114) of the transistor cells (102) is electrically connected to a side wall of the contact structure (120) in the semiconductor body (104). [2] Semiconductor device according to claim 1, wherein a shape of the field electrode trenches (110) on the first side (108) corresponds to at least one of the shapes round, elliptical, polygonal and polygonal with rounded corners. [3] Semiconductor device according to one of the preceding claims, wherein each of the field electrode trenches (110) has a single field electrode which is electrically coupled to a source electrode. [4] Semiconductor device according to claim 1, wherein a gate electrode (1062) of the gate electrode structure comprises first and second gate electrode parts (1063) which are spaced apart from each other along a lateral direction between two adjacent field electrode trenches. [5] Semiconductor device according to claim 4, wherein body and source regions (116, 114) are arranged between the first and second gate electrode parts. [6] Semiconductor device according to claim 4, wherein body and source regions (116, 114) are arranged between the first gate electrode part and one of two adjacent field electrode trenches (110) and between the second gate electrode part and the other of the two adjacent field electrode trenches (110). [7] Semiconductor device according to one of the preceding claims, wherein a gate electrode (1062) of the gate electrode structure (106) has a single gate electrode part between the two adjacent field electrode trenches (110). [8] Semiconductor device according to claim 7, wherein a net dopant concentration in an upper part of a mesa region (122) adjacent to a gate dielectric (1061) is smaller than in a lower part of the mesa region (112) below the upper part. [9] Semiconductor device according to claim 7, wherein a net dopant concentration in an upper part of a mesa region (122) adjacent to a gate dielectric (1061) is greater than in a lower part of the mesa region (122) below the upper part. [10] Semiconductor device according to one of the preceding claims, wherein a width wm of the mesa area (122) between two adjacent field electrode trenches (110) on the first side (108) is smaller than a width wt of each of the field electrode trenches (110). [11] Semiconductor device according to one of the preceding claims, wherein each of the field electrode trenches (110) has a plurality of field electrodes arranged successively along a vertical direction perpendicular to the first side (108). [12] Semiconductor device according to one of the preceding claims, wherein the semiconductor device is a vertical field-effect transistor with an insulated gate, having a first load electrode on the first side and a second load electrode on a second side opposite the first side, and wherein the semiconductor device also has a junction termination region (125) which at least partially surrounds the transistor cell arrangement, and the junction termination region (125) has junction termination structures. [13] Semiconductor device according to claim 12, wherein the transition termination structures have a plurality of transition termination trenches (138) extending from the first side (108) into the semiconductor body (104), and each of the transition termination trenches (138) has a transition termination electrode structure (139) electrically coupled to a source electrode, and wherein a depth dd of the transition termination trenches (138) is greater than a maximum lateral dimension wwmax of the transition termination trenches (138) at the first side. [14] Method for manufacturing a semiconductor device comprising: Forming field electrode trenches extending from a first side into a semiconductor body, wherein a depth d of the field electrode trenches is greater than a maximum lateral dimension wmax of the field electrode trenches along any arbitrary lateral direction at the first side (S100); Forming a field electrode structure in the field electrode trenches (S110); Forming a planar, strip-shaped gate electrode on the semiconductor body on the first side (S120); and forming a source region in the semiconductor body by ion implantation of dopants self-aligned to the gate electrode and the field electrode structure, which constitute an ion implantation mask (S130), and wherein the method further comprises: Forming a contact trench in the semiconductor body by removing an upper part of a field dielectric from the field electrode structure in the field electrode trenches; and Filling the contact trench with conductive material that is electrically connected to the source area through a side wall of the contact trench. [15] The method of claim 14, which further comprises: Formation of a body region in the semiconductor body by ion implantation of dopants self-aligned to the gate electrode and the field electrode structure, which represent an implantation mask. [16] The method of claim 14, which further comprises: Formation of a doped auxiliary region in an upper part of a mesa region by ion implantation of dopants self-aligned to the gate electrode structure, which represents an implantation mask.

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