TECHNIQUES BASED ON ELECTROMIGATION PROPERTIES OF A CELL COMPOUND

Abstract

A procedure that includes the following: Performing initial routing to couple a multitude of cells according to an initial circuit layout; identifying a multitude of standard rule lines and a multitude of non-standard rule lines within the initial circuit layout; Determining a first electromigration level for the standard control lines within a first cell in the initial circuit arrangement and selectively increasing the line widths of the standard control lines depending on whether the first electromigration level exceeds a first electromigration threshold, thereby providing a first modified circuit arrangement; Determining a second electromigration level for the non-standard rule lines in the first modified circuit arrangement and selectively increasing the line widths of the non-standard rule lines depending on whether the second electromigration level exceeds a second electromigration threshold, thereby providing a second modified circuit arrangement; Calculating a first maximum capacity value for the Nth cell of the first modified circuit arrangement; Calculating a second maximum capacity value for the Nth cell of the second modified circuit arrangement; and Selective reduction of a line width of a first non-standard rule line between the cell and at least one other cell in the second modified circuit arrangement depending on whether the first maximum capacitance value corresponds to the second maximum capacitance value in a predetermined ratio.

Description

BACKGROUND

[0001] Electromigration is the transport of atoms within a conductive material caused by collisions that transfer momentum between electrons traversing the conductive material (e.g., carrying current) and the atoms of the conductive material. Current integrated circuit chips frequently experience electromigration in metal compound layers. Electrons carrying current to a semiconductor device collide with metallic atoms in the metal compound layers. These collisions cause metal atoms to move within the metal compound layers (i.e., undergo electromigration), creating vacancies in the metal compound layers that can lead to the failure of the integrated circuit.

[0002] US 6,038,383 A describes a method for designing and fabricating an integrated circuit. The connection widths of the signal lines are determined by electromigration analysis on a test layout of the integrated circuit. A representative circuit for the integrated circuit is designed, and a test layout with multiple nets is created. A preprocessor eliminates nets that do not require further validation. An extraction process generates an RC network representation of each remaining net to be validated in order to create a distributed load simulation model. The distributed capacitance and resistance of the signal lines, along with the load capacitance of the receivers, are considered to obtain an accurate current flow profile. A current flow profile in the signal line of each net is determined by simulating the operation of each net using a simulator. Peak current, RMS current, and average current are determined.The post-processor determines, based on the current profile calculated for each network, whether the electromigration parameters are violated. The widths of the various signal line segments in the different networks are selected to be greater than or equal to a minimum width defined by the post-processor.

[0003] Further state of the art is known from US 5 164 817 A, US 9 009 645 B2 and KAHNG, Andrew B.; KANG, Seokhyeong; LEE, Hyein: Smart non-default routing for clock power reduction. In: Proceedings of the 50th Annual Design Automation Conference. 2013. pp. 1-7. BRIEF DESCRIPTION OF THE FIGURES

[0004] Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. Note that various features are not shown to scale, in accordance with standard industry practice. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. The Fig. Figure 1 shows a block diagram of a clock tree that provides a clock signal to a large number of synchronous circuit elements. The Fig. Figure 2 shows an exemplary cross-sectional view of a first, a second, and a third clock buffer element for use with the Fig. 1 matching embodiments. The Fig. Figure 3 shows an exemplary plan view of an upper metal layer of a first, a second, and a third pulse buffer element for use with the Fig. 1 matching embodiments. The Fig. Figure 4 shows a schematic diagram of two converters, which represent an example of circuit elements and / or clock buffer elements. The Fig. Figure 5 shows a method for circuit design synthesis according to some embodiments. The Fig. Figures 6A-6C to 9A-9C show a series of drawings at different steps of a circuit design synthesis according to some embodiments. The Fig. Figure 10 shows a block diagram of a processor-based system for adjusting the conductor width of a metal conductor according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter disclosed. Specific examples of components and arrangements are described below to simplify the present disclosure. Forming a first feature over or on top of a second feature, as described below, may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Furthermore, reference numerals may be repeated in various examples in the present disclosure.This repetition serves for simplicity and clarity and does not in itself indicate any connection between the various embodiments and / or configurations explained.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used here for the simplicity of description to describe the relationship of an element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The devices may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may also be interpreted accordingly.

[0007] The schematic diagram of an integrated circuit is a representation of an integrated circuit (IC) using geometric shapes whose structures correspond to different IC layers. These geometric shapes can represent, for example, dielectric layers, metal layers, or semiconductor layers, such as n-doped and p-doped regions, among others, and together they can define the functional elements of the integrated circuit. The geometric shapes are designed according to a circuit design specification, such as a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist, which includes a variety of functional elements, such as logic gates or transistors. The circuit design specification describes how the functional elements are to be operationally coupled to determine a circuit design that can meet the specifications.

[0008] The circuit diagram must pass a series of tests in a process called physical verification to ensure that it conforms to the circuit design specification when actually manufactured. Part of physical verification is design rule checking (DRC), which determines whether the circuit diagram meets a set of recommended parameters called design rules. A set of design rules prescribes certain geometric and binding constraints for the different IC layers to provide sufficient error margins to account for the variability of semiconductor manufacturing processes and ensure that most manufactured ICs function correctly.Some examples of design rules for DRC include: minimum active-active spacing, minimum recessed spacing, minimum channel length for transistors, minimum metal width for interconnects, and minimum metal-to-metal spacing.

[0009] Many of the rules in DRC are “default rules” because they are based on parameters specified by the manufacturing equipment and are generally applicable to all structures within a given layer. DRC rules can be determined using a scaling factor, often called lambda (“λ”), or they can be determined using an actual dimension. For example, a manufacturing equipment might provide a user with default rules for widths and spacings for metal-3 conductors with a scaling factor λ = 2 µm, where each metal-3 conductor has a minimum width of 5λ (or 1 µm), and where nearest sidewalls of adjacent metal conductors are separated by a minimum spacing of 3A (or 0.6 µm).If a metal 3 conductor is thinner than this minimum spacing, or if adjacent metal conductors are closer together than the minimum spacing, there is an increased probability that the manufacturing equipment is not suitable for producing the part correctly, or that the part will have reliability problems after manufacturing. Therefore, in such cases, a DRC defect is reported, and the width of the metal 3 conductor can be increased, or the spacing between adjacent metal conductors can be increased to mitigate the design problem.

[0010] However, in some cases, developers may want to "relax" or "tighten" these standard rules, which include sensitive nets or traces for some geometric shapes of a given layer but not all. For example, developers might want to use a non-default rule (NDR) for clock lines for one metal layer, while other M3 metal traces are still bound by standard rules rather than non-standard rules, because clock signals carried over a clock line are very sensitive to clock deviations. In some cases, the NDR might, for example, require double-width or triple-width metal traces for clock lines and at least double the width spacing between clock lines to avoid potential clocking problems.NDRs can in principle be anything the developer specifies, as long as they comply with the DRC rules (for example, the minimum or maximum metal widths should not be violated).

[0011] Aspects of this disclosure are based on the finding that non-default rule (NDR) lines of uniform width (e.g., where each NDR line is "thick," such as double-width or triple-width metal lines) can be suboptimal. It has been found that selectively using thinner NDR lines for some clock lines and wider NDR lines for others can improve routing efficiency by allowing more clock lines to be placed in a denser area and optimizing routing and capacity issues. Therefore, the width of the NDR lines can be adjusted as a function of the expected current to be fed into the NDR lines, based on current loads between different NDR lines, for example, due to differences in the positions of the NDR lines within a clock tree.A first NDR line can be made wider, for example, if a higher output current is expected to be fed into the first NDR line, while a second, thinner NDR line can be used where a lower output current is expected. Because the first NDR line is wider, it can help to compensate for electromigration problems for the first NDR line that result from the higher output current expected through the first NDR line, while the second NDR line, being thinner, can still ensure sufficient electromigration and simultaneously reduce the conductor space required for the line, thus freeing up conductor space for other lines.

[0012] In synchronized IC designs, data transmissions between functional elements of the circuit are synchronized by one or more clock signals provided by a clock tree. Regarding the Fig. Figure 1 shows a clock tree 100 that couples the clock source 102 to several synchronous circuit elements 104. The clock source 102 can be a phase-locked loop (PLL), a crystal oscillator, or another type of on-chip or off-chip oscillator, and each of the synchronous circuit elements 104 receives the clock signal through the clock tree 100. The synchronous circuit elements 104 are represented as flip-flops 104-104f, each comprising an input data terminal (Di), an output data terminal (Do), and a clock terminal (CLK). Connections to the Di and Do terminals are omitted for clarity and ease of understanding, but it is evident that the Di and Do terminals can be coupled to synchronous or asynchronous circuits to achieve a suitable circuit function.The synchronous circuit elements 104 may in some embodiments include volatile memory (e.g. SRAM, DRAM, etc.) and / or non-volatile memory (e.g. Flash, MRAM, RRAM, PCRAM, FRAM, etc.).

[0013] The clock tree 100 comprises a root line 112, which is coupled to the clock source 102, and branching points (e.g., 10a, 106b) where a clock line divides into one or more clock lines. For example, a first clock line 114 divides or branches at branching point 106a into three clock lines 114a, 114b, 114c, and a second clock line 116 divides or branches at branching point 106b into two clock lines 116a, 116b. It is possible that some clock lines, such as clock line 118, do not divide or branch, but rather extend continuously from one circuit element to another. It is evident that the Fig. The bar tree shown in Figure 100 is merely an example, and a variety of bar tree structures are considered to be part of the subject matter of the present disclosure, including H-tree arrangements, zero-bar deviation arrangements, bar trees with multiple bar sources, etc., but not limited thereto.

[0014] Clock buffer elements 108 are arranged on different clock lines within the clock tree 100. A first clock buffer element 108a, a second clock buffer element 108c, and a third clock buffer element 108g are designated, for example, and described in more detail below. The first clock buffer element 108a comprises a first input (i1) and a first output (o1), the second clock buffer element 108c comprises a first input (i2) and a second output (o2), and the third clock buffer element 108g comprises a third input (i3) and a third output (i3), with clock lines operationally coupling the clock buffer elements 108 as shown. Other clock buffer elements also comprise inputs (i) and outputs (o), but a detailed discussion is omitted for the sake of clarity.

[0015] The number of branches between a clock buffer element and the next level of clock buffers is called the output branching ("fan out"). A first clock tree section 120 typically includes more branches originating from a single clock line (e.g., three clock lines 114a, 114b, 114c branch from the first clock line 114), while a second clock tree section 122 typically includes fewer branches originating from a single clock line (e.g., two branches from each clock line in the second clock tree section 122); and a third clock tree section 124 includes no or a limited number of branches / divisions. The first clock tree section 120 shown thus has more output load than the second clock tree section 122, and the second clock tree section 122 has more output load than the third clock tree section 124.Although a minimum output load is always present due to the nature of a clock tree 100, a particularly large output load factor that is not attenuated can lead to large capacity values ​​in different areas within the clock tree, and cause drive problems and / or clock deviation problems within the clock tree 100.

[0016] The clock buffer elements 108 are dimensioned such that they each output different output currents depending on their position within the clock tree. The first clock buffer element 108a thus comprises transistors dimensioned to provide a first output current level i o1 Output from the first input o1. A portion of the first output current level i o1 The input i2 of the second clock buffer element 108c is fed via the first clock line 114, while other parts of i o1 are directed to the clock buffer elements 108b and 108d.

[0017] The second clock buffer element 108c comprises transistors dimensioned to provide a second output current level i o2 Output from the second output o2. A portion of the second output current level i o2 The input i3 of the third clock buffer element 108g is fed via the second clock line 116, while other parts of i o2 to be routed to the clock buffer 108h. The second output current level i o2 deviates from the first output current level i o1 off. The first output current level i o1 can in the Fig. In the embodiment shown in 1, for example, the output current level is higher than the second output current level i. o2 This is to help compensate for the fact that the first timing tree section 120 has a larger output load than the second timing tree section 122. This will limit drive and / or timing deviation problems.

[0018] The third clock buffer element 108g comprises transistors dimensioned to output a third output current level io3 from the third output o3. The third clock line 118 couples the third clock buffer element 108g to a synchronous circuit element (e.g., flip-flop 104c). The third output current level i o3 can be derived from the first output current level i o1 and from the second output current level i o2 deviate. The first output current level i o1 and the second output current level i o2 are in the Fig. In the embodiment shown in 1, for example, each higher than the third output current level i o3 , to help compensate for the fact that the first and second clock tree sections 120, 122 have a larger output load than the third clock tree section 124. However, it is evident that the Fig. 1 is merely an example, and other embodiments, other output current levels and other output loads are provided, which are also part of this disclosure.

[0019] The clock lines (e.g., 114, 116, 118) have line widths that are set based on the output current level that the corresponding clock line is expected to carry. The first clock line, 114, thus has a first line width w1, which corresponds to the first output current level i. o1 is directly proportional, and the second clock line 116 has a second line width w2, which corresponds to the second output current level i o2 is directly proportional. The third clock line 118 similarly has a third line width w3, which corresponds to the third output current level i. o3is directly proportional. The widths of these conductors can be calculated and set on a buffer-by-buffer basis during clock tree fabrication, and each clock buffer element 108 can thus have its own conductor width at its output, corresponding to its own output current level, which can be unique based on the location of the buffer within the clock tree 100. This provides a good balance between ensuring electromigration and minimizing conductor routing space, and can be implemented according to routing techniques that are efficient in that they can use standard buffer cells and perform conductor width adjustments in upper metal layers, requiring no or only minor modifications to the underlying standard cells.

[0020] The Fig. Figure 2 shows a cross-sectional view of a portion of the clock tree 100, comprising the first clock buffer element 108, the second clock element 108c, and the third clock buffer element 108g, which are arranged in and / or above a semiconductor substrate 200, such as a silicon or silicon-on-insulator substrate. Semiconductor devices 202 are contained within the clock buffer elements and are arranged in and / or above the substrate 200. An interconnection structure 204 is arranged above the substrate 200 and operationally couples the semiconductor devices to one another.

[0021] The semiconductor devices 202 are in the embodiment of the Fig. 2 are shown as metal-oxide-semiconductor field-effect transistors (MOSFETs) 202a, 202b, 202c, although other types of devices, such as bipolar junction transistors (BJTs), fin field-effect transistors (FinFETs), diodes, and junction field-effect transistors (JFETs), among others, can also be used. The MOSFETs shown comprise source regions 206 and drain regions 208, which have a first conductivity type, and channel regions 210, which separate the source regions and the drain regions from each other and which have a second conductivity type, the opposite of the first conductivity type. Conductive gate electrodes 212, which can be made of polysilicon or metal, such as copper or aluminum, are located over the channel regions 210 and are separated from the channel regions 210 by the gate dielectrics 214.

[0022] The interconnect structure 204 comprises several conductive layers stacked on top of each other and several vias extending vertically between adjacent conductive layers. The interconnect structure 204 shown, for example, includes a gate layer 216, a first metal layer 218, a second metal layer 220, and a third metal layer 222, although it is evident that any number of conductive layers can be present. Each conductive layer is typically made of polysilicon or a metal, such as copper or aluminum. Conductive lines extend horizontally within each conductive layer in one or more directions and act as conductors. A dielectric structure 224, such as silicon dioxide or a low-K dielectric material, provides electrical insulation between the different conductive layers.Vias 226 extend vertically between adjacent conductive layers to operationally couple the metal conductors, and contacts 228 extend vertically to electrically couple the first metal conductors to the semiconductor devices 202. One or more lower metal layers, such as layers 218 and 220 of the . Fig. Each of the two components within the compound structure 204 can have a first thickness t1. One or more upper metal layers, such as layer 222, can have a second thickness t2 that is greater than the first thickness t1.

[0023] In some embodiments, the first clock line 114, the second clock line 116, and the third clock line 118 are arranged within the upper metal layers 222. The first clock buffer 108a comprises a first output coupled via the first clock line 114 to the second input of the second clock buffer 108c, and the second clock buffer 108c comprises a second output coupled via the second clock line 116 to the third input of the third clock buffer 108g. The first clock line 114, the second clock line 116, and the third clock line 118 are shown such that, measured from a top surface 200s of the semiconductor substrate 200, they are arranged at a first height h1, a second height h2, and a third height h3, respectively.In some embodiments, the first, second, and third heights (h1, h2, and h3) are the same and / or the first, second, and third clock lines 114, 116, 118 comprise uppermost surfaces that are coplanar to each other. In some embodiments, the first, second, and third clock lines 114, 116, 118 comprise at least one surface, wherein these surfaces are coplanar to each other.

[0024] The first clock line 114 indicates, as in the Fig. 3 shown, in which an exemplary plan view of the upper metal layers 222 as from the section line of the Fig. Figure 2 indicates a first line width w1, the second clock line 116 has a second line width w2, and the third clock line 118 has a third line width w3. In some embodiments, the second line width w2 is an integer multiple of the third line width w3, and the first line width w1 is a second integer multiple of the third line width w3; the second integer multiple being larger than the first integer multiple in the illustrated example. In some embodiments, the second line width w2 lies between 1.1 times the third line width w3 and approximately three times the third line width w3; and the first line width w1 lies between 1.1 times the second line width w2 and approximately three times the second line width w2.The first, second and third line widths (w1, w2, w3) are directly proportional to the first, second and third output current levels (each i. o1 , i o2 , i o3 ) which is expected to be transmitted by the first, second, and third clock lines (114, 116, 118 respectively). The first line width w1 is therefore directly proportional to the first output current level i. o1 ; the second line width w2 is directly proportional to the second output current level i o2 ; and the third line width w3 is directly proportional to the third output current level i o3 Since the first, second, and third output currents i o1 , i o2 , i o3Since the first, second, and third line widths w1, w2, and w3 are expected to differ, they differ in this example due to differences in the output load. In the example shown, the first output current is i o1 expected to be greater than the second output current i o2 , and the first line width w1 is larger than the second line width w2; the second output current i o2 is expected to be greater than the third output current i o3 , and the second conductor width w2 is larger than the third conductor width w3. These conductor width differences help to mitigate electromigration problems arising from these differences in the output currents, while enabling dense conductor routing.

[0025] In some embodiments, the line widths are directly proportional to the corresponding output current level they are expected to experience. This means that if the output current expected to be carried by a given clock line increases, the line width can increase accordingly, either linearly or otherwise. Conversely, if the output current expected to be carried by the clock line decreases, the corresponding line width can decrease, either linearly or otherwise.

[0026] The lower metal layers 218, 220 are, in some embodiments, standard rule layers in the IC structure, while traces in the upper metal layer 222 comprise a mixture of standard rule traces, such as non-clock metal traces, and non-default rule (NDR) traces, such as clock traces. The standard rule traces (e.g., non-clock metal traces) in the upper metal layer 222 can have thicknesses t2 that are the same as those of the NDR traces (e.g., clock traces) in the upper metal layer 222 and, in some embodiments, can have metal trace widths that are independent of the output current level they carry. Thus, depending on how the design synthesis was implemented, the upper metal layer 222 (e.g., M3) can include "standard rule" M3 metal traces (which, for example,each have a width w4, which is the same as that of the other standard rule lines M3, and is independent of the output current for these lines), as well as NDR-M3 metal lines, which have different line widths that can vary depending on the output current level they are expected to carry (e.g. w1, w2 and w3 in the . Fig. 3) These standard rule non-clock metal lines can, in other embodiments, also have metal line widths similar to the clock lines, which depend on the output drive current they transmit.

[0027] Although the Fig. As described and illustrated in sections 1-3 with regard to the tact tree 100, it is evident that although the application of the present disclosure tact tree structures may have various advantages, the disclosure is not limited to this application. Fig. Figure 4 shows some embodiments of an integrated circuit 400, which is applicable to clock tree structures, but is also applicable to other synchronous and / or asynchronous circuits. The integrated circuit 400 comprises a first circuit element 402, a second circuit element 404, and a third circuit element 406. A first metal conductor 408 couples an output (out1) of the first circuit element 402 to an input (in2) of the second circuit element 404. A second metal conductor 410 couples an output (out2) of the second circuit element 404 to an input (in3) of the third circuit element 406, and a third metal conductor 412 is coupled to an output (out3) of the third circuit element 406.

[0028] The first, second, and third metal conductors (408, 410, and 412, respectively) have first, second, and third conductor widths (w1, w2, and w3, respectively) that are independent of the first, second, and third output current levels (i, respectively). o1 , i o2 , i o3 ) are, which they are expected to transmit. Consequently, the first metal conductor 408 has a first conductor width w1, which is determined according to a conductor width-output current ratio (w / i). o ) directly proportional to the first output current level i o1 The second metal conductor 410 has a second conductor width w2, which differs from the first conductor width w1, but according to the conductor width-output current ratio (w / i) o ) directly proportional to the second output current level i o2The third metal conductor 412 has a third conductor width w3, which differs from the first and second conductor widths w1, w2; however, according to the conductor width-output current ratio (w / i) o ) directly proportional to the third output current level i o3 is.

[0029] The first circuit element 402 is represented as a first converter for illustrative purposes and ease of understanding, and the second circuit element 404 is represented as a second converter, although the disclosure is not limited to the use of converters for these circuit elements. The first converter consists of an NMOS transistor 414 and a first PMOS transistor 416, the gate electrodes of which receive a first input signal (in1) and the source / drain regions of which output a first output signal (out1). The first NMOS transistor 414 is shown for illustrative purposes as having a width-to-length ratio (w).n1 / l n1 ) would have a value of 3 / 1, while the first PMOS transistor 416 is shown as if it were a w p1 / l p1 -ratio of 9 / 1, although w / l ratios can vary widely depending on the implementation.

[0030] The second circuit element 404 is a second converter consisting of a second NMOS transistor 418 and a second PMOS transistor 420, whose gate electrodes receive a second input signal (in2) and whose source / drain regions output a second output signal (out2). For illustrative purposes, the second NMOS transistor 418 is shown as having a width-to-length ratio (w). n2 / l n2 ) would have a 2 / 1, while the second PMOS transistor 420 is shown as if it were a w p2 / l p2The w / l ratio would be 6:1, although the w / l ratios can vary widely depending on the implementation. Due to the existing w / l ratios, the second output signal (out2) has a second output current level i. o2 on, which is less than the first output current level i o1 amounts.

[0031] The third circuit element 406 is a third converter consisting of a third NMOS transistor 422 and a third PMOS transistor 424, whose gate electrodes receive a third input signal (in3) and whose source / drain regions output a third output signal (out3). For illustrative purposes, the third NMOS transistor 422 is shown as having a width-to-length ratio (w). n3 / l n3 ) would have a coefficient of 1 / 1, while the third PMOS transistor 424 is shown as if it were a w p3 / l p3The third output signal (out3) would have a ratio of 3:1, although the w / l ratios can vary widely depending on the implementation. Due to the existing w / l ratios, the third output current level i is also present. o3 on, which is less than the second output current level (i o2 ) amounts.

[0032] In some embodiments, the first circuit element 402 can correspond to a first clock buffer circuit (e.g., the first clock buffer element 108a in the Fig. 1) The second circuit element 404 can correspond to a second clock buffer circuit (e.g., the second clock buffer element 108c of the Fig. 1), and the third circuit element 406 can correspond to a third clock buffer circuit (e.g. the third clock buffer element 108g of the Fig. 1) A ratio of the first, second, and third output currents i o1 / i o2 / i o3It can also be configured to correspond to a ratio of the output load at the outputs of the respective clock buffer elements. Furthermore, a ratio of the first, second, and third line widths can also correspond to a ratio of the output currents and the ratio of the output load at the outputs of the respective clock buffer elements.

[0033] The Fig. Figure 5 shows a process according to some embodiments as a flowchart 500. Although the depicted process (e.g., the process described by flowchart 500) is presented and described as a sequence of actions or events, it is evident that the presented sequence of such actions or events is not to be interpreted restrictively. For example, some actions may occur in different sequences and / or simultaneously with other actions or events than those depicted and / or described. Furthermore, it may be that not all of the depicted actions are necessary to implement one or more aspects or embodiments of the present description, and one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0034] In the 502, initial routing is performed to couple a plurality of cells according to an initial circuit arrangement. In some embodiments, the cells of the plurality of cells can, for example, be arranged such that their outer edges are in contact with the outer edges of adjacent cells, so that the cells of the plurality of cells are coupled to achieve a circuit arrangement as described in an electronic design specification, such as a SPICE netlist. This initial routing can be referred to as clock tree synthesis (CTS) in some embodiments where the design specification of an electronic circuit corresponds to a clock tree, and the plurality of cells corresponds to a plurality of clock buffer elements.

[0035] In 504, the method identifies a plurality of standard control lines and a plurality of non-standard control lines within the initial circuit arrangement. The standard control lines may, in some embodiments, correspond to one or more lower metal layers, such as polysilicon lines, metal-o lines, metal-1 lines, and metal-2 lines, which are arranged entirely within the individual cells, while the non-standard control lines may correspond to one or more upper metal layers, such as metal lines, which extend between two or more cells to couple different cells together.The non-standard control lines can also be lines that exhibit higher sensitivity to clock and / or clock deviations compared to the standard control lines, so that the rising and falling signal edges on the non-standard control lines are closer to a maximum acceptable utilization level than those of signals on the standard control lines, and in some examples, they can correspond to clock lines. The non-standard control lines can be identified by a name or label assigned to them by a developer or software module. A cell identification index (N) can also be set to an initial value, such as N = 1, for block 504.

[0036] In the 506, a first electromigration level is determined for the standard control lines within an Nth cell in the initial circuit arrangement. The widths of the standard control lines are then selectively increased depending on whether the first electromigration level exceeds a first electromigration threshold, thus providing a first modified circuit arrangement. If the width-to-length ratio of a transistor controlling, for example, a standard control line of the Nth cell is expected to control a current level greater than a current-carrying capacitance of the standard control line, such as a polysilicon layer or one or more lower metal layers within the cell output, the width of the standard control line of the Nth cell can be increased to reduce the electromigration level for the Nth cell below the electromigration threshold.In some embodiments, only the conductor widths of the polysilicon layers and / or lower metal layers of the Nth cell in this block are set, and conductor widths of one or more non-standard rule conductors remain unchanged (i.e., are not set).

[0037] In 508, a first maximum capacity value (C1) for the Nth cell is calculated based on the standard control lines, including, for example, the polysilicon layers and the lower metal layers for the Nth cell. Consequently, in some embodiments, the first maximum capacity value does not take into account one or more non-standard control lines and / or upper metal layers that couple the Nth cell to neighboring or adjacent cells, and / or does not consider geometries of other cells that lie outside the Nth cell.

[0038] At 510, a second electromigration level is determined for the non-standard rule lines in the first modified circuit arrangement. The line widths of the non-standard rule lines are then selectively increased depending on whether the second electromigration level exceeds a second electromigration threshold, thus providing a second modified circuit arrangement. For example, if the second electromigration level exceeds the second predetermined electromigration threshold, some embodiments of the method may increase all line widths of the non-standard rule lines to reduce the second electromigration level below the second predetermined electromigration threshold.

[0039] At 512, a second maximum capacitance (C2) is calculated for sections of the non-standard control lines that couple the Nth cell to at least one other cell. This second maximum capacitance value can take into account the geometry of the standard control lines in addition to the non-standard control lines within the Nth cell, as well as for other cells in the second modified circuit arrangement.

[0040] In embodiment 514, the method determines whether C1 and C2 satisfy a predetermined ratio. In some embodiments, the method determines whether C2 is greater than C1.

[0041] In 516, the method selectively modifies the geometry of one or more non-standard control lines for the Nth cell until the predetermined ratio is met. In some embodiments, for example, the method selectively modifies a line width for the non-standard control line at the output of a cell, while leaving the line widths of the lower metal layers unchanged, thereby maintaining standard routing within the cells and simplifying data processing.

[0042] If C1 and C2 do not satisfy the predetermined ratio (i.e., "No" in 514), the procedure continues, for example, with 518, where a geometry of a non-standard rule conduit coupling an output of the Nth cell to an adjacent cell is adjusted until the predetermined ratio is satisfied (i.e., until C2 is greater than C1). If C2 is smaller than C1, the width of the non-standard rule metal conduit for the Nth cell can be reduced, for example, until C2 is smaller than C1.

[0043] In section 520, an example is shown where the Nth cell (N=1) has a first modified line width for the non-standard rule line such that the predetermined ratio for C1 and C2 is satisfied. The first line width for the non-standard rule line can be based on a current output of the Nth cell.

[0044] After the N=1 cell has been processed in this way, the procedure increments N at 522, and the procedure is reset to 506 and actions 506-514 are repeated for the next cell, and at 514 it is determined whether C1 and C2 satisfy the predetermined ratio for the next cell.

[0045] If C1 and C2 satisfy the predetermined ratio for the next cell (i.e., "Yes" at 514), the geometry of the non-standard rule line that couples the output of the next cell to an adjacent cell remains unchanged at 524. If, for example, C2 is larger than C1 for the next cell, the width of the non-standard rule line for the next cell can remain unchanged.

[0046] Figure 526 shows an example where the next cell (N=2) has a second non-standard rule line width, such that the predetermined ratio for C1 and C2 is satisfied. This second non-standard rule line width for the second non-standard rule line can be based on the current output of the N=2 cell. Additional cells are processed in this way.

[0047] Regarding the Fig. 6A-6C to 9A-9C are a series of representations to illustrate some embodiments of the design synthesis method. Fig. 5 to explain. The Fig. 6A, Fig. 7A, Fig. 8A and Fig. Figure 9A shows a schematic view of a circuit at different steps of the design synthesis; the Fig. 6B, Fig. 7B, Fig. 8B and Fig. Figure 9B shows top-down (plan) views of the circuit at the various stages of the design synthesis; and the Fig. 6C, Fig. 7C, Fig. 8C and Fig. Figures 9C show a cross-sectional view of the floor plan at various stages of the design synthesis. Although the Fig. 6A-6C to 9A-9C are described in relation to procedure 500, it is evident that the Fig. 6A-6C to 9A-9C are not limited to Procedure 500, but can rather be considered individually. Similarly, it is evident that although Procedure 500 is limited to the Fig. The procedure is described in sections 6A-6C to 9A-9C, but does not apply to the Fig. 6A-6C to 9A-9C is limited, but rather each can be considered individually.

[0048] In the Fig. 6A-6C, which will now be described one after the other, and which, for example, correspond to the 502 of the Fig. To correspond to 5, a multitude of cells are provided which should be operationally coupled according to an initial circuit arrangement. In the example of the Fig. In cells 6A-6C, the cells comprise a first converter 602 and a second converter 604. The first converter 602 comprises a first NMOS transistor 606 and a first PMOS transistor 608, while the second converter 604 comprises a second NMOS transistor 610 and a second PMOS transistor 612. The first NMOS transistor 606 has a width-to-length ratio (W) n1 / L n1 ) of 2 / 1, and the first PMOS transistor 608 has a W p1 / L p1 of 6 / 1, so that a first output current is transferred from the output (out1) of the first converter. The second NMOS transistor 610 has a width-to-length ratio (W) n1 / L n1 ) of 1 / 1, and the second PMOS transistor 612 has a W p1 / L p1from 3 / 1, such that a second output current, less than the first current, is transmitted during the operation from the output (out2) of the second converter. The first output (out1) comprises a first metal conductor 611 having a first conductor width w1; and the second output (out2) comprises a second metal conductor 615 having a second conductor width w2 equal to w1.

[0049] The converters are, as in the Fig. Figures 6B-6C show the transistors arranged in or on substrate 614, such as a microcrystalline silicon substrate or an SOI substrate. The first NMOS transistor 606 comprises a first and a second source / drain region (616, 618) that are heavily doped with a first conductivity type (e.g., N+) and that may be arranged in a lightly doped well region 620 that has a second conductivity type (e.g., P-). The first PMOS transistor 608 comprises a third and a fourth source / drain region (622, 624) that are heavily doped with the second conductivity type (e.g., P+) and that may be arranged in a lightly doped well region 626 that has the first conductivity type (e.g., N-). The second NMOS transistor 610 comprises a fifth and a sixth source / drain region (628, 630) of the first conductivity type (e.g. N+) and a lightly doped hollow region 632, which represents the second conductivity type (e.g.The first PMOS transistor 612 has a seventh and eighth source / drain region (634, 636) of the second conductivity type (e.g., B Plus) and a lightly doped hollow region 638 of the first conductivity type (e.g., N-). The first and second gate electrodes (640, 642), which may be of metal or polysilicon, act as data input terminals for the first and second converters, and metal leads 644 and 646 couple the transistors to achieve converter functionality. Metal leads 648, which may include the first metal lead 611 and the second metal lead 615, couple the converters to each other. The first metal lead 611 is, as in the... Fig. 6B shown, from which in the Fig. The cross-sectional plane shown in 6C is set back. Although the first metal conductor 611 is shown in the Fig. The first metal conductor 611 in the cross-sectional plane shown in 6C would not actually be visible. Fig. 6C has been drawn with a dashed profile to illustrate the operational coupling between out1 of the first converter 602 and in2 of the second converter 604, and the height of the first metal conductor 611 relative to the heights of layers 644 and 646. During operation, the voltage at the gate electrodes selectively couples a high voltage (VDD) or low voltage (GND) to the outputs of the first and second converters, such that the output is the logical opposite of the input. For example, if the input of a converter is a high voltage, the output of the converter will be a low voltage, and vice versa.

[0050] The Fig. 7A-7C, which are described together below, illustrate a first modified circuit arrangement and can, for example, replace 506 of the Fig. 5 correspond. In the example of the Fig. 7A-7C can use standard control lines (such as metal lines 646a, 646b, which couple VDD to the PMOS transistors 608, 612, and metal lines 646c, 646f, which couple GND to the NMOS transistors 606, 610) Fig. (6A-6C coupling) exhibit an electromigration level that exceeds a first electromigration threshold. Thus, the width of these standard control lines in the first modified circuit arrangement of the Fig. 7A-7C regarding the preceding Fig. 6A-6C has been increased. The width of line 646a' in the Fig. 7B, for example, refers to line 646s in the Fig. 6B has been doubled, and the width of line 646d' in the Fig. 7B is in relation to line 646d in the Fig. 6B has been doubled, although other contributions to the width change could be used. Upper metal layers and / or non-standard rule conductor layers are not set in the cells during this electromigration verification in some embodiments. Again, although the first metal conductor 611 in the Fig. 7B in the in the Fig. The cross-sectional plane shown in 7C would not actually be visible, the first metal conductor 611 in the Fig. 7B has been drawn with a dashed profile to represent the operational coupling between out1 of the first converter 602 and in2 of the second converter 604 and the height of the first metal conduit 611 with respect to the heights of layers 644, 646.

[0051] The Fig. 8A-8C, which are described together below, show a second modified circuit arrangement and can, for example, replace 510 of the Fig. 5 correspond. One or more of the non-standard rule lines (e.g. Fig. 6: Metal conduits 611, 615) can be used in the example of the Fig. 8A-8C exhibit an electromigration level that exceeds a second electromigration threshold, so that the width of these non-standard rule lines (e.g. Fig. 8: the metal conductors 611', 615') in the second modified circuit arrangement of the Fig. 8A-8C has been increased. The width of these NDR lines 611', 615' is in the Fig. 8 in some embodiments by a factor of two or a factor of three larger than the first modified circuit arrangement in the Fig. 6. The widths w1', w2' are in the embodiment of the Fig. 8 compared to that of the Fig. 6, for example, has been tripled, although other factors could be used to change the width. Lower metal layers and / or standard control lines are not adjusted under cells in some embodiments during this electromigration verification. Although the NDR line 611' is on the one in the Fig. 8C shown cross-sectional plane in the Fig. 8B would not actually be visible, but the NDR line 611' is in the Fig. Figure 8B in Fig. 8C has been drawn with a dashed profile to show the operational coupling between out1 of the first converter 602 and in2 of the second converter 604 and the height of the NDR line 611' with respect to the heights of layers 644, 646.

[0052] A geometry of a non-standard rule line that couples an output of one cell to an input of another cell is described in the Fig. 9A-9C, which are described together below, are modified until the predetermined ratio for C1 and C2 is met. The width of the second non-standard rule line is 615" in the example of the Fig. 9A-9C selectively reduced because its previous width w2' was larger than necessary to provide sufficient electromigration protection given the output current provided via the second non-standard rule line. Therefore, the width of the second non-standard rule line 615" is three times the width w2' in the Fig. 8B to a double width w2" in the Fig. 9B has been reduced, thereby creating space for further cable routing and reducing the capacitance. The width w1' of the first non-standard rule cable 611', on the other hand, is in the Fig. 9B remains unchanged because a sufficiently large output current is provided via the first non-standard control line 611' to ensure three times the line width w1'. Lower metal layers and / or standard control lines are not adjusted under cells in some embodiments during this electromigration verification.

[0053] A block diagram of 1000 of some embodiments of a process-based system for adjusting conductor widths based on electromigration properties of cell connections is shown with reference to the Fig. 10. This system, which may be formed by a computer system running auto-place-and-route programs, synthesis programs, time verification programs, etc., may implement the preceding procedures using program code on one or more general-purpose computer or processor-based systems, such as electronic design automation (EDA) programs from Mentor Graphics, Corporation; Cadence Design Systems, Inc.; Synopsis, Inc.; and others (e.g., the procedure of Fig. 5).

[0054] The processor-based system is, as in the Fig.Figure 10 is a general-purpose computing platform and can be used to implement the processes described herein. The processor-based system can include a processing unit 1002, such as a desktop computer, workstation, laptop, or a dedicated unit set up for a specific application. The processor-based system can also be equipped with a display 1004 and one or more input / output (I / O) devices 1006, such as a mouse, keyboard, or printer.

[0055] The processing unit 1002 can comprise a CPU 1008, a memory 1010, a mass storage device 1012, a video adapter 1014, and an I / O interface 1016, all connected to a bus 1018. The bus 1018 can be one or more of several types of bus architectures, including a memory bus or memory controller, an outer edge bus, or a video bus. The CPU 1008 can comprise any type of electronic data processor, and the memory 1010 can comprise any type of storage system, such as standard random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).The mass storage unit 1012 can include any type of storage device configured to store data, programs, and other information, and to make data, programs, and other information accessible via the bus 1018. For example, the mass storage unit 1012 can include one or more hard disk drives, a magnetic drive, or an optical drive. The video adapter 1014 and the I / O interface 1016 provide interfaces for connecting external devices to the processor unit 1002. Examples of external devices include the display 1004, which is connected to the video adapter 1014, and the I / O device 1006, such as a mouse, keyboard, printer, and the like, which are connected to the I / O interface 1016. Other devices can be connected to the processor unit 1002, and additional or fewer interface cards can be used.A serial interface card (not shown) can be used, for example, to provide a serial interface for a printer. The 1002 processor unit can also include a 1020 network interface, which can be a wired connection to a LAN (local area network), a WAN (wide area network), and / or a wireless connection.

[0056] Note that the processor-based system may include other components. For example, the processor-based system may include power sources, wiring, a motherboard, removable memory, casings, and the like. These other components are considered part of the processor-based system, even though they are not shown. Also note that the procedures described herein can be implemented on the processor-based system, such as by means of a program executed by the CPU 1008.

[0057] The invention relates to a method. In this method, initial conductor routing is performed to couple a plurality of cells according to an initial circuit arrangement. A plurality of standard control lines and a plurality of non-standard control lines are identified within the initial circuit arrangement. A first electromigration level for the standard control lines within a first cell in the initial circuit arrangement is determined, and the conductor widths of the standard control lines are selectively increased depending on whether the first electromigration level exceeds a first electromigration threshold, thereby providing a first modified circuit arrangement.A second electromigration level for the non-standard rule lines in the first modified circuit arrangement is determined, and the line widths of the non-standard rule lines are selectively increased depending on whether the second electromigration level exceeds a second electromigration threshold, thereby providing a second modified circuit arrangement. In the second modified circuit arrangement, the line width of a first non-standard rule line between the cell and at least one other cell is selectively decreased.

Claims

[1] Method comprising the following: Performing initial routing to couple a multitude of cells according to an initial circuit layout; identifying a multitude of standard rule lines and a multitude of non-standard rule lines within the initial circuit layout; Determining a first electromigration level for the standard control lines within a first cell in the initial circuit arrangement and selectively increasing the line widths of the standard control lines depending on whether the first electromigration level exceeds a first electromigration threshold, thereby providing a first modified circuit arrangement; Determining a second electromigration level for the non-standard rule lines in the first modified circuit arrangement and selectively increasing the line widths of the non-standard rule lines depending on whether the second electromigration level exceeds a second electromigration threshold, thereby providing a second modified circuit arrangement; Calculating a first maximum capacity value for the Nth cell of the first modified circuit arrangement; Calculating a second maximum capacity value for the Nth cell of the second modified circuit arrangement; and Selective reduction of a line width of a first non-standard rule line between the cell and at least one other cell in the second modified circuit arrangement depending on whether the first maximum capacitance value corresponds to the second maximum capacitance value in a predetermined ratio. [2] Method according to claim 1, wherein the line width of the first non-standard rule lines remains unchanged when the second maximum capacity value is greater than the first maximum capacity value, and wherein the line width of the first non-standard rule lines is reduced when the first maximum capacity value is greater than or equal to the second maximum capacity value. [3] Method according to one of claims 1 and 2, wherein the non-standard control lines comprise clock lines, and wherein the standard control lines comprise non-clock lines. [4] Method according to any of the preceding claims, wherein, when the second electromigration level exceeds the second predetermined electromigration threshold, all conductor widths of the non-standard rule conductors are increased in order to reduce the second electromigration level below the second predetermined electromigration threshold. [5] Method according to any of the preceding claims, wherein the line widths of one or more non-standard control lines remain unchanged. [6] Method according to any of the preceding claims, wherein the second conductor width is an integer multiple of the first conductor width. [7] Method according to any of the preceding claims, wherein the line width of the standard control lines is independent of the output current level they transmit. [8] A method according to any of the preceding claims, wherein an integrated circuit arrangement is produced which comprises: a first clock line having a first line width and being arranged at a first height measured from a top side of the semiconductor substrate, and a second clock line having a second line width and differing from the first line width, wherein the second clock line is located at a second height measured from the top of the semiconductor substrate, the second height being equal to the first height. [9] Processor-based system for carrying out the method according to any of the preceding claims.

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