Method for operating a storage device and storage device

Abstract

Method for operating a storage device, wherein the storage device comprises multiple storage cells, the method comprising: Determining a state of the storage device (810); Determine whether reading one of the multiple memory cells with the storage device in the specified state will result in an offset read voltage or offset read current which is offset from a target voltage or target current (820); if so, switching to another state of the storage device, wherein the storage device in the other state is designed to provide a compensation voltage or compensation current to compensate for the offset (830); and, After switching, reading the memory cell using the memory device in the other state (840).

Description

Technical area

[0001] Various embodiments generally relate to a method of operating a memory device and a memory device. background

[0002] In many semiconductor memory devices, during a read operation, a read current originating in a memory cell of the memory device can be measured and evaluated in a so-called sense amplifier. The result of the read current evaluation can be digital information (for a two-level memory cell, for example, the digital information can be 0 or 1, representing a state of the memory cell). Capacitive coupling can lead to distortion, also referred to as noise, of the read current, which makes correct evaluation of a cell current (the part of the read current originating in the memory cell, i.e., the undistorted read current) difficult or even impossible. The capacitive coupling can, for example, lead to such severe distortion of the read current that an incorrect digital value is assigned to the state of the memory cell (for example, 0 instead of 1, or vice versa).

[0003] Typically, the evaluation of data stored in memory cells can be made more reliable by increasing the distance between the read signal and a reference signal. However, such measurements can typically result in either a larger chip size or, for example, a shorter lifetime of the memory device, which can lead to a reduction in the maximum number of cycles, e.g., the memory device cannot be reprogrammed as frequently as less reliable memory devices.

[0004] In semiconductor memory devices, e.g. in flash memories, but also in other non-volatile memories, e.g. MRAM, RRAM or others, a memory cell can deliver a read current I during a read operation, which, if not distorted, is also referred to as a cell current I CELL which can charge a capacitor C, also known as C INT(for example, a capacitor formed by the bit line). After a certain time t (also called integration time t INT referred to) a signal voltage V (also referred to as voltage for short, or as integration voltage V INT ) according to the following equation (1): V=l∗t / C

[0005] In other words, the read current supplied by the memory cell can be integrated using a capacitor and thus converted into an electrical voltage.

[0006] Typically, appropriate circuits can be designed to provide, for a given capacitor, integration time, and range of the read current, a voltage that may be ideal for evaluating the logic state of the memory cell, e.g., with respect to a reference voltage.

[0007] If capacitive coupling leads to an increase in the read current I, the signal voltage V may also be increased, and thus, the distance to a fixed reference voltage may be reduced, making signal evaluation difficult. The described disturbance may not occur during every read operation, but may instead be limited to certain, well-known, situations, such as after a change in a word line address, which may lead to a coupling, e.g., a capacitive coupling, of the word line to an associated control line.

[0008] To avoid reading potentially corrupted memory cell values, a memory application may wait until a corrupted signal (e.g., a signal to which a read bias is added, which may decrease over time) has returned to the normal signal, in other words, until the read bias is in an acceptable state, before starting a sense amplifier to perform the read process.

[0009] In other cases, instead of an undesirable increase in the read current due to capacitive coupling, an increase in the read current, e.g., an increased cell current, may be desired or intended, for example, for testing purposes. For higher currents, the optimal voltage range can be reached much more quickly than for the typical read current. Therefore, determining and / or evaluating the higher currents may require accelerating the timing of the read process, which can be technically difficult and complex.

[0010] Sense amplifiers can serve a central function in memory circuits (e.g., in volatile memories such as SRAM, in non-volatile memories (also called NVM), etc.). Smaller dimensions and faster access time may require solutions to compensate for parasitic effects such as coupling and leakage. Parasitic effects can now be taken into account when configuring a sense amplifier (definitions of margins, operating conditions, etc.). However, such configurations may require a relatively large amount of semiconductor space (and therefore be expensive), may be undesirably limited in their range of operating conditions (e.g., with regard to operating temperature), and the like.

[0011] US 2016 / 0 064 044 A1 discloses a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, upon reading a memory cell of the memory cell group, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines depending on the states of the one or more local bit lines of the memory cell group.

[0012] US 2014 / 0 241 049 A1 discloses an apparatus for compensating a voltage rise on a word line in a memory, comprising a bit line, a memory cell coupled to the bit line, a bipolar selector coupled to the memory cell, a word line coupled to the bipolar selector, and a word line driver coupled to the word line. The apparatus further comprises a model word line circuit configured to model an impedance of the word line and an impedance of the word line driver, and a sensing circuit coupled to the bit line and the model word line circuit. The sensing circuit is configured to sense a state of the memory cell based on a cell current and to provide a sensing signal indicative of a state of the memory cell.The sensing circuit is further configured to adjust a bitline voltage in response to an increase in the wordline voltage, as modeled by the model wordline circuit.US 8 824 191 B2 discloses a three-dimensional array particularly suitable for memory elements that reversibly change electrical conductance in response to an applied voltage difference. Memory elements are formed on multiple levels positioned at different distances above a semiconductor substrate. A two-dimensional array of bitlines, to which the memory elements of all levels are connected, is aligned vertically from the substrate and through the plurality of levels. To compensate for the wordline resistance during reading, a sense amplifier accesses a stored reference value at a specific location on the wordline when reading a memory element.To facilitate referencing, a layout with a series of sense amplifiers is provided between two memory arrays. A selected memory element is reset without resetting neighboring elements when subjected to a bias voltage under specified conditions. Brief description

[0013] A method of operating a memory device according to claim 1 and a memory device according to claim 8 are provided. Further embodiments are described in the dependent claims.

[0014] A method of operating a memory device is provided. The memory device may include a plurality of memory cells, and the method may include: determining a state of the memory device; determining whether reading a memory cell of the plurality of memory cells with the memory device in the determined state will result in an offset read voltage or current that is offset from a target voltage or current, respectively; if so, switching to a different state of the memory device, wherein the memory device in the different state is configured to provide a compensation voltage or current to compensate for the offset; and, after switching, reading the memory cell using the memory device in the different state. Short description of the drawings

[0015] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale; instead, emphasis is generally placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which: Fig. 1A shows a graphical representation of a typical signal of a memory cell; Fig. 1B shows a graphical representation of a distorted signal of a memory cell; Fig. Figure 2A shows a graphical representation of a typical signal of a memory cell; Fig. 2B shows a graphical representation illustrating an evaluation of a typical signal of a memory cell; Fig. 2C, Fig. 2D and Fig. 2E show respective graphs illustrating an evaluation of a signal of a memory cell in cases of increased cell current; Fig. 3 shows a graphical representation of a compensated distorted signal of a memory cell of a memory device according to various embodiments; Fig. 4 shows a schematic diagram of a memory device; Fig. 5A and Fig. 5B shows schematic diagrams of a memory device according to various embodiments; Fig. 6 shows a schematic diagram of a memory device according to various embodiments; Fig. 7 shows a schematic diagram of a memory device according to various embodiments; and Fig. 8 shows a process flow for a method of operating a memory device according to various embodiments. Description

[0016] In the following detailed description, reference is made to the accompanying drawings which, for the purpose of illustration, show specific details and embodiments in which the invention may be practiced.

[0017] Various aspects of the disclosure are provided for devices, and various aspects of the disclosure are provided for methods. It is understood that basic properties of the devices also apply to methods, and vice versa. Therefore, duplicate descriptions of such properties may have been omitted for the sake of brevity.

[0018] Here, a distinction can be made between a cell current coming from a memory cell and a sense current supplied to a sense amplifier. In the case of an undistorted signal, the cell current may be identical to the sense current, whereas in the case of a distorted signal, the sense current may be different from the cell current, e.g., higher or lower than the cell current. In other words, the sense current may include or consist of the cell current and a distortion current, where the distortion current may be added or subtracted. The current including the distortion current may be referred to as the distorted sense current or the distorted cell current.

[0019] Herein, in various embodiments, a voltage is used as a read signal, and in various embodiments, a current is used as a read signal. It is to be understood that an underlying principle described herein is independent of whether the read signal is voltage or current, and that described embodiments in which either only voltage or only current is specified as the type of read signal are to be understood as also describing, with appropriate modifications, the alternative in which the other type of read signal is used. In cases where wording such as "in an offset read voltage or an offset read current whichwhich has an offset from a target voltage or a target current" or the like," it is understood that if the voltage is used as the read signal, the offset read voltage has an offset from the target voltage, and if the current is used as the read signal, the offset read current has an offset from the target current, etc.

[0020] In various embodiments, a method may be provided for compensating for or minimizing interference that may occur during a read operation of a semiconductor memory. For example, distortion of a read signal may be compensated for or minimized. This may increase the reliability of the read operation.

[0021] In various embodiments, a situation in which the distortion of the read signal may occur and also a magnitude of the distortion may be known, and it is then possible to activate the compensation only for a read operation that can be expected or is known to be affected by the distortion of the read signal.

[0022] In various embodiments, a wordline change may be an example situation that may cause signal distortion in a memory cell to be read. The wordline change, which may represent a specific type of address change, may be detected, and the read signal compensation may be enabled.

[0023] In various embodiments, compensation can be achieved, e.g., when it has been detected that a read situation occurs that is expected to be affected by signal distortion (e.g., of a known magnitude), by coupling, e.g., electrically connecting, e.g., connecting in parallel, a further capacitor to a (regular) capacitor, e.g., the bit line used for the read operation. A capacitance of the capacitor can be selected such that the undistorted signal, e.g., the undistorted signal voltage, results from the distorted cell current, in combination with a system including the (regular) capacitor and the further capacitor, according to equation (1). In various embodiments, the distortion may not be fully compensated, but may be mitigated.In other words, when compensation is applied, a difference between the distorted, compensated signal and the undistorted signal can be smaller than a difference between the distorted signal and the undistorted signal.

[0024] In various embodiments, a direction of the distortion and a compensation measure may be considered to achieve (at least partial) compensation. This can be understood as taking into account whether the distortion adds current to the read signal (e.g., through capacitive coupling) or subtracts current from the read signal (e.g., through leakage), and whether a compensation measure according to various embodiments is configured to add current to or subtract current from the read current, or is configured to add current to or subtract current from a reference current.

[0025] If no address change of word lines is required to read the memory cell, coupling, e.g., capacitive coupling, of the word line current to an associated control line may not occur. Therefore, in this case, it is possible in various embodiments that the compensating capacitor is not activated, provided no other disturbances are expected.

[0026] In various embodiments, in an integrating semiconductor memory, a read current that may have been increased in an undesirable manner, e.g., due to capacitive coupling, can be compensated by adding a compensating capacitor to a read circuit, e.g., using a switch, such that it is connected in parallel with an integrating capacitor. This compensation can, in various embodiments, only be applied when a disturbance, e.g., the undesirably increased read current, actually occurs. Such a situation in which the disturbance occurs can be detected in various embodiments by determining that an address change, e.g., a word line change, has occurred. Thus, in such a case, the compensation circuit can only be activated when the disturbance is expected.

[0027] In various embodiments, a signal voltage may be obtained by charging a capacitor with a read current that includes a cell current from a memory cell. In various embodiments, if an offset voltage to a target voltage occurs or is expected to occur, the offset may be compensated, e.g., by a compensation voltage. In various embodiments, the compensation voltage may be applied to the signal voltage. In various embodiments, the compensation voltage may be applied to a reference voltage. To provide the compensation voltage, one or more switchable capacitors and / or one or more circuits that source or sink a current may be used, wherein the capacitor(s) and / or the circuit(s) may be connected to a circuit of the memory device, e.g.,a read circuit or a reference circuit, depending on whether the offset voltage is present (its presence is expected) or not.

[0028] In various embodiments, a method may be provided to enable or simplify testing of a semiconductor memory device, or to enhance testing.

[0029] In various embodiments, the accuracy of a sense amplifier can be improved, e.g., increased, with a view to shorter access time and smaller dimensions of the memory cells within a memory array. Better accuracy of the sense amplifier can help improve the reliability and quality of a memory circuit.

[0030] In various embodiments, dynamic adjustment of a characteristic of the sense amplifier may be provided to minimize sense inaccuracy in an application in conjunction with a high-performance and large, embedded, non-volatile memory.

[0031] In various embodiments, a better detection window for detecting the read signal and thus higher reliability can be achieved for large non-volatile memory arrays operating at high read throughput.

[0032] In various embodiments, depending on the method used, an increase in the chip area of ​​the memory device can be expected to be small.

[0033] In various embodiments, a situation when a new row in a memory array (which can be addressed by a (new) word line) is activated can be improved. This event (activating the new row, i.e., changing the word line) can generate a read bias transition in a selected region for a limited time. In other words, a transient (e.g., decreasing) read bias can be formed. The transition time can, in various embodiments, be long relative to a target read access time, so that the read operation would, in principle, take place during a time in which the read bias can be present.

[0034] To avoid a waiting time, which can conventionally be used to avoid reading a signal that may be disturbed by the sense bias, activation of sense compensation may be provided according to various embodiments. In addition to a conventional sense amplifier, the following circuit parts may be implemented according to various embodiments: a detection circuit for row (word line) activation events, an annulment circuit that can deactivate the compensation in the event of a long delay between an activation event and the start of the sense amplifier, and a compensation circuit.

[0035] In various embodiments, an integration capacitance may be increased, for example, in a case where a higher read current, e.g., a distorted memory cell current, is expected, for example, in certain well-known situations, such as after a wordline change, or when a device temperature is high, e.g., above a predefined threshold. The increase in the integration capacitance may be achieved by connecting a discrete capacitor element in parallel with the integration capacitor (e.g., electrically conductive, e.g., in a non-permanent manner, e.g., using a switch), e.g., as part of a read circuit. The additional capacitor may require additional chip area, for example, for forming the additional capacitor as a metal-to-metal capacitor.

[0036] In various embodiments, the additional capacitors may not be provided as discrete elements dedicated solely to serving as additional capacitors. Instead, parasitic capacitance of lines (e.g., bit lines), which may be present anyway, may be used as the additional capacitor(s). This means that additional circuit complexity may be minimal. The capacitor(s) need not require additional semiconductor real estate (e.g., chip area), as they may be present anyway.

[0037] In various embodiments of a semiconductor memory device, a memory cell to be read may be connected to a sense amplifier by means of a bit line. The bit line may be hierarchical, e.g., by having a global bit line connected to a local bit line of a plurality of local bit lines. A parasitic capacitance of these bit lines, which may, for example, have its origin in a metal-to-metal capacitor formed in combination with neighboring bit lines, may, e.g., during a read operation, be used as an integration capacitor for converting a read current from the memory cell into a read voltage. For this purpose, unused local bit lines, e.g.,Bit lines of a neighboring sector, which may not be coupled to an addressed memory cell, can be coupled, e.g., electrically connected, to the global bit line, thereby increasing the integration capacity.

[0038] In various embodiments, by adding different numbers of local bit lines, a total capacitance can be increased in units corresponding to a capacitance of a local bit line. A value of an integration capacitance can therefore be adjusted to result in an optimal combination of read current, integration capacitance, integration time, and read voltage. An optimal combination can mean, for example, that the read voltage of a distorted read current can be identical or nearly identical to a read voltage corresponding to a non-distorted read current, and / or that the read voltage has a value within a range that can be reliably evaluated by a sense amplifier.

[0039] In various embodiments, a wordline change detector and / or a temperature sensor may be used to determine whether reading a memory cell will result in an offset read voltage or current that is offset from a target voltage or current, respectively. In various embodiments, any further sensor that can provide information about a state of the memory device and / or the read process and that can be used to estimate whether a read voltage offset may occur may be included in the memory device. An output from the sensor may be used to operate the switch, which may connect one or more additional circuit components to the read circuitry and / or the reference circuitry of the memory device.

[0040] In the following, an operating principle of a memory device and a method of operating a memory device according to various embodiments may be described using exemplary numbers (e.g., values), which may be different for other embodiments.

[0041] Fig. 1A shows a graphical representation 100 of a typical signal of a memory cell (also referred to as a cell) of an integrated semiconductor memory device, or more specifically, how a memory cell signal may change over time during a read operation (also referred to as a read process) of the memory cell. The memory cell may be, for example, a flash memory cell, or any other memory cell that may be configured to supply a cell current to the bit line.

[0042] First, at the beginning of a read cycle, a bit line can be discharged to approximately 0V (in Fig. 1A in the area labeled "Discharge" and indicated by the corresponding arrow) and may be electrically connected to the memory cell. The discharge may be initiated essentially independently of any voltage level that the bit line may have had prior to the discharge (in Fig. 1A by four exemplary voltage levels before discharging). Subsequently, the memory cell can be switched to an electrically conductive state, for example by means of a word line, and a read current can charge the bit line according to equation (1), which is Fig. 1A in a section labeled “Integration time T INT ” and an arrow. The cell current I CELL(I in equation (1)) can be determined by the state of the cell. The state of the memory cell can be binary (e.g., 0 / 1), but generally does not have to be binary, but can, for example, have multiple levels, i.e., the memory cell can be in any of more than two possible states. After the integration time t INT a voltage of the bit line can reach a value V (in Fig. 1A as signal V), which can be compared with a reference signal (in Fig. 1A not shown, but see for example Fig. 2B to Fig. 2E, which are described in more detail below and which show a similar application involving a reference voltage), to evaluate the state of the memory cell (in Fig. 1A in a section labelled “Evaluation”).

[0043] In an exemplary case, the memory cell can deliver a higher cell current (e.g., I CELL = 10µA) when it is in the "0" state than when it is in the "1" state (e.g. I CELL = 1µA). After a predetermined integration time (e.g. t INT = 5ns) for an integration capacity of e.g. C INT = 125fF, a corresponding signal voltage V can be obtained according to equation (1). In the present example, the cell current I CELL = 10µA results in a signal voltage V = 400mV.

[0044] Fig. 4 shows a schematic diagram of an exemplary memory device 400, for example a shared memory device 400, which may be configured to provide the signal described in Fig. 1A and Fig. 1B. The memory device 400 may include a plurality of memory cells 442, each of which is located at an intersection of one of a plurality of word lines WL (to distinguish the individual word lines WL, they are numbered WL0, WL1, etc.) with one of a plurality of bit lines BL. Each memory cell 442 of the plurality of memory cells 442 may be addressed by a unique combination of a word line WL and a bit line BL. Each bit line BL of the plurality of bit lines BL may be hierarchically configured, e.g., structured.For example, each bit line BL may include a global bit line section GBL (also referred to as a global bit line GBL), which may, for example, be common to all bit lines (in other words, all memory cells 442 of the plurality of memory cells 442 may be connected to a sense amplifier SA through the global bit line section GBL), and a local bit line section LBL (also referred to as a local bit line LBL), which may be individual for each bit line BL or may be common to only some of the bit lines BL, or a combination of both. The local bit line LBL may also be considered as forming a further hierarchical structure, for example, as including an intermediate section (in . Fig. 4 not marked as such), for example a section which may be common to some but not all memory cells 442, for example sections which may be common to all memory cells of a sector (dashed boxes indicate two separate sectors, sector 0 and sector 1, respectively, of the memory device, which may be arranged between a 1-of-n decoder 444 and the global bit line GBL, and the individual sections which may be arranged between the 1-of-n decoder 444 and the memory cell 442).

[0045] As another way to describe the hierarchical structure of the bit lines, a memory cell to be read may be directly connected to one of several local bit lines LBL, with only this one bit line, which may be part of a sector of the memory device (sector 0 in the case of Fig. 4), may be connected by a 1-of-n switch to a global bit line GBL, which may be connected to a sense amplifier. Other local bit lines LBL located in other sectors (only one of the other sectors is in Fig. 4), may be completely separated from the global bit line GBL. A memory cell in sector 0 may be addressed by activating its associated word line WL0. A read current may flow to the local bit line LBL and to the global bit line GBL and may charge them. The capacitance of each of the local bit lines LBL may be, for example, 100 fF, and a capacitance of the global bit line GBL may be, for example, 25 fF, so that an assumed value of a total bit line capacitance of 125 fF may result. Using this total capacitance, the read process, as described in connection with Fig. 2A and Fig. 2B, can be carried out in an ideal manner, ie the signal voltage can be within the reliable voltage range of the sense amplifier SA.

[0046] The word lines WL, the bit lines BL and the sense amplifier SA can be considered as components of a read circuit of the memory device 400.

[0047] As in Fig. 4, the shared memory device 400 may be configured to activate only a single word line (WL0, represented by the thick line) and a single bit line BL (also represented by the thick line) at any given time. Therefore, a cell state of the memory cell 442 addressed by the activated word line WL and the activated bit line BL may be evaluated using the sense amplifier SA, to which the bit line may be connected. Within a sector, the local bit line LBL to be used may be selected using the 1-of-n decoder 444, which may drive one of n switches 440 to select the local bit line LBL and thereby the corresponding memory cell 442.

[0048] Fig. Figure 1B illustrates a situation in which a disturbance (also called a distortion) reduces the read current by an amount I distvia the cell current. Otherwise, the graphical representation 101 of the graphical representation 100 of Fig. 1A similar.

[0049] The increased current I CELL +I dist (in Fig. 1B as I+I dist referred to) can cause the bit line to reach a higher voltage level V dist is charged (also called a disturbed signal or a distorted signal) than is required for the cell current I CELL would be expected or appropriate, and is therefore unsuitable for the condition of the memory cell.

[0050] The memory cell can be activated, for example, by increasing a voltage supplied to a word line WL from 0 V to a voltage with a value VWL. This can cause a cell current of 2 µA. By increasing the voltage on the word line, a signal, e.g., a distorted signal, of several hundred mV can be induced in a parallel control line CG, which can also be connected to the memory cell, e.g., electrically conductively. Due to the increased control line voltage (CG voltage), the read current can be increased, for example, by a distortion current of approximately 1.5 µA above the cell current.

[0051] For an assumed (undistorted) cell current of 2 µA and for an assumed bit line capacitance C INT = 125 fF and integration time t INT = 5 ns a signal voltage V INTof 80 mV. If the read current is increased by injecting an additional 1.5 µA as assumed, the read current can be increased to 3.5 µA, which (e.g., after the integration time t INT ) to a signal voltage V INT of 140 mV.

[0052] Fig. 2A shows a graphical representation 200 of a typical signal of a memory cell. Fig. 2B shows a graphical representation 201 illustrating an evaluation of a typical signal of the memory cell, and Fig. 2C, Fig. 2D and Fig. 2E show respective graphical representations 202, 203 and 204 illustrating an evaluation of the signal of the memory cell in cases of an increased cell current and an increased reference current.

[0053] Fig. 2A shows, similar to Fig. 1A, how a signal of a memory cell of a memory device can change over time. However, while in Fig. 1A shows a memory cell of an integrating memory device, in Fig. 2A, a change in the signal over time does not consist of an increase, but rather a decrease. Consequently, before switching the memory cell into a conductive state, the bit line can be charged to a defined voltage V BL During the integration time t INT the bit line (which can form a capacitor) can be discharged, whereby a difference between the voltage V BL and a voltage level (V0 in case of Fig. 2A), which after the integration time t INT is reached, than the signal can be considered (in Fig. 2A by the arrow between V BL and the signal V0). Thus, the signal of the memory cell can be Fig. 2A can also be described by equation (1), which can therefore be applied regardless of whether a voltage of the bit line is applied during the integration time (as in Fig. 1A) is increased (e.g. from 0 V) ​​or during the integration time (as shown in Fig. 2A) is reduced (e.g. from an initial voltage V BL out of).

[0054] As a result, embodiments described herein may be applicable to any of the described types of memory cells (signal that increases over time or signal that decreases over time), even though they may only be shown or described in connection with one of the types.

[0055] In Fig. 2B is a typical reading process, as in Fig. 2A. Two possible signals, V0, corresponding to a dashed line, and V1, corresponding to a dash-dotted line, which can correspond to two cell states 0 and 1, respectively, are shown together with a reference signal V REF (solid line). To form the reference signal V REF a reference bit line may be designed to provide a suitable reference current which drives the reference bit line during the integration time t INT to a reference level V REF can be discharged, as shown by the solid line. The bit line of the memory cell to be read can be discharged by the cell current I CELL Depending on the amount of cell current I CELL the bit line can be discharged relatively strongly, so that the resulting voltage level V0 ultimately falls below the reference signal V REF lies (in the graphic representation 201 of Fig. 2B, since the signal is the difference to the initial voltage V BL is measured, the higher cell current I CELL correspond to a higher signal), or the bit line can be discharged relatively weakly, so that a resulting voltage level V1 is ultimately above the reference signal V REF lies (in the graphic representation 201 of Fig. 2B, since the signal is the difference to the initial voltage V BL is measured, the low cell current I CELLcorrespond to a lower signal). The two voltage levels V1, V0 can thus correspond to logical states of the memory cell, e.g., "1" and "0," respectively. In a sense amplifier, the voltage levels can be differentiated by comparing them with the reference voltage, and the sense amplifier can provide a logical data signal resulting from the comparison (e.g., for signal V0, the sense amplifier can provide the logical data signal "0," and for signal V1, the sense amplifier can provide the logical data signal "1"). The process of comparing the voltage level supplied to the sense amplifier with the reference level and assigning the logical data signal can be referred to as evaluation or the evaluation process.

[0056] A typical acquisition amplifier may, depending on the implementation, have a certain voltage range (also called the reliable voltage range or reliable range) in which the evaluation works reliably. Fig. In Figure 2B, the reliable range is shown as a dotted box. For a voltage signal outside the reliable voltage range, the evaluation may be incorrect in certain cases.

[0057] Usually, e.g., for regular applications, a circuit, e.g., a read circuit, can be optimized by using a capacitance C INT the bit line and an integration time t INT be tuned in such a way that for the expected cell currents I CELL the resulting voltage after the integration time is usually always in the reliable voltage range at the end.

[0058] However, a memory device can be operated not only in the normal operating mode, but also in a test mode, for example to determine an accurate value of the cell current (since the read mode described above only allows a distinction as to whether the read current is smaller or larger than the reference value).

[0059] Such a test mode is in Fig. 2C, which, apart from the differences set out below, essentially Fig. 2A or Fig. 2B may correspond.

[0060] In Fig. 2C can, as in Fig. 2A and in Fig. 2B, the bit line is charged to a certain predefined voltage level. During the integration time t INT the bit line can be discharged to a level corresponding to a signal voltage V0. By varying the reference current V REFVarious different voltage levels can be set. By digitally evaluating a difference (V0 - V REF ) a possible voltage range can be scanned, and a voltage for which V0 = V REF (and therefore a comparator can switch from 0 to 1 or from 1 to 0) can be determined exactly. From the voltage V0, the corresponding cell current I CELL As above in Fig. As shown in Figure 2B, the sense amplifier may have a reliable voltage range (also referred to as an optimal voltage range). If the cell current is too high, the voltage level, e.g., V0, may ultimately be outside the optimal range at the end of the integration time, as shown in Fig. 2D and in Fig. 2E. In some cases, as shown in Fig. 2E, the bit line can even be completely discharged at or before the end of the integration time, which allows a correct evaluation of the voltage difference V BL - V0 can be difficult or even impossible due to the detection amplifier.

[0061] Using the above exemplary values ​​for the integration time t INT and the capacity C INT and a cell current I CELL (which may be identical to the read current) of, for example, 20 µA, equation (1) can be used to determine an integrated voltage of 800 mV. In the case of a bit line voltage V BL of 500 mV, for example, this means that the magnitude of the discharge voltage (the integrated voltage) is greater than the bit line voltage, which is the Fig. 2E, in which the bit line is completely discharged and a meaningful evaluation of the state of the memory cell may be impossible.

[0062] In various embodiments, as in Fig. 3, which shows a graphical representation 300 of a compensated distorted signal of a memory cell of a memory device according to various embodiments, a distorted signal as shown in Fig. 1B.

[0063] Fig. 5A / Fig. 5B, Fig. 6 and Fig. 7 show schematic diagrams of memory devices 500, 600, and 700, respectively, according to various embodiments. Each of the embodiments of Fig. 5A / Fig. 5B, Fig. 6 and Fig. 7 (and others) may be used to perform a method of operating a memory device according to various embodiments. For example, any of the embodiments of Fig. 5A / Fig. 5B, Fig. 6 and Fig. 7 (and others) to produce a distorted signal, for example as in Fig. 1B. Furthermore, any of the embodiments of Fig. 5A / Fig. 5B, Fig. 6 and Fig. 7 (and others) to shift a target value range, e.g., to a reliable range of the source amplifier SA. Some elements, structures, materials, working processes, etc., may be similar or identical to those used in conjunction with Fig. 4. Therefore, a repetition of their description can be omitted here.

[0064] In various embodiments, during the integration phase t INT , also referred to as integration time, an additional capacitor 552, 660, also referred to as a compensating capacitor 552, 660, which has a suitable compensating capacitance C compcan provide, be connected, e.g., electrically conductively connected, to the read circuit of the memory device, e.g., the memory device 500 or 600. The additional capacitor 552, 660 can, for example, be connected to the (e.g., currently activated) bit line BL, e.g., to the global section GBL of the bit line BL.

[0065] In various embodiments, the method of operating a memory device may include determining a state of the memory device 500, 600, for example, whether or not the at least one additional capacitor 552, 660 is currently connected to a circuit of the memory device 500, 600.

[0066] In various embodiments, the method of operating a memory device may include determining whether reading a memory cell of the plurality of memory cells with the memory device 500, 600 in the determined state will result in an offset read voltage having an offset from a target voltage. In various embodiments, situations may be known which will result in an offset read voltage, e.g., with a known direction (e.g., if a current is added to or subtracted from the read current), and optionally with a known magnitude. For example, in a case where reading the memory cell requires a wordline change, a distortion current may be added to the read current (e.g., for a certain duration, e.g., with a decreasing magnitude over the duration).As another example, a distortion current may be added to the read current in case of a high operating temperature of the device.

[0067] In various embodiments, if reading the memory cell of the plurality of memory cells with the memory device 500, 600 in the particular state will result in an offset read voltage that is offset from a target voltage, the memory device may be switched to another state, wherein the memory device in the another state may be configured to provide a compensation voltage to compensate for the offset. The another state may be another one of the possible states in which the memory device 500, 600 may be. As an example of the switching, the at least one additional capacitor 552, 660 may be connected to the circuitry of the memory device, for example, to the read circuitry or to the reference circuitry.

[0068] In various embodiments, the memory cell may be read in the other state after switching using the memory device 500, 600.

[0069] In various embodiments, as in Fig. 5A and Fig. 5B, the additional capacitor 552 may be a dedicated additional capacitor 552, in other words, an additional capacitor 552 added to the memory device 500 for the purpose of forming the additional capacitor 552. In various embodiments, a plurality of additional capacitors 552 may be provided in the memory device 500. In this case, two, three, or more of the plurality of additional capacitors 552 may be connected simultaneously to the read circuitry of the memory device 500, e.g., in parallel.

[0070] In various embodiments, as in Fig. 6, the additional capacitor 660 may be formed by bit lines BL of the memory device 600 that are not currently used for reading from / writing to one of the memory cells 442 (and which may be referred to as the unused bit lines BL). The unused bit lines BL may be electrically connected to the read circuit. In other words, the additional capacitance C comp can be contributed by one or more of the unused bit lines BL. Fig. 6, two unused bit lines BL, characterized by an area provided with diagonal stripes, may be connected simultaneously as the additional capacitor 660 to the read circuit of the memory device 500, e.g., in parallel. The additional bit lines 660 may have a common section, e.g., the global bit line section GBL, and two local bit lines LBL. While in various embodiments, the global bit line section GBL may always be connected to the sense amplifier SA and their capacitance C GBL can also be taken into account in a common memory device, the local bit lines LBL of the unused bit lines BL can be connected to the read circuit of the memory device, e.g., connected to the source amplifier SA, by switching their respective switches 440 to a closed state.

[0071] In a common storage device, e.g., the storage device 400 of Fig. 4, it may be impossible to switch two or more of the switches 440 to a closed state simultaneously. The common read circuit, e.g., a 1-of-n decoder, may be designed to allow only one of the switches 440 to close, i.e., the switch that activates the active bit line BL of the currently read memory cell 442.

[0072] In contrast, in various embodiments, e.g., as in the memory device 600 of Fig. 6, one of the switches 440 may be switched to the closed state to activate a bit line for reading a memory cell 442 of the plurality of memory cells, wherein the memory cell 442 may be readable because its associated word line WL0 may be activated at the same time. Although in each of the sectors, the plurality of switches 440 may be switched using an m-of-n decoder 662, in other words, more than one (i.e., m) of the switches 440 may be switched to a closed state at the same time, the memory device 600 may be configured to switch only one of the switches 440 of memory cells 442 connected to the same active word line WL to the closed state.In other words, at any given time, only one memory cell 442 can be read, and no local bit line LBL, which may be connectable to the same word line WL as the currently read memory cell 442, can be connected to the read circuit while that one memory cell is being read. This can be achieved by a suitable driver, which can force m = 1 if one of the memory cells 442 connectable by the m-of-n decoder 662 is currently being read (thus, the m-of-n decoder 662 can serve as a 1-of-n decoder 444 in this case), and can allow other values ​​of m in addition to m = 1, e.g., m = 2 to n, if none of the memory cells 442 connectable by the m-of-n decoder 662 is currently being read.

[0073] In various embodiments, by connecting the additional capacitor 552, 660 during an integration time t INTconnected to the reading circuit, a capacitance which can be charged by a reading current (which is a combination of the cell current I CELL and the distortion current I dist can be) to determine the capacity C comp As a result, according to equation (1), a signal Vcomp, also called the compensated signal Vcomp, can be obtained compared to the disturbed signal V dist In various embodiments, the additional capacity C comp be designed such that the compensated signal Vcomp is identical or substantially identical to the undisturbed signal V. In various embodiments, the additional capacitance C comp be designed such that the compensated signal Vcomp is closer to the undisturbed signal V than the disturbed signal V dist .

[0074] In the example above, which is used in conjunction with Fig. 1B was calculated for an assumed (undistorted) read current, which can thus correspond to the cell current, of 2 µA and for an assumed bit line capacitance C INT = 125 fF and an integration time t INT = 5 ns determines that a signal voltage V INT of 80 mV, and it was determined that an increased (distorted) read current of 3.5 µA results in a signal voltage V INT of 140 mV.

[0075] In various embodiments, in order to compensate for the distortion, in other words, to achieve a signal voltage V INT corresponding to the undisturbed signal (80 mV in the case of our example), the capacitance C INTto 220 fF. This can be achieved, for example, by adding an additional capacitor having an additional capacitance of approximately or exactly 95 fF. In various embodiments, the additional capacitor may only be added to the circuit if the distortion is actually present (or at least expected to be present), for example, in a case of a word line change; in other words, if the memory cell to be read is addressed by a word line that is not currently being read.

[0076] As in Fig. 5A and Fig. 5B, in various embodiments, a switch 550 may be used to switch the additional capacitor 552, which has an additional capacitance C comp can contribute to the read circuit, e.g., to the bit line BL, e.g., to the global section of the bit line GBL. In Fig. 5B illustrates such a situation in which the additional capacitor 552 is connected to the read circuit. Thus, the additional capacitor 552 can actively compensate for the distortion that occurs in the read current in the memory device 500 in the Fig. 5B shown configuration occurs.

[0077] In various embodiments, the memory device 500 may also be in a configuration as shown in Fig. 5A, in which the additional capacitor may not be connected to the reading circuit, so that the additional capacitance C comp may be added. In other words, in the Fig. In the configuration illustrated in Figure 5A, the additional capacitance 552 may be inactive. In various embodiments, the memory device 500 may be switched to this configuration (e.g., using switch 550) or left in it in a case where no distortion is occurring or expected for an upcoming read process.

[0078] In various embodiments, known situations may occur in which the read current may be reduced compared to the undistorted cell current. In such a case, adding a capacitor would further reduce the read signal. Therefore, instead of providing the entire “regular” capacitance, i.e., the capacitance used for evaluating an undistorted cell current, through an appropriately dimensioned bit line (as in Fig. 4 in conjunction with Fig. 1A), the “regular” capacitance may consist of a bit line having a lower capacitance than required and an additional switchable capacitor 552 providing additional capacitance, such as in Fig. 5A. In various embodiments, an undisturbed cell current (e.g., when reading a memory cell addressed by a word line has already been enabled, a device temperature is within a normal operating range, and the like) may be supplied to the sense amplifier using the bit line BL and the additional capacitor 552. In various embodiments, in the event of signal distortion that reduces the cell current, the additional capacitor 552 may be switched out of the sense circuit, i.e., deactivated.

[0079] In various embodiments, in the case of known distortions that can either reduce or increase the cell current, a combination of the embodiments described above can be applied. The capacitor for evaluating the undistorted signal can include the bit line and the switchable capacitor 552 (which can also include more than one capacitor for switching the capacitance in multiple stages), wherein the one or more switchable capacitors 552 can be disconnected from the read circuit if a distorted signal with a read current below the undistorted cell current is expected, and one or more further capacitors for increasing the capacitance by adding one or more of the further capacitors to the read circuit if the read current is increased by the distortion.

[0080] In various embodiments, as in Fig. 6 and described above, instead of providing a dedicated capacitor 552, one or more unused (e.g., not currently read) bit lines BL may be used as the additional capacitor 660.

[0081] In the example given above in connection with Fig. 2E, it was determined that the integrated voltage is 800 mV, which would not allow a useful evaluation of the memory cell state if the bit line voltage V BLhas a value of, for example, 500 mV. In order to shift the signal voltage to a useful voltage range, for example, to a voltage that can be reliably evaluated by the source amplifier SA, for example, by discharging the bit line BL, which may be precharged with 500 mV, by a voltage signal of 300 mV, which may result in a voltage of 200 mV, which may be within a reliable range of the source amplifier SA, it may be necessary to increase the capacitance charged by the memory cell from 125 fF to approximately 330 fF.

[0082] In various embodiments, this can be achieved as described above in connection with Fig. 5A and Fig. 5B by adding a dedicated capacitor 552 having a capacitance C compof approximately or exactly 205 fF. For example, the dedicated capacitor 552 may allow the required additional capacitance to be achieved exactly, or at least almost exactly.

[0083] However, such a dedicated capacitor 552 may require additional area, e.g., semiconductor area, which may be larger or smaller depending on the technology used. Furthermore, a suitable switching element 550, which may occupy additional space, may be required to control the addition of the capacitor. Depending on the application, such an increase in chip area may be undesirable.

[0084] In various embodiments, as in Fig. 6, instead of or in addition to using the dedicated capacitor, unused bit lines BL may be used to increase a total capacitance charged by the sense current, e.g., a total capacitance of the bit line BL.

[0085] As above in connection with Fig. 2E, in an exemplary case, a capacitance of the bit line may need to be increased to approximately 330 fF. This may be achieved by additionally connecting unused local bit lines LBL (with a capacitance C LBL ) can be connected to the reading circuit, for example as in Fig. 6 shown.

[0086] A capacitance of the combined bit line BL can therefore be increased by 2 x 100 fF to approximately 325 fF, which can be very close to the desired capacitance of 330 fF, so that the integration process can be carried out in an ideal range, in other words, so that the resulting signal voltage can be within the reliable voltage range of the sense amplifier SA. Since the local bit lines and the switches can be present anyway to switch the bit lines BL, in various embodiments, essentially no additional chip area may be required. In various embodiments, only a control of the switches can be modified in such a way that an m-of-n decoding may be possible in addition to the conventional 1-of-n decoding. Such a modification may require only minor modifications to a circuit, e.g.a driver circuit for the switch, which should hardly require any additional chip area.

[0087] In various embodiments, a direction of the distortion and a compensation measure may be taken into account to achieve the (at least partial) compensation. For example, if the distortion adds current to the read signal (e.g., through capacitive coupling, as described above) and the additional capacitance is designed to be connected to the read circuit, the additional capacitance may be connected to the read circuit if the distortion is present or expected, and the read circuit may be used in the configuration without the additional capacitor if the distortion is not present. For example, if the distortion subtracts current from the read signal (e.g.,due to leakage) and the additional capacitor is designed to be connected to the read circuit, the additional capacitor can be connected to the read circuit if the distortion is not present, and the read circuit can be used in the configuration without the additional capacitor if the distortion is present or expected.

[0088] For example, if the distortion adds current to the read signal (e.g., through capacitive coupling, as described above) and the additional capacitance is designed to be connected to the reference circuit, the additional capacitor can be connected to the read circuit if the distortion is not present, and the reference circuit can be designed to be used in the configuration without the additional capacitor if the distortion is present or expected. For example, if the distortion subtracts current from the read signal (e.g., through leakage) and the additional capacitor is designed to be connected to the reference circuit, the additional capacitor can be connected to the reference circuit if the distortion is present or expected, and the reference circuit can be used in the configuration without the additional capacitor if the distortion is not present.

[0089] Fig. 7 shows a schematic diagram of a memory device 700 according to various embodiments.

[0090] Some elements, structures, materials, work processes, etc. may be similar or identical to those used in connection with Fig. 4 and with the Fig. 5A, Fig. 5B and Fig. 6. Therefore, a repetition of their description can be omitted here.

[0091] In various embodiments, similar to those used in connection with Fig. 5A, Fig. 5B and Fig. 6, a circuit arrangement of the memory device 700 can be switched between a first arrangement having an additional circuit section 770 and a second arrangement without the additional circuit section 770.

[0092] In various embodiments, the additional circuit portion 770 may be configured to conduct a current. The current may be referred to as a compensation current. In various embodiments, the additional circuit portion may be configured to supply an additional current either to a read circuit portion of the circuit (as a result, a read current may be increased by the additional current) or to a reference circuit portion of the circuit (as a result, a reference current may be increased by the additional current).

[0093] In various embodiments, the additional circuit portion may be configured to divert a current portion either away from the read circuit portion of the circuit, as in Fig. 7 (as a result, the read current can be reduced by the current component), or from the reference circuit section of the circuit (as a result, the reference current can be reduced by the current component).

[0094] In various embodiments, the method of operating a memory device may include determining a state of the memory device 700, for example, whether or not the additional circuit portion is currently connected to a circuit of the memory device 700.

[0095] In various embodiments, the method of operating a memory device may include determining whether reading a memory cell of the plurality of memory cells with the memory device 700 in the determined state will result in an offset read voltage that is offset from a target voltage. In various embodiments, situations may be known that will result in an offset read voltage, e.g., with a known direction (e.g., if a current is added to or subtracted from the read current), and optionally with a known magnitude. For example, if reading the memory cell requires a wordline change, a distortion current may be added to the read current (e.g., for a certain duration, e.g., with a decreasing magnitude over the duration). As another example, a distortion current may be added to the read current in case of a high operating temperature of the device.

[0096] In various embodiments, if reading the memory cell of the plurality of memory cells with the memory device 700 in the determined state will result in an offset read voltage that is offset from a target voltage, the memory device 700 may be switched to another state, wherein the memory device in the another state may be configured to provide a compensation voltage to compensate for the offset, for example, by increasing or decreasing the read current or the reference current. The another state may be another one of the possible states in which the memory device 700 may be. As an example of the switching, the at least one additional circuit portion 770 may be connected to the circuitry of the memory device 700, for example, to the read circuitry or to the reference circuitry.

[0097] In various embodiments, the memory cell may be read in the other state after switching using the memory device 700.

[0098] In various embodiments, to achieve compensation, an amount of the compensation current may be the same as or nearly the same as the distortion current, or within a certain percentage range of the distortion current. For example, the amount of the compensation current may be in a range from about 20% of the distortion current to about 180% of the distortion current, e.g., from about 50% to about 150%, e.g., from about 80% to about 120%, e.g., from about 90% to about 110%, or may be, e.g., approximately or exactly 100%. In various embodiments, it may be important that a direction of the compensation current (e.g., whether the compensation current is added or branched off) is adjusted to achieve compensation.For example, if the distortion current adds current to the read current and the additional circuit portion is designed to be connected to the read circuit, the compensation current may be designed to be subtracted, e.g.to be branched off; if the distortion current reduces the read current and the additional circuit section is designed to be connected to the read circuit, the compensation current can be designed to be added to the read current; if the distortion current adds current to the read current and the additional circuit section is designed to be connected to the reference circuit, the compensation current can be designed to be added to the reference current; and if the distortion current subtracts current from the read current and the additional circuit section is designed to be connected to the reference circuit, the compensation current can be designed to be subtracted from the reference current, e.g., branched off.

[0099] In various embodiments, a current supplied to or branched from the additional circuit portion 770 may be configured to vary over time, in other words, to be time-dependent.

[0100] In various embodiments, the circuit may be switched to include the additional circuit portion 770 by means of a switch, e.g., to switch the additional circuit portion 770 to a conducting state.

[0101] In various embodiments, the additional circuit portion 770, e.g., the switch, may include a wordline activation event detection circuit (also referred to as row activation events) 772. The wordline activation event detection circuit 772 may, in various embodiments, be or include a digital circuit, for example, as known in the art. The wordline activation event detection circuit 772 may be configured to store a previous wordline address, compare an address bus (a portion of a wordline address) to the stored previous wordline address (e.g., using bitwise XOR), and generate an activation event signal if at least one bit in the current wordline address is different from the previous wordline address (e.g., using bitwise OR).

[0102] In various embodiments, the additional circuit portion 770, e.g., the switch, may include a cancellation circuit 774.

[0103] In various embodiments, for example, if the activation event signal is generated, the signal may be forwarded to the cancellation circuit 774. The cancellation circuit 774 may, in various embodiments, be or include a digital circuit, for example, as known in the art. The cancellation circuit 774 may be configured to start a counter with the activation event, e.g., using an internal calibrated oscillator. The cancellation circuit 774 may be configured to generate a deactivation signal after a predefined number of pulses. The cancellation circuit 774 may optionally be configured to generate a timing signal (counter) for controlling a compensation circuit 776.

[0104] In various embodiments, the additional circuit portion 770 may include the compensation circuit 776. In various embodiments, the compensation circuit 776 may be or include an analog circuit, for example, as known in the art, e.g., a current mirror.

[0105] In various embodiments, the compensation circuit 776 may be configured to change a characteristic of a sense amplifier, for example, by activating a compensation reference current, also referred to as an offset reference current (here it is assumed that a sense amplifier SA with a reference current can be used).

[0106] In various embodiments, a value of the compensation offset may be a fixed value.

[0107] In various embodiments, the value of the compensation current may be a dynamic (i.e., time-dependent) value. For example, the value may depend on the optional time signal (counter).

[0108] In various embodiments, the compensation current can be deactivated by the cancellation signal. In other words, if the cancellation signal is sent, no compensation current can be supplied or diverted. This can be used, for example, in the case of a distortion current that is time-dependent. For example, the distortion current that can be induced in the read current after a wordline change can decrease over time and may be insignificant after a certain time. A period during which the distortion can be so significant that it can be compensated can be referred to as a distortion period.

[0109] In various embodiments, the additional circuit portion 550, 660, or 770 may be included in a microcontroller with non-volatile memory, e.g., a high-performance microcontroller with embedded non-volatile memory (e.g., eFlash or other non-volatile memory devices such as RRAM or MRAM).

[0110] Fig. 8 shows a process flow 800 for a method of operating a memory device according to various embodiments.

[0111] In various embodiments, the memory device may include multiple memory cells.

[0112] In various embodiments, the method may include: determining a state of the memory device (in 810); determining whether reading a memory cell of the plurality of memory cells with the memory device in the determined state will result in an offset read voltage or current that is offset from a target voltage or current, respectively (in 820); if so, switching to another state of the memory device, wherein the memory device in the another state is configured to provide a compensation voltage or current to compensate for the offset (in 830); and, after switching, reading the memory cell using the memory device in the another state (in 840).

[0113] In various embodiments, a method of operating a memory device is provided. The memory device may include a plurality of memory cells, and the method may include: determining a state of the memory device; determining whether reading a memory cell of the plurality of memory cells with the memory device in the determined state will result in an offset read voltage or current that is offset from a target voltage or current, respectively; if so, switching to a different state of the memory device, wherein the memory device in the different state is configured to provide a compensation voltage or current to compensate for the offset; and, after switching, reading the memory cell using the memory device in the different state.

[0114] In various embodiments, the memory device may further comprise a circuit for evaluating a state of the memory cell, an additional circuit portion, and a switch for switching between a connected state of the additional circuit portion in which it is connected to the circuit and a disconnected state of the additional circuit portion in which it is disconnected from the circuit.

[0115] In various embodiments, determining a state of the storage device may include determining whether the storage device is in the connected state or the disconnected state, and the other state may be the other of the connected state and the disconnected state.

[0116] In various embodiments, determining whether reading the memory cell with the memory device in the determined state will result in an offset read voltage or current that is offset from a target voltage or current, respectively, may include providing an address of the memory cell, and determining whether a word line connected to the memory cell will be re-enabled for reading the memory cell.

[0117] In various embodiments, the method may further include determining a delay time between activation of the word line and reading, comparing the delay time to a delay time limit, and, if the delay time is shorter than or equal to the delay time limit, switching to the further state.

[0118] In various embodiments, determining whether reading the memory cell with the memory device in the determined state will result in an offset read voltage or current that is offset from a target voltage or current, respectively, may include determining whether a temperature of the memory device exceeds a temperature threshold.

[0119] In various embodiments, the memory device may comprise at least one further additional circuit section, thereby forming a plurality of additional circuit sections, wherein in the connected state one or more of the additional circuit sections may be connected to the circuit.

[0120] In various embodiments, the memory device may include a plurality of bit lines hierarchically configured as global and local bit lines, reading the memory cell may be configured to use only one bit line of the plurality of bit lines, and the additional circuit portion may include at least one unused local bit line.

[0121] In various embodiments, a memory device is provided. The memory device may comprise at least one memory cell, and a circuit including: a read circuit configured to provide a voltage or a current corresponding to a state of the at least one memory cell, a reference circuit configured to provide a reference voltage or a reference current, an additional circuit portion, and a switch configured to switch between a connected state of the additional circuit portion, in which it is connected to the circuit, and a disconnected state of the additional circuit portion, in which it is disconnected from the circuit, wherein the voltage or current provided in the connected state may be different from the voltage or current provided in the connected state.provided in the disconnected state and / or the reference voltage or current provided in the connected state may be different from the reference voltage or current provided in the disconnected state.

[0122] In various embodiments, the memory device may further comprise a sense amplifier, wherein the additional circuit portion may be configured to be connected to the circuit when the at least one memory cell is connected to the sense amplifier.

[0123] In various embodiments, if the voltage or current provided in the connected state is different from the voltage or current provided in the disconnected state, the at least one additional circuit portion may be connectable to the read circuit.

[0124] In various embodiments, if the voltage or current provided in the connected state is different from the voltage or current provided in the disconnected state, the at least one additional circuit portion may be connectable to the reference circuit.

[0125] In various embodiments, the additional circuit portion may include a capacitor.

[0126] In various embodiments, the additional circuit portion is configured to provide additional current.

[0127] In various embodiments, the additional current may be time-dependent.

[0128] In various embodiments, the memory device may further include a controller circuit configured to control the switch.

[0129] In various embodiments, the controller circuit may be configured to provide a period of switchability in which the memory device is switchable between the disconnected state and the connected state, and a period of non-switchability in which the memory device is not switchable between the first state and the further circuit state.

[0130] In various embodiments, the memory device may further include a temperature sensor.

[0131] In various embodiments, the memory device may further comprise a word line change detector, ie, an address change detector.

[0132] In various embodiments, the memory device may further comprise a plurality of bit lines hierarchically configured as global and local bit lines, the read circuit may include a used bit line of the plurality of bit lines, and the additional circuit portion may include at least one unused local bit line.

Claims

[1] A method of operating a memory device, the memory device comprising a plurality of memory cells, the method comprising: Determining a state of the memory device (810); Determining whether reading a memory cell of the plurality of memory cells with the memory device in the determined state will result in an offset read voltage or an offset read current that is offset from a target voltage or current, respectively (820); if so, switching to another state of the memory device, wherein the memory device in the other state is configured to provide a compensation voltage or a compensation current for compensating the offset (830); and, after switching, reading the memory cell using the memory device in the other state (840). [2] Method according to claim 1, wherein the memory device further comprises a circuit for evaluating a state of the memory cell, an additional circuit section, and a switch for switching between a connected state of the additional circuit section in which it is connected to the circuit and a disconnected state of the additional circuit section in which it is disconnected from the circuit; wherein estimating a state of the storage device comprises determining whether the storage device is in the connected state or in the disconnected state and where the other state is the other state of the connected state and the disconnected state. [3] The method of claim 1 or 2, wherein determining whether reading the memory cell with the memory device in the determined state will result in an offset read voltage or an offset read current that is offset from a target voltage or current, respectively, comprises providing an address of the memory cell and determining whether a word line connected to the memory cell will be re-enabled for reading the memory cell. [4] The method of claim 3, further comprising: Determining a delay time between activation of the word line and reading; Comparing the delay time with a delay time limit; and, If the delay time is shorter than or equal to the delay time limit, switch to the next state. [5] The method of any one of claims 1 to 4, wherein determining whether reading the memory cell with the memory device in the determined state will result in an offset read voltage or an offset read current that is offset from a target voltage or current, respectively, comprises determining whether a temperature of the memory device exceeds a temperature threshold. [6] The method of any one of claims 2 to 5, wherein the memory device comprises at least one further additional circuit portion, thereby forming a plurality of additional circuit portions, wherein in the connected state one or more of the plurality of additional circuit portions are connected to the circuit. [7] Method according to one of claims 2 to 6, wherein the memory device comprises a plurality of bit lines hierarchically configured as global and local bit lines; wherein reading the memory cell is configured to use only one bit line of the plurality of bit lines; and wherein the additional circuit portion comprises at least one unused local bit line. [8] A storage device (400, 500, 600, 700) arranged to operate according to the method of claim 1, comprising: at least one memory cell (442); and a circuit comprising: a read circuit configured to provide a voltage or current corresponding to a state of the at least one memory cell (442); a reference circuit designed to provide a reference voltage or provide a reference current; an additional circuit section (770); and a switch (440) configured to switch between a connected state of the additional circuit portion (770) in which it is connected to the circuit and a disconnected state of the additional circuit portion (770) in which it is disconnected from the circuit; wherein the voltage or current provided in the connected state is different from the voltage or current provided in the disconnected state, and / or the reference voltage or current provided in the connected state is different from the reference voltage or current provided in the disconnected state. [9] The storage device (400, 500, 600, 700) of claim 8, further comprising: a detection amplifier (SA); wherein the additional circuit portion (770) is adapted to be connected to the circuit when the at least one memory cell (442) is connected to the sense amplifier (SA). [10] The memory device (400, 500, 600, 700) of claim 8 or 9, wherein, if the voltage or current provided in the connected state is different from the voltage or current provided in the disconnected state, the at least one additional circuit portion (770) is connectable to the read circuit. [11] The memory device (400, 500, 600, 700) of claim 8 or 9, wherein, if the voltage or current provided in the connected state is different from the voltage or current provided in the disconnected state, the at least one additional circuit portion (770) is connectable to the reference circuit. [12] The memory device (400, 500, 600, 700) of any one of claims 8 to 11, wherein the additional circuit portion (770) comprises a capacitor. [13] The memory device (400, 500, 600, 700) of any one of claims 8 to 11, wherein the additional circuit portion (770) is configured to provide an additional current. [14] The memory device (400, 500, 600, 700) of claim 13, wherein the additional current is time dependent. [15] The memory device (400, 500, 600, 700) of any one of claims 8 to 14, further comprising a controller circuit configured to control the switch (440). [16] The memory device (400, 500, 600, 700) of any one of claims 8 to 15, wherein the controller circuit is configured to provide a period of switchability in which the memory device is switchable between the disconnected state and the connected state, and a period of non-switchability in which the memory device is not switchable between the first state and the further circuit state. [17] The memory device (400, 500, 600, 700) of any one of claims 8 to 16, further comprising a temperature sensor. [18] The memory device (400, 500, 600, 700) of any one of claims 8 to 17, further comprising a word line change detector. [19] Storage device (400, 500, 600, 700) according to one of claims 8 to 10, 12 or 15 to 18, further comprising: several bit lines (BL) that are hierarchically configured as global and local bit lines; wherein the reading circuit comprises a used bit line of the plurality of bit lines (BL); and wherein the additional circuit section (770) comprises at least one unused local bit line (LBL).

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