Method for forming a fin structure

Abstract

Method comprising: in a first etching step, etching a semiconductor substrate (20) to form first recesses in first device regions (68A) and second recesses in a second device region (68B) simultaneously, wherein first upper semiconductor fins (136A) are formed between the first recesses, and a second semiconductor fin (136B) is formed between the second recesses, in a second etching step, etching the semiconductor substrate (20) to extend the second recesses in the second device region such that they are lower than the first recesses in the first device regions, wherein first semiconductor fins (148A) comprising the first upper semiconductor fins (136A) are formed in the first device regions, Filling the first recesses and the second recesses with a dielectric material (54) to form first insulation regions (58) in the first recesses and second insulation regions (58) in the second recesses, and Recessing the first isolation regions and the second isolation regions, wherein portions of the semiconductor substrate in at least one of the first device regions protrude higher than upper surfaces of the first isolation regions (58) to form a first semiconductor fin (60A), and portions of the semiconductor substrate in the second device region protrude higher than upper surfaces of the second isolation regions (58) to form a second semiconductor fin (60B); further comprising the steps: Formation of several mask rings (28-1, 28-2), Performing a first cut on the plurality of mask rings to remove portions of the plurality of mask rings, wherein remaining portions of the plurality of mask rings (28-1) are used as an etching mask for the first etching step, and after the second etching step, performing a second cut to remove one of the first semiconductor fins (148A-1).

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting material layers over a semiconductor substrate, and then patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] A transistor is an element used openly in semiconductor devices. For example, a single integrated circuit (IC) may contain a large number of transistors (e.g., hundreds, thousands, or millions of transistors). A common type of transistor used in semiconductor device manufacturing is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). A planar transistor (e.g., a planar MOSFET) typically includes a gate dielectric disposed over a channel region in a substrate and a gate electrode formed over the gate dielectric. A source region and a drain region of the transistor are formed on either side of the channel region.

[0003] Multi-gate field-effect transistors (MuGFETs) are a new development in semiconductor technology. One type of MuGFET is called a fin field-effect transistor (FinFET), which is a transistor comprising a fin-shaped semiconductor material raised vertically from the semiconductor surface of an integrated circuit.

[0004] US 2014 / 0001562 A1 relates to an integrated circuit comprising a substrate, a first FinFET device supported by the substrate, wherein the first FinFET device has a first fin with a non-stepped fin profile.

[0005] US 2016 / 0155670 A1 relates to a method for manufacturing a semiconductor device comprising forming a first spacer having a first spacer width over a substrate, wherein the first spacer masks a first portion of the substrate during a first etching process.

[0006] US 2015 / 0243667 A1 relates to a layout of an integrated circuit comprising a first rectangular region, wherein the first rectangular region has its longer sides in a first direction and its shorter sides in a second direction that is orthogonal to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 to 13 show top and cross-sectional views of various intermediate stages of fabricating a fin field effect transistor (FinFET) according to some embodiments. Fig. 14 to 16 show the cross-sectional views of FinFETs and the respective fin structures according to some embodiments. Fig. 17 shows a process flow for forming a FinFET according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is done for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0009] In addition, terms relating to spatial relativity, such as "underlying," "beneath," "lower," "overlying," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0010] Fin field-effect transistors (FinFETs) and the method of forming them are provided according to various embodiments. The intermediate stages of forming the FinFETs are illustrated according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and embodiments.

[0011] Fig. 1A to 13 show the top and cross-sectional views of intermediate stages in the formation of FinFETs according to some embodiments of the present disclosure. Fig. The steps shown in Figures 1A to 13 are also shown schematically in the Fig. 17. When two figures have the same reference numeral, one followed by the letter "A" and the other by the letter "B", the figure with the reference numeral followed by the letter "A" shows a plan view, and the figure with the reference numeral followed by the letter "B" shows a cross-sectional view of the same structure.

[0012] Fig. 1B shows a cross-sectional view of a wafer 10 including a substrate 20. The substrate 20 may be a bulk substrate or an SOI (semiconductor on an insulator) substrate. According to some embodiments of the present disclosure, the substrate 20 is formed from a semiconductor material selected from, but not limited to, silicon germanium, silicon carbon, germanium, and III-V compound semiconductor materials such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. The substrate 20 may be lightly doped with a p-type or an n-type impurity.

[0013] A pad oxide 22 and a hard mask 24 are formed over the semiconductor substrate 20. According to some embodiments of the present disclosure, the pad oxide 22 is formed from silicon oxide, which may be formed by oxidizing a surface layer of the semiconductor substrate 20. The hard mask 24 may be formed from silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like. According to some embodiments of the present disclosure, the hard mask 24 is formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to alternative embodiments of the present disclosure, the hard mask 24 is formed by thermal nitriding of silicon, plasma-enhanced chemical vapor deposition (PECVD), or anodic plasma nitriding.

[0014] An oxide layer 26, which may be formed from silicon oxide, is formed over the hard mask 24. According to some embodiments of the present disclosure, the oxide layer 26 is formed from silicon oxide. A plurality of mask rings 28-1, 28-2, 28-3, 28-4, 28-5, and 28-6 (collectively referred to as mask rings 28) are formed over the oxide layer 26. The corresponding step is described as step 202 in the Fig. The process flow shown in Figure 17 is shown. The mask rings 28 can be formed from silicon nitride, silicon oxynitride, silicon carbide, or the like.

[0015] Fig. 1A shows a top view of the Fig. 1B shown mask rings 28. The Fig. The structure shown in Figure 1B is obtained from the plane containing the line 1B-1B in Fig. 1A contains. As in Fig. 1A, outer mask rings 28-2, 28-4, and 28-6 surround the inner mask rings 28-1, 28-3, and 28-5, respectively. According to some embodiments of the present disclosure, forming the mask rings 28 includes forming three mandrel rings (not shown), each located in one of regions 32, forming a blanket spacer layer on the mandrel rings, and then performing an anisotropic etch to remove the horizontal portions of the blanket spacer layer. The remaining portions of the blanket spacer layer therefore form the mask rings 28. The inner mask rings 28-1, 28-3, and 28-5 are formed on the inner sides of the respective mandrel rings, and the outer mask rings 28-2, 28-4, and 28-6 are formed on the outer sides of the respective mandrel rings. The mandrel rings are then removed, leaving the mask rings 28 as shown in Fig. 1A and Fig. 1B.

[0016] Fig. 1A and Fig. 1B also show the formation and patterning of a photoresist 30 that covers some portions of the mask rings 28 and leaves other parts of the mask rings 28 exposed. Although the photoresist 30 is Fig. 1B is shown to be a single-layer photoresist, the photoresist 30 may also be replaced by a three-layer comprising a lower layer formed of a photoresist, a middle layer formed of an inorganic material, and an upper layer formed of another photoresist.

[0017] Next, the exposed portions of the mask rings 28 are etched in a first etching process, alternatively referred to as a fine cut, to define the positions and sizes of semiconductor fins that will be formed in subsequent steps. The corresponding step is designated as step 204 in the Fig. 17. After the fine cut, the photoresist 30 is removed. The resulting structure is shown in Fig. 2A and Fig. 2B, which show a top view and a cross-sectional view, respectively (In the illustrated embodiment, the right part of the structure 28-3, which was not covered by the mask 30, should be included in the Fig. 2A and Fig. 3A may also have been removed. The same applies to structure 148B-1 in Fig. 8A.). The Fig. The structure shown in Figure 2B is obtained from the plane containing the line 2B-2B in Fig. 2A. The remaining portions of the mask rings 28 are hereinafter referred to as the hard mask 28.

[0018] Next, as in Fig. 3A and Fig. 3B, the hard masks 28 are used to etch the underlying oxide layer 26, the hard mask 24, the pad oxide 22 and the substrate 20. The Fig. The structure shown in Figure 3B is obtained from the plane containing the line 3B-3B in Fig. 3A. The etching can be carried out in two stages. For example, in the first stage, the hard masks 28 ( Fig. 2A and Fig. 2B) is used as an etching mask to etch the underlying oxide layer 26 and the hard mask 24, and the etching is stopped at the upper surface of the pad oxide layer 22. In the second stage, the patterned hard mask 24 is used as an etching mask to etch the pad oxide layer 22 and the semiconductor substrate 20. The corresponding step is shown as step 206 in the Fig. 17 is shown. In the resulting structure, as shown in Fig. 3B, trenches 34 are formed such that they extend into the semiconductor substrate 20. Accordingly, semiconductor fins 136A and 136B are formed. According to some embodiments of the present disclosure, some semiconductor fins 136A are arranged closely together to form a semiconductor fin group, while semiconductor fins 136B are spaced further apart than the fins 136A in the same fin group. According to some embodiments of the present disclosure, the etching of the substrate 20 is performed using a dry (anisotropic) etching process, wherein process gases such as HBr / Cl2 / O2, HBr / Cl2 / O2 / CF2, C2F6, CF4, or the like may be used. Although Fig. 3B illustrates the sidewalls of semiconductor fins 136A and 136B as being vertical, it will be appreciated that these sidewalls may be beveled, as described with reference to Fig. 14, Fig. 15 and Fig. 16 will be discussed in detail. According to some embodiments, a depth H1 ( Fig. 3B) of the trenches 34 in a range between approximately 2 nm and approximately 800 nm.

[0019] With reference to Fig. 4, a patterned lithographic mask is formed. According to some embodiments of the present disclosure, the patterned lithographic mask comprises a three-layer structure 44 including a bottom layer (also known as a bottom layer) 38, a middle layer 40 over the bottom layer 38, and a top layer 42 over the middle layer 40. According to some embodiments of the present disclosure, the bottom layer 38 and top layer 42 are formed from photoresists. The middle layer 40 may be formed from an inorganic material, which may be a carbide (such as silicon oxycarbide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The top layer 42 is patterned to cover the lands 136A and 136B.According to some embodiments, each structure of the structured upper layer 42 overlaps one of land groups 136A or one of discrete lands 136B. In addition, to leave a process tolerance, the structured upper layer 42 extends beyond the edges of the respective underlying land groups 136A and discrete lands 136B.

[0020] Next, an anisotropic etching is performed. The middle layer 40 is etched using the patterned upper layer 42 as an etch mask, so that the patterns of the upper layer 42 are transferred to the middle layer 40. During the patterning of the middle layer 40, the upper layer 42 is at least partially or completely consumed. After the middle layer 40 has been etched through, the lower layer 38 is anisotropically patterned using the middle layer 40 as an etch mask. The upper layer 42 is also completely consumed during the patterning of the lower layer 38, if it was not completely consumed during the patterning of the middle layer 40. The resulting structure is shown in Fig. 5 shown.

[0021] Fig. 6 shows the second etching process of the semiconductor substrate 20 using the patterned lower layer 38 as an etching mask. The corresponding step is designated as step 208 in the Fig. 17. Accordingly, semiconductor fins 148A (comprising 148A-1 and 148A-2) and 148B (comprising 148B-1 and 148B-2) are formed. Throughout the description, semiconductor fins 148A and 148B are collectively referred to as semiconductor fins 148. Trenches 34 extend further into semiconductor substrate 20 and separate semiconductor fins 148A and 148B from each other. In the top view of wafer 10, trenches 34 may have elongated portions having mutually parallel longitudinal directions. Furthermore, in the top view of wafer 10, each or some of semiconductor fins 148A and 148B may be surrounded by respective trenches 34. According to some embodiments of the present disclosure, a depth H2 of the portions of the trenches 34 formed in the second etch is in the range between about 3 nm and about 1000 nm.

[0022] According to some embodiments of the present disclosure, semiconductor fins 148A-1 and 148A-2 are referred to as crown-shaped semiconductor fins. Each of semiconductor fins 148A-1 and 148A-2 includes a base 146A and semiconductor fins 136A above the respective bases 146A. Semiconductor fins 148B-1 and 148B-2 include a lower portion 146B and the respective upper semiconductor fin 136B, with dashed lines drawn to show where the lower portions 146B are connected to the respective upper semiconductor fin 136B. Although Fig. 6 shows that three semiconductor fins 136A are located above a base 146A, the number of semiconductor fins 136A on each of the respective bases 146A may be any integer, such as 2, 4, 5, or more, depending on the planned drive currents of the resulting FinFETs.

[0023] According to some embodiments, as in Fig. 6, during the etching of the substrate 20, the lower layer 38 is recessed laterally toward the center of the respective land group 136A, and therefore the outer edge of the outermost land 136A in a land group can be vertically aligned with the outer edge of the respective underlying base 146A. For example, the lower layer 38 can be recessed from the positions of the lines 49A in the directions of arrows 51A toward the edges of the respective bases 146A, as shown in Fig. 6. Because the fins 136A are close to each other, for example, with pitches D1 less than approximately 20 nm, the portions of the lower layer 38 between the fins 136A in the same fin group are slowly consumed and are left to protect (along with the hard mask 24) the underlying semiconductor substrate 20 from etching. Accordingly, the bases 146A are formed. According to alternative embodiments, the bases 146A extend laterally beyond the outermost edges of the outermost fins 136A if the lateral recessing of the lower layer 38 is not fast enough. The hard mask 24 over the fins 136B also protects the underlying fins 136B and the substrate 20, so that the fin portions 146B are formed.Likewise, during the etching of the substrate 20, the lower layer 38 is recessed laterally from the position of line 49B in the direction of arrow 5B (toward the center of the respective land 136B), and therefore the outer edges of the land portion 136B can be vertically aligned with the outer edges of the respective underlying land portions 146B. The gradual laterally recessing of the lower layer 38 (and the fact that the second etch goes deeper into the substrate 20 than the first etch) during the etch also causes the edges of the base 146A to become more chamfered than the overlying lands 136A, and the edges of the land portions 146B to be more chamfered than the respective overlying portions 136B. The details will be described with reference to FIG. Fig. 14 to 16 shown and discussed.

[0024] According to some embodiments, the depth (height) H1 of the webs 136A and 136B is smaller than the depth (height) H2 of the web base 146A and the web portion 146B. The ratio H1 / H2 may, according to some embodiments, be in the range between approximately 0.5 and approximately 0.8. Next, the remaining lower layer 38 is removed, and the resulting structure is shown in Fig. 7 shown.

[0025] Fig. 8A, Fig. 8B, Fig. 9A and Fig. 9B show a rough cutting process for removing unwanted portions of the semiconductor fins 148A and 148B. The corresponding step is shown as step 210 in the Fig. 17 is shown. For example, as shown in Fig. 8A and Fig. 8B, a photoresist 50 is formed. The photoresist 50 can also be replaced by a three-layer structure. According to some embodiments, as shown in Fig. 8A, the photoresist 50 covers the central portions of the semiconductor fins 148B-1, 148B-2 and the crown-shaped fin 148A-2, while leaving the entirety of the crown-shaped semiconductor fin 148A-1 exposed. Fig. The structure shown in Figure 8B is obtained from the plane containing the line 8B-8B in Fig. 8A. The exposed portions of the semiconductor fins 148A and 148B are then etched, followed by the removal of the photoresist 50. The crown-shaped semiconductor fin 148A-1 can be completely removed and is therefore referred to below as the (crown-shaped) dummy fin 148A-1. The resulting structure is shown in Fig. 9A and Fig. 9B, where the Fig. 9B was obtained from the plane that forms the line 9B-9B in Fig. 9A contains.

[0026] As in Fig. 9B, the etching of the dummy land 148A-1 ( Fig. 8B) after it has been completely removed, so that recesses 53 ( Fig. 9B) extending from the lower level of the ridges 148B-1, 148B-2, and 148A-2 further downward into the semiconductor substrate 20. According to some embodiments of the present disclosure, the recesses 53 have a W-shape. If the number of ridges 136A ( Fig. 8B) is one of three different, the recesses 53 may have other shapes. The recesses 53 may help improve / change the stress in the resulting wafer 10 and are beneficial for improving device performance. When forming the recesses 53, it is understood that discrete lead fins, such as 148B-1 and 148B-2, may also be removed, and recesses may also be formed that extend lower than the bottom surfaces of the removed fins 148B.

[0027] Although semiconductor fins 148A and 148B are illustrated as being arranged closely to one another, it should be noted that, according to some embodiments, they may also be arranged in different regions of a die in any combination. For example, semiconductor fins 148A may be located in a first device region, and semiconductor fins 148B may be located in a second device region separate from the first device region.

[0028] Next, with reference to Fig. 10 a dielectric region / material 54 is formed to fill the trenches 34, as in Fig. 9B. According to some embodiments of the present disclosure, the dielectric region 54 comprises a liner oxide and a dielectric material (not separately shown) over the liner oxide. The liner oxide may be formed as a conformal layer whose horizontal portions and vertical portions have thicknesses that are close to each other. The thickness of the liner oxide may range between approximately 1 nm (10 Å) and approximately 5 nm (50 Å). According to some embodiments of the present disclosure, the liner oxide is formed by oxidizing the wafer 10 in an oxygen-containing environment, for example, using LOCOS (Local Oxidation of Silicon), where oxygen (O2) may be included in the respective process gas.According to other embodiments of the present disclosure, the liner oxide is formed, for example, using in-situ steam generation (ISSG), wherein the water vapor or a composite gas of hydrogen (H2) and oxygen (O2) is used to oxidize the exposed semiconductor substrate 20 and the semiconductor fins 148A and 148B. The ISSG oxidation may be performed at an elevated temperature. According to still other embodiments, the liner oxide is formed using a deposition technique such as subatmospheric chemical vapor deposition (SACVD).

[0029] The dielectric material is then formed to fill the remaining portions of the trenches 34, which is shown in Fig. 10 results. The dielectric material can be formed from silicon oxide, silicon carbide, silicon nitride, or multilayers thereof. The method for forming the dielectric material can be selected from FCVD (flowable chemical vapor deposition), spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), LPCVD, and the like.

[0030] According to some embodiments using FCVD, a silicon and nitrogen-containing precursor (e.g., trisilylamine (TSA) or disilylamine (DSA)) is used, and therefore the resulting dielectric material is flowable (jelly-like). According to alternative embodiments of the present disclosure, the flowable dielectric material is formed using an alkylaminosilane-based precursor. During deposition, a plasma is turned on to activate the gaseous precursors to form the flowable oxide. After the dielectric material is formed, an annealing / curing step is performed that converts the flowable dielectric material to a solid dielectric material.

[0031] A planarization, such as chemical mechanical polishing (CMP) or mechanical grinding, is then performed until the hard mask 24 is exposed. The remaining portions of the isolation regions 54 are referred to as STI (shallow trench isolation) regions 58, as shown in Fig. 11. The corresponding step is shown as step 212 in the Fig. 17. The hard mask 24 can be used as the CMP stop layer, and therefore the upper surfaces of the hard mask 24 are substantially coplanar with the upper surface of the STI regions.

[0032] The Hard Mask 24 ( Fig. 10) is then removed. If formed from silicon nitride, the hard mask 24 can be removed in a wet process using hot H3PO4 as an etchant. Next, as shown in Fig. 11, the STI areas 58 are omitted, and the pad layer 22 ( Fig. 10) can also be removed in the same process. Accordingly, semiconductor fins 60A and 60B are formed. The corresponding step is described as step 214 in the Fig. 17. The recessing of the STI regions 58 may be performed using an isotropic etching process, which may be a dry etching process or a wet etching process. According to some embodiments of the present disclosure, the recessing of the STI regions 58 is performed using a dry etching process using process gases including NH3 and NF3. According to alternative embodiments of the present disclosure, the recessing of the STI regions 58 is performed using a wet etching process in which the etchant solution is a dilute HF solution.

[0033] Removing the STI regions 58 results in the semiconductor fins 60A and 60B protruding higher than the top surfaces of the STI regions 58. According to some embodiments of the present disclosure, the portions of the STI regions 58 directly above the base 146A have some remaining portions, and the top surfaces of the remaining STI regions 58 are higher than the top surface of the base 146A. According to alternative embodiments of the present disclosure, the portions of the STI regions 58 directly above the base 146A are removed, and the top surfaces of the remaining STI regions 58 are substantially coplanar with or slightly lower than the top surface of the base 146A.

[0034] Fig. 12 shows the formation of dummy gate stacks 62 according to some embodiments of the present disclosure. The corresponding step is shown as step 216 in the Fig. 17. The dummy gate stacks 62 may include a dummy gate dielectric 64 and a dummy gate electrode 66 over the dummy gate dielectric 64. The dummy gate dielectric 64 may be formed from silicon oxide. The dummy gate electrode 66 may be formed from polysilicon, according to some embodiments. Fig. 12B shows a cross-sectional view of the Fig. 12A, wherein the cross-sectional view may be obtained from the vertical plane which is one of the lines 12B-12B in Fig. 12A contains. As in Fig. 12A and Fig. As shown in Figure 12B, dummy gate stacks 62 are formed on the sidewalls and top surfaces of the respective semiconductor fins 136A or 136B, with some other portions of the semiconductor fins 60A and 60B exposed. Gate spacers 67 are formed on the sidewalls of the dummy gate stacks 62.

[0035] Next, the exposed portions of the semiconductor fins 60A and 60B ( Fig. 12B) that are not covered by the dummy gate stacks 62 may be removed in an etching process. After the etching, the portions of the semiconductor fins 146B and the base 146A remain. In other embodiments, the exposed portions of the semiconductor fins 60A and 60B are not etched.

[0036] With further reference to Fig. 12A, epitaxy is performed to re-grow epitaxial regions 68A and 68B. The epitaxial region 68A may be grown from the top surface of the base 146A when the fins 60A are etched, or it may be grown directly from the fins 60A. The epitaxial regions 68B are grown from the top surfaces of the remaining semiconductor fins 60B or from the ridges 146B when the fins 60B are etched. The epitaxial regions 68A and 68B form the source / drain regions of the resulting FinFETs. The corresponding step is described as step 218 in the Fig. 17. According to some embodiments of the present disclosure, epitaxial regions 68B are formed from silicon germanium doped with a p-type impurity, such as boron, and epitaxial regions 68A are formed from silicon phosphorus. The FinFETs formed on the basis of regions 68A and 68B are therefore an n-channel FinFET and a p-channel FinFET, respectively. Epitaxial regions 68A and 68B may have upward-facing surfaces and downward-facing surfaces, according to some embodiments, or they may have other shapes. According to alternative embodiments, epitaxial regions 68A and 68B are formed from silicon germanium (doped with boron) and silicon phosphorus, respectively.

[0037] Subsequently, several process steps are performed to complete the formation of the FinFETs 80A and 80B, as shown in Fig. 13. The FinFET 80A represents the FinFET formed from the crown-shaped active region 148A, and the FinFET 80B represents the FinFET formed from the single fin active regions 60B. An example of a FinFET is shown in Fig. 13, which is labeled 80A / 80B to indicate that both FinFET 80A and 80B may have similar cross-sectional views. Fig. 12A and Fig. 12B are replaced by replacement gates 70, with a replacement gate 70 in Fig. 13. Each of the replacement gates 70 includes a gate dielectric 72 on the top surfaces and sidewalls of the respective fin 60A or 60B, and a gate electrode 74 over the gate dielectric 72. The gate dielectric 72 may be formed by thermal oxidation and may therefore comprise thermal silicon oxide. Forming the gate dielectric 72 may also include one or more deposition steps, and the resulting gate dielectric 72 may comprise a high-k dielectric material or a non-high-k dielectric material. The gate electrode 74 is then formed on the gate dielectric 72 and may be formed from metal stacks. The formation processes of these components will not be discussed in detail. Source / drain silicide regions 76 are formed on the surfaces of the source / drain regions 68A / 68B.Source / drain contact plugs 78 are formed in an interlayer dielectric layer (ILD) 82 and are electrically connected to the respective source / drain silicide regions 76.

[0038] According to some embodiments, the FinFET 80A is an n-channel FinFET and the FinFET 80B is a p-channel FinFET. Due to the material difference, the epitaxial regions 68A of the n-channel FinFET (e.g., silicon phosphorus) tend to grow horizontally, and the portions of the epitaxial regions 68A grown by different fins 60A can easily merge. Accordingly, forming closely spaced fins 60A supports the formation of a large unified source / drain. The drive current is therefore higher, and it is easy to place source / drain contact plugs. On the other hand, the epitaxial regions 68B of the p-channel FinFET (e.g., silicon germanium boron) tend not to grow horizontally. It is therefore more process-friendly to form p-channel FinFETs from discrete fins. The p-channel FinFETs can be connected in parallel as needed to generate large currents.According to alternative embodiments, the FinFET 80A is a p-channel FinFET and the FinFET 80B is an n-channel FinFET.

[0039] Fig. 14 to 16 show the profiles of various semiconductor fins 148A and 148B formed as a result of the process described in the previous sections. Fig. The structures shown in 14 to 16 correspond to the Fig. 12A, where more details are shown. In addition, the profiles of the semiconductor fins and the isolation regions 58 also correspond to the corresponding parts in Fig. 13. In Fig. 14 to 16, inclination angles θ1, θ2 and θ3 of the substantially straight portions of the sidewalls of the semiconductor fins / fins are achieved. In Fig. 14 to 16, horizontal dashed lines are drawn to indicate the boundaries of web sections 136B and 146B.

[0040] With reference to Fig. 14, the semiconductor fins 136B have a tilt angle θ1 that is less than 90 degrees, and therefore the sidewalls of the semiconductor fins 136B are chamfered. The tilt angle θ1 of the fins 60B (fin portions 136B) may range between approximately 60 degrees and 90 degrees. The tilt angle θ2 of the fin portions 146B may range between approximately 50 degrees and 80 degrees. The tilt angle θ3 of the fins 60A may range between approximately 60 degrees and 90 degrees. According to some embodiments, the tilt angle θ2 is greater than the tilt angle θ3, wherein the difference (θ2-θ3) may be greater than approximately 10 degrees, according to some embodiments.

[0041] The semiconductor fins 148B include the lower portions 146B and the upper portions 136B. Due to the two separate etching processes for forming the fin portions 146B and 136B, the inclination angle θ1 of the sidewalls of the upper fin portions 136B is greater than the inclination angle θ2 of the sidewalls of the lower fin portions 146B. Accordingly, the interconnection of the fin portions 146B and 136B can be recognized.

[0042] Fig. 15 shows the profiles of various semiconductor fins 148A and 148B according to alternative embodiments. Due to the two-stage etching process and further due to the structural difference between fin 148B and crown-shaped fin 148A, the tilt angle θ2 of the lower fin portion 146B is greater than the tilt angle θ4 of the crown base 146A. According to some embodiments, the tilt angle θ2 is in the range between approximately 60 degrees and 90 degrees, and the tilt angle θ4 is in the range between approximately 60 degrees and 90 degrees, with a difference greater than approximately 10 degrees or 15 degrees. In other words, due to the two-stage etching, the sidewall of the single-fin fin portion 146B is steeper than the sidewall of the crown-shaped base 148A. In addition, the inclination angle θ1 is also larger than the inclination angle θ2, and the inclination angle θ2 is larger than the inclination angle θ3, similar to what was mentioned with reference to Fig. 14 was shown and discussed.

[0043] Fig. Figure 16 shows the profiles of various semiconductor fins 148A and 148B according to alternative embodiments. Due to the two-stage etch process, the trench (and corresponding STI region) between fin 148B-2 and its immediately adjacent crown-shaped fin 148A-2 is deeper than the trench (and corresponding STI region) between single-fin fins 148B-1 and 148B-2. For example, in Fig. 16, a height H3 greater than a height H4. According to some embodiments, the height H3 is in the range between approximately 3 nm and approximately 1000 nm, and the height H4 is in the range between approximately 2 nm and approximately 800 nm. The difference (H3-H4) may be in the range of between approximately 1 nm and approximately 100 nm.

[0044] The embodiments of the present disclosure have several advantageous features. The semiconductor fins, on the basis of which semiconductor fins are formed, are formed in two etching steps. The second etching may result in semiconductor bases for some FinFETs (such as n-channel FinFETs) and discrete fins for some other FinFETs (such as p-channel FinFETs). This matches the property of the materials of the source / drain regions, and the resulting FinFETs are more process-friendly.

[0045] According to some embodiments of the present disclosure, a method includes forming a plurality of mask rings and removing portions of the plurality of mask rings. In a first etching step, the remaining portions of the plurality of mask rings are used to etch a semiconductor substrate. Consequently, a first semiconductor fin and a second semiconductor fin are formed simultaneously, and the second semiconductor fin is located in a semiconductor fin group comprising a plurality of semiconductor fins. A patterned photoresist is formed to protect the first semiconductor fin and the semiconductor fin group. In a second etching step, the semiconductor substrate is etched to simultaneously extend the first semiconductor fin such that it extends deeper into the semiconductor substrate. A semiconductor base is therefore formed simultaneously as the first semiconductor fin is extended, and the semiconductor fin group overlaps the semiconductor base.

Claims

[1] Method comprising: in a first etching step, etching a semiconductor substrate (20) to form first recesses in first device regions (68A) and second recesses in a second device region (68B) simultaneously, wherein first upper semiconductor fins (136A) are formed between the first recesses, and a second semiconductor fin (136B) is formed between the second recesses, in a second etching step, etching the semiconductor substrate (20) to extend the second recesses in the second device region such that they are lower than the first recesses in the first device regions, wherein first semiconductor fins (148A) comprising the first upper semiconductor fins (136A) are formed in the first device regions, Filling the first recesses and the second recesses with a dielectric material (54) to form first insulation regions (58) in the first recesses and second insulation regions (58) in the second recesses, and Recessing the first isolation regions and the second isolation regions, wherein portions of the semiconductor substrate in at least one of the first device regions protrude higher than upper surfaces of the first isolation regions (58) to form a first semiconductor fin (60A), and portions of the semiconductor substrate in the second device region protrude higher than upper surfaces of the second isolation regions (58) to form a second semiconductor fin (60B); further comprising the steps: Formation of several mask rings (28-1, 28-2), Performing a first cut on the plurality of mask rings to remove portions of the plurality of mask rings, wherein remaining portions of the plurality of mask rings (28-1) are used as an etching mask for the first etching step, and after the second etching step, performing a second cut to remove one of the first semiconductor fins (148A-1). [2] The method of claim 1, wherein when the semiconductor substrate (20) is etched in the second etching step, portions of the semiconductor substrate on opposite sides of the first semiconductor fin are etched to form a semiconductor base (146A), wherein a plurality of upper semiconductor fins (136A) comprising the first upper semiconductor fin are located on top of the semiconductor base (146A) and together with the semiconductor base form the first semiconductor fin. [3] The method according to claim 1 or 2, wherein in the second etching step, a height of the second semiconductor fin (148B) is increased. [4] The method of any preceding claim, wherein after the second etching step, the second semiconductor fin (148B) comprises an upper portion (136B) and a lower portion (146B), a first sidewall of the upper portion and a second sidewall of the lower portion having a discernible change in tilt angles, and the first sidewall having a first tilt angle (Θ1) that is greater than a second tilt angle (Θ2) of the second sidewall. [5] The method of any preceding claim, wherein after the second etching step, the first semiconductor fin (148A) has a first sidewall with a first straight portion proximate a bottom surface of the first semiconductor fin, and the second semiconductor fin (148B) has a second sidewall with a second straight portion proximate a bottom surface of the second semiconductor fin, and the first sidewall has a first inclination angle (θ4) that is smaller than a second inclination angle (θ2) of the second sidewall. [6] The method of claim 1, wherein the second cut continues until a portion of the semiconductor substrate (20) directly beneath a bottom surface of the first semiconductor fin (148A-1) is etched. [7] Method according to one of the preceding claims, further comprising: before the second etching step, forming a photoresist (44) to protect both the first upper semiconductor fin (136A) and the second semiconductor fin (148B-1), and Using the photoresist (44) as an etching mask in the second etching step, wherein in the second etching step portions of the semiconductor substrate (20) on opposite sides of the second semiconductor fin are recessed, and portions of the semiconductor substrate (20) on opposite sides of the first upper semiconductor fin (136A) are not recessed. [8] Method comprising: Formation of several mask rings (28-1, 28-2), Removing sections of the multiple mask rings, in a first etching step, using remaining portions of the plurality of mask rings (28-1, 28-2) to etch a semiconductor substrate (20), wherein a first semiconductor fin (136B) and a second semiconductor fin (136A) are formed simultaneously, and the second semiconductor fin is located in a semiconductor fin group comprising a plurality of semiconductor fins, Forming a patterned photoresist (44) to protect the first semiconductor fin (136B) and the semiconductor fin group, and in a second etching step, etching the semiconductor substrate to simultaneously extend the first semiconductor fin (136B, 148B) such that it extends deeper into the semiconductor substrate (20), wherein a semiconductor base (146A) is formed simultaneously as the first semiconductor fin is extended, and the semiconductor fin group overlaps the semiconductor base. [9] The method of claim 8, wherein the semiconductor fin group comprises a central fin (136A), and when the semiconductor base (146A) is formed, a height of the central fin remains unchanged. [10] The method of claim 8 or 9, wherein an additional semiconductor fin group and an additional semiconductor base (146A-1) are each formed simultaneously with the semiconductor fin group and the semiconductor base, and the method further comprises removing the additional semiconductor base and the additional semiconductor fin group. [11] The method of claim 10, further comprising: after the additional semiconductor base (146A-1) has been completely removed, further etching the semiconductor substrate. [12] Method according to one of the preceding claims 8 to 11, further comprising: Filling a dielectric material (54) to embed the first semiconductor fin (148B) and the second semiconductor fin (136A) in isolation regions (58), Recessing the isolation regions, wherein an upper portion of the first semiconductor fin (148A-2) forms a first semiconductor fin (60B), and upper portions of the plurality of semiconductor fins (136A) form second semiconductor fins (60A), Forming a first fin field effect transistor, FinFET, on the basis of the first semiconductor fin (60B), and Forming a second FinFET based on the plurality of semiconductor fins (60A). [13] Method according to one of the preceding claims 8 to 12, further comprising: Forming a patterned photoresist (44) to protect the first semiconductor fin (148B) and the semiconductor fin group (136A), wherein in the second etching step, portions of the patterned photoresist (38) remain between the plurality of semiconductor fins (136A) in the semiconductor fin group, and portions of the patterned photoresist (44) on opposite sides of the first semiconductor fin (148B) are completely consumed.

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