ARRAY SUBSTRATE, DISPLAY FIELD AND DISPLAY DEVICE

Abstract

Array substrate, with: a substrate (10) and multiple scanning lines (110) and multiple data lines (120) arranged on the substrate (10), wherein the multiple scanning lines (110) and the multiple data lines (120) are isolated and intersect to define multiple pixel units (130), wherein a pixel unit (130) comprises a thin-film transistor (131) and a pixel electrode (132), a gate electrode (210) of the thin-film transistor (131) is electrically connected to a scanning line (110), a source electrode (220) of the thin-film transistor (131) is electrically connected to a data line (120), and a drain electrode (230) of the thin-film transistor (131) is electrically connected to the pixel electrode (132) of the pixel unit (130), an active layer (240) of the thin-film transistor (131) comprises at least one channel region (241) and the channel region (241) comprises at least one first subchannel region (310) and at least one second subchannel region (320), and the at least one first subchannel region (310) is connected to a non-channel region of the active layer (240), and along a direction perpendicular to an extension direction of the channel area (241), each of the at least one first subchannel areas (310) has a first width, each of the at least one second subchannel areas (320) has a second width, and the second width is smaller than the first width. wherein in the direction perpendicular to the extension direction of the channel area (241) the non-channel area of ​​the active layer (240) has the first width, wherein the at least one first subchannel area (310) is connected to the at least one second subchannel area (320), and a width of the channel area (241) changes abruptly in a connecting area between the at least one first subchannel area (310) and the at least one second subchannel area (320).

Description

FIELD OF THE INVENTION

[0001] The present disclosure generally relates to the field of liquid crystal display technology, and more particularly relates to an array substrate, a display panel, and a display device. BACKGROUND

[0002] With the development of display technologies, the display effect of liquid crystal display products is continuously improved, thus greatly expanding the application range of liquid crystal display products.

[0003] The power consumption of display products is proportional to the display drive frequency. Therefore, to reduce the power consumption of display products, the display drive frequency must be reduced. However, in current display products, even after the drive frequency is reduced, the pixel electrode voltage may continue to decrease in a holding stage due to the presence of leakage current, and display image flicker is likely to occur, thus degrading the display effect.

[0004] US 2011 / 0 169 001 A1 discloses a liquid crystal display device or an organic electroluminescence (EL) display device.

[0005] From US 2015 / 0 060 863 A1 an array substrate is known, as well as a method for producing the same and a display device.

[0006] US 2015 / 0 301 378 A1 describes a display device including a light-shielding film located between the insulating substrate and the semiconductor layer.

[0007] JP 2016-167 590 A discloses a transistor and a semiconductor device.

[0008] The array substrate, display panel, and display device disclosed are directed to at least partially achieving the objects set forth above and other objects. SUMMARY OF REVELATION

[0009] In one aspect of the present disclosure, an array substrate is provided. The array substrate includes a substrate and a plurality of scan lines and a plurality of data lines arranged on the substrate. The plurality of scan lines and the plurality of data lines are insulated and intersect to define a plurality of pixel units. Each pixel unit includes a thin-film transistor and a pixel electrode, a gate electrode of the thin-film transistor is electrically connected to a scan line, a source electrode of the thin-film transistor is electrically connected to a data line, and a drain electrode of the thin-film transistor is electrically connected to the pixel electrode of the pixel unit. An active layer of the thin-film transistor includes at least one channel region, and the channel region includes a first sub-channel region and at least one second sub-channel region.Along a direction perpendicular to an extension direction of the channel region, the first subchannel region has a first width, the second subchannel region has a second width, and the second width is smaller than the first width. In the direction perpendicular to the extension direction of the channel region, a non-channel region of the active layer of the thin-film transistor has the first width. The at least one first subchannel region is connected to the non-channel region of the active layer. The at least one first subchannel region is connected to the at least one second subchannel region. A width of the channel region changes abruptly in a connection region between the at least one first subchannel region and the at least one second subchannel region.

[0010] In another aspect of the present disclosure, a display panel is provided that includes an array substrate. The array substrate includes a substrate and a plurality of scan lines and a plurality of data lines arranged on the substrate. The plurality of scan lines and the plurality of data lines are insulated and intersect to define a plurality of pixel units. Each pixel unit includes a thin-film transistor and a pixel electrode, a gate electrode of the thin-film transistor is electrically connected to a scan line, a source electrode of the thin-film transistor is electrically connected to a data line, and a drain electrode of the thin-film transistor is electrically connected to the pixel electrode of the pixel unit. An active layer of the thin-film transistor includes at least one channel region, and the channel region includes a first sub-channel region and at least one second sub-channel region.Along a direction perpendicular to an extension direction of the channel region, the first subchannel region has a first width, the second subchannel region has a second width, and the second width is smaller than the first width. In the direction perpendicular to the extension direction of the channel region, a non-channel region of the active layer of the thin-film transistor has the first width. The at least one first subchannel region is connected to the non-channel region of the active layer. The at least one first subchannel region is connected to the at least one second subchannel region. A width of the channel region changes abruptly in a connection region between the at least one first subchannel region and the at least one second subchannel region.

[0011] Further aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly explain technical solutions in embodiments of the present disclosure or current techniques, the drawings required for the embodiments or current techniques are briefly presented below. It is clear that the drawings described below correspond to only some embodiments of the present disclosure, and it is possible for a person of ordinary skill in the art to derive other drawings from the attached drawings without any design effort. Fig. 1 shows a pixel electrode voltage change in an exemplary frame according to disclosed embodiments; Fig. 2 shows an exemplary array substrate according to disclosed embodiments; Fig. 3 shows a cross-sectional view AA of an exemplary array substrate in Fig. 2, which corresponds to disclosed embodiments; Fig. Figure 4 shows a partially enlarged view of an exemplary array substrate in Fig. 2, which corresponds to disclosed embodiments; Fig. 5 shows a partially enlarged view of another exemplary array substrate according to disclosed embodiments; Fig. 6 shows another exemplary array substrate in accordance with disclosed embodiments; Fig. 7 shows a cross-sectional view BB of an exemplary array substrate in Fig. 6, which corresponds to disclosed embodiments; Fig. 8 shows an exemplary display panel according to disclosed embodiments; Fig. 9 shows a partial perspective view of an exemplary display panel according to disclosed embodiments; and Fig. 10 shows an exemplary display device according to disclosed embodiments. DETAILED DESCRIPTION

[0013] The present disclosure will now be described in more detail with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that the exemplary embodiments disclosed herein are for illustrative purposes only and are not intended to limit the present disclosure. Furthermore, for ease of description, the accompanying drawings illustrate only a portion, but not all, of the structures pertaining to the present disclosure.

[0014] As explained above, in existing display products, after the driving frequency is reduced, the pixel electrode voltage may further decrease in a holding stage due to the presence of the leakage current, and display image flicker may easily occur, thus deteriorating the display effect.

[0015] The present disclosure is directed to at least partially achieving the above-stated and other objects, and provides an improved array substrate, an improved display panel, and an improved display device. According to the present disclosure, by forming at least a second sub-channel region with a relatively narrow width in the thin-film transistor on the array substrate, the resistance of the thin-film transistor is increased. Furthermore, since the voltage between the two ends of the thin-film transistor is fixed, the leakage current of the thin-film transistor can be reduced, and the deviation of the pixel electrode voltage can be reduced. Accordingly, the flicker of the display image caused by a sharp reduction in the pixel electrode voltage can be avoided, thus improving the display effect under low-frequency driving.

[0016] In Fig. 1 illustrates a pixel electrode voltage change in an exemplary frame according to disclosed embodiments. As shown in Fig. As shown in Figure 1, Vg represents a gate electrode drive signal supplied to scanning lines, and Vp represents a pixel electrode voltage. Generally, the display of each frame can be divided into a charging stage c and a holding stage e. In the charging stage c, the gate electrode drive signal Vg may be at a high voltage level, and a thin-film transistor connected to the pixel electrode may be turned on to charge the pixel electrode. Thus, the pixel electrode voltage Vp may become a corresponding grayscale voltage. That is, the writing of the information to be displayed by the entire image can be completed. In the holding stage e, the scanning lines may supply a certain DC signal or may not supply a signal, and the thin-film transistor may be turned off until the next frame signal begins.

[0017] Due to the influence of leakage current, during the hold stage e, electric charges from the pixel electrode may leak through the thin-film transistor, and the pixel electrode voltage Vp may continue to decrease over time. If the drive frequency of the display panel is reduced, the duration of the hold stage e may be increased, and the decrease in the pixel electrode voltage Vp may be relatively large. Accordingly, the pixel electrode voltage Vp during the hold stage may not meet the image display requirements, and image flicker may easily occur, thus degrading the display effect.

[0018] In Fig. 2 shows an exemplary array substrate corresponding to disclosed embodiments. In Fig. 3 is a cross-sectional view AA of an exemplary array substrate in Fig. 2, which corresponds to disclosed embodiments. With reference to Fig. 2 and Fig. 3, the array substrate may include a substrate 10, a plurality of scan lines 110 disposed on the substrate 10, and a plurality of data lines 120 disposed on the substrate 10. The plurality of scan lines 110 and the plurality of data lines 120 may be isolated and intersect to define a plurality of pixel units 130.

[0019] With reference to Fig. 2, the pixel unit 130 may include a thin-film transistor 131 and a pixel electrode 132. The thin-film transistor 131 may include a gate electrode 210, a source electrode 220, and a drain electrode 230. The gate electrode 210 may be electrically connected to the scan line 110, the source electrode 220 may be electrically connected to the data line 120, and the drain electrode 230 may be electrically connected to the pixel electrode 132. With reference to Fig. 3, the pixel unit 130 may also have a (in Fig. 2 not shown) common electrode 133.

[0020] In Fig. 4 is an enlarged view of an exemplary array substrate in Fig. 2, which corresponds to disclosed embodiments. In Fig. 4 is in particular an enlarged view of an area C in Fig. 2. With reference to Fig. 3 and Fig. 4, an active layer 240 of the thin-film transistor 131 may include at least one channel region 241. The channel region 241 may include a first sub-channel region 310 and at least one second sub-channel region 320. In particular, along the direction perpendicular to an extension direction of the channel region 241, the first sub-channel region 310 may have a first width D1, the second sub-channel region 320 may have a second width D2, and the second width D2 may be smaller than the first width D1.

[0021] Furthermore, the gate electrode 210 of the thin-film transistor 131 and the scan line 110 may be fabricated using the same process. The gate electrode 210 may be a part of the scan line 110. As shown in Fig. 2 and Fig. 4, the gate electrode 210 and the scan line 110 are not distinguished. Furthermore, the gate electrode 210 may overlap with the active layer 240. The channel region 241 of the thin-film transistor 131 may be an overlap region between the active layer 240 of the thin-film transistor 131 and the scan line 110 (or the gate electrode 210).

[0022] Furthermore, the width of the channel region 241 of the thin-film transistor 131 may be inversely proportional to the resistance of the thin-film transistor 131. That is, as the width of the channel region 241 decreases, the resistance of the thin-film transistor 131 may increase accordingly. In one embodiment, at least a second sub-channel region 320 having a relatively narrow width may be disposed in the channel region 241 of the thin-film transistor 131, thereby increasing the resistance of the thin-film transistor 131. Moreover, since the voltage between two ends of the thin-film transistor 131 is fixed, the leakage current of the thin-film transistor 131 can be reduced and the deviation of the pixel electrode voltage can be reduced. Accordingly, the flickering of the display image caused by a sharp decrease in the pixel electrode voltage can be avoided, thus improving the display effect under low-frequency driving.Thus, a lower driving frequency can be applied to the thin film transistor 131 and the power consumption of the display panel can be reduced.

[0023] Optionally, the ratio of the second width D2 to the first width D1 may be less than or equal to 0.6. Specifically, under the condition that the first width D1 is fixed, the smaller the ratio of the second width D2 to the first width D1, the higher the resistance of the thin-film transistor 131. By setting the ratio of D2 to D1 to be less than or equal to 0.6, the second sub-channel region 320 can be ensured to have a relatively narrow width. Accordingly, the thin-film transistor 131 can be ensured to have a relatively high resistance, and the leakage current of the thin-film transistor 131 can be reduced.

[0024] Furthermore, the ratio of the length L of the second sub-channel region 320 along the extension direction of the channel region 241 to the first width D1 may be greater than 0.25 and less than 2. Specifically, under the condition that the width D2 of the second sub-channel region is fixed, the longer the length L of the second sub-channel region 320, the higher the resistance of the thin-film transistor 131. By setting the ratio of the length L to the first width D1 to be greater than 0.25 and less than 2, once the requirements of existing processes are met, it can be ensured that the second sub-channel region 320 has a considerable length. Accordingly, the resistance of the thin-film transistor 131 can be maximized, the leakage current can be reduced, and the flickering of the display image caused by a sharp decrease in the pixel electrode voltage can be avoided, thus improving the display effect under low-frequency driving.

[0025] Optionally, the first width D1 can be in a range of approximately 2 to 4 micrometers. Specifically, by setting the first width D1 to be in a range of approximately 2 to 4 micrometers, it can be ensured that the channel region 241 of the thin-film transistor 131 has a relatively narrow width. Accordingly, the overall resistance of the thin-film transistor 131 can be increased, the leakage current of the thin-film transistor 131 can be reduced, and the display effect under low-frequency driving can be improved.

[0026] The disclosed values ​​or ranges of the first width D1, the second width D2, and the length L may be target values ​​or ranges under given processing conditions. However, the present disclosure is not intended to limit the values ​​or ranges of D1, D2, and L. That is, if the processing conditions permit, the first width D1 and the second width D2 may be made smaller, and the length L may be made larger.

[0027] Optionally, along the direction perpendicular to the extension direction of the channel region 241, a non-channel region of the active layer in the thin-film transistor 131 may have the first width D1. Specifically, the non-channel region may be the region other than the channel region 241 in the active layer 240. Since the non-channel region and the first sub-channel region 310 have the same width, the processing difficulty in forming the active layer 240 can be reduced. Furthermore, the non-channel region may have a relatively narrow width, thus reducing the resistance of the thin-film transistor 131.

[0028] Optionally, in one embodiment, the first sub-channel region 310 and the second sub-channel region 320 may be connected. Since the width of the channel region 241 may change abruptly in the connecting region between the first sub-channel region 310 and the second sub-channel region 320, the resistance of the channel region 241 may be more easily reduced. Fig. 4 illustrates an exemplary array substrate according to disclosed embodiments. In particular, Fig. 4 illustrates an exemplary method for connecting the first sub-channel region 310 to the second sub-channel region 320.

[0029] As in Fig. 4, the fact that the width of the channel region 241 changes abruptly from the first width D1 to the second width D2 is not intended to limit the present disclosure. In some embodiments, other methods for connecting the first sub-channel region 310 to the second sub-channel region 320 may be disclosed.

[0030] In Fig. 5 is a partially enlarged view of another exemplary array substrate according to disclosed embodiments. With reference to Fig. 5, a third sub-channel region 330 may be arranged between the first sub-channel region 310 and the second sub-channel region 320. Along the extension direction of the channel region 241, the width of the third sub-channel region 330 may gradually change from the first width D1 to the second width D2 along the direction perpendicular to the extension direction of the channel region 241. Specifically, one side of the third sub-channel region 330 having the first width D1 may be connected to the first sub-channel region 310, and one side of the third sub-channel region 330 having the second width D2 may be connected to the second sub-channel region 320.

[0031] In particular, by forming the third sub-channel region 330 as a width transition region between the first sub-channel region 310 and the second sub-channel region 320, the processing difficulty of forming the active layer 240 can be reduced. Furthermore, when the width D1 and the length L of the second sub-channel region 320 are fixed, by providing the third sub-channel region 330, the width of the channel region 241 of the thin-film transistor 131 can be further reduced and the leakage current can be further reduced.

[0032] Furthermore, in Fig. 5 merely illustrates the situation in which the width of the third sub-channel region 330 changes gradually and linearly from the first width D1 to the second width D2. That is, in Fig. 5 only illustrates the situation in which two outer sides of the third channel region 330 are straight lines. However, the present disclosure is not limited thereto. In other embodiments, the two outer sides of the third channel region 330 may have other shapes. For example, the two outer sides may be arcuate.

[0033] In Fig. 6, another exemplary array substrate is shown that corresponds to disclosed embodiments. With reference to Fig. 6, the active layer 240 of the thin-film transistor 131 may have a first channel region 241a and a second channel region 241b. In an extension direction of the first channel region 241a, the first channel region 241a may include at least one second sub-channel region 320. In an extension direction of the second channel region 241b, the second channel region 241b may include at least one second sub-channel region 320.

[0034] Specifically, by forming the thin-film transistor 131 to have two channel regions, the total length of the channel region of the thin-film transistor 131 can be increased. Thus, the resistance of the thin-film transistor 131 can be further increased, and the leakage current of the thin-film transistor 131 can be reduced. Furthermore, by forming at least one second sub-channel region 320 in the first channel region 241a and the second channel region 241b, the length of the area with a relatively narrow width in the entire channel region can be increased. Thus, the resistance of the thin-film transistor 131 can be increased, and the leakage current of the thin-film transistor 131 can be reduced. Accordingly, the variation in the pixel electrode voltage can be reduced, and flickering of the display image caused by a sharp decrease in the pixel electrode voltage can be avoided, thus improving the display effect under low-frequency driving.

[0035] In Fig. 7 is a cross-sectional view BB of an exemplary array substrate in Fig. 6, which corresponds to disclosed embodiments. With reference to Fig. 7, the thin-film transistor 131 may be a top-gate electrode, and the channel region of the thin-film transistor 131 may be disposed on a side of the gate electrode 210 facing the substrate 10. Thus, the gate electrode 210 may shield the channel region of the thin-film transistor 131. Accordingly, when light exits from a side of the active layer 240 facing the pixel electrode 132, an increase in leakage current caused by photon-generated carriers induced by light irradiating the channel region can be avoided.

[0036] Furthermore, the pixel unit 130 may also include a light-shielding layer 134, and the light-shielding layer 134 may be disposed on a side of the channel region of the thin-film transistor 131 facing the substrate 10. The perpendicular projection of the light-shielding layer 134 onto the substrate 10 may cover the perpendicular projection of the channel region of the thin-film transistor 131 onto the substrate 10. In particular, by forming the light-shielding layer 134 to shield the channel region of the thin-film transistor 131, when light exits from a side of the active layer 240 facing the substrate 10, the photocurrent induced by light irradiating the channel region can be prevented. In this way, the characteristics of the thin-film transistor 131 can be improved, and leakage losses caused by the photocurrent can be prevented.Furthermore, the deviation of the pixel electrode voltage can be reduced and the display effect can be improved under low-frequency driving.

[0037] Alternatively, the thin-film transistor 131 may be a low-temperature polysilicon thin-film transistor (LTPS thin-film transistor). In particular, the low-temperature polysilicon thin-film transistor may have a relatively high electron transfer rate, thus the response speed of the thin-film transistor 131 may be relatively high, and the charging and discharging speed of the pixel unit 130 may not be affected after the width of the channel region of the thin-film transistor 131 decreases. Furthermore, by using the low-temperature polysilicon thin-film transistor, the area occupied by the thin-film transistor 131 can be smaller and thinner. Accordingly, not only can the power consumption of the display panel be reduced, but a relatively high aperture ratio of the pixel unit can also be ensured.

[0038] The above-described embodiments illustrate the present disclosure merely by way of an exemplary array substrate in a liquid crystal display panel. However, the present disclosure is not limited thereto; in some other embodiments, the array substrate may be applied to a self-luminous display panel, such as an organic light-emitting display panel.

[0039] The present disclosure also provides a display panel. In Fig. 8 illustrates an exemplary display panel according to disclosed embodiments. As shown in Fig. As shown in Figure 8, the disclosed display panel may include an array substrate 100 described in any of the above embodiments of the present disclosure. Furthermore, the display panel may also include a color film substrate 300 disposed opposite to the array substrate 100 and a liquid crystal layer 200 located between the array substrate 100 and the color film substrate 300.

[0040] In Fig. 9 is a partial perspective view of an exemplary display panel according to disclosed embodiments. As shown in Fig. 9, a black matrix (ie, a light-shielding matrix) 301 may be disposed on the color film substrate, and a perpendicular projection of the thin film transistor 131 onto the color film substrate 300 may be located within the black matrix 301.

[0041] Optionally, the refresh rate of the display panel may be in a range of approximately 0.5 Hz to 45 Hz. If the refresh rate is higher than 45 Hz, the power consumption of the display panel may be relatively high, resulting in resource and energy depletion. However, the disclosed display panel having a structure constructed according to any of the above-described embodiments can effectively reduce the refresh rate while maintaining stable display images when the display panel operates at a relatively low frequency. Accordingly, a relatively high image display quality can be ensured, and at the same time, the power consumption of the display panel can be reduced.

[0042] In the disclosed display panel, by forming at least one second sub-channel region with a relatively narrow width in the thin-film transistor arranged on the array substrate, the resistance of the thin-film transistor can be increased. Since the voltage between the two ends of the thin-film transistor is fixed, the leakage current of the thin-film transistor can be reduced, and the deviation of the pixel electrode voltage can be reduced. Accordingly, the flickering of the display image caused by a sharp reduction in the pixel electrode voltage can be avoided, thus improving the display effect under low-frequency driving. Thus, the thin-film transistor can use a lower driving frequency, and the power consumption of the display panel can be reduced.

[0043] The present disclosure also provides a display device. In Fig. 10 illustrates an exemplary display device according to disclosed embodiments. As shown in Fig. 10, the display device 400 may include a display panel 500 illustrated in any embodiment described above. In particular, the display device 400 may include a Fig. 10, a computer, a television station, or a smart portable display device, etc. The present disclosure is not intended to limit the particular type of display device.

[0044] It should be noted that the above detailed descriptions merely illustrate preferred embodiments of the present disclosure, as well as technologies and principles employed herein. It will be apparent to those skilled in the art that the present disclosure is not limited to the particular embodiments described herein, and numerous substantial changes, modifications, and alternatives may be devised by those skilled in the art without departing from the spirit and scope of the present disclosure. Thus, while the present disclosure has been specifically illustrated in the embodiments described above, the present disclosure is not limited to the above embodiments. Any equivalent or modification thereof that does not depart from the spirit and principle of the present invention is intended to be within the true scope of the present invention, and the scope of the present disclosure is defined by the appended claims.

Claims

[1] Array substrate, with: a substrate (10) and a plurality of scan lines (110) and a plurality of data lines (120) arranged on the substrate (10), wherein the plurality of scan lines (110) and the plurality of data lines (120) are insulated and intersect to define a plurality of pixel units (130), wherein a pixel unit (130) comprises a thin-film transistor (131) and a pixel electrode (132), a gate electrode (210) of the thin-film transistor (131) is electrically connected to a scanning line (110), a source electrode (220) of the thin-film transistor (131) is electrically connected to a data line (120), and a drain electrode (230) of the thin-film transistor (131) is electrically connected to the pixel electrode (132) of the pixel unit (130), an active layer (240) of the thin-film transistor (131) comprises at least one channel region (241), and the channel region (241) comprises at least a first sub-channel region (310) and at least one second sub-channel region (320), and the at least one first sub-channel region (310) is connected to a non-channel region of the active layer (240), and along a direction perpendicular to a direction of extension of the channel region (241), each of the at least one first sub-channel regions (310) has a first width, each of the at least one second sub-channel regions (320) has a second width, and the second width is smaller than the first width, wherein in the direction perpendicular to the extension direction of the channel region (241), the non-channel region of the active layer (240) has the first width, wherein the at least one first sub-channel region (310) is connected to the at least one second sub-channel region (320), and a width of the channel region (241) changes abruptly in a connecting region between the at least one first sub-channel region (310) and the at least one second sub-channel region (320). [2] The array substrate according to claim 1, wherein: a ratio of the second width to the first width is less than or equal to 0.

6. [3] The array substrate according to claim 1, wherein: a ratio of a length of the second sub-channel region (320) in the extension direction of the channel region (241) to the first width is greater than 0.25 and less than 2. [4] The array substrate according to claim 1, wherein: the first width is in a range of about 2 - 4 micrometers. [5] The array substrate according to claim 1, wherein: the active layer (240) of the thin-film transistor (131) has a first channel region (241a) and a second channel region (241b), in an extension direction of the first channel region (241a), the first channel region (241a) comprises at least one second sub-channel region (320) and in an extension direction of the second channel region (241b), the second channel region (241b) comprises at least one second sub-channel region (320). [6] The array substrate according to claim 1, wherein: the pixel unit (130) further comprises a light-shielding layer (134), the light-shielding layer (134) is arranged on a side of the thin-film transistor (131) facing the substrate (10), and a perpendicular projection of the light-shielding layer (134) onto the substrate (10) covers a perpendicular projection of the channel region (241) of the thin-film transistor (131) onto the substrate (10). [7] The array substrate according to claim 1, wherein: the thin-film transistor (131) is a top-gate structure and the channel region (241) of the thin-film transistor (131) is arranged on a side of the gate electrode (210) facing the substrate (10). [8] The array substrate according to claim 1, wherein: the thin-film transistor (131) is a low-temperature polysilicon thin-film transistor. [9] A display panel comprising an array substrate (100), the array substrate (100) comprising: a substrate (10) and a plurality of scan lines (110) and a plurality of data lines (120) arranged on the substrate (10), wherein the plurality of scan lines (110) and the plurality of data lines (120) are insulated and intersect to define a plurality of pixel units (130), wherein a pixel unit (130) comprises a thin-film transistor (131) and a pixel electrode (132), a gate electrode (210) of the thin-film transistor (131) is electrically connected to a scanning line (110), a source electrode (220) of the thin-film transistor (131) is electrically connected to a data line (120), and a drain electrode (230) of the thin-film transistor (131) is electrically connected to the pixel electrode (132) of the pixel unit (130), an active layer (240) of the thin-film transistor (131) comprises at least one channel region (241), and the channel region (241) comprises at least a first sub-channel region (310) and at least one second sub-channel region (320), and the at least one first sub-channel region (310) is connected to a non-channel region of the active layer (240), and along a direction perpendicular to a direction of extension of the channel region (241), each of the at least one first sub-channel regions (310) has a first width, each of the at least one second sub-channel regions (320) has a second width, and the second width is smaller than the first width, wherein in the direction perpendicular to the extension direction of the channel region (241), the non-channel region of the active layer (240) has the first width, wherein the at least one first sub-channel region (310) is connected to the at least one second sub-channel region (320), and a width of the channel region (241) changes abruptly in a connecting region between the at least one first sub-channel region (310) and the at least one second sub-channel region (320). [10] A display panel according to claim 9, further comprising: a color film substrate (300) arranged opposite to the array substrate (100), and a black matrix (301) arranged on the color film substrate (300), wherein a perpendicular projection of the thin film transistor (131) onto the color film substrate (300) is located within the black matrix (301). [11] A display panel according to claim 9, wherein: a refresh rate of the display panel is approximately 0.5 Hz to 45 Hz. [12] A display device comprising the display panel according to any one of claims 9 to 11.

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