Method for manufacturing a micro-technical component

Abstract

Method for manufacturing a micro-technical component (100) with a substrate (3) as a semiconductor substrate, which has a front (2) and a back (1) and with at least one electrical via (150, 150') in the substrate (3), the method comprising the following steps ... - Producing a protective layer (4) over a component structure (5) that is produced on and / or in a front face (2) of the substrate (3); - Forming at least one deep or long, hollow cylindrical contact hole (14,14') to form the at least one via (150), wherein the aspect ratio of the at least one via is greater than or equal to eight and extends from a surface of the back side (1) of the substrate to a contact surface (5a) of the component structure (5); - Forming a metal-containing and therefore conductive lining (8,9,10) in the or each deep or long contact hole (14,14'), so that a hollow, electrically conductive structure (110) is formed in the or each contact hole (14,14'); - Application of a passivation layer (11) over the back of the substrate (3), which spans the hollow conductive structure to form at least one electrical via (150,150'); wherein the passivation layer (11) is provided with openings or a local structuring takes place, adapted or suitable for subsequent coating with further metal layers (12) and for the placement of solder balls (13) over the back (1) of the substrate (3); and with the fabrication of a wiring structure (10a, 10b) on the surface of the back side for connecting the via (150) to a solder ball structure (13), wherein the connection is a conductor track (10a) exhibits; wherein the spanning of the hollow conductive structure by the passivation layer (11) is carried out and the process parameters during manufacturing are set in such a way that the vias (150) are covered without or without significant material input into the contact holes (14), thereby spanning them, in particular the hollow conductive structures (110).

Description

[0001] This disclosure (and claims) generally relates to the field of manufacturing microtechnical components, e.g., micro-electronic, micro-optical, micro-mechanical component structures that are manufactured in and on a substrate and require through-hole plating through the substrate for further connection of the component structure.

[0002] In microelectronics and microsystems technology, there is a growing trend to not only reduce lateral dimensions—that is, the dimensions across the surface of a suitable substrate, such as a semiconductor wafer—but also to create connections in the dimension perpendicular to the substrate, thus enabling three-dimensional integration. The integration of micromechanical systems in conjunction with CMOS technology plays a particularly significant role in this development. Electrical vertical vias are important components for the electrical connection of component structures, such as micromechanical structures (MEMS), electronic structures, such as CMOS structures with transistors, and the like, to other component structures located at different positions on the same substrate, on opposite sides of the substrate, or on a separate substrate.In such three-dimensional applications, the focus is often on connecting or stacking similar component structures, for example, stacking memory or logic chips. So-called heterogeneous integration is also used in the pursuit of more compact designs for larger electronic units, where different component types are connected, for example, when chips without packages are directly connected to printed circuit boards.

[0003] The vertical electrical through-hole technology (also known as "via") used for these applications, especially for through-hole technology of a semiconductor wafer, is suitable for a wide range of applications in microelectronics / microsystems technology and is therefore considered a suitable means in many new developments.

[0004] In general, an electrical vertical via is understood as a narrow hole extending through the semiconductor substrate, its wall lined with an insulating layer and filled with a conductive material. In recent developments, a metal or metal alloy is predominantly used, at least partially, as the conductive material. The conductive material, or metal, is in contact with the nearest contact plane, thus achieving the desired conductivity for the via. Typically, the dimensions of a via are intended to be as small as possible to save valuable space on the substrate and keep material costs down. When using an electrical via, the design and manufacturing process are often tailored to the specific application of the via.The design of the via and the process for its production are therefore often dependent on the component structure to be manufactured or already manufactured, which is intended for the front and / or back of the substrate. In particular, the point in the process chain at which the via is produced is crucial in this coordination between the manufacturing and type of via and the type and manufacturing of the component structures.

[0005] Generally, there are three possible points in time for the production of a via, although in certain cases a mixture of these three points in time is also possible, i.e., production only partially taking place at certain manufacturing times... Via-first contact (so-called via-first) The vertical via is created first, and then the component structures, e.g. MEMS / CMOS structures, are created on the front and / or back of the substrate. Through-hole connection (so-called via-middle) The manufacturing processes for through-hole plating are carried out during the production of the component structure, but take place before the production of the metallization layers that serve to connect the individual components of the component structure (BEOL). Via last (so-called via-last) The through-hole plating is created only during or after the production of the metallization layers for the component structures.

[0006] The strategy to be applied is generally selected depending on the component structure to be manufactured, in order to exploit the advantages of the respective strategy while simultaneously minimizing the associated disadvantages in light of the overall manufacturing process. In particular, the mechanical and thermal influences of the manufacturing processes are of great importance for through-hole plating with regard to compatibility with the component structures to be manufactured or already manufactured, e.g., with CMOS / MEMS assemblies.

[0007] Therefore, for standard applications of vias, the approach "via first" or "via in the middle" is chosen to minimize corresponding compatibility problems between the process control for the via and the component structure.

[0008] Due to the many different specifications for vertical via applications, a corresponding new via variant typically needs to be developed for each newly developed component structure technology. Existing process strategies for manufacturing vias are often too specialized to allow for modular, flexible application. For example, the "via first" or "via in the middle" approach severely limits the scope of application, as contamination of standard semiconductor processes is extremely problematic when using metals such as copper. In particular, many process systems are equipped with vacuum handling devices for the back side of semiconductor wafers, which limits the usability of a previously processed wafer back side in such systems.Significant problems also arise with regard to the conductive material of the via. Copper, the most commonly used material, leads to an excessively high temperature coefficient difference compared to the semiconductor substrate and also diffuses into adjacent material structures until copper saturation is reached, unless appropriate protective intermediate layers are provided. These properties of copper, as well as its plastic-elastic properties, can lead to significant problems with material delamination and adhesion, and / or contribute to mechanical stress in the various material layers.

[0009] Furthermore, the effect of the ambient atmosphere on copper layers is typically associated with a temperature-dependent oxidation of this layer, which is detrimental to conductivity.

[0010] Furthermore, the deposition of layers in vertical vias is very difficult to achieve for larger aspect ratios, especially when a relatively complex layer structure is required, as with copper.

[0011] Conventional methods for layer deposition reach their limits, particularly with large aspect ratios, in terms of the deposition rates to be achieved and the time required, which are incompatible with the usual requirements for mass production.

[0012] Considerable material costs arise, particularly when copper or tungsten are used as conductive materials for through-hole plating.

[0013] US 3,761,782 A, designated D1, functionally describes a semiconductor structure in which structural components on the back side are conductively connected from the front side via contact holes. The depicted contact holes lack vertical sidewalls, instead forming a pyramidal structure, which necessitates a large surface area at the end of the contact holes for connecting active semiconductor elements. Transistors, for example, are proposed as active elements. In this document, solder balls are used in the large, flat end of the pyramidal structure of the contact holes, simplifying the connection process. The diameters of the solder balls are dimensioned such that a significant portion extends into the openings of the contact holes.

[0014] DE 10 2008 053 ​​427 A1, as D2, describes structures and methods for forming contact pads for through-substrate interconnects (TSVs) by forming stacked semiconductor components in substrates. The TSVs described therein have a trench structure and a metal layer in the trench, which is filled with a conductive filler material. The thickness of the semiconductor structure described therein is on the order of 10 µm to 15 µm. The trench structure for through-hole plating extends from a front side with a contact pad to the back side. The contact pad is electrically connected to the trench. The side with the contact pad is referred to as the front side, and the side that forms the (lower) end of the TSV trench, as described therein, is referred to as the front side. Fig. The reverse side, shown in section 6j, shall be called the back side. A comparison with the claimed invention is thus possible. Relatively little is disclosed in this document regarding the design of the reverse side; see paragraphs

[064] and

[065] and the information therein. Fig. 6. The design of an aluminum bond pad and the use of a solder ball on the upper surface of the TSV are mentioned there, for the purpose of bonding to another TSV chip. Alternatively, an interposer is proposed. No graphic representation is provided. A via extends from the back to a contact surface on the front (there 145 / 160). The via is hollow internally, as described in sections

[0059] to

[0064] .

[0015] WO 2001 / 099 182 A2 as D3, cf. page 10, second paragraph to page 11, last paragraph, points to common in-situ processes of a CVD barrier layer and a CVD nucleation layer in a contact hole with otherwise comparable technical characteristics (CVD barrier layer, CVD nucleation layer, electroplating of copper as filling), in particular also with an explicit reference to a suitability for high aspect ratios of the contact holes.

[0016] US 2002 / 0 076 492 A1 as D4 may or could suggest to the person skilled in the art, especially in the case of high aspect ratios of the contact holes, the use of MOCVD as a barrier layer.

[0017] US 2010 / 0 320 609 A1 as D5 refers to a technique of “pre-wetting” (under vacuum) to improve electrolytic deposition.

[0018] US 3 761 782 A as D1, as functionally cited above, see in this source in particular its Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. 8 and the associated description in column 2, line 30 to column 7, line 65. This reference discloses a method for forming an electrical via in a substrate, specifically comprising, - the creation of a protective layer (there 18) over a component structure (there 11) that was created on and / or in a front face of the substrate (there 11); - the formation of at least one contact hole (there 21) which extends from a surface of the back of the substrate to a contact surface of the component structure; - the formation of a metal-containing, and therefore conductive, lining (there 41) in the or each contact hole (there Fig. 8), so that a hollow, electrically conductive structure is created in the or in each contact hole - Applying a passivation layer over the back of the substrate, which spans the hollow conductive structure to form an electrical via (this is disclosed by layer 18 therein);

[0019] Additionally, a passivation layer (61) is also deposited on the front side of the substrate.

[0020] EP 2 899 760 A1 as D6 makes the following available to the person skilled in the art (with reference numerals from this source) - The creation of a protective layer (9) over a component structure (16) that was created on and / or in a front face of the substrate (1) or consists there Fig. 1); - Forming at least one deep or long hollow cylindrical contact hole (14) for through-hole plating, which extends from a surface of the back of the substrate to a contact surface of the component structure (there Fig. 1); - The formation of a metal-containing, and therefore conductive, lining (15) in the or each contact hole (there Fig. 1) so that a hollow, electrically conductive structure is created in the or in each contact hole;

[0021] The application of a passivation layer (19) over the back side of the substrate, which can or could span the hollow conductive structure to form at least one electrical via, could be understood by the person skilled in the art from section

[023] and the description therein. Fig. 1 (it can be filled with further electrically conductive material and / or with a dielectric material, especially the material of the passivation layer 19). In connection with the one there Fig. 1. The person skilled in the art can or could conclude that the passivation layer spans the hollow conductive structure ... (and simultaneously fills it with the passivation layer).

[0022] That the passivation layer (19) is provided with openings (there Fig. 1) or a local structuring is carried out, adapted or suitable for subsequent coating with further metal layers and for the placement of solder balls (18) over the back of the substrate (1), the person skilled in the art can or could make the local structuring suitable for subsequent coating with further metal layers and for the placement of solder balls (18) over the back of the substrate (1). Fig. Remove 1.

[0023] The fabrication of a wiring structure (17) on the surface of the back side for connecting the via (4) to a solder ball structure (18), wherein the connection has a conductor track (17) is described therein. Fig. 1 revealed.

[0024] One object of the (claimed) invention is to create an electrical via at lower cost and with increased flexibility with regard to the micro-technical semiconductor structures to be connected via the via.

[0025] Claim 1 solves this problem.

[0026] The method comprises the production of a protective layer over a component structure that is produced on and / or in a front face of the substrate (if it is already present or exists, it was previously produced in accordance with the claimed method, hence the past tense in claim 1). Furthermore, at least one deep or long contact hole is formed, wherein the aspect ratio of the via is greater than or equal to eight, which is not directly and unambiguously apparent from EP 2 899 760 A1. The at least one contact hole according to the invention extends from a rear face of the substrate to a contact surface of the component structure. For example, after insulating the side wall of the contact hole, a metal-containing conductive lining is formed in the at least one claimed contact hole such that a hollow, conductive structure is created.A passivation layer is applied to the back surface of the substrate. This layer only covers the hollow, conductive structure without filling it. The passivation layer is either perforated or locally structured, and is adapted or suitable for subsequent coating with additional metal layers and for the placement of solder balls on the back surface of the substrate. A wiring structure is created on the back surface to connect the via to the solder ball structure, with the connection forming a conductive trace.

[0027] The method according to the invention is applicable to structures of at least one contact hole with very high aspect ratios. "Very high" means ratios of the depth (or length) of the contact hole to the diameter of the contact hole of up to 15:1 (or only 15), but at least greater than eight. In particular, the application of metal-organic chemical vapor deposition (MOCVD) offers the possibility of producing a thin conformal layer for the metal-containing material even under these extreme conditions.

[0028] The method according to the invention is extremely flexible with regard to the process technology used, for example, to manufacture the component structure, due to the selection of the point in time for the production of the via (after the component structure has already been manufactured). According to the invention, the via is therefore produced after the completion of a technology or semiconductor top surface, e.g., after a CMOS or MEMS process. For example, the method according to the invention is suitable for MEMS components with cover disks, since the cover disks for covering the mechanical structures (substrate) can be positioned without restriction due to the via.

[0029] However, contacts can also be created for assemblies, for example sensors with a typical disk thickness of 400µm, if a connection to glass substrates or directly to printed circuit boards is required.

[0030] The method according to the invention is also suitable for chip stacking and the integration of various technologies. While adhering to the design specifications, the position of the vertical via in the chip structure can be freely selected. Realizing the via using a lining that forms a hollow conductive structure, for example, a hollow cylinder, leads, on the one hand, to a corresponding cost reduction through more economical and effective use of raw material compared to completely filling the contact hole with the conductive material. On the other hand, the effects, which are particularly well-known for copper and are considered extremely problematic in conventional strategies—i.e., the plastic-elastic properties of copper—can be almost negligible due to the mere presence of a lining instead of a solid material.

[0031] The passivation layer, which spans the hollow conductive structure, allows these advantageous properties to be maintained with regard to plastic-elastic deformation during further processing and especially during the use of the component.

[0032] In a further advantageous embodiment, the step of forming a metal-containing lining in the contact hole comprises the following steps: applying a first metal-containing layer as a barrier and / or for adhesion, and applying a second, different metal-containing layer as a seed layer for a third metal-containing layer. The third metal-containing layer is electrolytically deposited onto the second layer, with the first and second layers being applied under vacuum and the vacuum being maintained continuously.

[0033] The inclusion of multiple metal-containing layers leads to the desired properties, for example with regard to adhesion to the side wall of the contact hole or with regard to possible barrier properties that prevent, for example, unwanted diffusion of critical metal atoms, e.g., copper atoms.

[0034] In this process, the first and second metal-containing layers are produced specifically or preferably without interrupting the vacuum, in particular using an in-situ process in which no intermediate steps, e.g. disk transport or any other change in the position of the disk, are required or at least greatly reduced.

[0035] Intermediate cleaning steps can typically be eliminated, resulting in a more reliable process flow due to a reduction in potential sources of interference. This also leads to cost and / or time savings by eliminating the need for these complex intermediate processes. Furthermore, avoiding interruptions to the vacuum conditions during the deposition of the first and second metal-containing layers significantly contributes to process quality.

[0036] In general, combining several deposition processes into a single process allows for the achievement of multiple objectives, such as barrier and adhesive layers, metallization of the contact hole in conjunction with metal deposition for a wiring layer, processes for passivation, and solder resist. This results in a streamlined, more efficient overall process flow, leading to time and / or cost reductions.

[0037] In further advantageous embodiments, the first and / or the second metal-containing layer is applied through a metal-organic chemical gas atmosphere.

[0038] Metal-organic vapor deposition (MEV) during the application of the second metal-containing layer, which serves as a seed layer, offers a significant advantage because, due to the properties of the MEV process, a continuous, reliably thin seed layer is created on all exposed surfaces. Potential irregularities in the sidewall topography, which can arise from the process and process variations during the creation of the contact hole and / or the deposition of an insulating layer, are compensated for.

[0039] These properties of metal-organic chemical vapor deposition (MED) are also advantageous when applying the first metal-containing layer, which serves as a barrier and / or adhesive layer, as reliable coverage of any irregularities on the respective sidewall is achieved. Therefore, the application of MED significantly improves flexibility and modularity when used later in the overall process, for example, after the semiconductor devices have been manufactured.

[0040] In a further advantageous embodiment, a wiring layer is produced on the back side of the substrate (its rear surface) during the formation of the metal-containing conductive lining. As mentioned previously, this allows for a significant increase in the efficiency of the entire manufacturing process, since additional, already necessary wiring layer(s) are integrated into the process of creating the via. This wiring layer includes the claimed conductor track, which connects the via to the solder ball structure, so that the solder ball structure is not located within the via.

[0041] In a further advantageous embodiment, surface wetting with preferably water takes place under vacuum conditions prior to the electrolytic deposition of the third metal-containing layer.

[0042] This vacuum pretreatment, which involves wetting the exposed surfaces, results in homogeneous wetting by the electrolyte for the deposition of the third metal-containing layer. In this way, continuous growth of the electrolytic layer and thus a reliable, conductive lining can be achieved without making the layer unnecessarily thick.

[0043] In another variant, a paint mask with negative paint is produced before the deposition of the third metal-containing layer to define positions for metal deposition.

[0044] The lacquer is applied over the contact hole in such a way that it is only covered but not filled, so that after the deposition of the third layer only very little lacquer material (as lacquer residue) has to be removed from the contact hole, which contributes to a shorter processing time and more efficient removal of material residue.

[0045] In a further advantageous embodiment, the highest process temperature occurring during the production of the via is less than 501°C.

[0046] By defining this maximum process temperature, a high degree of flexibility is achieved in its application to various types of component structures, as many process technologies used to manufacture the component structure are typically compatible with this temperature range. For example, if a CMOS process is used to fabricate the component structure prior to via plating, the selected temperature range for via plating ensures that this does not impose any restrictions on the manufacturing process of the component structure.

[0047] In a further training course, the metal-containing lining is heated in a non-corrosive atmosphere before the passivation layer is applied.

[0048] This bake-out process allows the metal-containing lining and other metal structures simultaneously produced on the back of the substrate to be stabilized before further processing, whereby, as explained above, the process temperature during bake-out is advantageously less than 501°C.

[0049] In further embodiments, the component structure is fabricated as a microelectronic structure and / or a micromechanical structure and / or an optical structure and / or an electrical structure or a microfluidic structure prior to the fabrication of the contact hole. This allows the versatility of the inventive method to be effectively utilized, as it is relatively independent of the previously applied process technology and the type of component structure to be produced. In particular, the process parameters for the fabrication of the via are selected such that an adjustment of the process technology to be applied for the component structure is not necessary with regard to the subsequent fabrication of the via.

[0050] In one variant, the substrate is provided as a stack of several interconnected support materials.

[0051] This makes it possible to apply the inventive method to three-dimensional structures in which two or more substrates, e.g. semiconductor substrates, are used, wherein the component structures produced on the respective support materials are independent of the production of the vias with regard to the process technology used and the type of component structure.

[0052] In a further embodiment, the component structure is shielded with respect to another component structure and / or mechanically or electrically decoupled by creating at least one further via between the component structure and another component structure; i.e., between two component structures.

[0053] Due to the high flexibility and efficient decoupling of the fabrication of the via according to the invention from the component type and process technology used to manufacture the component structures, the via can also be fabricated for the purposes of shielding and / or decoupling in substrates without having a significant impact on the preceding manufacturing processes for the component structure.

[0054] Due to a freely selectable lateral position of the via on or in the substrate and due to the favorable mechanical and thermal properties mentioned above, the vias according to the invention can be provided in a suitable number and with a suitable position to fulfill other tasks as well, e.g. thermal and mechanical tasks that do not require electrical connection to existing conductive structures.

[0055] Due to its design, the electrical via can provide high conductivity by incorporating a metal-containing lining, such as copper, a copper alloy, or the like, while simultaneously avoiding undesirable side effects associated with (fully) filled vias. These include the plastic-elastic properties found in many metals, which can contribute to significant stresses in other component layers, such as metallization layers, in conventional components. Furthermore, the hollow design of the via according to the invention allows for material savings, which in turn has a positive impact on manufacturing costs.

[0056] The insulating cover over the via on the back is designed to cover the hollow conductive structure. This ensures reliable protection of the electrical via during any subsequent processing and use, while maintaining its mechanical properties, i.e., minimal susceptibility to deformation of the metal material.

[0057] The diameter of an unfilled area of ​​the via is larger than one or two layer thicknesses of the lining. This measure ensures that the influence of any potential plastic-elastic deformation of the metal lining material remains small relative to the overall size of the via.

[0058] The thickness of the metal-containing lining is chosen to be advantageous so that, while achieving the desired conductivity, the contribution to a possible mechanical influence on other layer systems remains low, since corresponding deformations and the like within the via mainly act inwards and therefore hardly stress surrounding areas.

[0059] In a more illustrative embodiment, the micro-technical component includes two or more electrically conductive vias that are provided laterally adjacent to the component structure and are arranged as at least one shielding element and / or as at least one element for electrical or mechanical decoupling of the component structure with respect to another component structure.

[0060] Due to the potential space-saving design and the mechanically favorable properties, the vias produced using the method of the present invention can be advantageously used for many different purposes in a substrate material, e.g. to selectively influence thermal and mechanical properties, e.g. when stacking two or more substrates, to enable efficient electrical decoupling of a component structure and / or generally to provide shielding, which, for example, can be provided at suitable positions in relation to a component structure.

[0061] Due to its efficient structure and the extremely flexible method for its manufacture, the through-hole plating according to the invention can be used for many different component structures, support substrates or the like.

[0062] With reference to the accompanying drawings, illustrative embodiments are now described in more detail. Embodiments of the invention are presented by means of one or more examples and not in a way that transfers or reads limitations from the figures into the claims, even if the words "in particular," "e.g.," or "for example" are not explicitly used at every point. Identical reference numerals in the figures indicate similar elements. Fig. Figure 1 is a functional flow diagram of an example of a method according to the invention for producing an electrical via, also showing some optional steps. Fig. 2 is a cross-section of a substrate 3 with an electrical via 150 according to an example of the invention. Fig. 3 a top view of the surface of the back side 1 of the substrate 3 with an electrical via 150 and a wiring structure for connecting the via to a solder ball structure 13. Fig. Figure 4 is a cross-sectional view of a substrate 100 with several electrical vias (contact holes 14, 14'), a backside wiring layer and a circuit board 17 which is electrically connected to the backside wiring layer via solder balls 13, 13'.

[0063] These – and other – examples of implementation are described in more detail, initially alternating between Fig. 1 and Fig. 2 is referred to.

[0064] Fig. Figure 1 schematically illustrates an example process flow for the fabrication of a component structure followed by the fabrication of an electrical via. As shown, a complete front-side processor cycle 200 is executed first, in which the desired component structure, for example, a CMOS structure, a MEMS structure in conjunction with electronic components, etc., is fabricated. The necessary process technologies are used for this purpose, as previously described, without considering the subsequent fabrication of the via(s).

[0065] Fig. Figure 2 shows a cross-sectional view of a component 100, which is referred to as a micro-technical component. This term denotes that at least some structural elements, e.g., semiconductor elements, or the like, have dimensions of 10 µm or smaller. The term "micro-technical" component thus encompasses any component that carries component structures exhibiting a micro-mechanical, micro-electronic, opto-electronic, optical, and / or electrical function, or a micro-fluidic function, and possessing dimensions within the previously specified range. The micro-technical component 100 has a substrate 3, e.g., a semiconductor substrate, or any other substrate, which has a front side 2 and a back side 1.

[0066] Substrate 3 has a suitable thickness, approximately in the range of several hundred micrometers, as is typical for the production of, for example, microelectronic component structures.

[0067] As previously mentioned in relation to Fig. As explained in section 1, the production of a component structure 5 or 5' has already been completed, as shown in the drawing of the Fig. 2 is represented merely as a contact surface 5a, whereby it should be noted that further structural elements in addition to the contact or connection surface 5a can typically form an extremely complex component structure. The process technologies used for this depend on the component structure to be manufactured, which is also represented here by the reference numeral 5 or 5' in Fig. It should be labelled 4.

[0068] For example, in the illustrated embodiment, an insulating layer 6 is provided in conjunction with the connection surface 5a, which is thus also intended to be representative of other component structures.

[0069] Again with reference to Fig. The second step, described in section 1, involves the fabrication of a protective layer 4 on the front surface. This process can also be considered a section of the manufacturing process sequence 200. For example, a corresponding protective layer is produced as part of a CMOS process flow. The protective layer 4 is thus deposited over the entire front surface of the substrate 3 and prevents the already fabricated component structure 5 from being damaged by the subsequent manufacturing processes 300 to 400 for the electrical vias.

[0070] In other embodiments, the deposition of the protective layer 4 can also be applied at any other time before the further processes for the production of the via(s).

[0071] Regardless of whether the deposition of the protective layer 4 is considered part of the manufacturing process 202 or part of the process for producing the via, the process continues according to one embodiment by processing the back side 1 of the substrate 3. In some embodiments, this involves grinding the back side 1 to the specified target thickness (step 302) and smoothing it (step 303), which can be done using a spin-etching process.

[0072] A mask layer is then fabricated on the back side 1 (on the surface of the back side) made of a suitable material to resist the subsequent process of forming a contact hole 14. Typically, materials such as silicon dioxide, silicon nitride, a mixture thereof, or the like are used for this purpose, and these materials are typically referred to as a hard mask. Subsequently, a contact hole 14 is formed from the (top) back side 1 of the substrate 3 by deep reactive ion etching (DRIE), step 314, the etching typically being carried out in several stages and, in certain embodiments, resulting in flank angles of 90° ± 5°. This anisotropic etching is selectively performed such that it halts, for example, at and within the insulating layer 6 beneath the contact surface 5a of the component structure 5 fabricated on the front side 2.

[0073] In a further reactive ion etching process, the remaining section of the insulating layer 6 exposed in the contact hole 14 is removed from the bottom of the contact hole, so that the contact surface 5a is exposed there or becomes electrically accessible from the contact hole.

[0074] Fig. Figure 2 schematically shows a contact hole 14 that extends through the back side 1 of the substrate 3 to the front side 2 and is also formed through the insulating layer 6, thus being in contact with the connection surface 5a of the component structure 5.

[0075] Furthermore, the side wall of the contact hole 14 and the top of the back side 1 are covered with an insulating layer 7, step 316, which in an illustrative embodiment is made from oxide (TEOS) based on an ethyl ester, the tetraethyl orthosilicate also called tetraethoxysilane.

[0076] The fabrication can be carried out using conventional deposition processes, whereby – as explained above – process temperatures are selected to be compatible with the already fabricated component structures 5 or 5' on the front face 2. In advantageous embodiments, the maximum process temperature during the entire sequence for fabricating the via 150 with the contact hole 14 is kept below approximately 500°C (i.e., below 501°C to avoid the term "essentially").

[0077] The (inner) insulating layer 7 is then removed from the bottom of the contact hole 14, e.g., by reactive ion etching, so that material is preferably removed from the bottom of the contact hole 14 without unnecessarily removing material from the side walls of the contact holes. This exposes the contact surface 5a of each component structure again, enabling a conductive connection to the respective contact surface 5a, while ensuring reliable insulation of the side walls (their surfaces) from the substrate 3 and also from other structures that may be present on the back side 1. Certain properties of the via can also be adjusted by means of the insulating layer 7, e.g., the breakdown voltage or the leakage current.

[0078] Fig. Figure 2 further shows a first metal-containing layer 8, which, applied in step 318, lines the contact hole 14 and is also present on the surface of the back side 1. In one embodiment, the first metal-containing layer 8 is composed of titanium nitride with a thickness of a few nm to a few tens of nm, depending on the desired layer structure for the via 150.

[0079] In the illustrative embodiment, the first layer 8 serves as a barrier and adhesive layer, which on the one hand prevents unwanted diffusion of metal ions from a subsequently applied metal layer into adjacent areas and on the other hand ensures excellent adhesion of the subsequently applied metallic material.

[0080] The example shows a second metal-containing layer 9, which is applied to the first metal-containing layer 8 and has a suitable thickness to serve as a "seed layer," enabling a reliable subsequent electrolytic deposition process. In one embodiment, the second layer 9 contains copper if a layer to be deposited subsequently also contains copper. Depending on the desired material structure, other metal-containing materials can also be used as the seed layer 9.

[0081] In an advantageous embodiment, the two layers 8 and 9 are produced in an in-situ process sequence, wherein the sequence is carried out without interrupting the vacuum conditions in a process plant, thus minimizing the effort required for substrate handling and for cleaning the process plant between the individual deposition processes.

[0082] In a straightforward embodiment, the first layer 8 is deposited by a metal-organic chemical vapor deposition (MOCVD 1), forming a conformal thin layer of material that provides a reliable barrier against metal migration to adjacent areas. Furthermore, the application of metal-organic chemical vapor deposition enables excellent adhesion of layer 8 to the metal, thus ensuring, for example, sufficient stability and adhesion of the second layer 9, which serves as a seed layer for subsequent electrolytic deposition.

[0083] In an advantageous embodiment, a metal-organic chemical vapor deposition (MOCVD 2) is also used for the deposition of the second layer 9. Applied in step 320, this MOCVD lines the contact hole 14, thus achieving a conformal thin layer even for large aspect ratios of the contact hole 14. This seed layer 9 facilitates the growth of the subsequent electrolytically deposited metal layer 10. In alternative embodiments, physical vapor deposition (PVD) can be used instead of MOCVD.

[0084] The process parameters for the deposition of layer 8 and / or layer 9 can be selected, particularly when using MOCVD, to ensure that the desired surface properties are obtained and reliable coverage of sidewall irregularities is achieved, typically requiring a layer thickness of less than 100 nm for each layer.

[0085] Fig. Figure 2 further shows a third metal-containing layer 10, which is formed on the side walls and the bottom of the contact hole 14 as well as in defined areas on the surface of the back surface 1. The third metal-containing layer 10 is made of a highly conductive material, thus determining the essential conductivity of the lining 110 of the contact hole 14, which is formed from layers 8, 9, and 10. The via 150 therefore has a hollow conductive structure 110, i.e., formed within the contact hole 14 with layers 8, 9, and 10, which has an electrical connection to the contact surface 5a and thus to the corresponding component structure 5.

[0086] As further in Fig. As shown in Figure 2, layers 8, 9, 10 are also formed on other areas of the top of the back surface 1, so that this layer system also forms the basis for a wiring layer on the (top of the) back surface 1 of the substrate 3.

[0087] As with Fig. As described in Figure 1, the metal-containing third layer 10 is produced by first applying a mask layer (not shown) to the structure, exposing the areas where the material layer 10 is to be deposited. Such a mask layer can, for example, be created as a paint mask.

[0088] In an advantageous embodiment, the lacquer mask is produced from a negative lacquer to define the corresponding positions for the deposition of the highly conductive, metal-containing material. The lacquer mask is produced in such a way that the contact hole 14 is not filled, but rather partially covered. As a result, very little lacquer residue needs to be removed from the contact hole 14 after exposure to the lacquer, thus reducing the effort required for removing the lacquer mask and subsequent cleaning.

[0089] In another illustrative embodiment, the back side 1 of the substrate 3 and thus also the side walls and the bottom of the contact hole 14 are subjected to a vacuum treatment and wetting with a fluid, e.g. water, so that homogeneous wetting by the electrolyte is achieved for a subsequent electrolytic deposition.

[0090] The electrolytic deposition can, for example, be carried out as a current-controlled plating with step 330, where the previously deposited layer 9 serves as the current distribution layer. In this way, the material of layer 10 is reliably deposited within the contact hole 14 and on horizontal areas at the desired positions, thereby creating a hollow conductive structure represented by the contact hole 14, the conductivity of which is essentially determined by the material of layer 10.

[0091] If the contact hole 14 has an essentially round cross-sectional shape, i.e., in a section in the plane perpendicular to the drawing plane of the Fig. 2, thus essentially resulting in a hollow cylinder. However, it should be noted that, depending on the criteria to be met, the contact hole 14 can be adjusted, particularly during anisotropic etching through the substrate 3, by having corresponding flank angles or cross-sectional shapes. For example, bulged cross-sections or the like can be realized if this is considered advantageous for the general function of the via 150. In this way, the conformal deposition processes based on the previously described metal-organic chemical vapor deposition of layers 8 and 9 still achieve reliable coverage of the side wall of each contact hole 14 (two of them in the example).

[0092] In advantageous embodiments, the current-conducting electroplated material of layer 10 forms the structure for the entire backside wiring level 10a and 10b of the component 100, so that no additional deposition steps are required to provide a suitable contact structure on the backside surface.

[0093] How with Fig. 1 described and in Fig. 2 and Fig. As shown in Figure 3, in the illustrated embodiment a corresponding wiring level 10a and 10b is represented on the surface of the back side 1.

[0094] This wiring level is supplemented by a permanent passivation layer 11, which on the one hand covers the via 150, i.e. the contact hole 14 or the hollow conductive structure 110, without completely filling it, and on the other hand passivates the other areas, in particular the wiring level 10a and partially 10b produced at the same time as the via 150.

[0095] In the further steps for the production of the in Fig. The structure shown in section 2, as well as with Fig. Figure 1 shows the removal of the lacquer mask used for the electrolytic deposition of the material of layer 10. Known (common) lacquer removal processes can be applied, thereby exposing layers 8 and 9 on the back side 1. This material removal process from layers 8 and 9 can optionally be carried out without a mask, since the layer thickness of layers 8 and 9 is very small compared to the thickness of layer 10, which serves as a mask in the illustrated embodiment. In other embodiments, an additional lacquer mask can be produced before etching layers 8 and 9, if required.

[0096] Following appropriate structuring or isolation of the metal structures in step 340 on the back side by etching the barrier and adhesion layer 8 and the seed layer 9 in conjunction with optional cleaning steps, a bake-out process is carried out in a non-corrosive gas atmosphere to stabilize the metal layer 10, in illustrative embodiments, wherein the process temperature is less than 501°C, as previously described.

[0097] In a further embodiment, the passivation layer 11 is applied in step 350, wherein one or more suitable materials are deposited by processes known per se. The process parameters are defined such that the via 150 is merely covered without or without significant material input into the contact hole 14, so that the contact hole 14 or the hollow conductive structure 110 of the via 150 is spanned.

[0098] In the passivation layer 11, openings are created at the corresponding positions, for example at the position of the solder ball 13, by masking steps, whereupon an “undermetallization” 12 is deposited in step 355. For example, a nickel / gold material can be applied to a desired thickness using electroless electrolytic deposition to produce the undermetallization 12 of the solder ball 13.

[0099] The selection of materials for the sub-metallization 12, as well as the number of sub-layers for the sub-metallization 12, can vary depending on design criteria or the like. Subsequently, the material for the solder ball 13 is applied in step 360, either using a mask or without one, followed by melting to obtain the desired shape of the solder ball(s) 13.

[0100] This completes the process of creating the wiring plane and via 150 with step 400.

[0101] How to Fig. As outlined in section 1, further processes 500 may now follow for the processing of the component 100.

[0102] Fig. Figure 3 schematically shows a top view of the back side 1, wherein the via 150 is electrically connected to the hollow conductive structure 110 in the contact hole 14 by means of the third metal-containing layer 10 and the non-visible layers 8, 9 with the solder ball 13.

[0103] In the figure, this connection is represented as a conductor track 10a. As explained previously, the corresponding conductor tracks 10a can be produced as desired as part of the electrolytic deposition for the lining of the contact hole 14 for the via 150, in order to form the wiring layer(s) on the back side.

[0104] It should be noted that not every via 150 is necessarily connected to a corresponding solder ball.

[0105] For example, several vias 150 can be provided at suitable positions, so that, for example, shielding of sensitive areas in and on the substrate 3, mechanical decoupling of certain substrate areas and / or thermal coupling to possible heat sinks, and / or electrical decoupling, etc., is achieved.

[0106] In particular, the compact design and the relative independence of process technologies used to manufacture the component structures make it possible to select the positions of the vias 150 with and without electrical connection to a corresponding contact surface 5a on the front and / or an electrical connection to a contact point, e.g. a solder ball 13, on the back.

[0107] Fig. Figure 4 schematically shows a cross-sectional view in which the component 100 has vias 150, 150' which have hollow, conductive structures 110 in the contact holes 14, 14' and are arranged to be connected to and / or located near a component structure 5 or 5' to fulfill a corresponding function, e.g., an electrical connection, a mechanical connection, shielding, or the like. One or more of the vias 150, 150' can be connected to one or more solder balls 13, 13', as specified by the design rules.

[0108] A printed circuit board 17 has suitable contact points 16, 16' which are electrically connected to the corresponding solder balls 13 and 13' respectively, with passivation 15 being provided on the printed circuit board 17 (on the side of the solder balls). The joining of the printed circuit board 17 to the at least one component 100 (also called a chip) can be accomplished by soldering or other contact methods. The "suitable" contact points 16 are such that they allow a spatially and geometrically appropriate docking to the solder balls (so-called "bumps") in order to establish conductive contact(s) with the printed circuit board 17.

[0109] The examples of the invention thus provide methods and components in which a through-hole plating is produced based on a process sequence that is not specifically tailored to manufacturing technologies for semiconductor devices.

[0110] The relevant components, in the form of mechanical, electrical, optoelectronic, and / or optical components, are therefore fully processed before the actual fabrication of the via begins. By appropriately selecting process parameters, particularly with regard to the maximum process temperature encountered during via fabrication, a high degree of flexibility is achieved with respect to the preceding process technologies.

[0111] In particular, a highly conductive material is used to line a contact hole for through-hole plating, creating at least a hollow conductive structure that is significantly less susceptible to the problem of plastic-elastic deformation, as is known, for example, for fully or nearly fully filled copper through-hole plating. This also results in a high degree of material savings.

[0112] In advantageous embodiments, in particular some layers of the conductive lining are produced by a metal-organic gas phase in an in-situ process, resulting in a high degree of reliability in the processing as well as in the production of a thin but opaque material layer as a basis for the subsequent deposition of the actual conductive material.

Claims

[1] Method for manufacturing a micro-technical component (100) with a substrate (3) as a semiconductor substrate, which has a front (2) and a back (1) and with at least one electrical via (150, 150') in the substrate (3), the method comprising the following steps ... - Producing a protective layer (4) over a component structure (5) that is produced on and / or in a front face (2) of the substrate (3); - Forming at least one deep or long, hollow cylindrical contact hole (14,14') to form the at least one via (150), wherein the aspect ratio of the at least one via is greater than or equal to eight and extends from a surface of the back side (1) of the substrate to a contact surface (5a) of the component structure (5); - Forming a metal-containing and therefore conductive lining (8,9,10) in the or each deep or long contact hole (14,14'), so that a hollow, electrically conductive structure (110) is formed in the or each contact hole (14,14'); - Application of a passivation layer (11) over the back of the substrate (3), which spans the hollow conductive structure to form at least one electrical via (150,150'); wherein the passivation layer (11) is provided with openings or a local structuring takes place, adapted or suitable for subsequent coating with further metal layers (12) and for the placement of solder balls (13) over the back (1) of the substrate (3); and with the fabrication of a wiring structure (10a, 10b) on the surface of the back side for connecting the via (150) to a solder ball structure (13), wherein the connection is a conductor track (10a) exhibits; wherein the spanning of the hollow conductive structure by the passivation layer (11) is carried out and the process parameters during manufacturing are set in such a way that the vias (150) are covered without or without significant material input into the contact holes (14), thereby spanning them, in particular the hollow conductive structures (110). [2] The method of claim 1, wherein forming a metal-containing lining in the contact hole comprises ... - Application of a first metal-containing layer (8) as a barrier layer and / or as an adhesive layer; - Application of a second metal-containing layer (9) that differs from the first metal-containing layer as a seed layer for a third metal-containing layer (10) which is electrolytically deposited on the second metal-containing layer, wherein the first and the second metal-containing layer are applied under vacuum and the vacuum is maintained without interruption at least during the application. [3] Method according to claim 2, wherein at least the second metal-containing layer (9) is applied by means of a metal-organic chemical gas atmosphere. [4] Method according to claim 3, wherein the first metal-containing layer (8) is applied by a metal-organic chemical gas phase. [5] Method according to one of the preceding claims, wherein the wiring structure (10a, 10b) is produced on the surface of the back of the substrate (3) during the formation of the metal-containing lining, with which lining the electrically conductive structure (110) is formed. [6] Method according to claim 2, wherein prior to the electrolytic deposition of the third metal-containing layer (10) a surface wetting with a fluid is carried out under vacuum conditions, in particular with water. [7] Method according to claim 2, wherein a negative lacquer mask is produced to define positions for metal deposition prior to the deposition of the third metal-containing layer (10). [8] Method according to any of the preceding claims, wherein the highest process temperature occurring during the production of the via (150) is less than 501°C. [9] Method according to one of the preceding claims, wherein the metal-containing lining (8,9,10) is heated in a non-corrosive atmosphere before the passivation layer (11) is applied. [10] Method according to one of the preceding claims, wherein the component structure (5) is produced as part of a special structure prior to the production of the respective associated contact hole (14) and the special structure is one of the following structures: a micro-electronic structure, a micro-mechanical structure, an optical structure, an electrical structure, a micro-fluidic structure. [11] Method according to one of the preceding claims, wherein the substrate (3) is provided as a stack of several interconnected support materials. [12] Method according to one of the preceding claims, wherein the component structure (5) is shielded from a further component structure and / or mechanically or electrically decoupled by producing at least one further hollow, conductive or conductive structure (110) as a via (150) with a conductively lined contact hole (14) laterally between the component structure and the further component structure. [13] Method according to claim 1, wherein the melting of the solder balls (13,13') is carried out and adapted in such a way that subsequent mechanical and electrical joining of the substrate (3) or a finished chip (100) with a printed circuit board (17) is possible, in particular the solder balls dock spatially and geometrically appropriately at contact points (16,16') of a printed circuit board (17) in order to establish conductive contact(s) to the printed circuit board. [14] Method according to claim 1, wherein the formation of the at least one contact hole (14,14') is followed by the formation of an insulating layer on the back side (1) of the semiconductor substrate, which completely lines the contact hole (14) and is locally located at or away from the contact surface (5a). [15] Method according to one of the preceding claims, wherein several contact holes (14,14') or vias (150) are formed spaced apart from each other in the substrate (3).

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