Method for manufacturing a semiconductor device

Abstract

Procedure, comprehensive: Formation of a first fin (52) and a second fin (52) on a substrate Training a dummy gate material (58, 70) over the first fin and the second fin (52); Forming gatespacers (86) adjacent to the dummy gate material (58, 70) over the first fin (52) and the second fin (52); Forming a recess (94) in the dummy gate material between the first fin and the second fin; Formation of a sacrificial oxide (96) on side walls of the dummy gate material in the recess; Pouring an insulating material (98) between the sacrificial oxide on the side walls of the dummy gate material in the recess; Removal of the dummy gate material and sacrificial oxide; and Forming a first replacement gate (102, 104) above the first fin and a second replacement gate above the second fin; the formation of the recess (94) in the dummy gate material (58, 70) includes: Forming the recess (94) having a first width (W2) near each of the gatespacers (86) in a top view and a second width (W1) far from the gatespacers (86) in a top view, wherein the first width is greater than the second width.

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by structuring the various material layers using lithography and etching processes to form circuit components and elements.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, as minimum feature sizes are reduced, additional problems arise within each of the processes used, and these additional problems need to be addressed.

[0003] US 2016 / 0 181 425 A1 relates to a method for manufacturing a semiconductor device comprising a substrate with a plurality of active regions and a plurality of gate electrodes extending in a first direction to cut a section of the plurality of active regions, and first and second gate electrodes arranged such that they are adjacent to each other in the first direction, and a gate insulation section located between the first and second gate electrodes.

[0004] US 2016 / 0204215A1 relates to a Fin-FET semiconductor device with a rib structure extending in a first direction and formed on an insulating layer. The Fin-FET device also includes a gate stack comprising a gate electrode layer, a dielectric gate layer, sidewall insulating layers arranged on both sides of the gate electrode layer, and dielectric intermediates arranged on both sides of the sidewall insulating layers.

[0005] US 2016 / 0336320A1 concerns a semiconductor device comprising a first-ribbed FET having a first-rib structure extending in a first direction, a first-gate electrode formed above the first-rib structure, and a first-gate electrode formed above the first-gate electrode extending in a second direction perpendicular to the first direction. Brief description of the drawings

[0006] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Rather, the dimensions of the various features may have been enlarged or reduced as appropriate for clarity of discussion. Fig. Figure 1 shows an example of a FinFET in a three-dimensional view. Fig. Figures 2A to 19C are cross-sectional and top views of intermediate stages in the fabrication of FinFETs according to some embodiments. Detailed description

[0007] The invention is defined according to the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0009] A method for forming a semiconductor device is provided according to various embodiments. In particular, an isolation region is formed between adjacent gates of FinFET devices. The FinFET devices are formed in a gate-last process, with dummy gates made of polysilicon being formed in an intermediate fabrication step. A recess is formed in the dummy gates between adjacent fins, and exposed sidewalls of the dummy gates are oxidized to form a sacrificial oxide. The recess is filled with an insulating material that forms the isolation region. The dummy gates and the sacrificial oxide are removed and replaced by metal gates. Forming the sacrificial oxide after forming the isolation region but before forming the metal gates increases the gap fill distance between the isolation region and the metal gates.Therefore, the formation of cavities and pits between the insulation area and the metal gates can be reduced when the metal gates are formed.

[0010] Fig. Figure 1 shows an example of a FinFET in a three-dimensional view. The FinFET comprises a fin 56 on a substrate 50. The substrate 50 includes insulation regions 54, and the fin 56 projects above these regions and from the space between adjacent insulation regions 54. A gate dielectric 102 is located along side walls and over a top surface of the fin 56, and a gate electrode 104 is located above the gate dielectric 102. Source / drain regions 82 are arranged on opposite sides of the fin 56 with respect to the gate dielectric 102 and the gate electrode 104. Fig. Figure 1 further shows reference cross-sections and lines that will be used in later figures. A cross-section AA runs over a channel, the gate dielectric 102, and the gate electrode 104 of the FinFET. A cross-section BB is perpendicular to cross-section AA and runs along a longitudinal axis of the fin 56 and, for example, in a direction of current flow between the source / drain regions 82. Subsequent figures refer to these reference cross-sections for clarity.

[0011] Fig. Figures 2 to 5 are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2 to 5 are along the cross-section AA of Fig. 1 shown, with the exception of multiple FinFETs.

[0012] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, an SOI substrate (semiconductor on an insulator), or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon, germanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof.

[0013] The substrate 50 has a first region 50B and a second region 50C. The first region 50B can be used to form n-channel devices, such as n-channel metal-oxide-semiconductor field-effect transistors (NMOS field-effect transistors), e.g., n-channel FinFETs. The second region 50C can be used to form p-channel devices, such as p-channel metal-oxide-semiconductor field-effect transistors (PMOS field-effect transistors), e.g., p-channel FinFETs. In some embodiments, both the first region 50B and the second region 50C are used to form the same type of device, with, for example, both regions being used for n-channel devices or p-channel devices.

[0014] In Fig. 3. Fins 52 are formed in the substrate 50. The fins 52 are semiconductor bridges. In some embodiments, the fins 52 can be formed in the substrate 50 by etching grooves in the substrate 50. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The fins 52 can have parallel longitudinal axes.

[0015] In Fig. 4. An insulating material 54 is formed between adjacent fins 52 to create the insulating regions 54. The insulating material 54 can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by chemical vapor deposition using high-density plasma (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by curing to transform it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable process can be used. In the illustrated embodiment, the insulating material 54 is silicon dioxide formed by an FCVD process. A curing process can be performed after the insulating material is formed.The insulation material 54 can be referred to as isolation areas 54. Furthermore, it can be found in... Fig. 4 a planarization process, such as chemical-mechanical polishing (CMP), remove any excess insulation material 54 and form upper surfaces of the insulation areas 54 and upper surfaces of the fins 52 that are on the same plane.

[0016] In Fig. In step 5, the isolation regions 54 are recessed to form STI (Shallow Trench Isolation) regions 54. The isolation regions 54 are recessed such that the fins 56 in the first region 50B and in the second region 50C protrude from the space between adjacent isolation regions 54. Furthermore, the upper surfaces of the isolation regions 54 can have a flat surface, as shown, a convex surface, a concave surface (such as a bulge), or a combination thereof. The upper surfaces of the isolation regions 54 can be formed flat, convex, and / or concave by means of a suitable etching process. The isolation regions 54 can be recessed using a suitable etching process, such as one that is selective with respect to the material of the isolation regions 54.For example, chemical oxide removal can be performed using a CERTAS® etching or an Applied Materials SICONI tool or dilute hydrofluoric acid (dHF).

[0017] An average professional will easily understand that the one in relation to Fig. The process described in sections 2 to 5 is merely an example of how the fins 56 can be formed. In some embodiments, a dielectric layer can be formed over an upper surface of the substrate 50; trenches can be etched through the dielectric layer; homoepitaxic structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxic structures protrude from the dielectric layer to form fins. In some embodiments, heteroepitaxic structures can be used for the fins 52. For example, the fins 52 can be formed in Fig. 4. The substrate can be left uncut, and a material different from the fins 52 can be epitaxially grown instead. In a further embodiment, a dielectric layer can be formed over a top surface of the substrate 50; trenches can be etched through the dielectric layer; heteroepitaxic structures can be epitaxially grown in the trenches using a material different from the substrate 50; and the dielectric layer can be left uncut such that the heteroepitaxic structures protrude from the dielectric layer to form the fins 56. In some embodiments where homoepitaxic or heteroepitaxic structures are epitaxially grown, the grown materials can be doped in situ during growth, which can avoid prior and subsequent implantations, although in-situ and implantation doping can be used together.It can be even more advantageous to grow a material in an NMOS region that differs from the material in a PMOS region. In various embodiments, the fins 56 can be made of silicon germanium (Si. x Ge 1-x , where x can be between approximately 0 and 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0018] Furthermore, in Fig. Five suitable troughs (not shown) are formed in the fins 56, the fins 52, and / or the substrate 50. In some embodiments, a p-trough can be formed in the first region 50B, and an n-trough can be formed in the second region 50C. In some embodiments, a p-trough or an n-trough is formed in both the first region 50B and the second region 50C.

[0019] In embodiments with different well types, the various implantation steps for the first region 50B and the second region 50C can be achieved using a photoresist or other masks (not shown). For example, a photoresist can be formed over the fins 56 and the isolation regions 54 in the first region 50B. The photoresist is textured to expose the second region 50C of the substrate 50, such as a PMOS region. The photoresist can be formed using a rotational coating technique and can be textured using suitable photolithographic techniques. After the photoresist has been textured, n-type impurity implantation is performed in the second region 50C, and the photoresist can act as a mask to essentially prevent n-type impurities from being implanted into the first region 50B, such as an NMOS region.The n-type impurities can be phosphorus, arsenic, or the like, which enter the first area up to a concentration of less than or equal to 10. 18 cm -3 , such as between approximately 10 17 cm -3 and approximately 10 18 cm -3 , are implanted. After implantation, the photoresist is removed, e.g. using a suitable ashing process.

[0020] Following the implantation of the second region 50C, a photoresist is formed over the fins 56 and the isolation regions 54 in the second region 50C. The photoresist is patterned to expose the first region 50B of the substrate 50, such as the NMOS region. The photoresist can be formed using a rotary coating technique and can be patterned using suitable photolithographic techniques. After the photoresist has been patterned, p-type impurity implantation can be performed in the first region 50B, and the photoresist can be used as a mask to essentially prevent p-type impurities from being implanted into the second region 50C, such as the PMOS region. The p-type impurities can be boron, BF2, or the like, which are implanted into the first region to a concentration of less than or equal to 10 18 cm -3 , such as between approximately 10 17 cm -3and approximately 10 18 cm -3 , are implanted. After implantation, the photoresist can be removed, e.g. using a suitable ashing process.

[0021] Following the implantation of the first region 50B and the second region 50C, a curing procedure can be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the grown materials can be doped in situ by epitaxial fins during growth, thus avoiding the need for implantation, although in situ and implantation doping can be used together.

[0022] Fig. Figures 6A to 19C are cross-sectional and top views of further intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. Figures 6A to 19C ending with an "A" designation are located along cross-section AA of Fig. Figure 1 is shown, with the exception of multiple FinFETs. Figures ending with a "B" designation are shown along the cross-section BB of Fig. Figure 1 shows FinFETs in either the first area 50B or the second area 50C. Figures ending with a "C" designation are top views shown relative to corresponding CC lines shown in the cross-sectional views.

[0023] In Fig. 6A and Fig. In 6B, a dielectric dummy layer 58 is formed on the fins 56. The dielectric dummy layer 58 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable techniques. In some embodiments, the dielectric dummy layer 58 is formed conformally over the fins 56 and the insulation regions 54. In some embodiments (not shown), the dielectric dummy layer 58 is formed only on the upper surface and the side walls of the fins 56 and is not formed over the insulation regions 54.

[0024] Further information will be provided in Fig. 6A and Fig. 6B A dummy gate layer 60 is formed over the dielectric dummy layer 58. The dummy gate layer 60 can be deposited over the dielectric dummy layer 58 and then planarized, for example, using a CMP. The dummy gate layer 60 can be a conductive material and can be selected from a group comprising polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The dummy gate layer 60 can be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques known in the prior art and used for depositing conductive materials.The dummy gate layer 60 can be made from other materials that exhibit high etch selectivity with respect to etching isolation regions.

[0025] Further information will be provided in Fig. 6A and Fig. 6B A mask layer 62 is formed over the dummy gate layer 60. The mask layer 62 can be deposited over the dummy gate layer 60. The mask layer 62 can be formed from a dielectric and can, for example, comprise SiN, SiON, or the like.

[0026] In this example, a single dummy gate layer 60 and a single mask layer 62 are formed over the first region 50B and the second region 50C. In some embodiments, separate dummy gate layers and separate mask layers can be formed in the first region 50B and the second region 50C.

[0027] In Fig. 7A and Fig. 7B The mask layer 62 can be structured using suitable photolithographic and etching techniques to form masks 72. The structure of the masks 72 can then be transferred to the dummy gate layer 60 and the dielectric dummy layer 58 using a suitable etching technique to form dummy gates 70. The dummy gates 70 cover respective channel regions of the fins 56. The dummy gates 70 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of corresponding epitaxial fins.

[0028] Furthermore, in Fig. 7A and Fig. 7B Gate sealing spacers 80 are formed on exposed surfaces of the dummy gates 70, the masks 72 and / or the fins 56. The gate sealing spacers 80 can be formed by thermal oxidation or deposition followed by anisotropic etching.

[0029] After forming the gate sealing spacers 80, implantations for weakly doped source / drain regions (LDDs) (not shown) can be performed. In embodiments with different device types, similar to the above described Fig. 4A and Fig. As discussed in Section 4B, a mask, such as a photoresist, can be formed over the first region while the second region 50C is exposed, and impurities of a suitable type (e.g., n-type or p-type) can be implanted into the exposed fins 56 in the second region 50C. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed above, and the p-type impurities can be any of the p-type impurities discussed above. The lightly doped source / drain regions can have an impurity concentration of approximately 10 15 cm -3up to about 10 16 cm -3 exhibit. A healing process can be used to activate the implanted impurities.

[0030] In Fig. 8A and Fig. In embodiment 8B, epitaxial source / drain regions 82 are formed in the fins 56. The epitaxial source / drain regions 82 are formed in the fins 56 such that each dummy gate 70 is arranged between respective adjacent pairs of the epitaxial source / drain regions 82. In some embodiments, these epitaxial source / drain regions 82 can extend into the fins 52.

[0031] The epitaxial source / drain regions 82 in the first region 50B, e.g., the NMOS region, can be formed by masking the second region 50C, e.g., the PMOS region, and conformally depositing a dummy spacer layer in the first region 50B. This is followed by anisotropic etching to form dummy gate spacers (not shown) along the sidewalls of the dummy gates 70 and / or gate sealing spacers 80 in the first region 50B. Source / drain regions of the epitaxial fins are then etched in the first region 50B to form recesses. The epitaxial source / drain regions 82 in the first region 50B are epitaxially grown in these recesses. The epitaxial source / drain regions 82 can comprise any suitable material, e.g., one suitable for n-channel FinFETs. For example, if the fin is silicon 56, the epitaxial source / drain regions can comprise silicon 82, SiC, SiCP, SiP or the like.The epitaxial source / drain regions 82 may have surfaces raised from the respective surfaces of the fins 56 and may have rhombic surfaces. Subsequently, the dummy gatespacers in the first region 50B are removed, for example, by etching, just like the mask in the second region 50C.

[0032] The epitaxial source / drain regions 82 in the second region 50C, e.g., the PMOS region, can be formed by masking the first region 50B, e.g., the NMOS region, and conformally depositing a dummy spacer layer in the second region 50C. This is followed by anisotropic etching to form dummy gate spacers (not shown) along the sidewalls of the dummy gates 70 and / or gate sealing spacers 80 in the second region 50C. Source / drain regions of the epitaxial fins are then etched in the second region 50C to form recesses. The epitaxial source / drain regions 82 in the second region 50C are epitaxially grown in these recesses. The epitaxial source / drain regions 82 can comprise any suitable material, e.g., one suitable for p-channel FinFETs. For example, if the fin is silicon 56, the epitaxial source / drain regions can include SiGe, SiGeB, Ge, GeSn or the like.The epitaxial source / drain regions 82 may have surfaces raised from the respective surfaces of the fins 56 and may have rhombic surfaces. Subsequently, the dummy gatespacers in the second region 50C are removed, for example, by etching, just like the mask on the first region 50B.

[0033] In Fig. 9A and Fig. 9B Gatespacers 86 are formed on the gate sealing spacers 80 along the sidewalls of the dummy gates 70 and the masks 72. The gatespacers 86 can be formed by conformal deposition of a material and subsequent anisotropic etching of the material. The material of the gatespacers 86 can be a dielectric material, such as silicon nitride, SiCN, a combination thereof, or the like.

[0034] Dopants can be implanted into the epitaxial source / drain regions 82 and / or the epitaxial fins to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, which is followed by healing. The source / drain regions can have a contamination concentration of between approximately 10 19 cm -3 and approximately 10 21 cm -3 exhibit. The n-type and p-type impurities for source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0035] In Fig. 10A and Fig. 10B will have an ILD 88 above the one in Fig. 9A and Fig. The structure shown in Figure 9B is deposited. The ILD 88 can be formed from a dielectric material or a semiconductor material and can be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Semiconductor materials can be amorphous silicon, silicon germanium (Si), or silicon dioxide (Si). x Ge 1-x , where x can be between approximately 0 and approximately 1), include pure germanium or the like. Other insulating and semiconductor materials formed by any suitable process may be used.

[0036] In Fig. 11A and Fig. 11B A planarization process, such as a CMP, can be performed to flatten the top surface of ILD 88 with the top surfaces of the dummy gates 70. The planarization process can also remove the masks 72 on the dummy gates 70 and sections of the gate sealing spacers 80 and gate spacers 86. After the planarization process, the top surfaces of the dummy gates 70, the gate sealing spacers 80, the gate spacers 86, and the ILD 88 are on the same plane. Accordingly, the top surfaces of the dummy gates 70 are exposed by the ILD 88.

[0037] In Fig. 12A and Fig. 12B will be a mask layer 90, such as a hard mask, over which in Fig. 11A and Fig. The structure shown in Figure 11B is deposited. The mask layer 90 can be made of SiN, SiON, SiO2, the like, or a combination thereof. The mask layer 90 can be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on dielectric process, the like, or a combination thereof.

[0038] In Fig. 13A and Fig. In 13B, a photoresist 92 is formed and structured over the mask layer 90. In some embodiments, the photoresist 92 can be formed using a rotary coating technique and can be structured using suitable photolithographic techniques. After the photoresist 92 has been structured, a trimming process can be performed on the photoresist 92 to reduce the width of the structured photoresist 92. In one embodiment, the trimming process is an anisotropic plasma etching process, wherein process gases include O2, CO2, N2 / H2, H2, the like, a combination thereof, or any other gases suitable for trimming photoresist.

[0039] In some embodiments, the photoresist 92 is a three-layer photoresist. In these embodiments, the three-layer photoresist 92 comprises an upper photoresist layer, a middle layer, and a lower layer. Since the limits of photolithographic processes have been reached by advanced semiconductor manufacturing processes, there is a need for thinner upper photoresist layers to achieve smaller process windows. However, thin upper photoresist layers may not be sufficiently robust to support the etching of target layers (e.g., the mask layer 90). The three-layer photoresist provides a relatively thin upper photoresist layer. The middle layer can include antireflective materials (e.g., a BARC (backside anti-reflective coating) layer) to aid in the exposure and focus of the processing of the upper photoresist layer.By including the middle layer, the thin upper photoresist layer is used solely for structuring the middle layer. The lower layer can comprise a hard mask material, such as a carbon-containing material, which is easily removed using O₂ or an N₂ / H₂ plasma. The middle layer is used to structure the lower layer. In some embodiments, the middle layer exhibits high etch selectivity with respect to the lower layer, and in some embodiments, the lower layer is more than ten times thicker than the middle layer. Therefore, the three-layer photoresist 92 enables the robust structuring of underlying layers (e.g., the mask layer 90) while still providing a comparatively thin upper photoresist layer.

[0040] The top photoresist layer of the three-layer photoresist 92 can be patterned using any suitable photolithographic technique. For example, a photomask (not shown) can be placed over the top photoresist layer, which is then exposed to a radiation beam including ultraviolet (UV) radiation or an excimer laser, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser. Exposure of the top photoresist layer can be performed using an immersion lithography system to increase resolution and reduce the minimum achievable pitch.A baking or curing process can be performed to harden the top photoresist layer, and a developer can be used to remove either the exposed or the unexposed portions of the top photoresist layer, depending on whether a positive or negative photoresist is used. After structuring the top photoresist layer of the three-layer photoresist 92, a trimming process can be performed to reduce the width of the top photoresist layer of the three-layer photoresist 92. In one embodiment, the trimming process is an anisotropic plasma etching process, wherein process gases include O2, CO2, N2 / H2, H2, the like, a combination thereof, or any other gases suitable for trimming photoresist. After the trimming process, the middle and bottom layers can be structured, thereby reducing the thickness of the top photoresist layer. Fig. 13A and Fig. The structured three-layer photoresist shown in 13B remains.

[0041] In Fig. 14A, Fig. 14B and Fig. In 14C, the mask layer 90 and the dummy gates 70 are structured using the photoresist 92 as a mask. The structuring of the mask layer 90 can be carried out using any suitable etching process, such as an anisotropic dry etching process. The etching process can be continued to structure the dummy gates 70. In some embodiments, sections of the dielectric dummy layer 58 can also be removed by the etching process. The structuring forms openings 94 that separate the fins 56 in the first region 50B from the fins 56 in the second region 50C. Upper surfaces of the insulating regions 54 can be exposed through the openings 94. The photoresist 92 is then removed.

[0042] The openings 94 are defined by the exposed surfaces of the insulation areas 54, the side walls 70S of the remaining sections of the dummy gates 70, and the inner surfaces of the gatespacers 86. In some embodiments, the side walls 70S of the remaining dummy gates 70 are inclined with respect to a principal surface of the substrate 50. In other words, the side walls 70S of the remaining sections of the dummy gates 70 are neither parallel nor perpendicular to the principal surface of the substrate 50. Specifically, the side walls 70S of the remaining sections of the dummy gates 70 form an angle θ1 with a plane parallel to the principal surface of the substrate 50. In one embodiment, the angle θ1 is greater than approximately 90°, for example, in a range of approximately 92° to approximately 97°. Furthermore, when measured in a direction perpendicular to the longitudinal axes of the fins 56, the openings 94 are narrower at their interfaces with the isolation areas 54 (e.g.The underside of the openings 94 is wider than their upper side, so that the openings 94 taper from the top to the underside. Furthermore, the openings 94 have a dumbbell shape in a top view. Consequently, a first width W1 of the openings 94 in a central section far from the gatespacers 86 is smaller than a second width W2 of the openings 94 in a peripheral section near the gatespacers 86.

[0043] In Fig. 15A, Fig. 15B and Fig. At 15°C, a sacrificial oxide 96 is formed on exposed sidewalls of the dummy gates 70 in the openings 94. The sacrificial oxide 96 is an oxide of the dummy gate material 70 and can be, for example, a native oxide, a plasma oxide, or the like. The sacrificial oxide 96 can be similar to the dielectric dummy layer 58 or it can be different. The sacrificial oxide 96 can be formed using an oxidation process, such as a thermal oxidation process, an RTO process (rapid thermal oxidation), a chemical oxidation process, an ISSG process (in-situ stream generation), or an EISSG process (enhanced in-situ stream generation). For example, rapid thermal oxidation (RTA) can be carried out in an oxygen-containing environment. Thermal oxidation can be carried out at a temperature of approximately 800°C to approximately 1100°C, such as approximately 800°C.The temperature can contribute to the thickness of the sacrificial oxide 96; higher temperatures can lead to a thicker sacrificial oxide 96. The thermal oxidation can be carried out for a period of time from approximately 10 seconds to approximately 20 seconds, such as approximately 15 seconds. The duration can also contribute to the thickness of the sacrificial oxide 96; longer oxidation periods can lead to a thicker sacrificial oxide 96. Upon completion, the thermal oxidation can form the sacrificial oxide 96 to a thickness of approximately 2.8 nm (28 Å) to approximately 5.6 nm (56 Å), such as approximately 4 nm (40 Å). In some embodiments, other oxidation processes can be carried out. The oxidation process can oxidize only the material of the dummy gates 70, so that the sacrificial oxide 96 is formed only on the sidewalls of the dummy gates 70 and not on the mask layer 90.

[0044] In Fig. 16A, Fig. 16B and Fig. In section 16C, an insulating material is formed in the openings 94 to create insulating regions 98. The insulating regions 98 provide insulation between the dummy gates 70 in the first region 50B and the dummy gates 70 in the second region 50C. The insulating region can be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and can be formed by HDP-CVD, FCVD (e.g., CVD-based material deposition in a remote plasma system followed by curing to convert it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable process can be used. The insulating material of the insulating regions 98 can be the same as, or different from, the insulating material 54. In the illustrated embodiment, the insulating material is silicon nitride.After formation, the insulating regions 98 are arranged between the sacrificial oxides 96, which are formed on the respective side walls of the openings 94. In embodiments in which the insulating regions 98 are formed from SiN, the structure formed in the openings 94 can be described as an oxide-SiN-oxide sandwich structure, or more generally as an oxide-nitride-oxide sandwich structure.

[0045] The shape of the isolation areas 98 is defined by the openings 94, e.g., the exposed surfaces of the isolation areas 54, the exposed side walls of the dummy gates 70, and the exposed side walls of the gatespacers 86. In other words, the isolation areas 98 can have a shape similar to that of the openings 94. Therefore, the width at the bottom of the isolation areas 98 can be narrower than the width at the top of the isolation areas 98 (e.g., Fig. 16A), and the isolation area 98 may have a dumbbell shape in a top view (e.g. Fig. 16C). The longitudinal axis of the isolation region 98 is parallel to the longitudinal axes of the fins 56. Sidewalls of the isolation regions 98 between the adjacent gatespacers 86 form an angle θ1 with a plane parallel to the main surface of the substrate 50, similar to the corresponding sidewalls 70S of the remaining dummy gates 70. Furthermore, the sidewalls 70S of the remaining dummy gates 70 are not planar but rather convex in a plan view, with the isolation regions 98 being wider in plan view. In plan view, the isolation regions 98 have a dumbbell shape. The isolation regions comprise a central section 98S1 having a first width W1 and edge sections 98S2 having a second width W2. The edge sections 98S2 touch sidewalls of adjacent gatespacers 86, and the central section 98S1 extends between the edge sections 98S2.

[0046] In Fig. 17A, Fig. 17B and Fig. In step 17C, the sacrificial oxide 96, the gate sealing spacers 80, sections of the dielectric dummy layer 58 located directly beneath the exposed dummy gates 70, and the remaining sections of the dummy gates 70 are removed in an etching step(s), forming recesses 100. In some embodiments, the dummy gates 70 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reactive gas that selectively etches the dummy gates 70 without etching the insulation regions 98, the ILD 88, or the gate spacers 86. Each recess 100 exposes a channel region of a respective fin 56. Each channel region is arranged between adjacent pairs of epitaxial source / drain regions 82. During removal, the dielectric dummy layer 58 can be used as an etch stop layer when the dummy gates 70 are etched.The dielectric dummy layer 58 and the gate sealing spacers 80 can then be removed after the dummy gates 70 have been removed.

[0047] The sacrificial oxide 96 can be removed in the same etching step(s) used to remove the dielectric dummy layer 58. The etching step(s) performed can be selective with respect to the sacrificial oxide 96 material and / or the dielectric dummy layer 58. Removing the sacrificial oxide 96 can change the gap fill distance D. g(sometimes referred to as the “gap-filling window”) between the insulating regions 98 and the fins 56. During the formation of metal-gate electrodes 104 (shown below), metal can form along sidewalls of the insulating regions 98 and the fins 56. Increasing the gap-filling window can improve the window for metal filling, which can reduce the likelihood of metal fusing along each sidewall during formation. This can prevent the formation of pits and voids in the finished FinFET device. In addition to improving the window for metal filling, increasing the gap-filling window can also improve the window for etching. The gap-filling distance D g can be controlled by adjusting parameters of the oxidation process used to form the sacrificial oxide 96, thereby controlling the thickness of the sacrificial oxide 96.

[0048] In Fig. 18A, Fig. 18B and Fig. In 18C, gate dielectric layers 102 and gate electrodes 104 are formed for replacement gates. The gate dielectric layers 102 are conformally deposited in the recesses 100, such as on the upper surfaces and side walls of the fins 56, on side walls of the gate spacers 86, and on an upper surface of the ILD 88. The gate dielectric layers 102 may (or may not) be deposited on side walls of the insulation regions 98. According to some embodiments, the gate dielectric layers 102 comprise silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layers 102 comprise a high-k dielectric material, and in these embodiments the gate dielectric layers 102 may have a k-value greater than approximately 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.The methods for forming the gate dielectric layers 102 can include molecular beam deposition (MBD), ALD, PECVD and the like.

[0049] Next, the gate electrodes 104 are deposited over the gate dielectric layers 102, filling the remaining portions of the recesses 100. The gate electrodes 104 can comprise a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. After the gate electrodes 104 are filled, a planarization process, such as CMP, can be performed to remove the excess portions of the gate dielectric layers 102 and the gate electrode material 104, with the excess portions located above the top surface of the ILD 88 and the insulation regions 98. After the planarization process, the top surfaces of the insulation regions 98, the gate dielectric layers 102, and the gate electrodes 104 are on the same plane.The resulting remaining sections of material from the gate electrodes 104 and the gate dielectric layers 102 therefore form substitute gates for the resulting FinFETs. These substitute gates can be collectively referred to as a "gate stack" or simply "gates".

[0050] The formation of the gate dielectric layers 102 can occur simultaneously, so that the gate dielectric layers 102 comprise the same materials, and the formation of the gate electrodes 104 can also occur simultaneously, so that the gate electrodes 104 comprise the same materials. However, in other embodiments, the gate dielectric layers 102 can be formed using different processes, so that the gate dielectric layers 102 can comprise different materials, and the gate electrodes 104 can be formed using different processes, so that the gate electrodes 104 can comprise different materials. Different masking steps can be used to expose suitable regions when different processes are employed.

[0051] After the deployment of the backup gates, the isolation zones 98 separate the backup gates in the first zone 50B from the backup gates in the second zone 50C, which share the same longitudinal axis. The isolation zones 98 provide isolation between the backup gates in the first zone 50B and the backup gates in the second zone 50C.

[0052] In Fig. 19A, Fig. 19B and Fig. In process 19C, an ILD 106 is deposited over the ILD 88, and contacts 108 and 110 are formed by the ILD 106 and the ILD 88. The ILD 106 is formed over the ILD 88, the replacement gates, the gate spacers 86, and the isolation regions 98. The ILD 106 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited using any suitable method, such as CVD and PECVD. Openings and contacts 108 and 110 are formed by the ILDs 88 and 106. The openings can be formed using suitable photolithographic and etching techniques. A liner, such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like.The conductive material can be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from a surface of the ILD 106. The remaining liner and the conductive material form the contacts 108 and 110 in the openings. A curing process can be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and the contacts 108. The contacts 108 are physically and electrically coupled to the epitaxial source / drain regions 82. The contacts 110 are physically and electrically coupled to the gate electrodes 104.

[0053] Although not explicitly shown, an average professional will easily understand that further processing steps are performed on the structure in Fig. 19A, Fig. 19B and Fig.19C can be carried out. For example, various intermediate metal dielectrics (IMDs) and their corresponding metallizations can be formed over the ILD 106.

[0054] Different embodiments can offer advantages. Thinning the insulation areas between the fins can increase the gap-filling and etching windows of the device, which can prevent the formation of cavities and pits in the finished device. Enlarging the gap-filling window can allow polysilicon to be used for the dummy gates instead of other materials. Forming the dummy gate layer from polysilicon instead of a metal can reduce the lost ILD by up to 30 nm when the dummy gates are replaced. Polysilicon dummy gates may be easier to replace when device sizes and subsequently gate sizes are reduced.

[0055] One embodiment comprises a method. The method comprises: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on side walls of the dummy gate material in the recess; filling an insulating material between the sacrificial oxide on the side walls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

[0056] One embodiment comprises a method. The method comprises: forming a first fin in a first region of a substrate and a second fin in a second region of the substrate; forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material; forming a sacrificial oxide in the recess on sidewalls of the dummy gate material; filling an isolation material into the recess between the sacrificial oxide on the sidewalls of the dummy gate material; removing any remaining sections of the dummy gate material and the sacrificial oxide; and forming replacement gates over the first fin and the second fin.

Claims

[1] Procedure, encompassing: Formation of a first fin (52) and a second fin (52) on a substrate Training a dummy gate material (58, 70) over the first fin and the second fin (52); Forming gatespacers (86) adjacent to the dummy gate material (58, 70) over the first fin (52) and the second fin (52); Forming a recess (94) in the dummy gate material between the first fin and the second fin; Formation of a sacrificial oxide (96) on side walls of the dummy gate material in the recess; Pouring an insulating material (98) between the sacrificial oxide on the side walls of the dummy gate material in the recess; Removal of the dummy gate material and sacrificial oxide; and Forming a first replacement gate (102, 104) above the first fin and a second replacement gate above the second fin; the formation of the recess (94) in the dummy gate material (58, 70) includes: Forming the recess (94) having a first width (W2) near each of the gatespacers (86) in a top view and a second width (W1) far from the gatespacers (86) in a top view, wherein the first width is greater than the second width. [2] Method according to claim 1, wherein the filling of the insulating material (98) between the sacrificial oxide (96) on the side walls comprises the formation of silicon nitride between the sacrificial oxide (96) on the side walls. [3] Method according to claim 1 or 2, wherein the formation of the sacrificial oxide (96) comprises oxidizing the side walls of the dummy gate material (58, 70). [4] Method according to claim 3, wherein the oxidizing of the side walls of the dummy gate material (58, 70) comprises oxidizing the side walls at a temperature of 800 °C to 1100 °C. [5] Method according to claim 3 or 4, wherein the oxidizing of the side walls of the dummy gate material (58, 70) comprises oxidizing the side walls for a period of time of 10 seconds to 20 seconds. [6] Method according to any one of the preceding claims 3 to 5, wherein the oxidizing of the sidewalls of the dummy gate material (58, 70) comprises oxidizing the sidewalls to a thickness of 2.8 nm to 5.6 nm. [7] Method according to any one of the preceding claims 1 to 6, wherein the side walls of the dummy gate material in the recess (98) have a convex shape in a top view. [8] Method according to any of the preceding claims, wherein forming the first replacement gate (102, 104) over the first fin (52) and the second replacement gate (102, 104) over the second fin (52) comprises: Forming a metal between the first fin (52) and the insulating material and between the second fin (52) and the insulating material. [9] Procedures, comprehensive: Formation of a first fin (52) in a first area (50B) of a substrate (50) and a second fin (52) in a second area (50C) of the substrate; Forming a first isolation area (54) on the substrate, wherein the first isolation area surrounds the first fin and the second fin; Training a dummy gate material (58, 60) over the first fin and the second fin; Forming a recess (94) in the dummy gate material; Formation of a sacrificial oxide (96) in the recess on side walls of the dummy gate material; Pouring an insulating material into the recess between the sacrificial oxide on the side walls of the dummy gate material; Removal of remaining sections of the dummy gate material and sacrificial oxide; Forming replacement gates (102, 104) over the first fin and the second fin; forming gate spacers (86) adjacent to the dummy gate material (58, 70) over the first fin (52) and the second fin (52); and comprising forming the recess (94) in the dummy gate material (58, 70): Forming the recess (94) having a first width (W2) near each of the gatespacers (86) in a top view and a second width (W1) far from the gatespacers (86) in a top view, wherein the first width is greater than the second width.

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