Method for producing an adjustment mark

Abstract

A process that exhibits: Forming a trench structure with at least one first trench (104) in a first section (102) of a semiconductor body (100) and a second trench (105) that is wider than the at least one first trench, in a second section (103) of the semiconductor body (100); and Producing a semiconductor layer (200) on a surface of the semiconductor body (100) in the first section (102) and the second section (103) and in the at least one first trench (104) and the second trench (105) such that the semiconductor layer (200) has a substantially planar surface above the first section (102) and a residual trench (208) remains above the second section (105), wherein the fabrication of the semiconductor layer (200) comprises the fabrication of a first epitaxial layer (201) in a first epitaxial growth process and a second epitaxial layer (202) on the first epitaxial layer (201) in a second epitaxial growth process and wherein the first epitaxic growth process and the second epitaxic growth process differ in at least one process parameter selected from the group consisting of: Temperature; Hydrogen flow rate; and Precursor flow rate.

Description

[0001] This description generally concerns an epitaxy process, in particular the creation of an alignment mark in an epitaxial layer.

[0002] The fabrication of semiconductor devices can involve the production of two or more semiconductor layers stacked on top of each other and the processing of each semiconductor layer. The processing of each semiconductor layer can include one or more photolithography processes in which a mask is positioned above a surface of the respective semiconductor layer and used to selectively expose a photoresist deposited on the surface. The exposed photoresist layer can then be used as an implantation or etching mask, or used to fabricate such an implantation or etching mask. An alignment mark can be used to align the mask used to process a second semiconductor layer deposited on top of a first semiconductor layer with patterns formed in the first semiconductor layer.The alignment mark is a structure or pattern in the second semiconductor layer that results from a corresponding structure or pattern in the first semiconductor layer.

[0003] The subsequently published DE 10 2016 112 970 B3 describes a method for manufacturing a superjunction device in which several epitaxial layers are deposited on top of each other, wherein in each of the epitaxial layers, before the deposition of the next epitaxial layer, trenches are produced in the side walls of which dopant atoms are implanted.

[0004] US Patent 8 796 048 B1 describes a method for producing an epitaxial layer above a trench structure of a semiconductor body, wherein the trench structure has trenches of varying widths and wherein the epitaxial process is carried out such that during the epitaxial process first narrow trenches and then increasingly wider trenches are completely filled.

[0005] US Patent 2009 / 0273102A1 describes a method for creating an alignment mark in a semiconductor body. This method involves creating grooves in a highly doped semiconductor substrate and then fabricating an epitaxial layer on the substrate such that the grooves leave cavities in the semiconductor substrate, which can then be used as an alignment mark.

[0006] The object underlying the invention is to provide an efficient multi-stage epitaxy process that includes the production of an alignment mark. This object is achieved by a method according to claim 1.

[0007] An example concerns a method. The method comprises fabricating a trench structure with at least one first trench in a first section of a semiconductor body, fabricating a second trench wider than the first trench in a second section of the semiconductor body, and fabricating a semiconductor layer on a surface of the semiconductor body in the first and second sections, and in the at least one first trench and the second trench, such that the semiconductor layer above the first section has a substantially planar surface and a residual trench remains above the second section. Fabricating the semiconductor layer comprises fabricating a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process. Fig. 1A and Fig. Figure 1B illustrates an example of a method for producing an alignment mark in an epitaxial layer produced on a first section and a second section of a semiconductor body; Fig. Figure 2 shows an example of a top view of the first section of the semiconductor body; Fig. Figures 3A to 3D show various examples of top views of the second section of the semiconductor body; Fig. Figure 4 shows an example of a semiconductor body comprising a semiconductor substrate and an epitaxial layer produced on the substrate; Fig. Figure 5 shows an example of a semiconductor body comprising a semiconductor substrate and two epitaxial layers produced on top of each other on the substrate; Fig. Figure 6 shows a semiconductor wafer with multiple semiconductor bodies; Fig. 7A and Fig. Figure 7B illustrates an example of a method for producing the epitaxial layer on the semiconductor body; Fig. Figure 8 shows a semiconductor wafer with multiple semiconductor bodies in a process chamber (process reactor) during an epitaxy process; Fig. Figures 9A to 9D show a vertical sectional view of a first trench in the first section and a second trench in the second section at different P of a first epitaxial growth process; Fig. Figures 10A to 10C illustrate another example of a method for producing the epitaxial layer on the semiconductor body; Fig. 11A and Fig. Figure 11B illustrates the creation of another epitaxial layer on top of the epitaxial layer using the alignment mark; Fig. Figure 12 illustrates the semiconductor body after implantation of dopant atoms and before fabrication of the epitaxial layer; and Fig. Figure 13 shows a vertical sectional view of a semiconductor device.

[0008] The following detailed description refers to the accompanying drawings. The drawings form part of the description and illustrate specific examples of how the invention can be implemented. Naturally, the features of the various embodiments described herein can be combined unless explicitly stated otherwise.

[0009] The Fig. 1A and Fig. Figure 1B illustrates an example of a method for fabricating a semiconductor layer 200 on a semiconductor body 100. Fabricating the semiconductor layer 200 specifically comprises fabricating the semiconductor layer 200 such that it completely fills a trench structure with at least one first trench 104, which is fabricated in a first section 102 of the semiconductor body 100, and has a substantially planar surface above this trench structure. Furthermore, fabricating the semiconductor layer 200 comprises fabricating the semiconductor layer 200 such that a second trench 105, which is fabricated in a second section 103 of the semiconductor body 100, is reproduced.In this context, "reproduced" means that a residual trench 208 remains in the semiconductor layer 200 above the second trench 105, such that the position of the residual trench 208 is defined by the position of the second trench 105 in the semiconductor body 100, and thus the residual trench 208 is aligned with the second trench 105. The residual trench 208 can therefore be used as an alignment mark, which will be explained in detail below. The residual trench 208 will therefore also be referred to as the alignment mark in the following.

[0010] Referring to Fig. 1A The semiconductor body 100, before the semiconductor layer 200 is produced, comprises the trench structure with at least one first trench 104 in the first section 102 of the semiconductor body 100 and the second trench 105 in the second section 103 of the semiconductor body 100. For illustrative purposes only, the trench structure in the Fig. In the example shown in Figure 1A, several first trenches 104 are present. The second section 103 adjoins the first section 102 in a lateral direction of the semiconductor body 100, the lateral direction being a direction parallel to a first surface 101 of the semiconductor body 100. The first trenches 104 and the second trench 105 extend from the first surface 101 in a vertical direction into the semiconductor body 100. The "vertical direction" is a direction perpendicular to the first surface 101. The first trenches 104 and the second trench 105 can be produced by a conventional trench etching process, such as an anisotropic etching process. The first trenches 104 in the first section 102 and the second trench 105 in the second section 103 can be produced by the same etching process. This etching process can include the production of an etching mask 300 on the first surface 101.The etching mask 300 includes openings that define the positions and lateral dimensions of the first trenches 104 and the second trench 105. "Lateral dimensions" are dimensions in lateral directions, the latter being directions parallel to the first surface 101. During the etching process, an etchant is brought into contact with the semiconductor body 100 through these openings of the etching mask 300 in order to etch the first trenches 104 and the second trench 105.

[0011] For example, semiconductor body 100 is a monocrystalline silicon (Si) semiconductor body. The etching process includes, for example, at least one dry etching process or a plasma etching process.

[0012] In the following, the “width” of one of the first ditches 104 and of the second ditch 105 denotes the shortest lateral dimension of the respective ditch. Fig. 1A denotes w1 as the width of the first trench 104 and w2 as the width of the second trench 105. Hereinafter, the width w1 of the first trench 104 is referred to as the first width and the width w2 of the second trench 105 as the second width. The second trench 105 is wider than the first trench 104, so the first width w1 is smaller than the second width w2. By way of example, a ratio w2 / w1 between the second width w2 and the first width w1 is selected from a range between 1.5 and 5, in particular between 1.9 and 2.5. The first width w1 is, for example, between 1 micrometer (µm) and 7 micrometers, in particular between 3 micrometers and 5 micrometers. An aspect ratio of the first trenches 104, which is the ratio d1 / w1 between a depth d1 of the first trenches 104 and the width w1, is, for example, between 1.5:1 and 5:1, in particular between 2:1 and 4:1.The “depth d1” is the dimension in the vertical direction, which is a direction perpendicular to the first surface 101.

[0013] For example, the second trench 105 is deeper than the first trench 104; that is, the second trench 105 extends further from the first surface 101 into the semiconductor body 100 than the first trench 104. Such a deeper second trench 105 can be achieved by etching the first trench 104 and the second trench 105 in the same etching process. The openings in the etch mask 300 that define the second trench 105 are wider than the respective openings in the etch mask 300 that define the first trench 104. The wider opening in the etching mask 300 can have the effect that in the etching process the wider second trench 105 is etched faster than the narrower first trenches 104, so that at the end of the etching process the second trench 105 extends deeper into the semiconductor body 100 than the first trench 104.

[0014] A semiconductor region located between the trench structure with the first trenches 104 and the second trench 105 is hereinafter referred to as the first mesa region 106. A surface of this first mesa region 106 forms part of the first surface 101 of the semiconductor body 100. Furthermore, semiconductor regions located between the first trenches 104 of the trench structure are hereinafter referred to as second mesa regions. Surfaces of these second mesa regions 107 form further parts of the first surface 101 of the semiconductor body 100. It should be noted that the first surface 101 of the semiconductor body 100 is defined by such surface regions outside the trenches 104 and 105. The surface of a mesa region 106 or 107 is a section of the surface of the semiconductor body 100 and is located between the two trenches that define the respective mesa region. In the following, the general term “mesa region” refers to any of the first and second mesa regions 106, 107.The width of the first mesa region 107, for example, is between 0.5 times and twice the width of the first latitude, that is, between 0.5·w1 and 2·w1 or between 0.5 micrometers and 7 micrometers.

[0015] Fig. Figure 1B shows the semiconductor arrangement after the fabrication of semiconductor layer 200 on the semiconductor body 100. The fabrication of semiconductor layer 200 comprises the fabrication of a first epitaxial layer 201 on semiconductor layer 100 and the fabrication of a second epitaxial layer 202 on the first epitaxial layer 201. The in Fig. The semiconductor arrangement shown in Figure 1B, comprising the semiconductor body 100 and the semiconductor layer 200, is a monocrystalline semiconductor arrangement. This means that, based on the crystalline structure of the semiconductor arrangement, the semiconductor body 100 and the semiconductor layer 200, along with the two epitaxial layers 201 and 202, cannot be detected. In other words, there is no visible boundary or interface between the semiconductor body 100 and the epitaxial layers 201 and 202. However, for illustrative purposes, a boundary between the semiconductor body 100 and the semiconductor layer 200, and between the two epitaxial layers 201 and 202 of the semiconductor layer 200, is shown in Figure 1B. Fig. 1B is shown in dashed lines.

[0016] Referring to Fig. 1B comprises the fabrication of the first epitaxial layer 201 everywhere on the semiconductor body 100, that is, on the floors and sidewalls of the first trenches 104, on the floor and sidewalls of the second trench 105, and on the mesa regions 106, 107. In particular, the fabrication of the first epitaxial layer 201 comprises the fabrication of the first epitaxial layer 201 such that it completely fills the first trenches 104 and has a substantially planar surface above the first section 102 of the semiconductor body 100. "Substantially planar" means, by way of example, that the distance in the vertical direction between a position of the lowest point and a position of the highest point of the surface is less than 15%, less than 10%, or less than 5% of the depth d1 of the first trenches 104.The "depth" of the first trenches 104 is the dimension of the first trenches 104 in the vertical direction of the semiconductor body 100 before the fabrication of the first epitaxial layer 201. "Substantially planar" can include the fact that the distance in the vertical direction between the position of the lowest point and the position of the highest point is less than 1 micrometer. The second trench 105 is reproduced by the first epitaxial layer 201, that is, above the second trench 105 there is a residual trench in the first epitaxial layer 201. The second epitaxial layer 201 is fabricated such that it grows substantially in the vertical direction, thereby increasing the thickness of the second semiconductor layer 200 above the first section 102 and reproducing the residual trench in the first epitaxial layer 201. The reproduction of the residual trench in the first epitaxial layer 201 by the second epitaxial layer 202 forms the adjustment mark 208.Specific examples of how the first epitaxial layer 201 and the second epitaxial layer 202 can be produced are explained below.

[0017] As in Fig. As shown in Figure 1A, the first and second trenches 104, 105, according to an example, have essentially vertical sidewalls, that is, sidewalls perpendicular to the first surface 101. Furthermore, the bottoms of the first and second trenches 104, 105 can be essentially parallel to the first surface 101 of the semiconductor body 100. Trenches of this type can be described as U-shaped trenches. According to an example, the semiconductor body 100 is a monocrystalline silicon semiconductor body 100 with crystal orientations such that the first surface 101 lies in a {100}-crystal plane of the semiconductor lattice, the bottoms of the trenches lie in a {100}-crystal plane, and the sidewalls of at least the first trenches 104 lie in {010}-crystal planes.

[0018] As in Fig. Figure 1B shows that the residual trench 208, which forms the adjustment mark, has a shape that differs from the shape of the second trench 105. According to one example, the residual trench has a V-shape, that is, a shape with two sloping side walls that meet at the bottom of the trench 208.

[0019] According to a Fig. The first two examples shown are 104 elongated ditches. Fig. Figure 2 shows a horizontal sectional view of the second section 102 of the semiconductor body 100. The figures shown are for illustrative purposes only. Fig. Figure 2 shows three first ditches 104. “Elongated” means that the length 11 of the first ditches 104 is significantly greater than the first width w1. According to an example, the length 11 is at least 10 times, at least 100 times, at least 1,000 times, or at least 10,000 times the first width w1.

[0020] The Fig. Figures 3A to 3D illustrate various examples of how the second trench 105 can be realized. Each of these Fig. Figures 3A to 3D illustrate a horizontal sectional view of the semiconductor body 100 in the second section 103. According to a Fig. In the example shown in 3A, the second trench 105 is a single trench with a length l2 that is greater than the second width w2. Referring to Fig. 3B, two (as shown) or more (not shown) second trenches 105 can be constructed in the second section 103. In the case of the Fig. In the example shown in 3B, these trenches are essentially parallel. According to another example shown in Fig. As shown in 3C, the second trench 105 is cruciform. According to yet another example, which is in Fig. As shown in 3D, the second trench 105 is ring-shaped. According to an example, the second trench 105 is present in each of the... Fig. The examples shown in 3A to 3D are oriented such that at least two opposite side walls lie in {010} crystal planes of the crystal lattice of the semiconductor body 100.

[0021] In the Fig. 1A and Fig. Figure 1B shows the semiconductor body 100 only schematically. According to a Fig. In the example shown, the semiconductor body 100 comprises a semiconductor substrate 110 and a first epitaxial layer 120 grown on the substrate 110. In this example, the first trenches 104 and the second trench 105 are produced in the first epitaxial layer 120.

[0022] According to another example, which is in Fig. As shown in Figure 5, the semiconductor body 100 comprises the substrate 110 and the first epitaxial layer 120 with the first trenches 104 and the second trench 105, and a second epitaxial layer 130 between the substrate 110 and the first epitaxial layer 120. The second epitaxial layer 130 is grown on the substrate 110, and the first epitaxial layer 120 is grown on the second epitaxial layer 130. According to one example, the second epitaxial layer 130 is fabricated such that it has a higher base doping concentration than the first epitaxial layer 120. According to another example, the "base doping concentration" is an in-situ doping concentration established during the epitaxial growth process. According to another example, the first epitaxial layer 120 is undoped, that is, its base doping concentration is less than 1 × 10⁻⁴ cm⁻¹. -3 (1·10 14 cm -3A doping concentration of 130 in the second epitaxial layer, for example, is in the range of 5 x 15 cm. -3 and 1E17 cm -3 selected. According to an example, the base doping concentration of the semiconductor substrate 110 is higher than the base doping concentration of the first epitaxial layer 120 and the second epitaxial layer 130, respectively. According to an example, a base doping concentration of the semiconductor substrate 110 is selected from a range between 1E18 cm. -3 and 1E20 cm -3 .

[0023] The Fig. Figures 1A, 2, 3A to 3D, 4 and 5 each schematically illustrate only one section of the semiconductor body 100. The semiconductor body 100 can be part of a semiconductor wafer, which comprises several essentially identical semiconductor bodies (which may also be referred to as semiconductor chips or semiconductor dies). Fig. Figure 6 schematically illustrates a top view of a semiconductor wafer 1, which comprises several semiconductor bodies of the type described above. Fig. The six dotted lines shown illustrate lines along which the wafer 1 can be divided after processing to obtain multiple individual semiconductor dies. According to one example, these cutting lines pass through the second sections 103 in such a way that at least portions of the second sections 103 are removed when the wafer 1 is cut. These second sections 103 can also be referred to as "kerfs".

[0024] Although the figures described above and below only show a section of a semiconductor body 100 during processing, it should be noted that the process steps and process sequences described with reference to these figures can be applied to a semiconductor wafer 1 containing several semiconductor bodies 100. The individual process steps and process sequences are applied simultaneously to the individual semiconductor bodies 100 contained in the wafer 1. Hereinafter, the term "semiconductor body" is used to refer to a semiconductor body 100 in a state as it appears in Fig. 1A, Fig. 4 or Fig. 5 is shown, that is, before the semiconductor layer 200 is produced, but also during the manufacturing process. Accordingly, the term "wafer" is used to refer to the wafer in the Fig. to describe the state shown in 6, that is, before the semiconductor layer 200 is produced, but also during the manufacturing process.

[0025] The Fig. 7A and Fig. Figure 7B illustrates an example of a method for fabricating the semiconductor layer 200. In this example, fabricating the semiconductor layer 200 comprises fabricating the first epitaxial layer 201 on the semiconductor body 100 in a first epitaxial growth process. According to the example, the duration of this first epitaxial growth process is such that, at the end of the first epitaxial growth process, the first epitaxial layer 201 completely fills at least one first trench 104, covers the mesa regions 106 and 107, and has a substantially planar surface above the first section 102, but retains a residual trench 218 above the second trench 105. That is, the second trench 105 is reproduced by the first epitaxial layer 201.

[0026] In this process, the second epitaxial layer 202 is grown directly on top of the first epitaxial layer 201 in a second epitaxial growth process that immediately follows the first. The formation of the second epitaxial layer 202 results in an increased thickness of the second semiconductor layer 200 above the first section 102, but reproduces the residual trench 218 that is present in the first epitaxial layer 201 at the end of the first epitaxial growth process, so that the alignment mark 208 is formed in a second epitaxial layer 202. "That the second epitaxial growth process immediately follows the first epitaxial growth process" can include the wafer remaining in a process chamber (process reactor) of a processing setup from the beginning of the first epitaxial growth process until the end of the second epitaxial growth process.

[0027] A sectional view of an example of a processing arrangement 2 is shown schematically in Fig. Figure 8 shows the processing arrangement 2. The processing arrangement 2 comprises a process chamber 20 with a receptacle (susceptor) 21 for holding the wafer 1 during the manufacturing process, a heating system 221, 222 for heating the wafer 1, at least one inlet 23 for supplying process gases into the process chamber 2, and at least one outlet 24 for removing gaseous residues of the process from the process chamber 2. According to one example, the at least one inlet 23 and the at least one outlet 24 are arranged on opposite sides (side walls) of the process chamber 2, wherein a position of the at least one inlet 23 and the at least one outlet 24 relative to a position of the wafer 1 during the process is such that the process gas flows from the inlet along and laminarly parallel to the first surface 11 to the outlet.Chemical reactions take place on the first surface 11, so that the process gas coming from the inlet 23 differs from the residual gas passing through the outlet 24. Examples of these chemical reactions are explained below.

[0028] Referring to Fig. The susceptor 21 of a susceptor plate 211 for holding the wafer 1 and a shaft 212 on which the plate 211 is mounted can comprise the plate 211. During the process, the second surface 12 of the wafer 1 can lie on a surface of the plate 211. In one example, the plate 211 includes a pocket 213 approximately the size of the wafer 1, and the wafer lies in the pocket. In another example, the susceptor plate 211 is arranged in the chamber 20 such that the first surface 11 of the wafer is substantially aligned with the inlet 23 and the outlet 24, allowing the process gas to flow laminarly along the first surface 11. For example, a longitudinal direction (axis) of the shaft is substantially perpendicular to the first surface of the plate 211, and thus substantially perpendicular to the first and second surfaces 11, 12 of the wafer.According to one example, the shaft 212 rotates about its longitudinal direction to rotate the wafer 11 such that each edge region of the wafer periodically passes through the inlet 23. The “edge region” is a region adjacent to a lateral edge of the wafer 1. Such a rotation of the wafer 1 compensates for gas depletion due to the epitaxial growth process at the first wafer surface 11.

[0029] The heating system 221, 222 is located outside the process chamber and heats the wafer 1 through the process chamber housing. In one example, the heating system includes heating lamps, such as halogen lamps, and the process chamber housing is transparent so that light emitted by the lamps can pass through the housing and heat the wafer. In another example, the process chamber housing is made of quartz glass.

[0030] According to one example, the process gases comprise at least a silicon-containing precursor and hydrogen. In the process chamber, the precursor and hydrogen react, depositing silicon (Si) from the precursor in solid, monocrystalline form onto a first surface 11 of the wafer. The first surface 11 of the wafer is formed by the first surfaces 101 of the semiconductor bodies 100 contained in the wafer 1, so that the silicon is deposited onto the first surfaces 101 of the semiconductor bodies 100. The precursor may contain chlorine. In this case, in addition to the solid silicon, gaseous hydrochloric acid is produced from the gaseous precursor and the gaseous hydrogen.

[0031] At the in Fig. In the example shown in Figure 6, the heating system 221, 222 comprises two heaters, a first heater 221 which faces a first surface 11 of the wafer 1, and a second heater 222 which faces a second surface 12 opposite the first surface 11 of the wafer 1, wherein these heaters 221, 222 may each comprise several heating elements.

[0032] In one example, heaters 221 and 222 comprise halogen lamps. To reduce temperature gradients and thus minimize mechanical stress within wafer 1, the first heater 221 heats the first surface 11 of wafer 1, and the second heater 222 heats the susceptor plate 211, which may comprise graphite, and the second surface 12 of the wafer. The total heating power provided by the heating system can be distributed among the individual heaters 221 and 222 in such a way as to equalize a vertical temperature gradient between the different materials of the susceptor 21 and wafer 1. Furthermore, the total heating power can be distributed in such a way as to obtain a specific temperature profile in the lateral direction of wafer 1. In one example, this temperature profile is such that the temperature at every position of wafer 1 is essentially the same during the growth process."Essentially the same" includes, according to one example, a temperature difference of less than 10 K, in particular less than 5 K, between any positions of wafer 1. When wafer 1 is heated, the temperature at the edge of the wafer may be higher than in the center, according to one example. According to another example, the first and second heaters 221, 222 are configured to provide essentially the same heating power, such that each heater 221, 222 contributes essentially 50% to heating the process chamber 2 and wafer 1, respectively.

[0033] The first epitaxy growth process, which produces the first epitaxy layer 201, and the second epitaxy growth process, which produces the second epitaxy layer 202, differ in at least one of the following process parameters: temperature in the process chamber during the epitaxy growth process; flow rate of the precursor gas; flow rate of the hydrogen gas. The temperature is set by heaters 211 and 212. As shown in the example, the same precursor is used in both epitaxy growth processes.According to one example, at least one of the following is true: The temperature in the first epitaxic growth process is lower than in the second epitaxic growth process; the hydrogen flow rate in the first epitaxic growth process is lower than in the second epitaxic growth process; the precursor flow rate in the first epitaxic growth process is higher than in the second epitaxic growth process. According to another example, the difference between the lower temperature in the first epitaxic growth process and the higher temperature in the second epitaxic growth process is greater than 25 K and less than 100 K, in particular less than 40 K.

[0034] The difference in process parameters results in the first epitaxial layer 201 and the second epitaxial layer 202 growing differently with respect to their respective growth rates and with respect to growth on vertical surfaces, such as the sidewalls of the trenches 104, 105. Both epitaxial growth processes are, however, non-selective. For example, the difference in process parameters is such that the first epitaxial layer 201 has a greater tendency to grow at the bottom of the first and second trenches 104, 105 than on vertical surfaces and the mesa regions between the first trenches, while the second epitaxial layer 202 tends to grow substantially conformally on surfaces of the semiconductor body 100.

[0035] The Fig. Figures 9A to 9D illustrate a vertical sectional view of a first trench 104 in the first section 102 of the semiconductor body 100 and a second trench 105 in the second section 103 of the semiconductor body 100 at different stages of the first epitaxial growth process in which the first epitaxial layer 201 is grown. Fig. Figures 9A to 9D show the epitaxial layer after four stages of the epitaxial process, with each of these stages producing a section 2011, 2012, 2013, 2014 of the first epitaxial layer 201. These sections 2011-2014 constitute the first epitaxial layer 201, which is Fig. 9D is shown. The epitaxial layer 201 is a monocrystalline layer, so these sections, which can also be called sublayers, are not visible in the finished epitaxial layer. In particular, there is no visible boundary between these sublayers. Nevertheless, the sublayers are in the Fig. 9A-9D are shown in dashed lines. As in the Fig. As shown in Figures 9A-9D, the semiconductor material tends to accumulate more strongly at the bottom of the trenches, especially in corners between the bottom and side walls, than at the side walls of trenches 104, 105 and on the mesa area during the first epitaxic growth.

[0036] According to an example, the first epitaxic growth process ends when the first trenches 104 have been filled and the first epitaxic layer 201 has a substantially planar surface. Since the first trench 105 is wider than the first trenches 104, there is a residual trench 218 in the second section 103 when the first epitaxic growth process ends. This residual trench 218 would be filled if the first epitaxic growth process continued. However, changing the epitaxic growth process from the first to the second largely reproduces the residual trench 218, resulting in the adjustment mark 208. For illustrative purposes only, the residual trench 218 is shown in the Fig. The example shown in 9D has a V-shape. This type of trench is largely reproduced by an epitaxial growth process, such as the second epitaxial growth process, in which semiconductor material grows conformally onto the surfaces of the semiconductor body. In the example shown in Fig. In the example shown in 9D, the surface on which the second epitaxial layer grows is the surface of the first epitaxial layer 201. The first epitaxial layer is essentially planar in the first section 102 and includes the residual trench 218 in the second section 103.

[0037] In summary, what is in the Fig. As shown in Figures 9A to 9D, this process is suitable for producing a relatively thick epitaxial layer 200 on the semiconductor body 100, wherein the epitaxial layer above the first section 102 is essentially planar and reproduces the second trench 105 to produce the alignment mark 208 above the second section 103.

[0038] According to one example, the first and second epitaxial layers 201, 202 are produced such that the total thickness of the first and second epitaxial layers 201, 202 on the first surface 101, that is, on the mesa regions 106, 107, is between 0.3 and 1.3 times the depth d1 of the first trenches 104. According to another example, the first epitaxial layer 201 is grown such that its thickness on the first surface 101 is between 0.6 and 1.6 times the first width w1, and the second epitaxial layer 202 is then grown such that it has a thickness given by the desired total thickness minus the thickness of the first epitaxial layer 201.

[0039] The Fig. Figures 10A-10C illustrate a process according to another example. Each of these figures shows a vertical sectional view of the semiconductor body during / after different process steps. Fig. Figure 10A shows the semiconductor body after the fabrication of a first epitaxial layer 201' on the semiconductor body 100. In this example, the first epitaxial layer 201 is fabricated such that it has a residual trench 218' over the former second trench 105 in the second section 103 and further residual trenches 214' over the former first trenches 104 in the first section 102, the further residual trenches 214' above the first section 102 being less deep than the residual trench 218 in the second section 103.

[0040] Referring to Fig. In section 10B, the process further includes planarizing the first epitaxial layer 201' such that the residual trenches 214' above the first section 102 are substantially removed, but the residual trench 218' remains substantially intact. "Substantially" means that the depth of the residual trench 218' can be reduced by the planarizing process. The planarizing process may include a chemical and / or mechanical polishing process. According to one example, the residual trench 218' above the second section 103 is covered by a protective layer (not shown) during the planarizing process. Fig. Reference numeral 10B designates the first epitaxial layer with the essentially planar surface above the first section 102 after the planarization process, and reference numeral 218 designates the residual trench after the planarization process.

[0041] Referring to Fig. 10C further includes the creation of the second epitaxial layer 202 on the first epitaxial layer 201. This is described in the Fig. The method shown in sections 10A to 10C differs from that shown in the Fig. 7A and Fig. 7B explained the procedure by stating that the semiconductor assembly must be removed from the process chamber between the first and second epitaxy processes. On the other hand, in the Fig. Procedures 10A to 10C illustrated the same process parameters used in the first and second epitaxy growth processes, such as process parameters previously explained using the second epitaxy growth process.

[0042] The process for fabricating a semiconductor layer using an alignment mask on a trench array can be repeated multiple times to produce several epitaxial layers on top of each other. This is described in the Fig. 11A and Fig. 11B illustrates. Fig. Figure 11A shows the semiconductor arrangement with the semiconductor body 100 and the epitaxial layer 200 after fabricating a trench structure with at least one first trench 204 in a first section of the semiconductor layer 200 and after fabricating a second trench 205 in a second section of the semiconductor layer 200. The "first section of the semiconductor layer" is a region of the semiconductor layer 200 above the first section 102 of the semiconductor body 100, and the "second section of the semiconductor layer" is a region of the semiconductor layer 200 above the second section 102 of the semiconductor body 100. Fabricating this trench structure in the first section and the second trench 205 in the second section can involve an etching process using an etching mask.It may be desirable to fabricate the trench structure with the at least one first trench 204 in the semiconductor layer 200 such that it is aligned with the previous trench structure in the semiconductor body. This may involve arranging a position of the at least one first trench 204 in the semiconductor layer 200 exactly above a position of the at least one previous first trench in the semiconductor layer 100, or having a predefined lateral offset between these positions. In the semiconductor body 100, the at least one first trench 104 and the second trench 105 can be fabricated such that a known spatial relationship exists between these trenches 104 and 105. In the semiconductor layer 200, the alignment mark 208 identifies the position of the first trench in the semiconductor body 100 below the semiconductor layer.Based on the position of the alignment mark 208 and the known spatial relationship between the second trench 105 and the at least one first trench 104 in the semiconductor body 100, the position of the at least one first trench 104 in the semiconductor body 100 can still be identified after the semiconductor layer 200 has been fabricated. Thus, the alignment mark 208 can be used to fabricate the etching mask 3002 such that at least one opening in the etching mask is aligned with the position of the at least one first trench in the semiconductor body 100.

[0043] Fig. Figure 11B shows the semiconductor arrangement after fabricating an additional semiconductor layer 2002 on top of semiconductor layer 200. Fabricating the additional semiconductor layer 2002 can involve any of the previously described processes for fabricating semiconductor layer 200. In particular, fabricating the additional semiconductor layer 2002 includes fabricating an additional first semiconductor layer and an additional second semiconductor layer. Referring to Fig. 11B comprises the fabrication of the additional semiconductor layer 2002 and the fabrication of an additional alignment mark 2008, which results from the second trench 205 in the semiconductor layer 200. This additional alignment mark can be used to align at least one first trench of a trench structure (not shown) to be fabricated in the additional semiconductor layer 2002 with the previous trench structure in the semiconductor body 100 and the semiconductor layer 200. According to an example, the position of the additional alignment mark 2082 is offset in a lateral direction relative to the position of the alignment mark 208 in the semiconductor layer. The reason for this is that the second trench 205 in the semiconductor layer 200, which defines the position of the additional alignment mark 2082, is fabricated spaced apart from the alignment mark 208 to prevent the alignment mark from being removed during the fabrication of the second trench 205.

[0044] In each of the previously described examples, dopant atoms can be implanted into the sidewalls of the first trenches 104 in the semiconductor body 100 before the semiconductor layer 200 is produced. This is described in Fig. Figure 12 shows a vertical sectional view of the semiconductor body 100 after implantation of the dopant atoms. The implantation of the dopant atoms can include the implantation of dopant atoms of a first doping type (n or p) into first sidewalls to create first implanted regions 30, and the implantation of dopant atoms of a complementary doping type (p or n) into second sidewalls opposite the first sidewalls to create second implanted regions 40. This is shown in Fig. Figure 12 shows two trenches. Alternatively, dopant atoms of both the first doping type and the second doping type are implanted into both the first and second sidewalls to form third implanted regions 34. This is shown for one trench in Fig. 12 shown.

[0045] Accordingly, dopant atoms can be implanted into the sidewalls of the grooves of any further semiconductor layers. As explained above, multiple semiconductor layers can be fabricated on top of each other. Fig. Figure 13 shows an example of a superjunction semiconductor device based on a semiconductor arrangement with a semiconductor body 100 and several semiconductor layers 200-200 stacked on top of each other on the semiconductor body 100. n was manufactured. For illustrative purposes only, semiconductor body 100 is a semiconductor body manufactured using... Fig. 5 of the type described above and comprises a substrate 110, an epitaxial layer 120 in which initial trenches were created, and a further epitaxial layer between the first epitaxial layer 120 and the substrate 110. In connection with Fig. 13 The term semiconductor layer refers to the epitaxial layer 120 and any one of the semiconductor layers 200-200 produced on top of each other on the epitaxial layer 120. n .

[0046] Referring to Fig. 13 comprise the semiconductor layers 120, 200-200 n each several endowed areas 31-3 n+1 of the first doping type (hereinafter referred to as areas of the first type) and several doped areas 41-4 n+1 of the second doping type (hereinafter referred to as second doped areas). The areas of the first type 31-3 n+1 can be obtained through a diffusion process from the based on Fig. 12 explained first implanted areas 30 result and the areas of the second type 41-4 n+1 can result from a diffusion process from the second implanted areas described above. 40 Alternatively, the areas of the first type 31-3 can n+1 and the areas of the second type 41-4 n+1 from the described third implanted regions 40 by a diffusion process. In the latter case, the dopant atoms of the first type and the dopant atoms of the second type are chosen such that they have different diffusion constants, so that in the diffusion process these dopant atoms of the first type and the dopant atoms of the second type separate, so that, based on the third implanted regions, the regions of the first type and the regions of the second type are produced. The diffusion process can be a cladding process after the production of the several semiconductor layers 120, 200-200 n include.

[0047] At the in Fig. The example shown in Figure 13 depicts the arrangement with semiconductor layers 120, 200-200. n A drift region of the superjunction semiconductor device. In this device, the doped regions of the first type 31-3 n+1 of the individual semiconductor layers 120, 200-200 n arranged one above the other in a vertical direction z of the semiconductor device and the areas of the first type 31-3 n+1 of adjacent semiconductor layers 120, 200-200 n border each other, so that these areas of the first type 31-3 n+1 , which are arranged one above the other in the vertical direction z, form a continuous region of the first type 3. The creation of these regions of the first type 31-3 n+1 and of areas of the second type 41-4 n+1 can be achieved by creating the first trenches in the individual semiconductor layers 120, 200-200 none on top of the other. The previously explained alignment marks can help to achieve this.

[0048] The in Fig. The superjunction device shown in Figure 13 is implemented as a MOSFET. In this case, the substrate 120 forms a drain region 53, which is connected to a drain node D (located in Fig. 13 (shown only schematically) of the MOSFET is connected. The MOSFET can comprise several component cells, with two of these component cells in Fig. Figure 13 shows. Each of these device cells comprises a region of the first type 3 and a region of the second type 4. The multiple device cells share the drain region 53 formed by the substrate 110 and the epitaxial layer 130 adjacent to the substrate 110, the epitaxial layer 130 forming part of the drift region of the superjunction MOSFET.

[0049] Each component cell (transistor cell) 7 comprises a source region 52, a body region 51 that separates the source region 52 from the drift region, and a gate electrode 61, which is dielectrically insulated from the body region 51 by a gate dielectric 62. The gate electrodes 61 of the individual component cells are electrically connected to a common gate node G, and the source and body regions 52 and 51 of the individual component cells are electrically connected to a source node S via their respective source electrodes 71. The second-type region 4 of each component cell borders the body region 51, as shown in the example. The gate electrode 61 serves to control a conducting channel in the body region between the source region 52 and the drift region, in particular the second-type region 20 of the drift region.

[0050] The body regions 51 and the source regions 52 can be fabricated in an uppermost semiconductor layer 200 n by at least one implantation and one diffusion process. Prior to this at least one implantation and diffusion process, initial trenches (which form the Fig. 11A (the trenches shown correspond to 204) of the uppermost semiconductor layer 200 n according to one of the previously based on the Fig. The processes described in 7A and 7B and 10A to 10C are filled, that is, by epitaxial growth of a semiconductor layer that fills the initial trenches. The source and body regions 51, 52 can then be fabricated in this semiconductor layer using at least one implantation and diffusion process. The semiconductor layer 200 nThe layer in which the source and drain regions 51, 52 are fabricated can be thinner in the vertical direction than the other semiconductor layers 120, 200-2004. The gate dielectric 62, for example, comprises an oxide and can be fabricated using an oxidation or deposition process. The gate electrode 61, for example, comprises a metal and a highly doped polycrystalline semiconductor material, such as polysilicon.

[0051] The superjunction MOSFET can be an n-type or a p-type MOSFET. In an n-type MOSFET, the source region 52, the drain region 53, and the first-type drift region 3 are n-doped regions, while the body region 51 and the second-type drift region 5 are p-doped regions. In a p-type MOSFET, the individual device regions have a doping type complementary to the doping type of the respective device regions in an n-type MOSFET.

[0052] The superjunction MOSFET can be operated in an on-state or an off-state. In the on-state, the gate electrode 61 generates a current when driven by a drive voltage V applied between the gate node G and the source node S. GSA conducting channel exists in body region 51 between source region 52 and the region of the first type 20, such that when a voltage is applied between drain node G and source node S, a current can flow between drain node D and source node S. In the off state, the gate electrode 61 is driven such that the conducting channel in body region 51 is interrupted. For clarification, assume that the MOSFET is in the off state and a voltage is applied between drain node D and source node S, which reverse-biases a pn junction between body region 51 and the region of the first type 3 and a pn junction between the region of the first type 3 and the region of the second type 4. In this case, a space charge region spreads in the region of the first type 3, body region 51, and also in the region of the second type 4, whereby the region of the first type 3 and the region of the second type 4 can become completely depleted.For example, a doping concentration of body region 51 is high enough so that body region 51 is not completely depleted.

[0053] In the healing process described above, the areas of the first type 31-3 n+1 and the areas of the fourth type 41-4 n+1 diffuse in the lateral direction x in such a way that the areas of the first type and the areas of the second type adjoin each other. According to another example, which is given in Fig. As shown in Figure 13, areas with a base doping of the respective semiconductor layer can be 120, 200-200 n have, between the areas of the first type 31-3 n+1 and the areas of the second type 41-4 n+1 remain. The "basic doping" is a doping that coats the semiconductor layers 120, 200-200 n have before the areas of the first type 31-3 n+1 and the areas of the second type 41-4 n+1 be manufactured.

[0054] At the in Fig. In the semiconductor device shown in Figure 13, the gate electrode 61 of each device cell is a planar electrode located above a surface of the layer arrangement 100. However, this is only one example. According to another (not shown) example, the gate electrode of each device cell is a trench electrode. That is, the gate electrode 61 is located in a trench above the region of the first type 3 and adjacent to the body region 51 and the source region 52, and the gate electrode 61 is dielectrically insulated from these regions by the gate dielectric 62.

Claims

[1] Method comprising: Producing a trench structure having at least one first trench (104) in a first section (102) of a semiconductor body (100) and a second trench (105), which is wider than the at least one first trench, in a second section (103) of the semiconductor body (100); and Producing a semiconductor layer (200) on a surface of the semiconductor body (100) in the first section (102) and the second section (103) and in the at least one first trench (104) and the second trench (105) such that the semiconductor layer (200) has a substantially planar surface above the first section (102) and a residual trench (208) remains above the second section (105), wherein the formation of the semiconductor layer (200) comprises the formation of a first epitaxial layer (201) in a first epitaxial growth process and a second epitaxial layer (202) on the first epitaxial layer (201) in a second epitaxial growth process, and wherein the first epitaxial growth process and the second epitaxial growth process differ in at least one process parameter selected from the group consisting of: Temperature; hydrogen flow rate; and Precursor flow rate. [2] The method of claim 1, wherein the second epitaxial growth process directly follows the first epitaxial growth process. [3] Method according to claim 2, characterized in that the second epitaxial growth process directly follows the first epitaxial growth process, comprising that the semiconductor body (100) remains in a process chamber (2) from the beginning of the first epitaxial growth process until the end of the second epitaxial growth process. [4] The method of claim 1, wherein the temperature in the first epitaxial growth process is lower than in the second epitaxial growth process. [5] The method of claim 4, wherein a temperature difference between the lower temperature in the first epitaxial growth process and the higher temperature in the second epitaxial growth process is higher than 25K and less than 100K. [6] A method according to claim 5, wherein the temperature difference is less than 40K. [7] A method according to any one of the preceding claims, wherein the flow rate of hydrogen in the first epitaxial growth process is lower than in the second epitaxial growth process. [8] A method according to any one of the preceding claims, wherein the flow rate of the precursor in the first epitaxial growth process is greater than in the second epitaxial growth process. [9] The method of any one of claims 1 to 3, wherein forming the semiconductor layer (100) further comprises: Planarizing the first epitaxial layer (201) above the first section before forming the second epitaxial layer (202). [10] The method of claim 9, wherein planarizing the first epitaxial layer (201) comprises forming a protective layer on a surface of the first epitaxial layer (201) above the second portion (105). [11] The method of claim 9 or 10, wherein planarizing the first epitaxial layer (201) comprises at least one of a chemical polishing process and a mechanical polishing process. [12] A method according to any one of the preceding claims, wherein the at least one first trench (104) and the second trench (105) each have a U-shape. [13] Method according to claim 12, in which a bottom of the at least one first trench (104) lies in a {100} crystal plane of a crystal lattice of the semiconductor body (100) and in which opposite side walls of the at least one first trench (104) each lie in a {010} crystal plane of the crystal lattice. [14] Method according to claim 12 or 13, in which a bottom of the second trench (105) lies in a {100} crystal plane of a crystal lattice of the semiconductor body (100) and in which at least two opposite side walls of the second trench (105) each lie in a {010} crystal plane of the crystal lattice. [15] A method according to any one of the preceding claims, wherein the residual trench (208) has a V-shape. [16] A method according to any one of the preceding claims, wherein a total thickness of the first and second epitaxial layers (201, 202) on the surface of the semiconductor body (100) is between 0.3 times and 1.3 times a depth of the first trenches (104). [17] The method of claim 16, wherein a thickness of the first epitaxial layer (201) on the surface of the semiconductor body (100) is between 0.6 times and 1.6 times a width of the at least one first trench (104).

Images