Insulation structure that limits semiconductor epitaxy and associated manufacturing process

Abstract

Procedure, comprehensive: Providing a semiconductor structure (200) with an active region (204) and an isolation structure (212) adjacent to the active region, wherein the active region comprises source and drain regions (206) between which a channel region (208) for a transistor is arranged, wherein the semiconductor structure further comprises a gate structure (220) over the channel region; Etching a trench (230) in the source or the drain area, wherein the trench exposes a section of a side wall (232) of the insulation structure; epitaxial growth of a first semiconductor layer (236) in the trench; epitaxial growth of a second semiconductor layer (240) over the first semiconductor layer; Changing a crystal facet orientation of a section of an upper surface (242) of the second semiconductor layer by an etching process; after changing the crystal facet orientation, epitaxial growth of a third semiconductor layer (246) over the second semiconductor layer, wherein a first side face (242a) of the second semiconductor layer is oriented in the (111) crystal plane and a second side face (244a) of the second semiconductor layer is oriented in the (311), (511), (711) or (911) crystal plane; and wherein an upper surface (248a) of the third semiconductor layer (246) is parallel to an upper surface of the active region (204).

Description

BACKGROUND

[0001] As semiconductor devices have become increasingly smaller, strained source / drain (S / D) features (e.g., stressor regions) have been implemented using epitaxially grown semiconductor materials to promote charge carrier mobility and improve device performance. For example, forming a metal-oxide-semiconductor field-effect transistor (MOSFET) with stressor regions can epitaxially grow silicon (Si) to form raised S / D features for n-type devices and epitaxially grow silicon-germanium (SiGe) to form raised S / D features for p-type devices. Various techniques directed at the shapes, configurations, and materials of these S / D features have been implemented to further improve the performance of transistor devices. However, previous approaches to forming raised S / Ds have not been entirely satisfactory.

[0002] For example, forming raised S / D regions in an active region adjacent to an isolation region (or isolation structure) has been problematic. For example, trenches for growing epitaxial features at the boundary of the two regions do not need to have an ideal shape. Furthermore, these trenches are only partially surrounded by semiconductor material(s). As a result, epitaxial features grown from these trenches may be thinner than those grown entirely within the active region. Consequently, if contact features are formed over these epitaxial features, the contact landing may be skewed and the contact resistance may be high. Improvements in these areas are desired.

[0003] US 2013 / 0 084 682 A1 relates to a method for manufacturing a semiconductor device, comprising providing a substrate having a surface and forming a recess cavity in the substrate, wherein the recess cavity is positioned horizontally between a gate stack and an isolation feature. US 2013 / 0 082 309 A1 relates to a method of manufacturing a semiconductor device, comprising forming an epitaxial (epi) material in the recess cavity over a substrate, the epi material having a corner above the recess cavity, and providing a treatment to redistribute at least a portion of the corner to be located in the recess cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The invention is defined by the independent claims. The dependent claims relate to corresponding developments. The present disclosure is best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are for descriptive purposes only. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows a flowchart of a method of forming a semiconductor device according to various aspects of the present disclosure. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9 show cross-sectional views for forming a target semiconductor device according to the method of Fig. 1 according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] The present disclosure, in various embodiments, relates generally to semiconductor devices and methods of fabricating the same. More particularly, the present disclosure relates to forming raised epitaxial features in source and drain (S / D) regions of field-effect transistors (FETs). According to one embodiment, some of the raised epitaxial features are formed adjacent to (or contiguous to) isolation structures and include at least three layers of semiconductor materials. A first layer of semiconductor material (e.g., silicon germanium) is epitaxially grown from a trench partially surrounded by a semiconductor material (e.g., silicon). A second layer of semiconductor material (e.g., silicon) is epitaxially grown over the first layer and then etched to change a crystal facet orientation of at least a portion of its top surface.A third layer of semiconductor material (e.g., silicon) is epitaxially grown over the second layer, wherein the altered crystal facet of the second layer facilitates vertical growth of the third layer of semiconductor material. Advantageously, the third layer of semiconductor material achieves a desirable film thickness and facet for an S / D contact landing site. These and other embodiments of the present disclosure are described with reference to FIG. Fig. 1-9 further described.

[0008] Fig. 1 shows a flowchart of a method 100 for forming semiconductor devices according to the present disclosure. The method 100 is an example and is not intended to limit the present disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, and after the method 100, and some of the described operations may be replaced, removed, or rearranged for additional embodiments of the method. The method 100 is described below in connection with the Fig. 2-9, which illustrate cross-sectional views of a semiconductor device 200 during various manufacturing steps according to an embodiment of the method 100. The device 200 may be an intermediate device manufactured during processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs) and complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.Moreover, the various features, such as transistors, gate stacks, active regions, isolation structures, and other features, are provided in various embodiments of the present disclosure for convenience and ease of understanding and do not necessarily limit the embodiments to any type of device, number of devices, number of regions, or configuration of structures or regions.

[0009] With reference to Fig. 1, the method 100 provides, in operation 102, a structure (or semiconductor structure) 200 comprising a semiconductor substrate having various active regions for forming transistors, gate structures over the active regions, and isolation structures adjacent to the active regions. An embodiment of the structure 200 is shown in Fig. 2 shown.

[0010] Referring to Fig. 2, the structure 200 includes a substrate 202. The substrate 202, in the present embodiment, is a silicon substrate (e.g., comprising silicon in {110} crystal faces). Alternatively, the substrate 202 may include another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, the substrate 202 is a semiconductor-on-insulator (SOI).

[0011] The substrate 202 includes an active region 204 that is isolated from other active regions of the substrate 202 by isolation structures 212a and 212b. In the present embodiment, the active region 204 is a p-type field-effect transistor (FET) region, such as an n-well in a p-type substrate, for forming a PFET. In another embodiment, the active region 204 is an n-type FET region for forming an NFET. In yet another embodiment, the active region 204 includes both p-type FET region(s) and n-type FET region(s) for forming CMOS devices. In the present embodiment, the active region 204 includes various source and drain (S / D) regions 206a, 206b, and 206c and channel regions 208a and 208b disposed between a pair of S / D regions 206a-c. The S / D regions 206a-c may include lightly doped source / drain (LDD) features and / or heavily doped source / drain (HDD) features.For example, the LDD and HDD features may be formed by halo or lightly doped drain (LDD) implantation, source / drain implantation, source / drain activation, and / or other suitable techniques. In particular, the S / D region 206a is adjacent to the isolation structure 212a, the S / D region 206c is adjacent to the isolation structure 212b, and the S / D region 206b is entirely within the active region 204.

[0012] The isolation structures 212a and 212b are at least partially embedded in the substrate 202 and may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. The isolation structures 212a-b may be shallow trench isolation (STI) features. In one embodiment, the isolation structures 212a-b are STI features formed by etching trenches in the substrate 202, filling the trenches with one or more insulating materials, and planarizing the insulating materials using a chemical mechanical planarization (CMP) process. The isolation structures 212a-b may be other types of isolation features, such as field oxide and structures fabricated by local oxidation of silicon (LOCOS). The insulation structures 212a-b may have a multi-layer structure, for example, having one or more lining layers.

[0013] The structure 200 further includes various gate structures 220a, 220b, and 220c. In the present embodiment, the gate structures 220b and 220c are disposed over the active region 204, while the gate structure 220a is disposed over the isolation structure 212a. In particular, the gate structures 220b and 220c are disposed over the channel regions 208a and 208b, respectively, to form field-effect transistors. In one embodiment, the gate structure 220a functions as a local interconnect, for example, for connecting the S / D 206a to other parts of the device 200. The gate structure 220a includes a gate dielectric layer 222a, a gate electrode layer 224a, an L-shaped spacer 226a, and a sidewall spacer 228a. The gate structure 220b includes a gate dielectric layer 222b, a gate electrode layer 224b, an L-shaped spacer 226b, and a sidewall spacer 228b.The gate structure 220c includes a gate dielectric layer 222c, a gate electrode layer 224c, an L-shaped spacer 226c, and a sidewall spacer 228c.

[0014] The gate dielectric layers 222a-c may comprise a silicon oxide (SiO2) layer or a high-k dielectric layer such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), other suitable metal oxides, or combinations thereof. The gate dielectric layers 222a-c may be formed by ALD and / or other suitable methods.

[0015] In one embodiment, the gate electrode layers 224a-c comprise polysilicon. Alternatively, the gate electrode layers 224a-c comprise a metal such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials. The gate electrode layers 224a-c may be formed by CVD, PVD, plating, and / or other suitable methods.

[0016] The L-shaped spacers 226a-c may comprise a dielectric material such as silicon oxide, silicon oxynitride, another dielectric material, or combinations thereof. The sidewall spacers 228a-c may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, another dielectric material, or combinations thereof. The L-shaped spacers 226a-c and the sidewall spacers 228a-c may be formed by deposition (e.g., CVD) and etching techniques.

[0017] Each of the gate structures 220a-c may further include an interface layer beneath the respective gate dielectric layer, one or more dielectric hard mask layers over the respective gate electrode layer, and / or a workfunction metal layer. For example, the interface layer may include a dielectric material, such as a silicon oxide (SiO2) or silicon oxynitride (SiON) layer, and may be deposited by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and / or other suitable methods. For example, the hard mask layers may include silicon nitride, silicon oxynitride, and / or other suitable dielectric materials. For example, the workfunction metal layer may be a p-type or n-type workfunction layer.The p-type work function layer comprises a metal with a sufficiently high effective work function, which is selected, without limitation, from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work function layer comprises a metal with a sufficiently low effective work function, which is selected, without limitation, from the group consisting of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or combinations thereof. The work function metal layer may comprise a plurality of layers and may be deposited by CVD, PVD, and / or other suitable methods.

[0018] At operation 104, the process 100 ( Fig. 1) Trenches in the S / D regions 206a-c adjacent to the gate structures 208b-c. With reference to Fig. 3, trenches 230a, 230b, and 230c are formed in the S / D regions 206a, 206b, and 206c, respectively, for growing epitaxial features in subsequent steps. In the present embodiment, the process 104 includes several processes, such as a dry etching process, an ion implantation process, a wet etching process, and / or a cleaning process. For example, a dry (anisotropic) etching process may be performed to form substantially U-shaped trenches in the substrate 202. Then, ions, such as boron, are implanted into the active region 204 to change the crystal structure of a portion of the active region. Subsequently, a wet (isotropic) etching process is performed to expand the U-shaped trenches. The etching rate in the ion-implanted portion of the active region 204 is higher than in other portions. As a result, the U-shaped trenches are converted into hexagonal shapes like the one in Fig. 3. Then, a cleaning process may clean the trenches 230a-c with DHF, HF, or another suitable solution. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, a wet etching process may implement etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; TMAH solution; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or another suitable wet etchant. The etching processes are selective for the material of the substrate 202.In other words, the etching processes are tuned to remove the materials of substrate 202, but not the isolation structures 212a-b and the outer layers of the gate structures 220a-c. As a result, the trenches 230a and 230c do not have a hexagonal shape because one or more of their sidewalls are bounded by the isolation structures 212a and 212b, respectively.

[0019] With further reference to Fig. 3, trench 230a exposes a portion 232a of a sidewall (or side surface) of isolation structure 212a. Portion 232a becomes a sidewall of trench 230a. A sidewall 234a of trench 230a is opposite sidewall 232a with respect to a centerline of trench 230a. In the present embodiment, sidewall 234a is oriented in the (111) crystal plane. Similarly, trench 230c exposes a portion 232c of a sidewall of isolation structure 212b. Portion 232c becomes a sidewall of trench 230c. A sidewall 234c of trench 230c is opposite sidewall 232c with respect to a centerline of trench 230c. In the present embodiment, sidewall 234c is also oriented in the (111) crystal plane. Unlike trenches 230a and 230c, trench 230b is surrounded by one or more semiconductor materials of substrate 202 and, in this embodiment, has a hexagonal shape.The shapes of the trenches 230a-c may be obtained by tuning the parameters of the etching processes, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, RF bias voltage power, etchant flow rate, and other suitable parameters.

[0020] At operation 106, the process 100 ( Fig. 1) epitaxially deposit a first semiconductor layer 236 in the trenches 230a-c having features 236a, 236b and 236c. With reference to Fig. 4, the first semiconductor layers 236a and 236c only partially fill the trenches 230a and 230c, respectively, while the first semiconductor layer 236b completely fills the trench 230b in the present embodiment. The different volumes of the first semiconductor layers 236a-c are partly caused by the different materials on their sidewalls. Since the trench 230b ( Fig. 3) surrounded by semiconductor material(s), epitaxial growth of the first semiconductor layer 236b is promoted on all sides of the trench 230b. In contrast, epitaxial growth of the first semiconductor layers 236a and 236c is restricted by the isolation structures 212a and 212b, which comprise a dielectric material. As a result, the top surfaces (or side surfaces) 238a and 238c of the first semiconductor layers 236a and 236c, respectively, are tilted with respect to the top surface of the active region 204. In the present embodiment, the top surfaces 238a and 238c are oriented in the (111) crystal plane. Furthermore, the top surface of the first semiconductor layer 236b is oriented in the (001) crystal plane or an equivalent thereof. The semiconductor layers 236a and 236c may be formed depending on the profile of the trenches 230a and 230c and the distance between the sidewalls of the isolation structures 212a and 212b and the centerline of the trenches 230a and 230c, respectively.230c may be in contact with the insulation structures 212a or 212b, but do not have to be.

[0021] The first semiconductor layers 236a-c may be silicon, silicon-germanium (Si 1-x Ge x or simple SiGe) or other suitable semiconductor materials. In one embodiment, the first semiconductor layers 236a-c are formed by one or more selective epitaxial growth (SEG) techniques. In one embodiment, the SEG technique is a low-pressure vapor deposition (LPCVD) technique using a silicon-based precursor gas. Alternatively, the first semiconductor layers 236a-c may be formed by cyclic deposition and etch (CDE) epitaxy, molecular beam epitaxy (MBE), or other suitable epitaxy techniques.

[0022] In process 108, the process 100 ( Fig. 1) the first semiconductor layers 236a-c with one or more suitable dopants. In one embodiment, the first semiconductor layers 236a-c comprise silicon germanium (SiGe) for applying voltage and improving charge carrier mobility for PMOS devices. In an extension of this embodiment, process 108 dopes the silicon germanium layers 236a-c with a p-type dopant, for example, boron. The doping of the silicon germanium layers 236a-c may be performed in situ. In this case, processes 106 and 108 are performed concurrently. For example, the epitaxial growth process may use boron-containing gases such as diborane (B2H6), other p-type dopant-containing gases, or a combination thereof to in situ dope the silicon germanium layers 236a-c with a p-type dopant.Alternatively, if the silicon-germanium layers 236a-c are not doped during the epitaxial growth process, they may be doped in a subsequent process (ex situ), for example, by an ion implantation process, a plasma immersion ion implantation (PIII) process, other processes, or a combination thereof. In this case, the process 108 is performed after the process 106. An annealing process, such as a rapid thermal anneal and / or a thermal laser anneal, may be performed to activate the dopants in the silicon-germanium layers 236a-c.

[0023] In another embodiment, the first semiconductor layers 236a-c include silicon for applying voltage and improving charge carrier mobility for NMOS devices. Extending this embodiment, process 108 dopes the silicon layers 236a-c with an n-type dopant, such as phosphorus, arsenic, or combinations thereof. Similar to the above description, the doping of the silicon layers 236a-c can be performed in situ or ex situ.

[0024] At operation 110, the process 100 ( Fig. 1) epitaxially a second semiconductor layer 240 having features 240a, 240b and 240c over the first semiconductor layers 236a-c. With reference to Fig. 5, the second semiconductor layers 240a-c are disposed over the top surfaces of the first semiconductor layers 236a-c. In the present embodiment, the second semiconductor layers 240a-c comprise silicon. In alternative embodiments, the second semiconductor layers 240a-c comprise another elemental, compound, or alloy semiconductor material. In the present embodiment, the second semiconductor layer 240a has a top surface 242a (which is also a side surface) oriented in the (111) crystal plane, the second semiconductor layer 240b has a top surface 242b oriented in the (001) crystal plane or one of its equivalents, and the second semiconductor layer 240c has a top surface 242c (which is also a side surface) oriented in the (111) crystal plane.In certain embodiments, the second semiconductor layers 240a-c may be epitaxially grown using SEG, MBE, CDE, or other suitable epitaxial growth techniques. For example, the second semiconductor layers 240a-c may be epitaxially grown using a silicon-containing precursor gas such as SiH2Cl2 (DCS).

[0025] Note that the first and second semiconductor layers 236 and 240 still only partially fill the trenches 230a and 230c because epitaxial growth there is limited by the isolation structures 212a-b. If S / D contact features were formed directly above the second semiconductor layer 240a-c, the contact features would not land properly on features 240a and 240c due to the tilted surfaces, which could lead to defective devices (e.g., open circuits). Furthermore, features 240a and 240c are thinner than feature 240b, measured along a direction perpendicular to the respective top surfaces 242a, 242b, and 242c. This is because the second semiconductor layer 240 (e.g., silicon) has a lower growth rate in the (111) crystal plane than in the (001) crystal plane. Therefore, layers 240a and 240c may not have sufficient thickness for S / D contact formation.For example, the S / D contact hole etch may completely penetrate layers 240a and 240c, resulting in increased S / D contact resistance. On the other hand, continuing to grow layers 240a-c may cause overgrowth of layer 240b, which may result in shorting layer 240b to adjacent circuit features (not shown). In the present embodiment, method 100 performs a few subsequent processes to address the above issues.

[0026] At operation 112, the process 100 etches ( Fig. 1) the second semiconductor layer 240 to change a crystal facet orientation of at least a portion of the surfaces 242a and 242c. With reference to Fig. 6, process 112 creates new surfaces 244a, 244b, and 244c on the second semiconductor layers 240a, 240b, and 240c, respectively. The crystal facet orientation of surface 244b is approximately the same as that of surface 242b, although layer 240b may be reduced in thickness along the Z direction, which is perpendicular to the top surface of the active region 204. Surfaces 244a and 244c have a different crystal facet orientation than surfaces 242a and 242c, respectively. In the present embodiment, both surfaces 242a and 242c are in the (111) crystal plane, and both surfaces 244a and 244c are in the (311) crystal plane, or their equivalents (131) and (113).In various embodiments, both surfaces 244a and 244c may be oriented in one of the crystal planes (311), (511), (711), (911), (131), (151), (171), (191), (113), (115), (117), and (119), which are also referred to as {311}, {511}, {711}, and {911} for convenience. In the present embodiment, process 112 etches second semiconductor layer 240 using a chemical comprising hydrogen chloride (HCl). Alternatively, process 112 may use a different chemical, such as a hydride (e.g., HCl, HBr, HI, or HAt). The chemical etches the top corner of layers 240a and 240c (see FIG. Fig. 5) faster than it etches the lower body of layers 240a and 240c, forming surfaces 244a and 244c. Furthermore, the chemical is tuned to selectively etch the second semiconductor layer 240, but not the gate structures 220a-c and the isolation structures 212a-b in the present embodiment.

[0027] At operation 114, the process 100 ( Fig. 1) epitaxially depositing a third semiconductor layer 246 including features 246a, 246b and 246c over the second semiconductor layer 240a-c ( Fig. 7). The third semiconductor layer 246 may comprise silicon or one or more other suitable semiconductor materials. In various embodiments, the process 114 may grow the third semiconductor layer 246 using SEG, MBE, CDE, or other epitaxial techniques. For example, the process 114 may epitaxially grow the third semiconductor layer 246 using a silicon-containing precursor gas such as SiH2Cl2 (DCS) with 1% B2H6 gas.

[0028] With reference to Fig. 7, in the present embodiment, features 246a-c have multiple facets in their respective outer surfaces. For example, feature 246a has a side surface 247a and a top surface 248a. In one embodiment, side surface 247a is oriented in the (111) crystal plane, and top surface 248a is oriented in the (001) crystal plane or an equivalent thereof, which is parallel to a top surface of active region 204. Side surface 247a merges into top surface 248a via one or more facets. The thickness of layer 246a increases from a lower portion (adjacent isolation structure 212a) to an upper portion (above the top surface of active region 204).

[0029] Similarly, feature 246c includes a side surface 247c and a top surface 248c. In one embodiment, side surface 247c is oriented in the (111) crystal plane, and top surface 248c is oriented in the (001) crystal plane or an equivalent thereof, which is parallel to the top surface of active region 204. The thickness of layer 246c increases from a lower portion (adjacent isolation structure 212b) to an upper portion (above the top surface of active region 204). Feature 246b, in the present embodiment, provides a top surface 248b oriented in the (001) crystal plane.

[0030] The second and third semiconductor layers 240a-c and 246a-c together provide a desirably thick semiconductor layer for S / D contact landing sites. In particular, the top surfaces 248a and 248c provide a flat or nearly flat surface for supporting S / D contacts formed thereon.

[0031] In process 116, the process allocates 100 ( Fig. 1) the third semiconductor layers 246a-c with one or more suitable dopants. The third semiconductor layers 246a-c may be doped in situ (in which case, operations 116 and 114 are performed simultaneously) or ex situ (in which case, operation 116 is performed after operation 114), as described above with respect to operation 108. In an exemplary embodiment, the third semiconductor layers 246a-c comprise silicon and are doped in situ with boron using boron-containing gases such as diborane (B2H6) during the epitaxial growth process.

[0032] In the present embodiment, the dopant applied to the third semiconductor layers 246a-c is of the same type as the dopant(s) applied to the first semiconductor layers 236a-c. For example, they are both p-type dopant(s) or both n-type dopant(s). In another embodiment, the first and third semiconductor layers 236a-c and 246a-c are doped with the same dopant, but layers 246a-c have a higher dopant concentration than layers 236a-c. One purpose of this configuration is to reduce the contact resistance between the layers 246a-c to be formed thereon and the S / D contact features. In one example, the first semiconductor layers 236a-c comprise silicon germanium doped with boron with a boron concentration in the range of 1E17 to 1E20 atoms / cm 3 and the third semiconductor layers 246a-c boron, which has a boron concentration in the range of 1E20 to over 1E21 atoms / cm3 doped. Note that the second semiconductor layers 240a-c may be intentionally undoped. In some embodiments, the dopants in the layers 236a-c and 246a-c may diffuse into the second semiconductor layers 240a-c, whereby the second semiconductor layers 240a-c are still doped. In some embodiments, the dopant concentration of the second semiconductor layers 240a-c is lower than that of the third semiconductor layers 246a-c, at least at the boundary of the first and second semiconductor layers, and also lower than that of the first semiconductor layers 236a-c. In one example, the second semiconductor layers 240a-c comprise silicon doped with boron, with a boron concentration in the range of 1E19 to 1E20 atoms / cm 3 .

[0033] With further reference to Fig. 7, the method 100 has formed three epitaxial semiconductor layers 236a-c, 240a-c, and 246a-c. In particular, in each of the S / D regions 206a-c ( Fig. 1) a three-layer epitaxial structure is formed. In the S / D region 206a, the three-layer epitaxial structure comprises layers 236a, 240a, and 246a, which adjoin the isolation structure 212a. In particular, the two layers 240a and 246a are in direct contact with the isolation structure 212a. In the S / D region 206b, the three-layer epitaxial structure comprises layers 236b, 240b, and 246b, which are surrounded by semiconductor material(s). In the S / D region 206c, the three-layer epitaxial structure comprises layers 236c, 240c, and 246c, which adjoin the isolation structure 212b. In particular, the two layers 240c and 246c are in direct contact with the isolation structure 212b.In one embodiment, the first semiconductor layers 236a-c have a thickness in the range of 20 to 40 nm, the second semiconductor layers 240a-c have a thickness in the range of 2 to 10 nm, and the third semiconductor layers 246a-c have a thickness in the range of 5 to 10 nm.

[0034] In process 118, the procedure 100 ( Fig. 1) an interlayer dielectric (ILD) layer 250 over the substrate 202, the gate structures 220a-c, the isolation structures 212a-b and the third semiconductor layers 246a-c of ( Fig. 8). In one embodiment, prior to forming the ILD layer 250, the method 100 forms an etch stop layer (not shown) over the various structures. Examples of materials that may be used to form the etch stop layer include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials. The etch stop layer may be formed by a PECVD process and / or other suitable deposition or oxidation techniques. The ILD layer 250 may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 250 may be deposited by a PECVD process, a flowable CVD process, or another suitable deposition technique.

[0035] At process 120, the procedure 100 ( Fig. 1) conductive features 252a-c in the ILD layer 250 and electrically contacts the third semiconductor layers 246a-c, respectively. With reference to Fig. 9, the conductive feature 252b is disposed on a flat surface of the third semiconductor layer 246b, and the conductive features 252a and 252c are disposed on a relatively flat and thick portion of the third semiconductor layers 246a and 246c, respectively. This advantageously provides good contact between the respective conductive feature and the semiconductor layer and reduces their contact resistance. The process 120 may include a variety of methods, including etching contact holes to expose the third semiconductor layers 246a-c and depositing the conductive structures 252a-c in the contact holes. Each of the contact features 252a-c may include multiple layers, such as a barrier / adhesion layer and a metal fill layer over the barrier / adhesion layer. For example, the barrier / adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or other suitable materials.The barrier / adhesion layer can be formed by CVD, PVD, or other suitable processes. For example, the metal fill layer can comprise aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials. The metal fill layer can be formed by CVD, PVD, plating, and / or other suitable processes.

[0036] At operation 122, the procedure 100 ( Fig.1) Apply further manufacturing steps to the structure 200 to form a finished IC product. For example, the method 100 may perform a gate replacement process. The gate replacement process replaces the gate dielectric layers 222a-c and the gate electrode layers 224a-c, which in one embodiment are originally made of silicon oxide and polysilicon, with high-k gate dielectric layers and metal gate electrode layers. The gate replacement process may be performed before or after process 120. For another example, the method 100 may form gate contacts over the gate structures 220a-c. The gate contacts may be formed before, during, or after process 120. For yet another example, the method 100 may form an interconnect structure connecting the gate structures 220a-c, the conductive features 252a-c, and other portions of the device 200 (not shown).In a particular example, the interconnect structure may connect the gate structure 220a to the conductive feature 252a, in which case the gate structure 220a serves as a local interconnect for electrically connecting the S / D features (236a / 240a / 246a) to source, drain, or gate terminals of another transistor.

[0037] Without limitation, one or more embodiments of the present disclosure provide numerous advantages for a semiconductor device and its design. For example, embodiments of the present disclosure provide a three-layer epitaxial feature. The three-layer epitaxial feature provides good landing surfaces for S / D contacts, resulting in reduced contact resistance of the S / D contacts.

[0038] In one exemplary aspect, the present disclosure relates to a method for semiconductor manufacturing. The method comprises providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, wherein the active region comprises source and drain regions between which a channel region for a transistor is arranged, wherein the semiconductor structure further comprises a gate structure over the channel region.The method further comprises etching a trench in the source or drain region, the trench exposing a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystal facet orientation of a portion of an upper surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after changing the crystal facet orientation.

[0039] In another exemplary aspect, the present disclosure relates to a method for manufacturing a semiconductor device. The method comprises providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, wherein the active region has a source and a drain region between which a channel region for a transistor is arranged, wherein the semiconductor structure further comprises a gate structure above the channel region. The method further comprises etching a trench in the source or drain region, wherein a first side surface of the trench is part of a sidewall of the isolation structure and wherein a second side surface of the trench is oriented in the (111) crystal plane.The method further comprises epitaxially growing a first semiconductor layer in the trench and epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein a top surface of the second semiconductor layer is oriented in the (111) crystal plane. The method further comprises etching the second semiconductor layer, thereby changing the crystal facet orientation of a portion of the top surface of the second semiconductor layer. The method further comprises epitaxially growing a third semiconductor layer over the second semiconductor layer after etching the second semiconductor layer.

[0040] In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device comprises a substrate having an active region, the active region having a source and a drain region between which a channel region is arranged. The semiconductor device further comprises a gate structure over the channel region, an isolation structure at least partially embedded in the substrate, a first semiconductor layer embedded in a trench in the source or drain region, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer. Both the second and third semiconductor layers are in direct contact with the isolation structure.A first side surface of the second semiconductor layer is oriented in the (111) crystal plane and a second side surface of the second semiconductor layer is oriented in the {311}, {511}, {711} or {911} crystal plane.

[0041] The foregoing describes features of several embodiments so that one skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis to design or modify other methods and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit of the present disclosure and that they may make various changes, substitutions, and modifications herein without departing from the spirit of the present disclosure.

Claims

[1] Method comprising: Providing a semiconductor structure (200) having an active region (204) and an isolation structure (212) adjacent to the active region, wherein the active region comprises source and drain regions (206) between which a channel region (208) for a transistor is arranged, the semiconductor structure further comprising a gate structure (220) above the channel region; Etching a trench (230) in the source or drain region, the trench exposing a portion of a sidewall (232) of the isolation structure; epitaxially growing a first semiconductor layer (236) in the trench; epitaxially growing a second semiconductor layer (240) over the first semiconductor layer; Changing a crystal facet orientation of a portion of a top surface (242) of the second semiconductor layer by an etching process; after changing the crystal facet orientation, epitaxially growing a third semiconductor layer (246) over the second semiconductor layer, wherein a first side surface (242a) of the second semiconductor layer is oriented in the (111) crystal plane and a second side surface (244a) of the second semiconductor layer is oriented in the (311), (511), (711) or (911) crystal plane; and wherein an upper surface (248a) of the third semiconductor layer (246) is parallel to an upper surface of the active region (204). [2] The method of claim 1, wherein the first semiconductor layer (236) comprises silicon germanium. [3] The method of claim 1 or 2, further comprising: Doping the first semiconductor layer (236) with a p-dopant before epitaxially growing the second semiconductor layer (240). [4] A method according to any one of the preceding claims, wherein both the second and third semiconductor layers (240, 246) comprise silicon. [5] Method according to one of the preceding claims, further comprising: Doping the third semiconductor layer (246) with the p-dopant. [6] The method of any preceding claim, wherein the third semiconductor layer (246) is doped with a higher concentration of the p-dopant than the first semiconductor layer (236). [7] A method according to any one of the preceding claims, wherein prior to changing the crystal facet orientation, the portion of the upper surface (244) of the second semiconductor layer (240) is oriented in the (111) crystal plane, and after changing the crystal facet orientation, the portion of the upper surface (244) of the second semiconductor layer (240) is oriented in one of the following crystal planes: (311), (511), (711), (911), (131), (151), (171), (191), (113), (115), (117), and (119). [8] Method according to one of the preceding claims, further comprising: Forming an interlayer dielectric layer, hereinafter referred to as ILD layer, (250) over the third semiconductor layer (246); and Forming a contact feature (252) in the ILD layer (250) and contacting the third semiconductor layer (246). [9] A method according to any one of the preceding claims, wherein the etching process uses a chemical containing hydrogen chloride. [10] A method comprising: Providing a semiconductor structure (200) having an active region (204) and an isolation structure (212) adjacent to the active region, wherein the active region has a source and a drain region (206) between which a channel region (208) for a transistor is arranged, wherein the semiconductor structure (200) further has a gate structure (220) above the channel region; Etching a trench (230) in the source or drain region, wherein a first side surface of the trench is part of a sidewall (232) of the isolation structure (212) and wherein a second side surface (224) of the trench is oriented in the (111) crystal plane; epitaxially growing a first semiconductor layer (236) in the trench; epitaxially growing a second semiconductor layer (240) over the first semiconductor layer (236), wherein a top surface (242) of the second semiconductor layer is oriented in the (111) crystal plane; Etching the second semiconductor layer (240), thereby changing the crystal facet orientation of a portion of the upper surface (242, 244) of the second semiconductor layer; and after etching the second semiconductor layer (240), epitaxially growing a third semiconductor layer (246) over the second semiconductor layer (240), wherein a first side surface (242a) of the second semiconductor layer is oriented in the (111) crystal plane and a wide side surface (244a) of the second semiconductor layer is oriented in the (311), (511), (711) or (911) crystal plane; wherein an upper surface (248a) of the third semiconductor layer (246) is parallel to an upper surface of the active region (204). [11] The method of claim 10, wherein after etching the second semiconductor layer (240), the crystal facet orientation of the portion of the upper surface (244) of the second semiconductor layer is in one of the following crystal faces: {311}, {511}, {711} and {911}. [12] The method of claim 10 or 11, wherein the first semiconductor layer (236) comprises silicon germanium doped with boron. [13] The method of any one of claims 10 to 12, wherein each of the second and third semiconductor layers (240, 246) comprises boron-doped silicon. [14] The method of any one of claims 10, 11, or 13, wherein the first semiconductor layer (236) comprises silicon doped with an n-type dopant. [15] The method of any one of claims 10 to 14, wherein etching the second semiconductor layer (240) uses a chemical containing hydrogen chloride. [16] A semiconductor device (200) comprising: a substrate (202) having an active region (204), the active region having a source and a drain region (206) between which a channel region (208) is arranged; a gate structure (220) over the channel region; an insulation structure (212) at least partially embedded in the substrate; a first semiconductor layer (236) embedded in a trench (230) in the source or drain region (206); a second semiconductor layer (240) over the first semiconductor layer (236); and a third semiconductor layer (246) over the second semiconductor layer (240), wherein both the second and the third semiconductor layer are in direct contact with the isolation structure (212), wherein a first side surface (242a) of the second semiconductor layer is oriented in the (111) crystal plane and a second side surface (244c) of the second semiconductor layer is oriented in the (311), (511), (711) or (911) crystal plane; wherein an upper surface (248a) of the third semiconductor layer (246) is parallel to an upper surface of the active region (204). [17] A semiconductor device according to claim 16, further comprising: an interlayer dielectric layer, hereinafter referred to as ILD layer, (250) over the active region (204), the isolation structure (212) and the gate structure (220); and a conductive feature (252) embedded in the ILD layer (250) and contacting the third semiconductor layer (246). [18] A semiconductor device according to claim 16 or 17, further comprising: a further gate structure (220) above the insulation structure (212). [19] A semiconductor device according to any one of claims 16 to 18, wherein the first semiconductor layer (236) comprises silicon germanium doped with a p-type dopant, and both the second and third semiconductor layers (240, 246) comprise silicon doped with the p-type dopant.

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