CONFIGURABLE CLAMPING CIRCUIT AND METHOD

Abstract

Circuit that has: a configurable clamp driver circuit (300, 400) for clamping a voltage at a gate terminal of a first transistor (Q1) below a turn-on voltage threshold when the first transistor (Q1) is turned off, the clamp driver circuit (300, 400) being configured to operate in one of two modes, wherein: in a first operating mode of the two operating modes, an output terminal (CLAMP) of the clamp driver circuit (300, 400) is configured to be coupled to a gate terminal of the first transistor (Q1) to provide a first discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor is turned off, wherein the first discharge path bridges a resistor coupled to the gate terminal of the first transistor (Q1); and in a second operating mode of the two operating modes, the output terminal (CLAMP) of the clamp driver circuit (300, 400) is designed to be coupled to an input terminal of a clamp circuit (328), wherein the clamp circuit (328) is coupled to the gate terminal of the first transistor in order to provide a second discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor (Q1) is turned off, wherein the second discharge path bridges the resistor coupled to the gate terminal of the first transistor (Q1), wherein the terminal driver circuit (300, 400) has an output stage with a pull-up circuit coupled between a first power supply terminal and the output terminal (CLAMP) of the terminal driver circuit (300, 400), and a pull-down circuit coupled between a second power supply terminal and the output terminal (CLAMP) of the terminal driver circuit (300, 400), and wherein the circuit further comprises a voltage regulation circuit coupled between a power supply terminal and the output stage of the terminal driver circuit (300, 400).

Description

[0001] The present invention relates generally to the field of semiconductor electronics and, in certain embodiments, to the technical field of clamping circuits.

[0002] Gate driver circuits are widely used in many electronic applications, from computers to automobiles to solar power generation. A gate driver circuit can be used to implement part of a switched-mode circuit, including, for example, a switched-mode power supply or other switched-mode circuit. In many cases, voltages are generated within a switched-mode circuit system by performing DC-DC, DC-AC, and / or AC-DC conversion through the operation of a gate driver circuit coupled to a switch. The switch itself can be coupled to an inductor, transformer, motor, etc. Switched-mode circuits can also be implemented using a gate driver circuit to drive the gates of one or more switching transistors, such as IGBT or MOSFET power devices.However, parasitic turn-on or re-turn-on of the controlled switching transistor can be an undesirable phenomenon for gate driver circuits in many situations. Parasitic turn-on is a physical effect that can occur due to a rapid voltage change across the controlled switching transistor in combination with a parasitic gate-collector capacitance or gate-drain capacitance of the switching transistor, which parasitic capacitance is also known as Miller capacitance. For example, the rapid voltage change across a parasitic Miller capacitance of the switching transistor can generate a parasitic current, which in turn generates a parasitic voltage at the gate of the switching transistor. If the voltage raises the gate above the threshold voltage of the switching transistor, the switching transistor can be turned on even if the switching transistor is designed to be turned off.This parasitic turn-on can generate an overcurrent and can affect the efficiency and operation of the circuit. In some cases, a clamp circuit may be implemented in the gate driver circuit to reduce or eliminate effects due to parasitic turn-on.

[0003] US 8 994 437 B2 describes a driver circuit with a plurality of transistor half-bridges, which can be configured such that one half-bridge is used to switch a transistor on and off, or which can be configured such that one half-bridge is used to switch a transistor on and another half-bridge is used to drive an auxiliary transistor which is designed to switch the transistor off.

[0004] US 2015 / 0 085 403 A1 describes a motor control circuit with three transistor half bridges.

[0005] Embodiments of the invention relate to circuits according to claims 1 and 2, integrated circuits according to claims 12 and 13 and a method according to claim 21.

[0006] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram of a gate driver circuit coupled to a switching transistor; Fig. 2A-2B show embodiments of a gate driver circuit having a configurable clamp; Fig. 3A-3B show embodiments of a gate driver circuit having a configurable clamp with a voltage regulation subcircuit; and Fig. 4A-4B show embodiments of a gate driver circuit having a configurable clamp with a voltage limiting subcircuit.

[0007] Before embodiments of the present invention are explained in more detail below with reference to the figures, it should be noted that the same and functionally equivalent elements are provided with the same reference numerals in the figures, and a repeated description of these elements is omitted. Therefore, the description of the elements provided with the same reference numerals is interchangeable and / or applicable in the various embodiments.

[0008] In one embodiment, a configurable clamp driver can be configured to be either an integrated open-drain clamp or a gate driver driving an external discrete clamp transistor. The configurable clamp driver can be configurable, for example, through programmable logic, fuses, or metal change. In this way, a single clamp driver can be used as an electrical clamp driver or as a clamp itself. The configurable clamp driver can be coupled, for example, to a switching transistor, a power device, or a switching circuit.

[0009] Fig. 1 shows a circuit diagram of an example gate driver circuit 100 subject to parasitic turn-on. The example clocked circuit 100 includes a clocked driver 102 coupled to and configured to drive an output stage including a power device Q1. The power device Q1 is shown as an IGBT, although in other cases Q1 may be a different type of power device such as a power MOSFET, a silicon carbide MOSFET, a JFET, a HEMT, or the like, or a combination of power devices. The gate terminal 106 of Q1 is connected to the gate terminal 106 via a gate resistor R G coupled to the clocked driver 102. An example collector node 110 is shown coupled to the collector of Q1, and an example emitter node 112 is shown coupled to the emitter of Q1. Also in Fig. 1 shows a parasitic Miller capacitance C GCbetween the collector node 110 and the gate 106 of Q1. In some cases, Q1 may be paired with an additional power device (not shown) as part of a half-bridge topology. For example, the additional power device may be coupled to the collector node 110. In some cases, Q1 may be coupled to the driver 102 via an external amplifier (not shown).

[0010] In some cases, turning on a paired device (e.g., the additional power device coupled to Q1 described above) can cause a rapid voltage change between the collector node 110 and the emitter node 112 of Q1. For example, this voltage can be triggered by turning on the additional paired device in a half-bridge topology and by a load current flowing through a freewheeling diode of Q1 before the paired device is fully turned on. This high d VCE / dt across Q1 can generate a current I DIS by the parasitic Miller capacitor C GC generate. The current I DIS can then be accessed via R G create a voltage drop that increases the voltage at the gate 106. In this illustrative example, the current I DIS by the pull-down device 118 of the driver 102, which has a resistor R DSoff to VEE2. The voltage V generated at the gate terminal 106 G relative to the emitter node 112 can be calculated according to equations (1) and (2): IDIS=CGC*dVCE / dt VG=VVEE2+IDIS*(RG+RDSoff).

[0011] If V G higher than the threshold voltage of the power device Q1, Q1 is parasitically turned on. This dynamic turn-on of Q1 continues until the regular discharge path through R G the increased gate voltage V GIn some cases, the inductance of the connections between driver 102 and Q1 can increase a parasitic turn-on effect. For example, increased connection inductance can correspondingly increase the high-frequency impedance seen from the gate of Q1 to driver 102. A high-frequency current I DIS This increased high-frequency impedance also increases the voltage V generated on the gate terminal 106 G , which can parasitically turn on Q1. In some cases, the inductance of the connections between driver 102 and Q1 increases the time it takes for the discharge current to reach V G below the threshold. Parasitic turn-on can compromise the safety and efficiency of the system. For example, in some cases, a current shoot-through could occur between Q1 and a paired component, which could reduce efficiency and even damage the component itself.

[0012] The Fig. 2A-2B show circuit diagrams of a configurable clamp circuit 200 according to an embodiment of the present invention. The configurable clamp circuit 200 may be part of another circuit, such as a driver circuit such as that shown in Fig. 1. The configurable clamp circuit 200 includes a first driver transistor NM1 and a second driver transistor PM1. In some embodiments, the function of the second driver transistor PM1 can be implemented by a pull-up circuit using an n-channel MOSFET or a combination of n-channel and p-channel MOSFETs. Both NM1 and PM1 are coupled to a CLAMP pin coupled to the gate node 202 of a power device Q1. In the embodiments shown in the Fig. In the embodiments shown in Figures 2A-2B, Q1 is shown as an IGBT, although in other embodiments, Q1 may be a different type of power device as described above. According to one embodiment, the configurable clamp circuit 200 operates in one of two clamping configurations. In the embodiment shown in Fig. In the first configuration shown in Figure 2A, the external clamping transistor T1 is present and is used as a clamping transistor to shunt a parasitic current from the gate of Q1. Fig. In the configuration shown in Figure 2B, the external clamp transistor T1 is omitted, and the driver transistor NM1 is used as a clamp transistor to shunt a parasitic current from the gate of Q1. Each configuration is described in more detail below.

[0013] At the Fig. 2A, the voltage V Gat the gate node 202 of Q1 via the OUTH and OUTL pins. The OUTH and OUTL pins can be part of the configurable clamp circuit 200 or part of a separate gate driver circuit. To turn Q1 on, the OUTH pin injects current into the gate node 202, which increases the voltage V G above the threshold voltage of Q1. To turn Q1 off, the OUTL pin sinks current from the gate node 202, which raises the voltage V G below the threshold voltage of Q1. In some cases, the voltage V G at gate node 202 is monitored whenever Q1 is nominally off. When the voltage V Gdrops below a predetermined clamping voltage, the configurable clamp circuit 200 activates a clamping transistor T1, which provides a low-impedance path parallel to OUTL and shunts current away from the gate node 202. In some cases, the clamping transistor T1 is activated when Q1 is nominally off, without the voltage V G to monitor. In this way, in the event of parasitic turn-on, a parasitic current is effectively dissipated by the gate node 202, thereby eliminating or reducing the extent of parasitic turn-on. The clamp transistor T1 can remain activated until Q1 is turned on again. In some cases, this can be referred to as an "active Miller clamp" circuit, in which an additional low-side output of the driver R Gbridged to reduce the resistance between the gate terminal 202 and a current sink (typically a reference voltage node). For example, the clamping transistor can shunt the current to GND2 for a unipolar device implementation, to VEE2 for a bipolar device implementation, or to another node in another implementation. The voltage V G at the gate node 202 can be monitored, for example, by a comparator circuit or other circuit (not shown) coupled to the configurable clamp circuit 200. The voltage V G can be monitored, for example, via the OUTH pin, the CLAMP pin, or via another pin or node. The clamp voltage value of V Gcan be configured as a voltage less than the threshold voltage of Q1. For example, in some embodiments, the clamp voltage value may be a voltage relative to GND2, such as GND2+2V, GND2+3V, or another voltage difference relative to GND2 or another voltage, such as VEE2. In other embodiments, the clamp voltage value may be a fixed reference voltage or a voltage difference relative to another voltage, node, or pin.

[0014] In the first configuration of the embodiment, the gate terminal 210 of the external clamp transistor T1 is coupled to the driver transistors NM1 and PM1 via the CLAMP pin. The source terminal 212 of T1 is coupled to the voltage reference VEE2, although in other embodiments, the source terminal 212 may be coupled to a different voltage reference or node, such as GND or another voltage reference. The drain terminal 214 of T1 is coupled to the gate terminal 202 of Q1. Therefore, the driver transistors NM1 and PM1 can operate to turn on T1 and provide a low-impedance path through T1 that shunts a parasitic current through T1 to VEE2. In some embodiments, the external clamping transistor T1 may be a p-type or p-channel MOSFET, an n-type or n-channel MOSFET, another type of transistor, or a circuit including multiple transistors.In some embodiments, the external clamping transistor T1 is a low voltage transistor in which a VGS has a maximum voltage of about 15 to 20 V.

[0015] At the Fig. In the second configuration shown in Figure 2B, the external clamp transistor T1 is not present, and the drain terminal 216 of NM1 is directly coupled to the gate terminal 202 of Q1 via the CLAMP pin. In the second configuration, transistors NM1 and PM1 are not used as driver transistors. Specifically, PM1 is disabled, and only NM1 is used. Therefore, the configurable clamp circuit 200 can operate, for example, to turn on transistor NM1 and shunt a parasitic current through NM1 to VEE2.

[0016] The configuration of the configurable clamp circuit 200 (ie whether it is in the Fig. 2A shown first configuration or in the Fig. 2B) may be controlled by one or more control signals. The control signals may, for example, be provided by other circuits or logic within an integrated circuit. According to one example, the Fig. 2A-2B, the control signal clamp_driver_i can be a logic signal voltage such as a high voltage (such as 1V, 3.3V, 5V or another voltage) or a low voltage (such as 0V). Fig. In the embodiment shown in Figures 2A-2B, a high voltage on clamp_driver_i may signal that the configurable clamp circuit is operating in the first configuration (i.e., as a driver for an external clamp transistor). Similarly, a low voltage on clamp_driver_i may signal that the configurable clamp circuit 200 is operating in the second configuration (i.e., as a clamp transistor). In some cases, a control signal value corresponding to the configurable clamp circuit 200 configuration may be stored in a memory register.

[0017] In some cases, the operation of the clamping transistor (ie T1 in the first configuration example of Fig. 2A or NM1 in the second configuration example of Fig. 2B) can also be controlled by a control signal. For example, in one embodiment, a high voltage on clamp_i turns on the clamping transistor to shunt the excess current away from the gate terminal 202 of Q1. On the other hand, a low voltage on clamp__i turns off the clamping transistor.

[0018] In some embodiments, the control signals may be input to the Fig. 2A-2B are coupled to NM1 and PM1. The logic subcircuit 220 is coupled to other circuits or logic of the integrated circuit and couples clamp_driver_i and clamp_i to NM1 and PM1. The logic subcircuit 220 switches NM1 and PM1 on and off as appropriate depending on the configuration (as indicated by clamp_driver_i) and whether the clamp is desired to be turned on (as indicated by clamp_i). In some cases, additional logic may be employed, such as additional inverters 222, which may be used to maintain the appropriate logical meaning of clamp_i in the first configuration. In some cases, other circuitry may be coupled between the control signals and the driver transistors. For example, as shown in the Fig. As shown in Figures 2A-2B, a level shifter 224 may be implemented between logic subcircuit 220 and the gate terminal of PM1 to appropriately adjust the voltage of the control signal. However, logic subcircuit 220 is merely an example; other logic subcircuits or circuit configurations may be used in other embodiments.

[0019] In some cases where the configurable clamp circuit 200 is in the first configuration, voltage limiting may be desired to limit the voltage at the gate terminal 210 of the external clamp transistor T1 to reduce the risk of high-voltage damage to T1 during turn-on of T1. Fig. 3A-3B show schematic diagrams of an embodiment that includes a voltage regulator circuit 330 to limit the voltage at the gate terminal 328, and the Fig. 4A-4B show schematic diagrams of an embodiment that includes a voltage limiter circuit 450 to limit the voltage at the gate terminal 428. In the Fig. 3A-3B and the Fig. The embodiments shown in Figures 4A-4B are examples; other configurable clamp circuits may have other implementations or configurations for regulating or limiting the gate voltage of T1.

[0020] The design of the Fig. 3A-3B is similar to the configurable clamp circuit 200 of Fig. 2A-2B except that the Fig. The configurable clamp circuit 300 shown in Figures 3A-3B includes an example voltage regulation subcircuit 330 between the external power supply VCC2 and the driver transistors PM1 and NM1. A level shifter 334 within the voltage regulation subcircuit 330 is coupled to clamp_driver_i through the logic subcircuit 320. Fig. 3A shows the configurable clamp circuit 300 in the first configuration and Fig. 3B shows the configurable clamp circuit 300 in the second configuration. The voltage regulation subcircuit 330 is configured to maintain a voltage VREF at the source terminal 326 of PM1. Therefore, since the external clamp transistor T1 is controlled by PM1 and NM1, the maximum voltage at the gate terminal 328 of T1 is limited to VREF even during a turn-off of T1. When the configurable clamp circuit 300 is in the Fig. 3B, the voltage regulation subcircuit 330 is deactivated, the source terminal 326 of PM1 is pulled to VCC2, and therefore PM1 is deactivated. Otherwise, the operation is essentially the same as that shown in Fig. 2B. In some cases, a VREG pin may be coupled to the source terminal 326, and an external decoupling capacitor 340 may couple the VREG pin to VEE2 or another reference voltage. In the Fig. The voltage regulation subcircuit 330 shown in Figures 3A-3B uses an NMOS as the pass element, although other embodiments may use a PMOS as the pass element. Voltage regulation subcircuit 330 is only an example; other embodiments may use different voltage regulation subcircuits or circuit configurations.

[0021] The Fig. The configuration of the configurable clamp circuit 400 shown in Figures 4A-4B is similar to that shown in Figures Fig. 2A-2B, except that the circuits shown in Fig. 4A-4B, the configurable clamp circuit 400 includes an example voltage limiter subcircuit 450. Fig. 4A shows the configurable clamp circuit 400 in the first configuration, and Fig.4B shows the configurable clamp circuit 400 in the second configuration. The voltage limiter subcircuit 450 includes a source-follower pull-up stage implemented by a transistor NM5 and coupled to the driver transistor PM1. In some embodiments, an optional transistor NM4 and NM5 can be coupled in series to implement a back-to-back switch for disabling the high-side driver. The voltage limiting in the voltage limiter subcircuit 450 is implemented by a Zener diode 452. The Zener diode 452 is coupled to the drain terminal 326 of the driver transistor PM1 and to a reference voltage such as VSS2 or another reference voltage. The Zener diode 452 can have a specified Zener voltage such as 8V, 10V, 12V, or another voltage.The drain terminal 326 of transistor PM1 is limited to the Zener voltage of the Zener diode 452 relative to the Zener diode reference voltage, and thus the gate terminal 428 of T1 is also voltage-limited. However, the voltage limiter subcircuit 450 is only an example; other embodiments may use different voltage limiter subcircuits or circuit configurations. In some embodiments, the voltage limiting function of the Zener diode 452 is instead implemented by a voltage clamp circuit with a specific clamping voltage.

[0022] Advantages of embodiments include enabling a single driver to be suitable for lower and higher power levels and different applications. Furthermore, the configurable clamp circuit can provide a low-inductance clamp connection between the driver and the driven power device, or between the external clamp transistor and the driven power device. In some embodiments, an external clamp transistor can have higher current handling capability than an integrated clamp transistor. In some cases, an external clamp transistor can have higher gate voltage limiting than an integrated clamp transistor.

[0023] Another advantage is that using an external clamping transistor instead of an internal clamping transistor can reduce the inductance of the connection through the clamping transistor between the voltage reference and the gate terminal of the power device. To achieve improved clamping, the circuit layout can be optimized for low-inductance routing between the gate terminal of the power device and the CLAMP pin. As previously described, the connection inductance can increase the likelihood or magnitude of a parasitic current event. A longer connection path between the power device and the clamping transistor can have a higher inductance. Therefore, using an external clamping transistor reduces the length of the connection path and can reduce the inductance, thereby improving the clamping circuit's response to a parasitic current event.In some cases, the driver circuit must be placed away from the power component, for example, due to layout limitations or other considerations. By using an external clamping transistor placed close to the power component, a low-inductance connection can be established between the clamping transistor and the power component, allowing the driver circuit with the configurable clamp circuit to still be placed relatively far from the power component. This can allow for greater design flexibility.

Claims

[1] Circuit which features: a configurable terminal driver circuit (300, 400) for clamping a voltage at a gate terminal of a first transistor (Q1) to below a turn-on voltage threshold when the first transistor (Q1) is turned off, wherein the terminal driver circuit (300, 400) is configured to be operated in one of two operating modes, wherein: In a first operating mode of the two operating modes, an output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to a gate terminal of the first transistor (Q1) in order to provide a first discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor is switched off, wherein the first discharge path bridges a resistor coupled to the gate terminal of the first transistor (Q1); and In a second operating mode of the two operating modes, the output terminal (CLIDER) of the terminal driver circuit (300, 400) is configured to be coupled to an input terminal of a terminal circuit (328), wherein the terminal circuit (328) is coupled to the gate terminal of the first transistor in order to provide a second discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor (Q1) is switched off, wherein the second discharge path bridges the resistor coupled to the gate terminal of the first transistor (Q1). wherein the terminal driver circuit (300, 400) has an output stage with a pull-up circuit coupled between a first power supply terminal and the output terminal (CLEMM) of the terminal driver circuit (300, 400), and a pull-down circuit coupled between a second power supply terminal and the output terminal (CLEMM) of the terminal driver circuit (300, 400), and the circuit further includes a voltage regulation circuit which is coupled between a power supply terminal and the output stage of the terminal driver circuit (300, 400). [2] Circuit which features: a configurable terminal driver circuit (300, 400) for clamping a voltage at a gate terminal of a first transistor (Q1) to below a turn-on voltage threshold when the first transistor (Q1) is turned off, wherein the terminal driver circuit (300, 400) is configured to be operated in one of two operating modes, wherein: In a first operating mode of the two operating modes, an output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to a gate terminal of the first transistor (Q1) in order to provide a first discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor is switched off, wherein the first discharge path bridges a resistor coupled to the gate terminal of the first transistor (Q1); and In a second operating mode of the two operating modes, the output terminal (CLIDER) of the terminal driver circuit (300, 400) is configured to be coupled to an input terminal of a terminal circuit (328), wherein the terminal circuit (328) is coupled to the gate terminal of the first transistor in order to provide a second discharge path for a current flowing from the gate terminal of the first transistor (Q1) when the first transistor (Q1) is switched off, wherein the second discharge path bridges the resistor coupled to the gate terminal of the first transistor (Q1). wherein the terminal driver circuit (300, 400) has an output stage with a pull-up circuit coupled between a first power supply terminal and the output terminal (CLEMM) of the terminal driver circuit (300, 400), and a pull-down circuit coupled between a second power supply terminal and the output terminal (CLEMM) of the terminal driver circuit (300, 400), and wherein the circuit further comprises a voltage limiter circuit (450) which is coupled between a power supply terminal and the output stage of the terminal driver circuit (300, 400). [3] Circuit according to claim 2, wherein the voltage limiter circuit (450) comprises a Zener diode (452). [4] Circuit according to one of claims 1 to 3, which further comprises the clamping circuit (300, 400), wherein the clamping circuit (300, 400) comprises a second transistor, wherein the gate terminal of the second transistor is coupled to the output terminal (CLAMP) of the terminal driver circuit (300, 400) and an output terminal (CLAMP) of the second transistor is coupled to the gate terminal of the first transistor. [5] Circuit according to one of claims 1 to 4, wherein the terminal driver circuit (300, 400) is arranged on a semiconductor substrate and the terminal circuit (300, 400) is located outside the semiconductor substrate. [6] Circuit according to one of the preceding claims, wherein the first transistor (Q1) is located outside the terminal driver circuit (300, 400). [7] Circuit according to one of the preceding claims, wherein the first transistor (Q1) is an IGBT. [8] Circuit according to one of the preceding claims, wherein a polarity of a signal at the output terminal (CLIENT) of the terminal driver circuit (300, 400) depends on an operating mode of the terminal driver circuit (300, 400). [9] Circuit according to claim 8, wherein the signal has a first polarity in the first operating mode and a second polarity opposite to the first polarity in the second operating mode. [10] Circuit according to one of the preceding claims, wherein the pull-up circuit comprises a p-channel MOSFET and the pull-down circuit comprises an n-channel MOSFET. [11] Circuit according to one of the preceding claims, which further comprises a controller coupled to the terminal driver circuit (300, 400), wherein the controller is configured to send to the terminal driver circuit (300, 400) a first control signal which signals the operating mode of the terminal driver circuit (300, 400) and to the terminal driver circuit (300, 400) a second control signal which activates the terminal driver circuit (300, 400). [12] Integrated circuit comprising: a terminal driver circuit (300, 400) comprising a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled to a gate driver output terminal, the gate driver output terminal being configured to be coupled to an input terminal of a power transistor; and a logic circuit coupled to the pull-up circuit and the pull-down circuit, wherein the logic circuit is configured to control the pull-up circuit and the pull-down circuit; wherein the terminal driver circuit (300, 400) is configured to be coupled either in a first configuration or in a second configuration, wherein: In the first configuration, an output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to the gate terminal of the power transistor; and In the second configuration, the output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to a gate terminal of an external terminal transistor, wherein an output terminal (CLIENT) of the external terminal transistor is coupled to the gate terminal of the power transistor, and wherein the integrated circuit further comprises a voltage regulation circuit which is coupled between a power supply terminal and the output stage of the terminal driver circuit (300, 400). [13] Integrated circuit which features: a terminal driver circuit (300, 400) comprising a pull-up circuit and a pull-down circuit, wherein the pull-up circuit and the pull-down circuit are coupled to a gate driver output terminal, the gate driver output terminal being configured to be coupled to an input terminal of a power transistor; and a logic circuit coupled to the pull-up circuit and the pull-down circuit, wherein the logic circuit is configured to control the pull-up circuit and the pull-down circuit; wherein the terminal driver circuit (300, 400) is configured to be coupled either in a first configuration or in a second configuration, wherein: In the first configuration, an output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to the gate terminal of the power transistor; and In the second configuration, the output terminal (CLIENT) of the terminal driver circuit (300, 400) is configured to be coupled to a gate terminal of an external terminal transistor, wherein an output terminal (CLIENT) of the external terminal transistor is coupled to the gate terminal of the power transistor, and wherein the integrated circuit further comprises a voltage limiting circuit which is coupled to the terminal driver circuit (300, 400) and is configured to limit the voltage at the output terminal (CLIENT) of the terminal driver circuit (300, 400). [14] Integrated circuit according to claim 13, wherein the voltage limiting circuit comprises a Zener diode (452). [15] Integrated circuit according to one of claims 12 to 14, further comprising the power transistor. [16] Integrated circuit according to one of claims 12 to 15, wherein the power transistor is located outside the terminal driver circuit (300, 400). [17] Integrated circuit according to one of claims 12 to 16, wherein the terminal driver circuit (300, 400) is configured to dissipate a current from the gate terminal of the power transistor. [18] Integrated circuit according to any one of claims 12 to 17, wherein the power transistor comprises an IGBT. [19] Integrated circuit according to any one of claims 12 to 18, wherein the terminal driver circuit (300, 400) comprises a pull-up circuit coupled to the output terminal (CLIDER) of the terminal driver circuit (300, 400) and a pull-down circuit coupled to the output terminal (CLIDER) of the terminal driver circuit (300, 400). [20] Integrated circuit according to claim 19, wherein the pull-up circuit comprises a p-channel MOSFET and the pull-down circuit comprises an n-channel MOSFET. [21] Method which features: Configuring a terminal driver circuit (300, 400) in one of two configurations, wherein: Configuring the terminal driver circuit (300, 400) in a first configuration includes coupling an output terminal of the terminal driver circuit (300, 400) to a gate terminal of a first transistor; and Configuring the terminal driver circuit (300, 400) in a second configuration includes coupling the output terminal of the terminal driver circuit (300, 400) to a gate terminal of a terminal transistor, wherein an output terminal (CLIDER) of the terminal transistor is coupled to the gate terminal of the first transistor; Switching off the first transistor; Activating the terminal driver circuit (300, 400); and Limiting or regulating the voltage at the output terminal (CLIENT) of the terminal driver circuit (300, 400). [22] Method according to claim 21, wherein configuring the terminal driver circuit (300, 400) further comprises receiving a control signal at the terminal driver circuit (300, 400), wherein the control signal allows the configuration of the terminal driver circuit (300, 400) to be detected. [23] Method according to one of claims 21 to 22, wherein activating the terminal driver circuit (300, 400) comprises providing a low-resistance path from the gate terminal of the first transistor to a voltage supply.

Images