Semiconductor packages and methods for their formation

Abstract

Device comprising the following: a first device package (200) comprising the following: a first redistribution structure (116) comprising a first redistribution line (108A) and a second redistribution line (108B); a die (124) on the first redistribution structure (116); a first through-hole (122A) which is coupled to a first side of the first redistribution line (108A); a second via (122B) that is coupled to a first side of the second redistribution line (108B) and extends through the second redistribution line; an encapsulation (140) that surrounds the die (124), the first via (122A) and the second via (122B); and a second redistribution structure (142) above the encapsulation (140), wherein the second redistribution structure is electrically connected to the die (124), the first via (122A) and the second via (122B); a first conductive connector (314) coupled to a second side of the first redistribution line (108A), wherein the first conductive connector (314) is arranged along a different axis (Do) than a longitudinal axis of the first via; and a second conductive connector (314) coupled to a second side of the second redistribution line (108B), wherein the second conductive connector is arranged along a longitudinal axis of the second via; an intermetallic compound (318B) at the interface of the second redistribution line (108B) and the second electrical connector (314); wherein the second via (122B) extends through the second redistribution line (108B) in such a way that it is directly contacted with the intermetallic connection (318).

Description

GENERAL STATE OF THE ART

[0001] The semiconductor industry has grown rapidly due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). These improvements in integration density have largely resulted from iteratively reducing the minimum feature size, allowing more components to be integrated into a given area. As the demand for ever smaller electronic devices has increased, a need has arisen for smaller and more innovative packaging techniques for semiconductor dies. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and component density.PoP technology generally enables the production of semiconductor devices with improved functionalities and small required mounting areas on a printed circuit board (PCB).

[0002] US 2015 / 0262909A1 relates to a semiconductor package comprising a semiconductor die, a molding material into which the semiconductor die is formed, a through-connector that substantially passes through the molding material, wherein the through-connector has an end that tapers outwards and has rounded sidewall surfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity in the discussion. Fig. Figures 1 to 14 are different views of intermediate steps during a process for forming a device package according to some embodiments. Fig. Figures 15 to 18 are different views of intermediate steps during a process for forming a package structure according to some embodiments. DETAILED DESCRIPTION

[0004] The invention is defined according to the independent claims. The dependent claims relate to corresponding further developments. The following disclosure provides many different embodiments or examples for carrying out various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended as limitations. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.Additionally, this disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purposes of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, terms describing a spatial relationship, such as "below," "under," "lower," "above," "upper," and the like, may be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It is intended that terms describing a spatial relationship encompass, in addition to the orientation depicted in the figures, various orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the terms for spatial relationships used here may also be interpreted accordingly.

[0006] Semiconductor packages and methods for their formation according to some embodiments are disclosed. In particular, a first redistribution structure is formed, which includes redistribution lines. A first via is formed extending from a face of a first conductive feature. A second via is formed extending from a gap between a second and a third conductive feature. The second via is longer than the first via. Conductive connectors, such as solder, are attached to the back side of the first redistribution structure. A first conductive connector is coupled to the first conductive feature and is offset from the first via. Consequently, an intermetallic compound (IMC) formed during reflow does not extend laterally to the first via.A second conductive connector is coupled to the second and third conductive features and is aligned with the second via. Consequently, if an IMC forms during reflow, copper diffuses from the second via and not from the second and third conductive features. By preventing copper diffusion from the second and third conductive features, the detachment of nucleation layers used during via formation can be avoided.

[0007] Fig. Figures 1 to 14 are different views of intermediate steps during a process for forming a semiconductor package 200 according to some embodiments. Fig. Figures 1 to 14 are cross-sectional views. The device package 200 can be described as an Integrated Fan-Out Package (InFO).

[0008] In Fig. Figure 1 shows the device package 200 at an intermediate processing stage, which includes a peel layer 102 formed on a support substrate 100. A package region 600 for the formation of the device package 200 is illustrated. Although only one package region is shown, many formed package regions may be present.

[0009] The support substrate 100 can be a glass substrate, a ceramic substrate, or the like. The support substrate 100 can be a wafer such that multiple packages can be formed simultaneously on the support substrate 100. The release layer 102 can be made of a polymer-based material that can be removed together with the support substrate 100 from the overlying structures formed in subsequent steps. In some embodiments, the release layer 102 is a thermal release material based on epoxy resin that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 102 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light.The release layer 102 can be dispensed as a liquid and cured, can be a thin laminate layer laminated onto the carrier substrate 100, or the like. The surface of the release layer 102 can be leveled and can exhibit a high degree of coplanarity.

[0010] In Fig. 2 A dielectric layer 104 is formed on the release layer 102. The lower surface of the dielectric layer 104 may be in contact with the surface of the release layer 102. In some embodiments, the dielectric layer 104 is formed from a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 104 may be formed by any acceptable deposition process, such as spin deposition, chemical vapor deposition (CVD), lamination, or the like, or a combination thereof.

[0011] In Fig. 3 A nucleation layer 106 is formed above the dielectric layer 104. In some embodiments, the nucleation layer 106 is a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the nucleation layer 106 comprises a titanium layer and a copper layer above the titanium layer. The nucleation layer 106 can be formed using, for example, PVD or the like.

[0012] In Fig. A metallization structure 108 is formed over the dielectric layer 104. A photoresist (not shown) is formed and patterned on the nucleation layer 106. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 108. The patterning creates openings through the photoresist to expose the nucleation layer 106. A conductive material is formed in the openings of the photoresist and on the exposed portions of the nucleation layer 106. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof.The photoresist and sections of the nucleated layer 106 where the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or detachment process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed sections of the nucleated layer 106 are removed, for example, by using an acceptable etching process, such as wet or dry etching. The remaining sections of the nucleated layer 106 and the conductive material form the metallization structure 108.

[0013] The conductive features of the metallization structure 108 can be referred to as redistribution layers or redistribution lines. The redistribution lines may not be formed to have a uniform width, and some of the redistribution lines may comprise multiple conductive features. First, redistribution lines 108A may each comprise a single conductive feature that will be electrically connected to devices of the device package 200. Second, redistribution lines 108B may each comprise multiple conductive features separated by a gap 110 and will be electrically connected to each other and to devices of the device package 200. The combined width W B The second redistribution line 108B can be essentially the same width W A the first redistribution lines 108A or it may differ from them.

[0014] In some embodiments, the conductive features of the second redistribution lines 108B are formed separately during the formation of the metallization structure 108; for example, each conductive feature can correspond to an opening in the photoresist that exposes the nucleation layer 106. In some embodiments, a single conductive feature is formed during the formation of the metallization structure 108, and the gaps 110 are subsequently formed using acceptable etching techniques to subdivide the single conductive feature into multiple conductive features. The gaps 110 are formed to provide a width W GThe gaps 110 can extend from surfaces of the second redistribution lines 108B to lower surfaces of the second redistribution lines 108B, such that the dielectric layer 104 is exposed. The gaps 110 can be formed in the center of the second redistribution lines 108B, such that the conductive features of the second redistribution lines 108B have the same length, or they can be formed offset from the center of the second redistribution lines 108B, such that the conductive features of the second redistribution lines 108B have different lengths.

[0015] In Fig. 5 A dielectric layer 112 is formed on the metallization structure 108 and the dielectric layer 104. In some embodiments, the dielectric layer 112 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. In other embodiments, the dielectric layer 112 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 can be formed by spin coating, lamination, CVD, the like, or a combination thereof.

[0016] The dielectric layer 112 is then patterned to form the openings 114, exposing sections of the metallization structure 108. The patterning can be carried out by an acceptable process, such as exposing the dielectric layer 112 to light if the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching. The first openings 114A are formed by exposing the first redistribution lines 108A, and the second openings 114B are formed by exposing the second redistribution lines 108B. The second openings 114B are formed over the gaps 110 of the second redistribution lines 108B; in essence, sides of the conductive features are exposed, sections of the surfaces of the conductive features are exposed, and sections of the dielectric layer 104 are exposed.In the illustrated embodiment, the first openings 114A and the second openings 114B each have the same width W. O In other embodiments, the first openings 114A and second openings 114B have different widths. The width W O The opening 114 is larger than the width W G 110 gaps.

[0017] The openings 114 can be formed above the center of each of the metallization structures 108 or can be formed offset from the center. In the embodiment shown, the first openings 114A are formed offset from the centers of the metallization structures 108, and the second openings 114B are formed above the centers of the metallization structures 108.

[0018] The dielectric layers 104 and 112 and the metallization structures 108 can be referred to as a backside redistribution structure 116. As illustrated, the backside redistribution structure 116 comprises the two dielectric layers 104 and 112 and one metallization structure 108. In other embodiments, the backside redistribution structure 116 can include any number of dielectric layers, metallization structures, and vias. One or more additional metallization structures and dielectric layers can be formed in the backside redistribution structure 116 by repeating the processes for forming the metallization structures 108 and the dielectric layer 112. Vias can be formed during the formation of a metallization structure by forming the nucleation layer and the conductive material of the metallization structure in the opening of the underlying dielectric layer.The vias can therefore connect the different metallization structures and couple them electrically.

[0019] In Fig. 6 A nucleation layer 118 is formed over the backside redistribution structure 116 and in the openings 114. The nucleation layer 118 is located over the dielectric layer 112, exposed sections of the metallization structure 108, and exposed sections of the dielectric layer 104. In some embodiments, the nucleation layer 118 is a metal layer, which may be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the nucleation layer 118 comprises a titanium layer and a copper layer over the titanium layer. The nucleation layer 118 can be formed using, for example, PVD or the like.

[0020] In Fig. 7. A photoresist 120 is formed and structured on the nucleation layer 118. The photoresist 120 can be formed by spin coating or similar processes and can be exposed to light for structuring. The structure of the photoresist 120 corresponds to through-hole vias that are subsequently formed. The structuring creates openings through the photoresist 120 to expose the nucleation layer 118. The openings through the photoresist 120 are formed over the openings 114 in the dielectric layer 112 and can have the same width W over both the first openings 114A and the second openings 114B. P exhibit the width W P The opening is larger than the width W O of the openings 114.

[0021] In Fig. 8. A conductive material is formed in the openings of the photoresist 120 and on the exposed portions of the nucleated layer 118. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. The photoresist 120 and portions of the nucleated layer 118 on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or detachment process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the nucleated layer 118 are removed, such as by using an acceptable etching process, such as wet or dry etching.The remaining sections of the nucleation layer and the conductive material form continuous vias 122, which are electrically connected to the distribution lines.

[0022] Since the nucleation layer 118 is formed in the gaps 110 of the second distribution lines 108B, second vias 122B are formed, extending through the second distribution lines 108B. Conversely, first vias 122A are formed on the first distribution lines 108A and do not extend through them. The first vias 122A and second vias 122B can both have the same width W. P above the dielectric layer 112 and the same width W O in the openings 114. The second vias 122B also have the width W. Gin the gaps 110. Since the second vias 122B have three different widths, each with a decreasing width, the second vias 122B can be described as having a conductor structure. Since the first openings 114A were formed offset from the centers of the metallization structures 108, the first vias 122A are formed offset from the centers of the first redistribution lines 108A.

[0023] Although the first vias 122A are illustrated as having one change in width and the second vias 122B are illustrated as having two changes in width, it is understood that the first vias 122A and second vias 122B may have any number of changes in width in other embodiments. According to some embodiments, the second vias 122B have more changes in width than the first vias 122A.

[0024] In Fig. 9. Integrated circuit dies 124 are bonded to the dielectric layer 112 by an adhesive 126. As in Fig. Figure 4 illustrates how an integrated circuit die 124 is adhered to the package area 600. In other embodiments, multiple integrated circuit dies 124 can be adhered to each area. The integrated circuit dies 124 can include exposed dies, such as logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory - DRAM, static random access memory - SRAM, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), RF dies, sensor dies, microelectromechanical system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof.In some embodiments, the integrated circuit dies 124 in the different package areas (not shown) can have different sizes (e.g., different heights and / or surfaces), and in other embodiments, the integrated circuit dies 124 can have the same size (e.g., same heights and / or surfaces).

[0025] Before being bonded to the dielectric layer 112, the integrated circuit dies 124 can be processed according to applicable fabrication processes to form integrated circuits within the integrated circuit dies 124. For example, each integrated circuit die 124 comprises a semiconductor substrate 128, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can include other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.Devices such as transistors, diodes, capacitors, resistors, etc. can be formed in and / or on the semiconductor substrate 128 and can be interconnected by interconnection structures 130, which are formed, for example, by metallization structures in one or more dielectric layers on the semiconductor substrate 128, to form an integrated circuit.

[0026] The integrated circuit dies 124 further include terminals 132, such as aluminum terminals, for establishing external connections. The terminals 132 are what can be described as the corresponding active sides of the integrated circuit dies 124. Thin passivation layers 134 are located on the integrated circuit dies 124 and on sections of the terminals 132. Openings extend through the thin passivation layers 134 to the terminals 132. Die connectors 136, such as conductive pillars (which, for example, comprise a metal such as copper), are located in the openings through the thin passivation layers 134 and are mechanically and electrically coupled to the corresponding terminals 132. The die connectors 136 can be formed, for example, by plating or the like. The die connectors 136 electrically couple the respective integrated circuits to the integrated circuit dies 124.

[0027] A dielectric material 138 is located on the active sides of the integrated circuit dies 124, such as on the thin passivation layers 134 and the die connectors 136. The dielectric material 138 encapsulates the die connectors 136 laterally and is laterally adjacent to the corresponding integrated circuit dies 124. The dielectric material 138 may initially form to bury or cover the die connectors 136; if the die connectors 136 are buried, the surface of the dielectric material 138 may have an uneven topology.The dielectric material 138 can comprise a polymer, such as PBO, polyimide, BCB, or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; the like or a combination thereof, and can be formed, for example, by spin coating, lamination, CVD, or the like.

[0028] The adhesive 126 is located on the back side of the integrated circuit dies 124 and causes the integrated circuit dies 124 to adhere to the back-side redistribution structure 116, such as the dielectric layer 112 in the illustration. The adhesive 126 can be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 126 can be applied to a back side of the integrated circuit dies 124, such as a back side of the corresponding semiconductor wafer, or it can be applied over the surface of the support substrate 100. The integrated circuit dies 124 can be separated, for example by sawing or dicing, and adhered to the dielectric layer 112 by the adhesive 126 using, for example, a pick-and-place tool.

[0029] Although the integrated circuit dies 124 have been previously illustrated and described as exposed dies (e.g., open dies), in other embodiments the integrated circuit dies 124 can be enclosed chips (e.g., one or more exposed dies integrated with other package features, such as redistribution structures, passive devices, etc.). For example, the integrated circuit dies 124 can be a memory package (e.g., a hybrid memory cube) comprising multiple stacked and interconnected memory dies.

[0030] In Fig. 10. An encapsulation 140 is formed on the various components. The encapsulation 140 can be a molding compound, epoxy, or the like, and can be applied by compression molding, injection molding, or the like. The encapsulation 140 can be formed over the support substrate 100 such that the die connectors 136 of the integrated circuit dies 124 and / or the vias 122 are buried or covered. The encapsulation 140 is then cured.

[0031] In Fig. In 11, a planarization process is performed on the encapsulation 140 to expose the vias 122 and the die connectors 136. The planarization process can also grind the dielectric material 138. After the planarization process, the surfaces of the vias 122, die connectors 136, dielectric material 138, and encapsulation 140 are coplanar. The planarization process can be, for example, chemical-mechanical polishing (CMP), grinding, or the like. In some embodiments, the planarization can be omitted, for example, if the vias 122 and die connectors 136 are already exposed. As mentioned previously, the secondary vias 122B extend through the metallization structure 108.In principle, the second vias 122B are longer than the first vias 122A after the planarization process, if the first vias 122A and the second vias 122B are connected with the same metallization layer of the backside redistribution structure 116.

[0032] In Fig. In 12, a front-side redistribution structure 142 is formed on the encapsulation 140, the through-hole vias 122, and the die connectors 136. The front-side redistribution structure 142 comprises several dielectric layers and metallization structures. For example, the front-side redistribution structure 142 can be structured as several discrete metallization structures separated from each other by a corresponding dielectric layer(s).

[0033] In some embodiments, the dielectric layers are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers are formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers can be formed by spin deposition, lamination, CVD, the like, or a combination thereof.

[0034] After formation, the dielectric layers are patterned to expose underlying conductive features. The bottom dielectric layer is patterned to expose sections of the through-hole vias 122, and the die connectors 136 and the dielectric intermediate layer(s) are patterned to expose sections of underlying metallization structures. Patterning can be achieved by an acceptable process, such as exposing the dielectric layer to light if the dielectric layers are a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layers are photosensitive materials, they can be developed after exposure.

[0035] Metallization structures with vias are formed on each dielectric layer. A seed layer (not shown) is formed above the dielectric layer and in openings through the dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process such as PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin deposition or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure.The structuring process creates openings through the photoresist to expose the nucleation layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the nucleation layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and portions of the nucleation layer where the conductive material has not formed are then removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like.After the photoresist is removed, exposed sections of the seed layer are removed, for example, using an acceptable etching process such as wet or dry etching. The remaining sections of the seed layer and conductive material form the metallization structure and vias for a metallization plane of the front-side redistribution structure 142.

[0036] The front-side redistribution structure 142 is shown as an example. More or fewer dielectric layers and metallization structures than shown in front-side redistribution structure 142 can be formed. The average person will readily understand which steps and processes would be omitted or repeated to form more or fewer dielectric layers and metallization structures.

[0037] The upper dielectric layer of the front-side redistribution structure 142 is patterned to expose sections of the metallization structures for the formation of conductive connections. The conductive connections are used to couple with conductive connectors and can be referred to as under-bump metallizations (UBMs) 144. The patterning can be performed by an acceptable process, such as exposing the upper dielectric layer to light if the upper dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching. If the upper dielectric layer is a photosensitive material, it can be developed after exposure. The UBMs 144 are then formed on the outside of the front-side redistribution structure 142.The UBMs 144 are formed extending through openings in the upper dielectric layer to contact the metallization layers of the front-side redistribution structure 142.

[0038] As an example of the formation of the UBMs 144, a nucleation layer (not shown) is formed over the top dielectric layer and in openings through the top dielectric layer. In some embodiments, the nucleation layer is a metal layer, which may be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the nucleation layer comprises a titanium layer and a copper layer over the titanium layer. The nucleation layer may be formed using a deposition process such as PVD or the like. A photoresist is then formed and patterned on the nucleation layer. The photoresist may be formed by spin deposition or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the structure of the conductive terminals in the front-side redistribution structure 142.The structuring process creates openings through the photoresist to expose the nucleation layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the nucleation layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and portions of the nucleation layer where the conductive material has not formed are then removed. The photoresist can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma or the like.After the photoresist has been removed, exposed sections of the nucleation layer are removed, for example, using a suitable etching process such as wet or dry etching. The remaining sections of the nucleation layer and conductive material form the UBMs 144.

[0039] Conductive connectors 146 are formed on the UBMs 144. The conductive connectors 146 can be BGA connectors, solder balls, metal pillars, controlled-collapse chip connection (C4) contact bumps, contact bumps formed using electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connectors 146 can be formed from a metal or metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 146 are formed by initially forming a layer of solder using commonly used methods such as vapor deposition, electroplating, printing, solder feeding, ball placement, or the like. After a solder layer has been formed on the structure, reflow can be performed to shape the material into the desired contact bump shapes.In another embodiment, the conductive connectors 146 are metal columns (such as a copper column) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal columns may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cover layer (not shown) is formed on the top of the UBMs 144. The metal cover layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0040] In Fig. 13. A support substrate detachment is performed to remove (detach) the support substrate 100 from the backside redistribution structure 116, e.g., the dielectric layer 104. According to some embodiments, the detachment includes projecting light, such as laser light or UV light, onto the detachment layer 102, such that the detachment layer 102 decomposes under the heat of the light and the support substrate 100 can be removed. The structure is then turned over and placed on the tape 148.

[0041] Furthermore, in Fig. 13 The openings 150 are formed through the dielectric layer 104 to expose sections of the metallization structure 108. The openings can be formed, for example, using laser drilling, acceptable etching techniques, or the like. The first openings 150A are formed by exposing the first distribution lines 108A, and the second openings 150B are formed by exposing the second distribution lines 108B. The first openings 150A are formed offset from the centers of the first vias 122A such that the first openings 150A are at a distance D O Sections of the first vias 122A are arranged in the dielectric layer 112. The second openings 150B are formed centered beneath the second vias 122B, such that the nucleation layer 118 and sections of the nucleation layer 106 extending through the second redistribution lines 108B are exposed.

[0042] In Fig. 14. Sections of the nucleation layers 106 and 118 exposed through the openings 150 are thinned or completely removed. The exposed sections of the nucleation layers 106 and 118 can be thinned or removed by an acceptable etching process, such as wet or dry etching. In embodiments where the nucleation layers 106 and 118 comprise multiple layers, the etching process can remove some or all of the exposed multiple layers. In embodiments where the nucleation layers 106 and 118 comprise a titanium layer over the dielectric layer 104 and a copper layer over the titanium layer, the etching process can remove the titanium layer and leave the copper layer intact, thereby thinning the layer. In such embodiments, the etching process is carried out with one or more etchants that are selective for the titanium layer (e.g.,The titanium layer is etched at a substantially higher rate than the copper layer. In other embodiments, the exposed portions of the nucleation layers 106 and 118 are completely removed (e.g., all layers are removed).

[0043] Fig. Figures 15 to 18 are different views of intermediate steps during a process for forming a package structure 400 according to some embodiments. Fig. Figures 15 to 18 are cross-sectional views. Package structure 400 can be described as a package-on-package (PoP) structure.

[0044] In Fig. 15. A device package 300 is bonded to the device package 200. The device package 300 can be bonded to the device package 200 in any package area 600. The device package 300 comprises a substrate 302 and one or more stacked dies 308 (308A and 308B) coupled to the substrate 302. Although a single stack of dies 308 (308A and 308B) is illustrated, in other embodiments several stacked dies 308 (each comprising one or more stacked dies) can be arranged side by side and coupled to the same area of ​​the substrate 302.

[0045] The substrate 302 can consist of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, the substrate 302 can be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 302 is based on an insulating core, such as a glass fiber-reinforced resin core. An exemplary core material is glass fiber resin such as FR4.Alternatives for the core material include bismaleimide triazine resin (BT) or, alternatively, other printed circuit board (PCB) materials or thin films. Thin build-up layers, such as Ajinomoto Build-up Film (ABF) or other laminates, can be used for substrate 302.

[0046] The substrate 302 can include active and / or passive devices (not shown). As an average person skilled in the art will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to generate the structural and functional design requirements for the device package 300. The devices can be formed using any suitable methods.

[0047] The substrate 302 can also include metallization layers (not shown) and vias 306. The metallization layers can be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers can be formed from alternating layers of dielectric (e.g., low-k dielectric) and conductive material (e.g., copper) with vias that interconnect the conductive material layers and can be formed by any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate 302 is essentially free of active and passive devices.

[0048] The substrate 302 can have bond islands 303 on a first side of the substrate 202 for coupling to the stacked dies 308, and bond islands 304 on a second side of the substrate 302, the second side being opposite the first side of the substrate 302 for coupling to the conductive connectors 314. In some embodiments, the bond islands 303 and 304 are formed by creating recesses (not shown) in dielectric layers (not shown) on the first and second sides of the substrate 302. The recesses can be formed to allow the bond islands 303 and 304 to be embedded in the dielectric layers. In other embodiments, the recesses are omitted, since the bond islands 303 and 304 can be formed on the dielectric layer.In some embodiments, the bonding islands 303 and 304 comprise a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bonding islands 303 and 304 can be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, a currentless plating process, CVD, ALD, PVD, the like, or a combination thereof. The conductive material of the bonding islands 303 and 304 can be copper, tungsten, aluminum, silver, gold, nickel, the like, or a combination thereof.

[0049] In one embodiment, the bond islands 303 and 304 are UBMs comprising three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. For example, the bond islands 304 may comprise a layer of titanium (not shown), a main section 304A of copper, and a nickel surface finish 304B. The nickel surface finish 304B may improve the durability of the device package 300, which may be particularly advantageous if the device package 300 is a storage device, such as a DRAM module. However, the person skilled in the art will recognize that many suitable arrangements of materials and layers exist, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, which are suitable for forming the UBMs 303 and 304.It is understood that any suitable materials or layers of material that can be used for the UBMs 303 and 304 are intended to be fully encompassed within the intended scope of protection of the present application. In some embodiments, the through-hole vias 306 extend through the substrate 302 and couple at least one bonding island 303 to at least one bonding island 304.

[0050] In the illustrated embodiment, the stacked dies 308 are coupled to the substrate 302 by wire bonds 310, although other connections, such as conductive contact bumps, can also be used. In one embodiment, the stacked dies 308 are stacked memory dies. For example, the stacked memory dies 308 can comprise low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules. As mentioned previously, the bond islands 304 in such embodiments can have a nickel surface finish 304B.

[0051] In some embodiments, the stacked dies 308 and the wire bonds 310 can be encapsulated by a molding material 312. The molding material 312 can be formed onto the stacked dies 308 and the wire bonds 310, for example, using molding presses. In some embodiments, the molding material 312 is a molding compound, a polymer, an epoxy, a silicon dioxide filler material, the like, or a combination thereof. A curing step can be performed to cure the molding material 312, wherein the curing can be thermal curing, UV curing, the like, or a combination thereof.

[0052] In some embodiments, the stacked dies 308 and the wire bonds 310 are buried in the molding material 312, and after the molding material 312 has hardened, a planarization step, such as grinding, is carried out to remove excess sections of the molding material 312 and to provide a substantially flat surface for the fixture package 300.

[0053] After the device package 300 has been formed, it is mechanically and electrically bonded to the device package 200 by means of conductive connectors 314, bonding islands 304, and the metallization structure 108. In some embodiments, the stacked memory dies 308 are coupled to the integrated circuit dies 124 by wire bonds 310, bonding islands 303 and 304, vias 306, conductive connectors 314, vias 122, and the front-side redistribution structure 142.

[0054] The conductive connectors 314 can be similar to the previously described conductive connectors 146, and the description is not repeated here, although the conductive connectors 314 and the conductive connectors 146 need not be the same. The conductive connectors 314 can be arranged on a side of the substrate 302 opposite the stacked memory dies 308. In some embodiments, a solder mask (not shown) can also be formed on the side of the substrate 302 opposite the stacked memory dies 308. The conductive connectors 314 can be arranged in openings in the solder mask (not shown) to be electrically and mechanically coupled to conductive features (e.g., the bond islands 304) in the substrate 302. The solder mask can be used to protect areas of the substrate 302 from external damage.

[0055] In some embodiments, the conductive connectors 314 are coated with a flux (not shown), such as a residue-free flux, before bonding. The conductive connectors 314 can be immersed in the flux, or the flux can be blasted onto the conductive connectors 314. In another embodiment, the flux can be applied to the surfaces of the metallization structures 108.

[0056] In some embodiments, the conductive connectors 314 may have an optional epoxy flux (not shown) formed on them before they are reflow-soldered with at least some of the epoxy portion of the flux after the device package 300 has been attached to the device package 200. This remaining epoxy portion may act as a filler material to reduce stress and protect the connections resulting from the reflow of the conductive connectors 314.

[0057] Optionally, a filler material 316 can be formed between the device packages 200 and 300. In one embodiment, the filler material 316 is a protective material used to cushion and support the device packages 200 and 300 against deterioration caused by operation and environmental factors, such as stresses resulting from heat generation during operation. The filler material 316 can be injected into the space between the device packages 200 and 300 or formed therein in some other way and can, for example, be a liquid epoxy that is dispensed between the device packages 200 and 300 and then cures to harden.

[0058] Fig. 16A, Fig. 16B, Fig. 16C and Fig. Figure 16D shows detailed views of the conductive connectors 314 and metallization structures 108 after a bonding process has been performed to physically and electrically couple the device packages 200 and 300. The bonding between the device packages 200 and 300 can be solder bonding. In one embodiment, the device package 300 is bonded to the device package 200 by a reflow process. Fig. 16A and Fig. 16B are cross-sectional or top views showing a connection for the first redistribution lines 108A. Fig. 16C and Fig. 16D are cross-sectional or top views showing a connection for the second redistribution lines 108B.

[0059] In Fig. 16A, Fig. 16B, Fig. 16C and Fig. In step 16D, the bonding process is carried out to reflow the conductive connectors 314 such that they are in contact with the bonding islands 304 and metallization structures 108. After the bonding process, an intermetallic compound (IMC) 318 can form at the interfaces of the metallization structures 108 and conductive connectors 314. Since the exposed portions of the nucleation layers 106 and 118 have been partially or completely removed, the IMC 318 can extend partially or completely through the metallization structures 108. The IMC 318 can also extend over a distance D I extend laterally along the metallization structures 108 from the sides of the first openings 150.

[0060] The bonds formed by the bonding process comprise the conductive connectors 314 (e.g., solder) that contact two dissimilar metals. In one embodiment, the metallization structures 108 are formed from copper, and the bonding islands 304 have a nickel surface finish 304B, resulting in nickel-solder-copper bonds. When such bonds are formed, copper diffuses during reflow from the metallization structures 108 into the conductive connectors 314 and in the direction of the nickel surface finish 304B. A gradient of diffused copper is formed in the conductive connectors 314 in the direction of the solid arrows. Excessive diffusion of copper from the metallization structures 108 near the nucleation layers 118 can cause the nucleation layer 118 to detach from the metallization structures 108.In particular, the diffusion of copper from sections of the metallization structures 108 between the nucleation layers 118 and the dielectric layer 104 can cause the detachment of the nucleation layers 118.

[0061] In Fig. 16A and Fig. 16B are the first openings 150A in the dielectric layer 104 laterally at a distance D O Sections of the first vias 122A are arranged in the dielectric layer 112. The conductive connectors 314 are arranged laterally at a distance D in a top view. O from the sides of the first vias 122A and are not arranged along the longitudinal axes of the first vias 122A. The diameter D O is chosen to be sufficiently large, such that the IMC 318A does not extend laterally to the sides of the first vias 122A. In other words, the distance D O is greater than the distance D Iand can be at least twice as large as the distance D I be. In one embodiment, the distance D can be I from about 2 µm to about 13 µm, such as about 13 µm, and the distance D O can range from approximately 25 µm to approximately 35 µm, such as approximately 35 µm. The formation of the first openings 150A (see e.g. Fig. 13), such that the IMC 318A does not extend laterally to the sides of the first vias 122A, can prevent the diffusion of copper from sections of the first redistribution lines 108A between the seed layers 118 and the dielectric layer 104, thereby preventing the detachment of the seed layers 118.

[0062] In Fig. 16C and Fig. In 16D, the second openings 150B in the dielectric layer 104 are laterally aligned with the gaps 110 in the second distribution lines 108B. In a top view, the conductive connectors 314 are not laterally spaced from the sides of the second vias 122B and are arranged along the longitudinal axes of the second vias 122B. Since the exposed sections of the nucleation layers 106 and 118 have been partially or completely removed, the IMC 318 extends longitudinally into the second vias 122B. The formation of the IMC 318B such that it extends into the second vias 122B can result in some of the diffused copper being sourced from the second vias 122B instead of the metallization structures 108.This can reduce the copper that diffuses from the metallization structures 108, thereby avoiding the detachment of the nucleation layers 118 and also avoiding the reduction in the thickness of the second redistribution lines 108B.

[0063] As further shown, the metallization structure 108 comprises slots 322 arranged around the perimeter of the conductive connectors 314 and the vias 122. The slots 322 provide stress relief, thereby improving the reliability of the electrical connections. In particular, the slots 322 provide additional sidewalls for the metallization structures 108, thus improving the adhesion between the metallization structures 108 and polyimide materials, such as the dielectric layer 112. The slots 322 are arranged at least partially around the conductive connectors 314 in the first redistribution lines 108A and can be arranged completely around the conductive connectors 314 in the second redistribution lines 108B.

[0064] In Fig. 17. A singulation process 320 is carried out by singulation along scoring frame areas, e.g., between adjacent package areas. In some embodiments, the singulation process 320 includes a sawing process, a laser process, or a combination thereof. The singulation process 320 singulates the package area 600 from adjacent package areas (not shown). The resulting package structure 400 is shown after the singulation, which may be of the package area 600.

[0065] Fig. Figure 18 shows the package structure 400 after it has been attached to a substrate 500. The substrate 500 can be referred to as a package-substrate 500. The package-substrate 400 is attached to the substrate 500 by mounting the device package 200 to the substrate 500 using the conductive connections 146 on the substrate 500.

[0066] The Package Substrate 500 can consist of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the Package Substrate 500 can be a SOI substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the Package Substrate 500 is based on an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is glass fiber resin such as FR4.Alternatives for the core material include bismaleimide triazine resin (BT) or, alternatively, other PCB materials or thin films. Thin build-up layers, such as ABF or other laminates, can be used for the Package Substrate 500.

[0067] The package substrate 500 can include active and passive devices (not shown). As an average person skilled in the art will recognize, a wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to create the structural and functional design requirements for the package structure 400. The devices can be formed using any suitable methods.

[0068] The package substrate 500 can also include metallization layers and vias (not shown) and bond islands 502 over the metallization layers and vias. The metallization layers can be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers can be formed from alternating layers of dielectric (e.g., low-k dielectric) and conductive material (e.g., copper) with vias that interconnect the conductive material layers and can be formed by any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 500 is essentially free of active and passive devices.

[0069] In some embodiments, the conductive connectors 146 are reflow-soldered to attach the device package 200 to the bonding pads 502. The conductive connectors 146 couple the package substrate 500, including any metallization layers in the package substrate 500, electrically and / or physically to the device package 200. In some embodiments, passive devices (e.g., surface-mount devices (SMDs), not illustrated) can be attached to the device package 200 (e.g., bonded to the bonding pads 502) before being mounted to the package substrate 500. In such embodiments, the passive devices can be bonded to the same area of ​​the device package 200 as the conductive connectors 146.

[0070] The conductive connectors 146 may have an epoxy flux (not shown) formed on them before they are reflow-soldered with at least some of the epoxy portion of the flux remaining after the device package 200 has been attached to the package substrate 500. This remaining epoxy portion can act as a filler material to reduce stress and protect the connections resulting from the reflow of the conductive connectors 146. In some embodiments, a filler material (not shown) may be formed between the device package 200 and the package substrate 500 and surrounding the conductive connectors 146. The filler material may be formed by a capillary flow process after the device package 200 has been attached or may be formed by a suitable deposition process before the device package 200 is attached.

[0071] Advantages can be achieved with various embodiments. By arranging the conductive connectors 314 laterally with a sufficient distance D O From the perspective of the first vias 122A in a top view, the diffusion of copper from the metallization structures 108 near the seed layers 118 can be avoided. Forming the IMC 318B such that it extends into the second vias 122B can result in some of the diffused copper being sourced from the second vias 122B instead of the metallization structures 108. By reducing the amount of copper diffusing from the metallization structures 108 beneath the seed layers 118, delamination of the seed layers 118 can be prevented, thereby improving the reliability of the resulting devices.

[0072] According to some embodiments, a device comprises: a first device package comprising: a first redistribution structure comprising a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulation surrounding the die, the first via, and the second via; and a second redistribution structure above the encapsulation, the second redistribution structure being electrically connected to the die, the first via, and the second via.a first conductive connector coupled to a second side of the first redistribution line, wherein the first conductive connector is arranged along an axis other than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, wherein the second conductive connector is arranged along a longitudinal axis of the second via.

[0073] In some embodiments, the device further comprises: a second device package comprising a first bonding island and a second bonding island, wherein the first conductive connector is coupled to the first bonding island and the second conductive connector is coupled to the second bonding island. In some embodiments, the first bonding island and the second bonding island have a nickel surface finish. In some embodiments, the first redistribution line and the second redistribution line are formed of copper. In some embodiments, the first redistribution structure further comprises: a first dielectric layer, wherein the first redistribution line and the second redistribution line are arranged on the first dielectric layer; and a second dielectric layer on the first dielectric layer. In some embodiments, the second via is longer than the first via.

[0074] According to some embodiments, a method comprises the following: forming a first redistribution structure, which includes: depositing a first dielectric layer over a support substrate; forming a first conductive feature on the first dielectric layer; forming a second conductive feature on the first dielectric layer; forming a third conductive feature on the first dielectric layer; and depositing a second dielectric layer on the first conductive feature, the second conductive feature, and the third conductive feature; forming a first via on the first conductive feature; forming a second via on the second conductive feature, on the third conductive feature, and between the second conductive feature and the third conductive feature;Attaching a die to the first redistribution structure adjacent to the first and second vias; encapsulating the die, the first and second vias with an encapsulation; planarizing the encapsulation, the first and second vias; and forming a second redistribution structure over the encapsulation, the first via, the second via, and the die.

[0075] In some embodiments, the method further comprises: detaching the support substrate from the first redistribution structure; and attaching a device package to the first redistribution structure, wherein the device package is attached to the first conductive feature by a first connector, and wherein the device package is attached to the second conductive feature and the third conductive feature by a second connector. In some embodiments, the first connector is not arranged along a longitudinal axis of the first via. In some embodiments, the second connector is arranged along a longitudinal axis of the second via. In some embodiments, the first via is longer than the second via after planarization.

[0076] According to some embodiments, a method comprises: depositing a first seed layer on a first dielectric layer; plating a first conductive feature and a second conductive feature on the first seed layer; depositing a second dielectric layer on the first conductive feature and the second conductive feature; forming a first opening in the second dielectric layer, the first opening exposing the first conductive feature, the second conductive feature, and the first dielectric layer; depositing a second seed layer on the second dielectric layer and in the first opening; plating a first via of portions of the second seed layer in the first opening; attaching a die to the second dielectric layer; and encapsulating the first via and the die with an encapsulation.

[0077] In some embodiments, the method further comprises: forming a second opening in the first dielectric layer, wherein the second opening exposes the first seed layer and the second seed layer; forming a reflowable material in the second opening, wherein the reflowable material is arranged along a longitudinal axis of the first via;and reflowing the reflowable material to form an intermetallic bond between the reflowable material and the conductive material of the first seed layer, the second seed layer, and the first via. In some embodiments, the method further comprises: attaching a device package to the first conductive feature and the second conductive feature with the reflowable material. In some embodiments, the reflowing of the reflowable material comprises diffusing portions of the conductive material of the first via into the reflowable material. In some embodiments, the method further comprises: forming a third conductive feature on the first dielectric layer; depositing the second dielectric layer on the third conductive feature; forming a second opening in the second dielectric layer, the second opening exposing the third conductive feature;Deposition of the second seed layer in the second opening; and plating of a second via of sections of the second seed layer in the second opening; In some embodiments, the method further comprises: forming a third opening in the first dielectric layer, wherein the third opening exposes the first seed layer; forming a reflowable material in the third opening, wherein the reflowable material is arranged along a different axis than a longitudinal axis of the second via;and reflowing the reflowable material to form an intermetallic connection between the reflowable material and the conductive material of the first seed layer. In some embodiments, the reflowing of the reflowable material includes diffusing portions of the conductive material of the third conductive feature into the reflowable material. In some embodiments, no portion of the intermetallic connection is formed between the second via and the first dielectric layer. In some embodiments, the method further includes planarizing the first via, the second via, and the encapsulation, wherein the first via is longer than the second via after planarizing.

[0078] Previously, features of several embodiments were presented in such a way that the person skilled in the art could better understand the aspects of the present disclosure. The person skilled in the art should understand that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. The person skilled in the art should also understand that such equivalent designs do not deviate from the concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the concept and scope of protection of the present disclosure.

Claims

[1] Device comprising the following: a first device package (200) comprising the following: a first redistribution structure (116) comprising a first redistribution line (108A) and a second redistribution line (108B); a die (124) on the first redistribution structure (116); a first through-hole (122A) which is coupled to a first side of the first redistribution line (108A); a second via (122B) that is coupled to a first side of the second redistribution line (108B) and extends through the second redistribution line; an encapsulation (140) that surrounds the die (124), the first via (122A) and the second via (122B); and a second redistribution structure (142) above the encapsulation (140), wherein the second redistribution structure is electrically connected to the die (124), the first via (122A) and the second via (122B); a first conductive connector (314) coupled to a second side of the first redistribution line (108A), wherein the first conductive connector (314) is arranged along a different axis (Do) than a longitudinal axis of the first via; and a second conductive connector (314) coupled to a second side of the second redistribution line (108B), wherein the second conductive connector is arranged along a longitudinal axis of the second via; an intermetallic compound (318B) at the interface of the second redistribution line (108B) and the second electrical connector (314); wherein the second via (122B) extends through the second redistribution line (108B) in such a way that it is directly contacted with the intermetallic connection (318). [2] Device according to claim 1, further comprising: a second device package (300) comprising a first Bond island (304) and a second Bond island (304), wherein the first conductive connector (314) is coupled to the first Bond island (304), wherein the second conductive connector (314) is coupled to the second Bond island (304). [3] Device according to claim 2, wherein the first Bond island (304) and the second Bond island (304) have a nickel surface finish. [4] Device according to claim 2 or 3, wherein the first redistribution line (108A) and the second redistribution line (108B) are made of copper. [5] Device according to any of the preceding claims, wherein the first redistribution structure (116) further comprises: a first dielectric layer (104), wherein the first redistribution line (108A) and the second redistribution line (108B) are arranged on the first dielectric layer; and a second dielectric layer (112) on top of the first dielectric layer (106). [6] Device according to claim 5, wherein the second via (122B) is longer than the first via (122A). [7] Method which features the following: Forming a first redistribution structure (116) which includes the following: Deposition of a first dielectric layer (104) over a support substrate; Formation of a first conductive feature (108A) on the first dielectric layer; Formation of a second conductive feature (108B) on the first dielectric layer; Formation of a third conductive feature (108B) on the first dielectric layer; and Deposition of a second dielectric layer (112) on the first conductive feature, the second conductive feature and the third conductive feature; Forming a first via (122A) on the first conductive feature (108A); Forming a second via (122B) on the second conductive feature (108B), on the third conductive feature (108B) and between the second conductive feature (108B) and the third conductive feature (108B); Attaching a die (124) to the first redistribution structure (116) adjacent to the first via (122A) and the second via (122B); Encapsulation of the die (124), the first via (122A) and the second via (122B) with an encapsulation (140); Planarizing the encapsulation (140), the first via (122A) and the second via (122B); and Forming a second redistribution structure (142) over the encapsulation (140), the first via (122A), the second via (122B) and the die (124), wherein an intermetallic connection (318B) is formed at the interface of the second redistribution line (108B) and the second electrical connector (314) and the second via (122B) extends through the second redistribution line (108B) such that it is directly contacted with the intermetallic connection (318). [8] The method of claim 7, further comprising: Detachment of the carrier substrate (100) from the first redistribution structure (116); and Attaching a device package (300) to the first redistribution structure (116), wherein the device package is attached to the first conductive feature (108A) by a first connector (314), and wherein the device package is attached to the second conductive feature (108A) and the third conductive feature (108B) by a second connector (314). [9] Method according to claim 8, wherein the first connector is not arranged along a longitudinal axis (Do) of the first via. [10] Method according to claim 8 or 9, wherein the second connector is arranged along a longitudinal axis of the second via. [11] Method according to any one of claims 7 to 10, wherein the first via (122A) is longer than the second via (122B) after planarizing. [12] Method which features the following: Deposition of a first nucleation layer (106) on a first dielectric layer (104); Plating of a first conductive feature (108A) and a second conductive feature (108B) on the first germ layer; Deposition of a second dielectric layer (112) on the first conductive feature (108A) and the second conductive feature (108B); Forming a first opening (114A, 114B) in the second dielectric layer (112), wherein the first opening exposes the first conductive feature (108A), the second conductive feature (108B) and the first dielectric layer (104); Deposition of a second nucleation layer (118) on the second dielectric layer (112) and in the first opening (114A, 114B); Plating of a first through-hole (122A) of sections of the second nucleation layer (118) in the first opening (114A, 114B); Attaching a die (124) to the second dielectric layer (112); and Encapsulation of the first via (122A) and the die (124) with an encapsulation (140) Forming a second opening (114B) in the first dielectric layer (112), wherein the second opening exposes the first nucleus layer (106) and the second nucleus layer (118); Etching of exposed sections of the first germ layer and the second germ layer in order to remove at least one section of the first germ layer and the second germ layer; Forming a reflowable material (318B) in the second opening (114B), wherein the reflowable material is arranged along a longitudinal axis of the first via; and Reflow of the reflow-capable material to form an intermetallic connection between the reflow-capable material and conductive material of the first seed layer, the second seed layer and the first via. [13] The method of claim 12, further comprising: Attaching a device package (300) to the first conductive feature (122A) and the second conductive feature (122B) with the reflowable material. [14] Method according to claim 12 or 13, wherein the reflow of the reflowable material comprises diffusing sections of the conductive material of the first via into the reflowable material. [15] Method according to any one of the preceding claims 12 to 14, further comprising: Formation of a third conductive feature (108B) on the first dielectric layer (104); Deposition of the second dielectric layer (112) on the third conductive feature (118); Forming a second opening (114B) in the second dielectric layer (112), wherein the second opening exposes the third conductive feature (118); Deposition of the second germ layer (118) in the second opening; and Plating of a second via (122B) of sections of the second nucleation layer (118) in the second opening (114A); [16] The method of claim 15, further comprising: Forming a third opening in the first dielectric layer, wherein the third opening exposes the first nucleus layer (106); Etching of exposed sections of the first germ layer (106) in order to remove at least one section of the first germ layer (106); Forming a reflowable material (318A) in the third opening, wherein the reflowable material is arranged along a different axis than a longitudinal axis of the second via; and Reflow of the reflow-capable material to form an intermetallic bond between the reflow-capable material and the conductive material of the first seed layer. [17] Method according to claim 16, wherein the reflow of the reflowable material comprises diffusing sections of the conductive material of the third conductive feature into the reflowable material (318A). [18] Method according to claim 16 or 17, wherein no section of the intermetallic compound (318A) is formed between the second via (122A) and the first dielectric layer (104). [19] Method according to any one of the preceding claims 15 to 18, further comprising: Planarizing the first via (122A), the second via (122B) and the encapsulation (140), wherein the first via (122A) is longer than the second via (122B) after planarizing.

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