Method for operating a dynamic low-power double data rate 5 direct access memory (LPDDR5 DRAM)

Abstract

Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).

Description

BACKGROUND 1. Technical field

[0001] Exemplary embodiments relate generally to integrated semiconductor circuits and more specifically to a method for controlling on-die termination and a system that performs the method. In particular, the invention relates to a method for operating a dynamic low-power double data rate 5 direct access memory (LPDDR5 DRAM). 2. Discussion of the state of the art

[0002] On-die termination (ODT) is introduced to improve signal integrity by reducing signal reflection between a transmitter and a receiver. An ODT circuit can reduce signal reflection by providing a termination resistor matched to the impedance of a transmission line. However, while implementing ODT to improve signal integrity may increase power consumption, it can also increase overall power consumption.

[0003] From US Patent 2010 / 0182817A1, a memory system is known that comprises the following: a plurality of semiconductor memory devices, each containing a termination resistor circuit that can be switched on or off externally by means of a termination resistor control signal, and a memory controller. The memory controller includes a termination resistor control unit that outputs the termination resistor control signal, so that when a read or write command is executed on one of the semiconductor memory devices, the termination resistors of all semiconductor memory devices are switched on, and when a read or write command is executed on one of the semiconductor memory devices, the termination resistors of all semiconductor memory devices are switched off.The termination resistor circuit of one of the semiconductor memory devices is switched off, regardless of the level of the termination resistor control signal, when the semiconductor memory device outputs data in response to the read command.

[0004] From US 8 619 492 B2, an on-die termination (ODT) circuit of a memory chip is known, comprising: a memory chip with a memory core having a memory cell array; a data input / output pin connected to the memory core via a data buffer; and an on-die termination (ODT) circuit comprising: a termination circuit configured to provide a termination impedance at the input / output data pin, wherein the termination circuit has a switching device that selectively connects a termination impedance to the input / output data pin based on the presence of an asynchronous control signal (ACS), the ACS being generated based on the presence of a memory write instruction (WRITE).The storage device may further include a training circuit comprising: an asynchronous signal delay configured to delay the path of the ACS signal to the termination circuit; and a comparator configured to compare a phase difference between the ACS signal and a reference signal, the comparator comprising a phase detector and a replication delay, the replication delay being configured to delay the path of the ACS signal to the phase detector, and the phase detector being configured to output the phase difference as the training result. SUMMARY

[0005] The problem of the invention is solved by a method according to the main claim and by the methods according to the dependent claims. Further developments of the invention are specified in the dependent claims.

[0006] At least one embodiment of the inventive concept provides a method for controlling an ODT which is capable of reducing power consumption and increasing signal integrity.

[0007] At least one embodiment of the inventive concept provides for a system which performs a method for controlling an ODT which is capable of reducing power consumption and improving signal integrity.

[0008] According to an exemplary embodiment of the inventive concept, a method for controlling on-die termination (ODT) in a multi-rank or multi-bank system having a plurality of memory ranks comprises activating ODT circuits of the plurality of memory ranks to an initial state when the multi-rank memory system is powered on, activating the ODT circuits of a write-target memory rank and of non-target memory ranks among the plurality of memory ranks during a write operation, and deactivating the ODT circuit of a read-target memory rank amidst the plurality of memory ranks, while the ODT circuits of non-target memory ranks amidst the plurality of memory ranks are deactivated during a read operation.

[0009] According to an exemplary embodiment of the inventive concept, a method for controlling an on-die termination (ODT) in a storage device includes activating an ODT circuit of the storage device to an initial state to have a first resistance value when the storage device is turned on, activating the ODT circuit during a write operation with respect to the storage device, and deactivating the ODT circuit during a read operation with respect to the storage device.

[0010] According to an exemplary embodiment of the inventive concept, a system comprises a plurality of memory ranks or memory banks, each comprising a plurality of memory devices, and a memory controller configured to manage the plurality of memory ranks. On-die-terminator (ODT) circuits of the plurality of memory ranks are activated to an initial state when the system is powered on. The ODT circuits of the plurality of memory ranks are activated during a write operation with respect to a write-target memory rank and non-target memory ranks within the plurality of memory ranks. The ODT circuit of a read-target memory rank within the plurality of memory ranks is deactivated, while the ODT circuits of non-target memory ranks within the plurality of memory ranks are activated during a read operation.

[0011] According to an exemplary embodiment of the inventive concept, a system comprises a first memory rank and a second memory rank. The first memory rank comprises a plurality of first memory devices connected to a first on-die termination (ODT) circuit. The second memory rank comprises a plurality of second memory devices connected to a second ODT circuit. The first and second ODT circuits are activated during a write operation of the first memory rank, and the first ODT circuit is deactivated and the second ODT circuit is activated during a read operation of the first memory rank.

[0012] The method for controlling ODT and the system that performs the method according to exemplary embodiments can reduce power consumption and improve signal integrity through static ODT control such that the ODT circuits of the target memory rank and the non-target memory rank are generally maintained in the activated state, whereas the ODT circuit of the read target memory rank is deactivated during the read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Exemplary embodiments of the present disclosure will be more clearly understood from the following detailed description together with the accompanying drawings. Fig. Figure 1 is a flowchart illustrating a method for controlling on-die termination (ODT) according to an exemplary embodiment of the inventive concept. Fig. Figure 2 is a timing diagram illustrating a method for controlling an ODT according to an exemplary embodiment of the inventive concept. Fig. Figure 3 is a block diagram illustrating a multi-rank system according to an exemplary embodiment of the inventive concept. Fig. Figure 4 is a block diagram illustrating an exemplary embodiment of a storage device used in the multi-rank system of the Fig. 3 is included. Fig. Figure 5 is a block diagram illustrating one embodiment of a data input / output circuit, which is used in the storage device of the Fig. 4 according to an exemplary embodiment of the inventive concept. Fig. Figure 6 is a circuit diagram illustrating an ODT circuit, which is used in the data input / output circuit of the Fig. 5 according to an exemplary embodiment of the inventive concept. Fig. 7, Fig. 8A and Fig. Figure 8B are diagrams illustrating a method for controlling an ODT in a write operation according to an exemplary embodiment of the inventive concept. Fig. 9 and Fig. Figure 10 are diagrams illustrating a method for controlling an ODT in a read operation according to an exemplary embodiment of the inventive concept. Fig. Figure 11 is a diagram illustrating an embodiment of a resistance setting applied to a method for controlling an ODT according to an exemplary embodiment of the inventive concept. Fig. Figure 12 is a diagram for describing an equivalent resistance of the ODT circuit in a write operation, which corresponds to the resistance setting of the Fig. 11 corresponds to this. Fig. Figure 13 is a diagram for describing an equivalent resistance of the ODT circuit in a read operation, which corresponds to the resistance setting of the Fig. 11 corresponds to this. Fig. 14A and Fig. 14B are diagrams for describing a center-tapped termination (CTT = Center-Tapped Termination). Fig. 15A and Fig. 15B are diagrams to describe an initial pseudo-open-drain (POD) termination. Fig. 16A and Fig. 16B are diagrams to describe a second POD termination. Fig. Figure 17 is a diagram illustrating an embodiment of a resistance setting applied to a method for controlling an ODT according to an exemplary embodiment of the inventive concept. Fig. Figure 18 is a diagram illustrating a CAS instruction according to an exemplary embodiment of the inventive concept. Fig. 19A and Fig. Figure 19B shows diagrams for describing a mode register for an ODT according to an exemplary embodiment of the inventive concept. Fig. Figure 20 is a structural diagram illustrating a semiconductor storage device according to an exemplary embodiment of the inventive concept. Fig. Figure 21 is a block diagram illustrating a mobile system according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0014] The inventive concept will be described in more detail below with reference to the accompanying drawings, which show some exemplary embodiments of the inventive concept. In the drawings, similar reference numerals refer to similar elements throughout.

[0015] Fig. Figure 1 is a flowchart illustrating a method for controlling on-die termination (ODT) according to an exemplary embodiment of the inventive concept, and Fig. Figure 2 is a timing diagram illustrating a method for controlling an ODT according to an exemplary embodiment of the inventive concept.

[0016] The Fig. 1 and Fig. Figure 2 illustrates a method for controlling an ODT in a multi-rank system, which has a plurality of memory ranks. The multi-rank system is described below with reference to Fig. 3. In one embodiment, a memory rank is a set of memory chips connected to the same chip selection signal. Therefore, if there are multiple memory ranks, each memory rank receives a different chip selection signal. In another embodiment, the set of memory chips for a given memory rank uses the same instruction and control signals.

[0017] Referring to Fig. 1. When the multi-rank system is powered on, the ODT circuits of a plurality of memory ranks are activated to an initial state (S100). For example, activating the ODT circuits to an initial state can be accomplished by applying power to the ODT circuits and setting a resistor of each ODT circuit to the same resistance value. The ODT circuits of the plurality of memory ranks are activated during a write operation with respect to a write-target memory rank within the plurality of memory ranks (S200). For example, if one of the ODT circuits of a memory rank that is currently the target of a write is currently disabled due to a previous read operation of that memory rank, then that ODT will be activated during the write operation.Furthermore, the ODT circuit of the memory rank that is currently the target of the write operation can be activated some time before the actual write operation. The ODT circuit of a read target memory rank among a majority of memory ranks is deactivated during a read operation with respect to that read target memory rank (S300).

[0018] A memory access operation can consist of a write operation and a read operation, and it can be distinguished from other operations such as a mode register write operation, a mode register read operation, a refresh operation, etc. In the case of a write operation, the plurality of memory ranks can be divided by a write destination memory rank, which is an object of the write operation, and non-destination memory ranks, excluding the write destination memory rank. For example, during a write operation, data is written to a plurality of memory ranks (that is, the write destination memory rank), and the data is not written to the remaining memory ranks.In the case of a read operation, the plurality of memory ranks can be subdivided by a read target memory rank, which is an object of the read operation, and non-target memory ranks, with the exception of the read target memory rank. For example, during a read operation, data is read from one plurality of memory ranks (that is, the read target memory rank), and data is not read from the remaining memory ranks. The write target memory rank or the read target memory rank can simply be referred to as a target memory rank.

[0019] Referring to Fig. 2. At time T1, when the multi-rank system is switched on, the ODT circuits of the plurality of memory ranks are activated to their initial state. In an exemplary embodiment, each of the ODT circuits of the plurality of memory ranks is set to have a first resistance value in the initial state. Even if Fig. Figure 2 illustrates that if the activation time of the ODT circuits coincides with the switch-on time, the switch-on sequence can be completed first, and then, after a certain time interval has elapsed, the ODT circuits can be activated to the initial state.

[0020] During time intervals T2-T3 and T4-T5, while the write operation is being performed, all ODT circuits of the memory ranks, including the write-target memory rank and the non-target memory ranks, maintain an activated state. In one exemplary embodiment, the ODT circuits of the majority of memory ranks are maintained in their initial state to have the first resistance value during the write operation. In another exemplary embodiment, the resistance value of the ODT circuit of the write-target memory rank is changed from the first resistance value to a second resistance value different from the first resistance value during the write operation.

[0021] During a time interval T6-T7, while the read operation is being performed, the ODT circuit of the target memory rank is deactivated, and the ODT circuits of the non-target memory ranks are activated. In an exemplary embodiment, the ODT circuits of the non-target memory ranks are maintained in their initial state to have the first resistance value during the read operation. Even if Fig. Figure 2 illustrates that the time interval for disabling the read target memory rank coincides with the time interval of the read operation. Therefore, the time interval for disabling the read target memory rank can be shorter than the time interval of the read operation. In other words, it is sufficient for the ODT circuit of the read target memory rank to be disabled only while read data is being output through the data input / output contacts. For example, the ODT circuit of the read target memory rank can be disabled only while data being read from the target memory rank is being output through the target memory rank's contacts.

[0022] At time T8, when the multi-rank system is switched off, a power supply is blocked and the ODT circuits of all memory ranks are deactivated. For example, a switch may be present between the power supplied to the ODT circuits, and the blocking can be accomplished by opening the switch. For example, if the switch is a transistor, the switch can be opened based on a control signal applied to a gate of the transistor.

[0023] If only the ODT circuitry of the target memory rank is enabled and the ODT circuitry of the non-target memory ranks is disabled, signal integrity can be degraded because waves of signals injected into the non-target memory ranks are not terminated, and therefore jitter or noise can be caused. In contrast, according to at least one embodiment of the inventive concept, signal integrity can be improved by enabling the ODT circuitry almost always, except in the case of the read target memory rank. Even if the ODT circuitry of the non-target memory ranks is always enabled, standby power consumption in the case of pseudo-open drain termination will not be caused, as described below.

[0024] If the ODT circuits of the non-target memory ranks are enabled during the write operation and disabled during the read operation, all memory ranks are in a state of readiness to receive and decode a memory access command (for example, a write or read command). In this case, the ODT circuits do not enter a shutdown mode, and therefore the standby power consumption is increased. In contrast, according to an exemplary embodiment, the ODT circuits of the non-target memory ranks are maintained in the enabled state during both the write and read operations. In this case, the ODT circuits can more easily enter a shutdown mode, and therefore the standby power consumption can be reduced.

[0025] In one embodiment, the ODT circuits of the non-target memory ranks, located among the majority of memory ranks, have a constant resistance value independent of the memory access instruction (for example, a write instruction or a read instruction) issued by the memory controller. This constant resistance value can be based on a value stored in the mode register.

[0026] In an exemplary embodiment, the plurality of memory ranks corresponding to the target memory rank for the write or read operation are informed based on a plurality of rank selection signals, each provided for a plurality of memory ranks. In this case, all memory ranks in the standby state enter shutdown mode, and the target memory rank corresponding to the activated rank selection signal is woken up from shutdown mode to normal operating mode. The non-target memory ranks do not need to change the activated state of the ODT circuits, and therefore the shutdown mode can be maintained with respect to the non-target memory ranks.

[0027] As such, the method for controlling an ODT and the system that performs the method according to at least one embodiment can reduce power consumption and improve signal integrity through static ODT control such that the ODT circuits of the target memory rank and the non-target memory rank are generally maintained in the activated state, whereas the ODT circuit of the read target memory rank is deactivated during the read operation.

[0028] Although a method for controlling an ODT for the multi-rank system with reference to the Fig. 1 and Fig. As described in section 2, the exemplary embodiment can be applied to a system which has a storage device of a single storage rank.

[0029] In the case of the single-rank system, the single storage device corresponds to the write target memory rank during the write operation and the read target memory rank during the read operation. According to an exemplary embodiment, an ODT circuit of the storage device is activated to an initial state to have a first resistance value when the storage device is powered on. The ODT circuit can be activated during the write operation with respect to the storage device, and the ODT circuit can be deactivated during the read operation with respect to the storage device.

[0030] Fig. Figure 3 is a block diagram illustrating a multi-rank system according to an exemplary embodiment of the inventive concept.

[0031] Referring to Fig. Figure 3 comprises a multi-rank system 10, a memory controller 20, and a memory subsystem 30. The memory subsystem 30 has a plurality of memory ranks RNK1 to RNKM, and each of the memory ranks RNK1 to RNKM has one or more memory devices MEM, where M is a natural number greater than 1. The memory controller 20 and the memory subsystem can each have interface circuits for bidirectional communication. The interface circuits can be connected by a control bus for transmitting a command CMD, an address ADDR, and a control signal CTRL, etc., and by a data bus for transmitting data. In one embodiment, the command CMD has the address ADDR.The memory controller 20 can issue the command CMD and the address ADDR for accessing the memory subsystem 30, and data can be written to or read from the memory subsystem 30 under the control of the memory controller 20. In one embodiment, the memory controller 20 has separate contacts for issuing the control signal CTRL, the command CMD, the address ADDR, and for exchanging the data DATA with the memory subsystem 30. If the command CMD specifies the address ADDR, the memory controller 20 can omit the contact for issuing the address ADDR.According to an exemplary embodiment, ODT circuits of the plurality of memory ranks RNK1 to RNKM are activated in an initial state when the multi-rank system 10 is switched on, the ODT circuits of the plurality of memory ranks RNK1 to RNKM are activated during a write operation with respect to a write target memory rank amidst the plurality of memory ranks RNK1 to RNKM, and the ODT circuit of a read target memory rank amidst the plurality of memory ranks RNK1 to RNKM is deactivated during a read operation with respect to the read target memory rank.

[0032] Fig. Figure 4 is a block diagram showing an exemplary embodiment of a storage device used in the multi-rank system of the Fig. 3 is included, illustrating.

[0033] Referring to Fig. 4 includes a storage device 400, a control logic 410 (for example, a control logic circuit), an address register 420, a bank control logic 430 (for example, a bank control logic circuit), a line address multiplexer 440, a refresh counter 445, a line decoder 460, a column decoder 470, a memory cell arrangement 480, a read amplifier unit 485 (for example, a read amplifier circuit), an input / output (I / O) clock circuit (gating circuit) 490, and a data input / output (I / O) circuit 500.

[0034] The memory cell arrangement 480 comprises a plurality of bank arrangements 480a to 480h. The row decoder 460 comprises a plurality of bank row decoders 460a to 460h, each coupled to bank arrangements 480a to 480h. The column decoder 470 comprises a plurality of bank column decoders 470a to 470h, each coupled to bank arrangements 480a to 480h. The read amplifier unit 485 comprises a plurality of bank read amplifiers 485a to 485h, each coupled to bank arrangements 480a to 480h.

[0035] Address register 420 receives an address ADDR, which contains a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR, from memory controller 20. Address register 420 provides the received bank address BANK_ADDR for the bank control logic 430, the received row address ROW_ADDR for the row address multiplexer 440, and the received column address COL_ADDR for a column decoder 470.

[0036] The bank control logic 430 can generate bank control signals based on the bank address BANK_ADDR. One of the bank line decoders 460a to 460h, corresponding to the bank address BANK_ADDR, can be activated based on these bank control signals. Similarly, one of the bank column decoders 470a to 470h, corresponding to the bank address BANK_ADDR, can be activated based on these bank control signals.

[0037] The line address multiplexer 440 can receive the line address ROW_ADDR from address register 420 and can receive a refresh line address REF_ADDR from refresh counter 445. The line address multiplexer 440 can selectively output either the line address ROW_ADDR or the refresh line address REF_ADDR as a line address RA. The line address RA output by the line address multiplexer 440 can be applied to bank line decoders 460a to 460h.

[0038] The activated bank line decoder 460a to 460h can decode the line address RA, which is output by the line address multiplexer 440, and can activate a word line corresponding to the line address RA. For example, the activated bank line decoder can apply a word line driver voltage to the word line corresponding to the line address RA.

[0039] The column decoder 470 can include a column address latch. The column address latch can receive the column address COL_ADDR from the address register 420 and temporarily store the received column address COL_ADDR. In an exemplary embodiment, in burst mode, the column address latch generates column addresses that increment the received column address COL_ADDR. The column address latch can then apply the temporarily stored or generated column address to the bank column decoders 470a to 470h.

[0040] The activated one of the bank column decoders 470a to 470h can decode the column address COL_ADDR, which is output by the column address latch, and can control the input / output clock circuit 490 to output data corresponding to the column address COL_ADDR.

[0041] The I / O clock circuit 490 can include a circuit for gating input / output data. The I / O clock circuit 490 can also include read data latches for storing data output by bank arrangements 480a to 480h, and write drivers for writing data to bank arrangements 480a to 480h.

[0042] Data to be read from a bank arrangement 480a to 480h can be sampled by a read amplifier 485, which is coupled to the bank arrangement from which the data is to be read, and stored in the read data latches. The data stored in the read data latches can be made available to the memory controller 20 via the data I / O circuit 500. Data DQ to be written to a bank arrangement 480a to 480h can be made available to the data I / O circuit 500 by the memory controller 20. The write driver can write the data DQ to a bank arrangement 480a to 480h.

[0043] The control logic 410 can control operations of the storage device 400. For example, the control logic 410 can generate control signals for the storage device 400 to perform a write or read operation. The control logic 410 can include an instruction decoder 411, which decodes a CMD instruction received from the memory controller 20, and a mode register set 412, which sets an operating mode of the storage device. For example, a value in a register in the mode register set 412 can indicate the operating mode of the storage device.

[0044] Fig. Figure 5 is a block diagram illustrating an embodiment of a data input / output circuit, which is used in the storage device of the Fig. 4 according to an exemplary embodiment of the inventive concept.

[0045] Referring to Fig. Figure 5 comprises a data input / output circuit 500, an ODT circuit 300, a data input / output contact 600, a transfer driver DR710, and a receive buffer BF720. The transfer driver 710 drives the data input / output contact 600 based on read data, and the receive buffer 720 receives write data provided by the data input / output contact 600. For example, data read from a memory of a memory rank is output to the transfer driver 710, and the memory controller outputs write data to the receive buffer 720. In one embodiment, the transfer driver DR710 and the receive buffer BF720 are implemented by an operational amplifier.

[0046] The ODT circuit 300 includes a termination control unit 310 (for example, a termination control circuit) and a termination resistor unit 350.

[0047] The termination resistor unit 350 is coupled to the data input / output contact 600 and provides a termination impedance for a transmission line that is coupled to the data input / output contact 600. The method for controlling the ODT according to an exemplary embodiment can be used to control the termination of input / output contacts for bidirectional communication between the memory controller 20 and the storage device 30. Accordingly, the method according to an exemplary embodiment can be applied to a data strobe contact, a data mask contact, or a termination data strobe contact in addition to the data input / output contact 600. The ODT of an address contact, a command contact for unidirectional communication from the memory controller 20 to the storage device 30, is excluded from the method according to an exemplary embodiment.The term "contact" refers broadly to an electrical connection for an integrated circuit, for example a contact point or other electrical contact on the integrated circuit.

[0048] In one embodiment, the termination resistor unit 350 performs a pull-up termination operation to provide a termination resistor between a power supply voltage node and the data input / output contact 600, and / or a pull-down termination operation to provide a termination resistor between a ground node and the data input / output contact 600. A center-tapped termination (CTT) for both the pull-up and pull-down termination operations is described below with reference to the Fig. 14A and Fig. As described in 14B, a first pseudo-open-drain (POD) termination for only the pull-down termination operation is shown below with reference to the Fig. 15A and Fig. 15B is described and a second POD termination for only the pull-up termination operation is described below with reference to the Fig. 16A and Fig. 16B will be described.

[0049] Even if Fig. Figure 5 illustrates an exemplary embodiment in which a dedicated termination resistor unit 350 is provided. A signal driver (not shown) can itself act as a termination resistor in the transmission driver 710. For example, during the write operation, the transmission driver 710 does not transmit read data and acts as the termination resistor unit 350 while the receive buffer 720 is activated to receive write data.

[0050] When the termination resistor unit 350 performs the pull-up termination operation, the voltage of the transmission line connected to the data input / output contact 600 can be maintained essentially at the level of the power supply voltage. As a result, current flows through the termination resistor unit 350 and the transmission line only when data of a low logic level is transmitted. In contrast, when the termination resistor unit 350 performs the pull-down termination operation, the voltage of the transmission line connected to the data input / output contact 600 can be maintained essentially at the ground voltage. As a result, current flows through the termination resistor unit 350 and the transmission line only when data of a high logic level is transmitted.

[0051] The termination control unit 310 (for example, a termination control circuit) receives a strength code SCD and an output activation signal OEN. The termination control unit 310 generates a termination control signal TCS to control the termination resistor unit 350 in order to adjust the termination impedance based on the strength code SCD and the output activation signal OEN.

[0052] In an exemplary embodiment, the strength code SCD is a plurality of bits associated with a data rate. The data rate refers to an operating frequency of the storage device or a switching rate of data transmitted through the data input / output contact 600. For example, the termination impedance may be changed to a first impedance if the operating frequency is a first frequency, and to a second termination if the operating frequency is a second different frequency. As below, with reference to the Fig. 19A and Fig. As described in section 19B, the strength code SCD can be provided by several bits based on the values ​​stored in mode register 412 in Fig. 4 are stored.

[0053] In one embodiment, the output activation signal OEN is activated during a read operation. While the output activation signal OEN is active, the termination control unit 310 provides a termination control signal TCS at a predetermined logic level to control the termination resistor unit 350, thus eliminating the need for a termination impedance. In this case, the termination resistor unit 350 can be electrically decoupled from the data input / output contact 600 in response to the termination control signal TCF, which has the predetermined logic level. When the termination resistor unit 350 is electrically decoupled from the data input / output contact 600, the ODT circuit 300 or the termination resistor unit 350 can be considered "deactivated".

[0054] While the output activation signal OEN is disabled during a write operation, the termination control unit 310 generates the termination control signal TCS to control the termination resistor unit 350 to provide the termination impedance. The termination control unit 310 can modify a logic level of the termination control signal TCS in response to the strength code SCD to vary the termination impedance. For example, a value of the strength code SCD can indicate a specific termination impedance or resistance. If the termination resistor unit 350 was previously electrically decoupled from the data input / output contact 600, the termination resistor unit 350 is recoupled to the data input / output unit 600 in response to the application of the termination control signal TCS.

[0055] Fig. Figure 6 is a circuit diagram illustrating an ODT circuit, which is used in the data input / output circuit of the Fig. 5 according to an exemplary embodiment of the inventive concept.

[0056] Referring to Fig. 6 features an ODT circuit 300, a pull-up termination control unit 330, a pull-down termination control unit 340, a pull-up driver 360 and a pull-down driver 370.

[0057] The pull-up termination control unit 330 has a first to third selector 334 to 336 (e.g., multiplexer), and the pull-down termination control unit 340 has a fourth to sixth selector 344 to 346 (e.g., multiplexer). The pull-up driver 360 has a first to third PMOS transistor 361 to 363 and a first to third resistor R1 to R3. The first to third PMOS transistors 361 to 363 are connected to a power supply voltage VDDQ, and each of the first to third resistors R1 to R3 is connected between a respective first to third PMOS transistor 361 to 363 and the data input / output contact 600. The pull-down driver 370 has a first to third NMOS transistor 371 to 373 and a fourth to sixth resistor R4 to R6.The first to third NMOS transistors 371 to 373 are connected to a ground voltage VSSQ, and each of the fourth to sixth resistors R4 to R6 is connected between a respective one of the first to third NMOS transistors 371 to 373 and the data input / output contact 600.

[0058] Each of the first to third selectors 334 to 336 can receive the power supply voltage VDDQ as any of the first inputs, the first to third strength code bits SCD1, SCD2, and SCD3 as any of the second inputs, and the output enable signal OEN as any of the control signals. Each of the fourth to sixth selectors 344 to 346 can receive the ground voltage VDDQ as any of the first inputs, the fourth to sixth strength code bits SCD4, SCD5, and SCD6 as any of the second inputs, and the output enable signal OEN as any of the control signals. The strength code SCD can include strength code bits SCD1 to SCD6.

[0059] While the output enable signal OEN is enabled at a logic high level during a read operation, the first to third selectors 334 to 336 can output the first to third logic high termination control signals TCS1, TCS2, and TCS3, and the fourth to sixth selectors 344 to 346 can output the fourth to sixth logic low termination control signals TCS4, TCS5, and TCS6. The first to third PMOS transistors 361 to 363 are turned off in response to the first to third logic high termination control signals TCS1, TCS2, and TCS3, and the fourth to sixth PMOS transistors 371 to 373 are turned off in response to the fourth to sixth logic low termination control signals TCS4, TCS5, and TCS6. Accordingly, the data input / output contact 600 is electrically disconnected from the power supply voltage VDDQ and the ground voltage VSSQ, and the ODT circuit 300 is deactivated during the read operation.

[0060] While the output activation signal OEN is activated at a logic low level during a write operation, the first to third selectors 334 to 336 output the first to third strength code bits SCD1, SCD2 and SCD3 as the first to third termination control signal TCS1, TCS2 and TCS3, and the fourth to sixth selectors 344 to 346 output the fourth to sixth strength code bits SCD4, SCD5 and SCD6 as the fourth to sixth termination control signal TCS4, TCS5 and TCS6.

[0061] As described above, the strength code SCD, that is, the strength code bits SCD1 to SCD6, can be related to the data rate or the operating frequency. Consequently, if the data rate is relatively high, channels are quickly charged / discharged by decreasing the termination impedance. If the data rate is relatively low, power consumption can be reduced by increasing the termination impedance to decrease the DC currents flowing through the channels.

[0062] Although each of the first to sixth resistors R1 to R6 in Fig. Where 6 is illustrated as a single resistor, in exemplary embodiments each of the first to sixth resistors R1~R6 can be implemented with a plurality of resistors connected in parallel and / or in series, and a plurality of transistors for controlling connections of the plurality of resistors.

[0063] Fig. Figure 6 illustrates an exemplary embodiment of the CTT scheme of the Fig. 14A and Fig. 14B and the POD termination scheme can be understood from this. A configuration which uses the pull-up termination control unit 330 and the pull-up driver 360 from Fig. Omitting 6 corresponds to the first POD termination of the Fig. 15A and Fig. 15B, and a configuration which includes the pull-down termination control unit 340 and the pull-down driver 370 from Fig. Omitting 6 corresponds to the second POD termination of the Fig. 16A and Fig. 16B.

[0064] The Fig. 7, Fig. 8A and Fig. Figure 8B are diagrams illustrating a method for controlling an ODT in a write operation according to an exemplary embodiment of the inventive concept.

[0065] As in Fig. As illustrated in Figure 7, the memory controller MC is connected in parallel to the majority of memory ranks RNK1 to RNKM via the data input / output contacts PADC and PAD1 to PADM and the transmission line TL. The transmission line TL is branched off at a common node NC to the data input / output contacts PAD1 to PADM of the memory ranks RNK1 to RNKM.

[0066] Fig. Figure 7 illustrates an example case where the first memory rank, RNK1, corresponds to the write destination memory rank, and the other memory ranks, RNK2 to RNKM, correspond to the non-destination memory ranks. Fig. The activated elements are shaded. During the write operation, the transfer driver DR0 is activated and the receive buffer BF0 is deactivated in the memory controller MC, which corresponds to the data transmission device. Additionally, the receive buffer BF1 is activated in the write destination memory rank RNK1, which corresponds to the data receiver device, whereas the transfer driver DR1 in the write destination memory rank RNK1, the receive buffers BF2 to BFM, and the transfer drivers DR2 to DRM in the non-destination memory ranks RNK2 to RNKM are deactivated.

[0067] According to an exemplary embodiment, during the write operation, the ODT circuit TER1 in the write target memory rank RNK1 and the ODT circuits TER2 to TERM in the non-target memory ranks RNK2 to RNKM are all enabled. The ODT circuit TERO in the memory controller MC is disabled. The current path can be formed from the transfer driver DR0 in the memory controller MC to all of the ODT circuits TER1 to TERM in the memory ranks RNK1 to RNKM, and therefore signal reflection can be reduced and signal integrity can be increased.

[0068] In the Fig. 8A and Fig. 8B correspond to time points Ta0 to Tf1, edges of an operating clock signal pair CK_T and CK_C. A first rank selection signal CS_RNK1 and a first command signal CMD_RNK1 are dedicated to a first memory rank RNK1, and a second rank selection signal CS_RNK2 and a second command signal CMD_RNK2 are dedicated to a second memory rank RNK2. A data strobe signal pair WCK_T and WCK_C and data signals DQ [15:0] are provided by the memory controller MC for the write destination memory rank RNK1. ODT_RNK1 represents an ODT state of the first memory rank RNK1, and ODT_RNK2 represents an ODT state of the second memory rank RNK2. DES represents "deselect," and TRANSITION represents transition intervals when the ODT state changes.

[0069] The Fig. 8A and Fig. Figure 8B shows an example of a write operation where the first memory rank, RNK1, corresponds to the write target memory rank, and the second memory rank, RNK2, corresponds to the non-target memory rank. While the first rank selection signal, CS_RNK1, is enabled, the CAS instruction and the write instruction, WR, are transmitted via the first command signal, CMD_RNK1, and the second rank selection signal, CS_RNK2, and the second command signal, CMD_RNK2, maintain the disabled states.

[0070] According to an exemplary embodiment, during the write operation, the ODT circuits in the write-target memory rank RNK1 and the ODT circuit in the non-target memory rank RNK2 are activated. In an exemplary embodiment, as shown in Fig. As illustrated in Figure 8A, the ODT circuits in the write-destination memory rank RNK1 and the non-destination memory rank RNK2 maintain the initial state NT-ODT while the data signals DQ [15:0] switch for the write operation. In an exemplary embodiment, the ODT circuit in the non-destination memory rank RNK2 maintains the initial state NT-ODT, and the ODT circuit in the write-destination memory rank RNK1 changes to a state TG-ODT, which has a resistance value different from that of the initial state NT-ODT, while the data signals DQ [15:0] switch for the write operation. While data signals of 16-bit data are described above, the inventive concept is not limited thereto, since the size of the data can be less than 16 bits or greater than 16 bits in alternating embodiments.

[0071] The Fig. 9 and Fig. Figure 10 are diagrams illustrating a method for controlling an ODT in a read operation according to an exemplary embodiment of the inventive concept.

[0072] As in Fig. As illustrated in Figure 9, the memory controller MC is connected in parallel to the majority of memory ranks RNK1 to RNKM via the data input / output contacts PADC and PAD1 to PADM and the transmission line TL. The transmission line TL branches off at a common node NC to the data input / output contacts PAD1 to PADM of the memory ranks RNK1 to RNKM.

[0073] Fig. Figure 9 illustrates an example case in which the first memory rank, RNK1, corresponds to the read target memory rank, and the other memory ranks, RNK2 to RNKM, correspond to the non-target memory ranks. Fig. In section 9, the activated elements are shaded. During the read operation, the receive buffer BF0 is activated and the transfer driver DR0 is deactivated in the memory controller MC, which corresponds to the data receiver device. Additionally, the transfer driver DR1 is activated in the read destination memory rank RNK1, which corresponds to the data transmission device, whereas the receive buffer BF1 in the read destination memory rank RNK1, the receive buffers BF2 to BFM, and the transfer drivers DR2 to DRM in the non-destination memory ranks RNK2 to RNKM are deactivated.

[0074] According to an exemplary embodiment, the ODT circuit TER1 in the write target memory rank RNK1 is deactivated, and the ODT circuits TER2 to TERM in the non-target memory ranks RNK2 to RNKM are activated. The ODT circuit TER0 in the memory controller MC is activated. The current path can be formed from the transfer driver DR1 in the read target memory rank RNK1 to the ODT circuit TER0 in the transfer driver DR0 and the ODT circuits TER2 to TERM in the non-target memory ranks RNK2 to RNKM, and thus signal reflection can be reduced and signal integrity can be improved or increased.

[0075] In Fig. 10 correspond to the edges of an operating clock signal pair CK_T and CK_C. A first rank selection signal CS_RNK1 and a first command signal CMD_RNK1 are dedicated to a first memory rank RNK1, and a second rank selection signal CS_RNK2 and a second command signal CMD_RNK2 are dedicated to a second memory rank RNK2. A data strobe signal pair WCK_T and WCK_C and data signals DQ [15:0] are provided by the read target memory rank RNK1 to the memory controller MC. ODT_RNK1 represents an ODT state of the first memory rank RNK1, and ODT_RNK2 represents an ODT state of the second memory rank RNK2. DES represents "deselect," and TRANSITION represents transition intervals when the ODT state changes.

[0076] Fig. Figure 10 shows an example of a read operation where the first memory rank, RNK1, corresponds to the target memory rank and the second memory rank, RNK2, corresponds to the non-target memory rank. When the first rank selection signal, CS_RNK1, is enabled, the CAS instruction and the read instruction, RD, are transmitted via the first command signal, CMD_RNK1, and the second rank selection signal, CS_RNK2, and the second command signal, CMD_RNK2, maintain the disabled states.

[0077] According to one exemplary embodiment, during the read operation the ODT circuit in the read target memory rank RNK1 is deactivated and the ODT circuit in the non-target memory rank RNK2 is activated. In one exemplary embodiment, as in Fig. As illustrated in Figure 10, the ODT circuit in the non-target memory rank RNK2 maintains the initial state NT-ODT, and the ODT circuit in the read target memory rank RNK1 is changed to the disabled state NT-ODT OFF, while the data signals DQ [15:0] switch for the read operation.

[0078] Fig. Figure 11 is a diagram illustrating an embodiment of a resistance setting applied to a method for controlling an ODT according to an exemplary embodiment of the inventive concept.

[0079] Referring to Fig. 11. During the read operation, the ODT circuit in the target memory rank RNK_TG is deactivated, and the ODT circuits in the non-target memory rank RNK_NT and the memory controller MC have an initial resistance value of M*Rtt. During the write operation, the ODT circuits in the target memory rank RNK_TG and the non-target memory rank RNK_NT have an initial resistance value of M*Rtt, and the ODT circuit in the memory controller MC is deactivated. The initial resistance value M*Rtt can correspond to a resistance value of the aforementioned initial state. Therefore, as described with reference to Fig. As described in section 8A, the ODT circuits in the target memory rank RNK_TG and the non-target memory rank RNK_NT maintain the initial state to have the first resistance value M*Rtt during the write operation.

[0080] Fig. Figure 12 is a diagram for describing an equivalent resistance of the ODT circuit in a write operation, which corresponds to the resistance setting of the Fig. 11 corresponds to this.

[0081] Referring to Fig. During the write operation, while data is being transferred from the memory controller MC to the target memory rank RNK1, all ODT circuits in the target memory rank RNK1 and the non-target memory ranks RNK2 to RNKM have a first resistance value of M*Rtt. If the number of memory ranks RNK1 to RNKM is M, then M resistors with the first resistance value M*Rtt are connected in parallel between the common node NC and the power supply voltage VDDQ, and the equivalent resistance value between the common node NC and the power supply voltage VDDQ is Rtt. Similarly, the equivalent resistance value between the common node NC and the ground voltage VSSQ is Rtt. The various termination schemes corresponding to the equivalent resistance value Rtt are described below with reference to the Fig. Described in sections 14A to 16B.

[0082] Fig. Figure 13 is a diagram for describing an equivalent resistance of the ODT circuit in a read operation, which corresponds to the resistance setting of the Fig. 11 corresponds to this.

[0083] Referring to Fig. 13. During the read operation, while data is being transferred from the target memory rank RNK1 to the memory controller MC, the ODT circuit in the target memory rank RNK1 is disabled, and the ODT circuits in the non-target memory ranks RNK2 to RNKM and the memory controller MC have a first resistance value of M*Rtt. If the number of the majority of memory ranks RNK1 to RNKM is M, then M resistors with a first resistance value of M*Rtt are connected in parallel between the common node NC and the power supply voltage VDDQ, and the equivalent resistance value between the common node NC and the power supply voltage VDDQ is Rtt. Similarly, the equivalent resistance value between the common node NC and the ground voltage VSSQ is Rtt. The various termination schemes corresponding to the equivalent resistance value Rtt are described below with reference to the Fig. Sections 14A to 16B are described. The configurations of Fig. Figures 14A to 16B are exemplary embodiments to describe some possible termination schemes; however, the configuration of the transfer driver and the ODT circuit is not limited to these. For example, the N-type and P-type transistors can be exchanged and / or the power gating transistors can be added to the transfer driver.

[0084] The Fig. 14A and Fig. 14B are diagrams for describing a center tap termination (CTT).

[0085] Referring to Fig. 14A drives a transmission driver 70 in a transmitter device, which drives an input-output contact point PADH based on a transmission signal ST from an internal signal of the transmitter device. The input-output contact point PADH of the transmitter device is connected to input-output contact points PADS of a receiver device via a transmission line TL. A termination circuit 80 of the CTT scheme is connected to the input-output contact points PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI via the input-output contact points PADS with the reference voltage VREF to provide the buffer signal SB for an internal circuit of the receiver device.

[0086] The transmission driver 70 can include a pull-up unit connected between a first power supply voltage VDDQ and the input-output contact point PADH, and a pull-down unit connected between the input-output contact point PADH and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit can include a turn-on resistor RON and a p-channel metal-oxide-semiconductor (PMOS) transistor TP1, which is switched in response to the transmission signal ST. The pull-down unit can include a turn-on resistor RON and an n-channel metal-oxide-semiconductor (NMOS) transistor TN1, which is switched in response to the transmission signal ST.The switching resistors RON can be omitted and each switching resistor RON can represent a resistance between the voltage node and the input-output junction PADH when each of the transistors TP1 and TN1 is switched on.

[0087] Termination circuit 80 of the CTT scheme can include a first termination circuit connected between the first power supply voltage VDDQ and the input-output junction PADS, and a second termination circuit connected between the input-output junction PADS and the second power supply voltage VSSQ. The first termination circuit can include a termination resistor Rtt and a PMOS transistor TP2, which is turned on in response to a low voltage. The second termination circuit can include a termination resistor Rtt and an NMOS transistor TN2, which is turned on in response to a high voltage. The termination resistors Rtt can be omitted, and each termination resistor Rtt can represent a resistance between the voltage node and the input-output junction PADS when both transistors TP2 and TN2 are turned on.

[0088] In the case of termination circuit 80 of the CTT scheme in Fig. 14A can be the high voltage level VIH and the low voltage level VIL of the input signal SI as in Fig. 14B is represented. The second power supply voltage VSSQ can be assumed to be a ground voltage (i.e., VSSQ = 0), and the voltage drop along the transmission line TL can be neglected. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimal differential voltage VREF can be calculated according to Expression 1. VIH=VDDQ*(RON+Rtt) / (2RON+Rtt),VIL=VDDQ*RON / (2RON+Rtt),VREF=(VIH+VIL) / 2=VDDQ / 2

[0089] The Fig. 15A and Fig. 15B are diagrams to describe an initial pseudo-open-drain (POD) termination.

[0090] Referring to Fig. 15A drives a transmission driver 70 in a transmission device, driving an input-output contact point PADH based on a transmission signal ST from an internal signal of the transmission device. The input-output contact point PADH of the transmission device is connected to an input-output contact point PADS of a receiver device via a transmission line TL. A termination circuit 81 of the first POD termination scheme can be connected to the input-output contact point PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI through the input-output contact point PADS with the reference voltage VREF to provide the buffer signal SB for an internal circuit of the receiver device.

[0091] The transmission driver 70 can include a pull-up unit connected between a first power supply voltage VDDQ and the input-output junction PADH, and a pull-down unit connected between the input-output junction PADH and a second power supply voltage VSSQ, lower than the first power supply voltage VDDQ. The pull-up unit can include a turn-on resistor RON and a PMOS transistor TP1, which is switched on in response to the transmission signal ST. The pull-down unit can include a turn-on resistor RON and an NMOS transistor TN1, which is switched on in response to the transmission signal ST. The turn-on resistors RON can be omitted, and each turn-on resistor RON can represent a resistance between the voltage node and the input-output junction PADH when both transistors TP1 and TN1 are switched on.

[0092] Termination circuit 81 of the first POD termination scheme can include a termination resistor Rtt and an NMOS transistor TN2, which is switched on in response to a high voltage. The termination resistor Rtt can be omitted, and the termination resistor Rtt can represent a resistance between the voltage node and the input-output junction PADS when the NMOS transistor TN2 is switched on.

[0093] In the case of termination circuit 81 of the first POD termination scheme in Fig. 15A can be the high voltage level VIH and the low voltage level VIL of the input signal SI as Fig. 15B is represented. The second power supply voltage VSSQ can be assumed to be a ground voltage (i.e., VSSQ = 0), and the voltage drop along the transmission line TL can be neglected. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimal reference voltage VREF can be calculated according to expression 2. VIH=VDDQ*RTT / (RON+RTT),VIL=VSSQ=0,VREF=(VIH+VIL) / 2=VDDQ*RTT / 2(RON+RTT)

[0094] The Fig. 16A and Fig. 16B are diagrams to describe a second POD termination.

[0095] Referring to Fig. 16A drives a transmission driver 70 in a transmission device, driving an input-output contact point PADH based on a transmission signal ST from an internal signal of the transmission device. The input-output contact point PADH of the transmission device is connected to an input-output contact point PADS of a receiver device via a transmission line TL. A termination circuit 82 of the second POD termination scheme is connected to the input-output contact point PADS of the receiver device for impedance matching. The receive buffer BF in the receiver device can compare the input signal SI via the input-output contact point PADS with the reference voltage VREF to provide the buffer signal SB for an internal circuit of the receiver device.

[0096] The transmission driver 70 can include a pull-up unit connected between a first power supply voltage VDDQ and the input-output junction PADH, and a pull-down unit connected between the input-output junction PADH and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit can include a turn-on resistor RON and a PMOS transistor TP1, which is switched on in response to the transmission signal ST. The pull-down unit can include a turn-on resistor RON and an NMOS transistor TN1, which is switched on in response to the transmission signal. The turn-on resistors RON can be omitted, and each turn-on resistor RON can represent a resistance between the voltage node and the input-output junction PADH when each of the transistors TP1 and TN1 is switched on.

[0097] Termination circuit 82 of the second POD termination scheme can include a termination resistor Rtt and a PMOS transistor TP2, which is switched on in response to a low voltage. The termination resistor Rtt can be omitted, and the termination resistor Rtt can represent a resistance between the voltage node and the input-output junction PADS when the NMOS transistor TN2 is switched on.

[0098] In the case of termination circuit 82 of the first POD termination scheme in Fig. 16A can be the high voltage level VIH and the low voltage level VIL of the input signal SI as in Fig. 16B is represented. The second power supply voltage VSSQ can be assumed to be a ground voltage (i.e., VSSQ = 0), and the voltage drop along the transmission line TL can be neglected. Therefore, the high voltage level VIH, the low voltage level VIL, and the optimal reference voltage VREF can be calculated according to expression 3. VIH=VDDQ,VIL=VDDQ*RON / (RON+Rtt),VREF=(VIH+VIL) / 2=VDDQ*(2RON+Rtt) / 2(RON+Rtt)

[0099] As such, the ODT circuit, according to at least one exemplary embodiment, can employ various termination schemes. In one exemplary embodiment, a training process is performed to obtain the optimal reference voltages VREF according to Expressions 1, 2, and 3. In another exemplary embodiment, the memory controller takes into account the ODT resistors of the non-target memory ranks, which are continuously enabled, to adjust the resistance value of the ODT circuit in the memory controller or the turn-on resistance value of the transfer driver in the memory controller.

[0100] Fig. Figure 17 is a diagram illustrating an embodiment of the resistance setting applied to a method for controlling an ODT according to an exemplary embodiment of the inventive concept.

[0101] Referring to Fig. 17. During the read operation, the ODT circuit in the target memory rank RNK_TG is disabled, and the ODT circuits in the non-target memory rank RNK_NT and the memory controller MC have a first resistance value of M*Rtt. During the write operation, the ODT circuit in the target memory rank RNK_TG has a second resistance value M*Rtt + Rtg, which differs from the first resistance value M*Rtt. The ODT circuit in the non-target memory rank RNK_NT has the first resistance value M*Rtt, and the ODT circuit in the memory controller is disabled. The first resistance value M*Rtt can correspond to a resistance value of the initial state mentioned above. For example, the first resistance value M*Rtt can be approximately 70 Ω, and the second resistance value M*Rtt + Rtg can be approximately 150 Ω. Consequently, as with reference to Fig. As described in Figure 8B, the resistance value of the ODT circuit in the target memory rank RNK_TG is changed from the first resistance value M*Rtt to the second resistance value M*Rtt + Rtg, and the ODT circuit in the non-target memory rank RNK_NT can maintain the initial state to have the first resistance value M*Rtt during the write operation. In one embodiment, the second resistance value is greater than the first resistance value, the ODT circuit of the target memory rank RNK_TG is disabled, and the ODT circuits of the non-target memory ranks RNK_NT are enabled and set to the first resistance value during a read operation, and the ODT circuit of the target memory rank is enabled and set to the second resistance value during a write operation.

[0102] Fig. Figure 18 is a diagram illustrating a CAS instruction according to an exemplary embodiment.

[0103] Fig. Figure 18 illustrates an example CAS instruction that conforms to the Low Performance Dual Data Rate 5 (LPDDR5) standard. Referring to Fig. 18. A CAS instruction can be represented as a combination of instruction address signals CA0~CA5. "L" represents a logical low level, "H" represents a logical high level, and EDC_EN, WS_RD, WS_FAST, DC0-DC3, NT0, NT1, and BL represent field values ​​that form the CAS instruction. In particular, NT0 and NT1 represent the field values ​​for a termination control.

[0104] As in Fig. As illustrated in Figure 18, if the static ODT control is used according to an exemplary embodiment, NT0 and NT1 can be omitted and the corresponding section can be reserved for future use (RFU = Reserved For Future Use).

[0105] The Fig. 19A and Fig. Figure 19B contains diagrams for describing a mode register for an ODT according to an exemplary embodiment.

[0106] The information for the ODT control can be found in mode register 412 in Fig. 4 may be stored. For example, the corresponding section of mode register 412 may have mode register settings MRSET, as shown in the Fig. 19A and Fig. Figure 19B illustrates this. Some values ​​of operands OP0 to OP7 can represent information about a resistance value of the ODT circuit.

[0107] Fig. Figure 19A shows an ODT value for jointly controlling the resistance value of the ODT circuits in the target memory rank and the non-target memory rank as referenced in Fig. 8A is described. Fig. Figure 19B shows a first value TG-ODT for controlling the first resistance value of the ODT circuit in the target memory rank and a second value NT-ODT for controlling the second resistance value of the ODT circuit in the non-target memory rank, as described in reference to Fig. As described in section 8B, the values ​​ODT, TG-ODT, and NT-ODT, stored in mode register 412, can be provided by the memory controller for memory ranks via a mode register write operation. The strength code SCD mentioned above can be provided based on the values ​​ODT, TG-ODT, and NT-ODT.

[0108] Fig. Figure 20 is a structural diagram illustrating a semiconductor storage device according to an exemplary embodiment of the inventive concept.

[0109] Referring to Fig. 20. A semiconductor storage device 900 has a first to k-th integrated semiconductor circuit layer LA1 to LAk, in which the lowest first integrated semiconductor circuit layer LA1 is assumed to be an interface or control chip, and the other integrated semiconductor circuit layers LA2 to LAk are assumed to be slave chips which contain core memory chips. The slave chips can form a plurality of memory ranks, as described above.

[0110] The first to kth integrated semiconductor layers LA1 to LAk can transmit and receive signals between layers via substrate vias (e.g., silicon vias). The lowest integrated semiconductor layer LA1, acting as the interface or control chip, can communicate with an external memory controller via a conductive structure formed on an external surface.

[0111] Each of the first integrated semiconductor circuit layer 910 up to the k-th integrated semiconductor circuit layer 920 can include memory regions 921 and peripheral circuits 922 for driving and operating the memory regions 921, respectively. For example, the peripheral circuits 922 can include a row driver for driving word lines of a memory, a column driver for driving bit lines of the memory, a data input / output circuit for controlling input / output of data, an instruction buffer for receiving an instruction from an external source and buffering the instruction, and an address buffer for receiving an address from an external source and buffering the address.

[0112] The first integrated semiconductor circuit layer 910 may also include a control circuit. The control circuit can control access to the memory area 921 based on an instruction and an address signal from a memory controller and can generate control signals for accessing the memory area 921.

[0113] Fig. Figure 21 is a block diagram illustrating a mobile system according to an exemplary embodiment of the inventive concept.

[0114] Referring to Fig. 21 A mobile system 1200 includes an application processor 1210, a connectivity circuit 1220, a volatile memory device (VM = Volatile Memory) 1230, a non-volatile memory device (NVM = Non-Volatile Memory) 1240, a user interface 1250 and a power supply 1260.

[0115] The 1210 application processor can execute computer instructions stored on computer-readable media (such as storage devices), including applications such as a web browser, a game application, a video player, etc. The 1220 connectivity circuit can perform wired or wireless communication with an external device. The 1230 volatile storage device can store data processed or manipulated by the 1210 application processor or can function as working memory.For example, the volatile storage device 1230 can be a dynamic random access memory such as a dual-rate synchronous dynamic random access memory (DDR SDRAM), a low-performance dual-rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics dual-rate synchronous dynamic random access memory (GDDR SDRAM), a Rambus dynamic random access memory (RDRAM), etc. The non-volatile storage device 1240 can store a boot image for booting the mobile system 1200. The user interface 1250 can have at least one input device, such as a keyboard, a touchscreen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply 1260 can supply a power supply voltage to the mobile system 1200.In an exemplary embodiment, the mobile system 1200 further comprises a camera image processor (CIS = Camera Image Processor = Camera image processor) and / or a storage device such as a memory card, a solid state drive (SSD = Solid State Drive = Solid State Drive), a hard disk drive (HDD = Hard Disk Drive = Hard Disk Drive), a CD-ROM, etc.

[0116] The volatile storage device 1230 and / or the non-volatile storage device 1240 can be configured to perform the method for controlling an ODT according to exemplary embodiments, as referred to in the Fig. 1 to 19B described, have.

[0117] As described above, the method for controlling an ODT and the system that performs the method according to an exemplary embodiment can reduce power consumption and increase signal integrity through static ODT control such that the ODT circuits of the target memory rank and the non-target memory rank are generally maintained in the activated state, whereas the ODT circuit of the read target memory rank is deactivated during the read operation.

[0118] Embodiments of the inventive concept can be applied to various devices and systems that include a storage device. For example, the present inventive concept can be applied to systems such as a memory card, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.

Claims

[1] Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2). [2] Method according to claim 1, wherein the first memory rank (RNK1) is a target memory rank and the second memory rank (RNK2) is a non-target memory rank. [3] Method according to claim 2, wherein the ODT circuits (300) have a first resistance value of the plurality of storage ranks (RNK1 - RNKM) in an initial state. [4] Method according to claim 3, wherein activating the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command includes maintaining the ODT circuits (300) of the plurality of memory ranks (RNK1 - RNKM) in the initial state, such that they have the first resistance value. [5] Method according to claim 3, wherein activating the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command includes storing the first resistance value in a mode register (412). [6] Method according to claim 3, wherein activating the ODT circuit (300) of the second memory rank (RNK2) in response to the read command includes maintaining the ODT circuits (300) of the plurality of memory ranks (RNK1 - RNKM) in the initial state, such that they have the first resistance value. [7] Method according to claim 3, wherein activating the ODT circuit (300) of the second memory rank (RNK2) in response to the read command includes storing the first resistance value in a mode register (412). [8] Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command where the write command conforms to an LPDDR5 standard; Activating a receive buffer (720, BF1) in a first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disable receive buffer (720, BF2) and transmit driver (710, DR2) in a second memory rank (RNK2); Receiving a data strobe signal (WCK_T, WCK_C), where the data strobe signal (WCK_T, WCK_C) starts toggling after receiving the write command; Activating (S200) on-die terminal (ODT) circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; and Receiving a data signal while the data strobe signal (WCK_T, WCK_C) is toggled during the activation of the ODT circuit (300) of the first memory rank (RNK1) and the second memory rank (RNK2). [9] Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a read instruction intended for a first memory rank (RNK1), where the read instruction conforms to an LPDDR5 standard; Enabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in a second memory rank (RNK2); Disable (S300) an on-die terminal (ODT) circuit (300) of the first memory rank (RNK1) and enable an ODT circuit (300) of the second memory rank (RNK2) in response to the read instruction; Receiving a data strobe signal (WCK_T, WCK_C), wherein the data strobe signal (WCK_T, WCK_C) begins to toggle after receiving the write command; and Sending a data signal while the data strobe signal is toggled during the disabling of the ODT circuit (300) of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).