Optically detectable reference feature for die separation

Abstract

comprising semiconductor wafers (200): - a semiconductor body (10); - an insulating layer (11) on the semiconductor body (10); - an active region (210) with a power semiconductor die (100), wherein the active region (210) forms part of the semiconductor body (10); - a dividing line area (220) that is located next to the active area (210); - a passivation structure (13) arranged above the insulation layer (11) such that it leaves a section (111) of the insulation layer (11) exposed, the exposed section (111) being closed off by a termination edge (130) of the passivation structure (13); - an optically detectable reference feature (12) configured to serve as a reference position during a wafer separation processing stage, wherein the optically detectable reference feature (12): - is included in the active area (210), - is spatially offset from the end edge (131), - is freed from the passivation structure (13), and wherein: - the optically detectable reference feature (12) comprises a trench structure (121) and wherein the trench structure (121) comprises at least one electrically potential-free trench electrode (1211); and / or - the optically detectable reference feature (12) comprises one or more contact plugs (122) extending into the insulating layer (11).

Description

TECHNICAL FIELD

[0001] The present patent specification relates to embodiments of a semiconductor wafer, to embodiments of a power semiconductor die, to embodiments of a method for processing a semiconductor wafer, and to embodiments of a semiconductor wafer separator.In particular, the present patent specification relates to embodiments of a semiconductor wafer comprising one or more optically detectable reference features for die separation, to embodiments of a power semiconductor die comprising at least one optically detectable reference feature for die separation, to embodiments of a method for processing a semiconductor wafer comprising one or more optically detectable reference features for die separation, and to embodiments of a semiconductor wafer separation apparatus configured to separate a semiconductor wafer comprising one or more optically detectable reference features into a plurality of power semiconductor dies. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor devices.

[0003] For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including switches in power supplies and power converters.

[0004] A power semiconductor device typically comprises a power semiconductor die configured to conduct a load current along a load current path between two load terminals of the die. Furthermore, the load current path can be controlled by an insulated electrode, sometimes referred to as a gate electrode. Upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to, for example, a conducting state or a blocking state.

[0005] In terms of the manufacturing process, multiple power semiconductor dies are typically processed simultaneously in a single wafer; this means that the semiconductor wafer can contain multiple power semiconductor dies after processing. These power semiconductor dies can be separated from each other by scribe lines.

[0006] The wafer then undergoes a separation processing step, which may include a dicing and / or sawing step, and is divided into several separate power semiconductor dies by breaking the wafer (e.g., by sawing and / or dicing) along the scribe lines. After a quality inspection, the dies can then be enclosed in a respective package and subsequently delivered to the customer.

[0007] Quality control may include checking whether the die has been damaged during the separation processing step. For example, during separation, an insulation layer exposed to separation may be damaged, and / or a crack may extend into the edge termination area of ​​one of the dies. If the die is considered damaged, or if it cannot be reliably ensured that the die has not been damaged, the die will not be packaged but will be discarded.

[0008] Of course, the portion of the wafer used for the scribe lines cannot be used as a die area. Therefore, it is desirable to make the scribe lines as small as possible. However, the accuracy requirements of the separation processing stage increase with decreasing scribe line dimensions.

[0009] From US 9 679 855 B1 a so-called “polymer crack stop” is known, which interrupts the propagation of damage that can occur during the division of a wafer at the position of the “crack stop”.

[0010] US 2015 / 0 294 966 A1 describes a semiconductor device. The semiconductor device comprises a semiconductor body having a first surface and a second surface opposite the first surface. The semiconductor device further comprises a first insulation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first insulation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second insulation layer is provided on the electrostatic discharge protection structure. A gate contact region on the second insulation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electrical contact structure is arranged in an overlap region between the gate contact region and the semiconductor body.The electrical contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically insulated from the gate contact region.

[0011] According to the teaching of US 2004 / 0 161 880 A1, a conductor carrier provides separately manufactured conductive tracks at wafer level that can be connected to a wafer with fully fabricated integrated circuits. Such conductor carriers comprise an insulating body having two main surfaces, on each of which conductors are arranged, and conductors arranged within the insulating body to ensure signal continuity between different conductors on each of the two surfaces. An assembly can be formed by permanently or removably attaching the conductor carrier to the wafer. Conductor carriers can include an evacuation path suitable for removing air or other gases between the conductor and the wafer to create a pressure difference that presses the conductor carrier into contact with the wafer. Conductor carriers can include a groove suitable for receiving a sealing ring; and they can have a so-calledIncludes a road map suitable as a guide for a wafer sawing operation. SUMMARY

[0012] The present invention is defined by the independent claims. Features of some exemplary embodiments are set forth in the dependent claims.

[0013] Certain aspects of the present patent relate to an optically detectable reference feature serving as a marker for performing the wafer separation processing step. For example, the separation processing step includes the step of acquiring position data indicating the position of the optically detectable reference feature and controlling a relative movement between the wafer and a wafer separation device (e.g., a laser dicing device or a sawing device) based on the position data. The optically detectable reference feature is, for example, spatially offset from the scribe lines.

[0014] According to one embodiment, a semiconductor wafer comprises: a semiconductor body; an insulation layer on the semiconductor body; an active region including a power semiconductor die, wherein the active region forms part of the semiconductor body; a cleavage line region disposed adjacent to the active region; a passivation structure disposed over the insulation layer and such that it leaves a portion of the insulation layer exposed, wherein the exposed portion is terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage. The optically detectable reference feature is: (i) contained in the active region, (ii) spatially offset from the termination edge, and (iii) exposed by the passivation structure.

[0015] According to another embodiment, a method for processing a semiconductor wafer comprises providing a semiconductor wafer, the semiconductor wafer comprising: a semiconductor body; an insulation layer on the semiconductor body; an active region including a power semiconductor die, the active region forming part of the semiconductor body; a separation line region disposed adjacent to the active region; a passivation structure disposed over the insulation layer and such that it leaves a portion of the insulation layer exposed, the exposed portion being terminated by a termination edge of the passivation structure. The method further comprises providing an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage.The optically detectable reference feature is: (i) contained in the active region, (ii) spatially offset from the termination edge, and (iii) exposed from the passivation structure.

[0016] According to another embodiment, a power semiconductor die comprises: a semiconductor body; an insulation layer on the semiconductor body; an active region, wherein the active region forms a part of the semiconductor body; a remaining part of a semiconductor wafer separation line region arranged adjacent to the active region; a passivation structure arranged over the insulation layer and such that it leaves a portion of the insulation layer exposed, wherein the exposed portion is terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage. The optically detectable reference feature is: (i) contained in the active region, (ii) spatially offset from the termination edge, and (iii) exposed by the passivation structure.

[0017] According to another embodiment, a method for processing a semiconductor wafer comprises providing a semiconductor wafer, the semiconductor wafer comprising: a semiconductor body; an insulation layer on the semiconductor body; an active region comprising a power semiconductor die, the active region forming part of the semiconductor body; a separation line region disposed adjacent to the active region; a passivation structure disposed over the insulation layer and such that it leaves a portion of the insulation layer exposed, the exposed portion being terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage.The optically detectable reference feature is: (i) contained within the active region, (ii) spatially offset from the termination edge, and (iii) exposed from the passivation structure. The method further comprises: acquiring position data indicative of a position of the optically detectable reference feature; and controlling a relative movement between the semiconductor wafer and a wafer separation device based on the position data.

[0018] According to yet another embodiment, a semiconductor wafer separating apparatus for separating a semiconductor wafer into a plurality of power semiconductor dies is presented. The apparatus comprises a receiving device configured to receive the semiconductor wafer. The semiconductor wafer comprises: a semiconductor body; an insulating layer on the semiconductor body; an active region including a power semiconductor die, wherein the active region forms part of the semiconductor body; a separation line region arranged adjacent to the active region; a passivation structure arranged over the insulating layer and such that it leaves a portion of the insulating layer exposed, wherein the exposed portion is terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separating processing stage.The optically detectable reference feature is: (i) contained in the active region, (ii) spatially offset from the termination edge, and (iii) exposed from the passivation structure. The device further comprises: a detector configured to detect position data indicating a position of the optically detectable reference feature; a computing device configured to receive the position data and history data, wherein the history data is associated with the semiconductor wafer and defines a history of the at least one separation line region with respect to the position of the at least one optically detectable reference feature; and a wafer dicing device coupled to the computing device and configured to dicing the semiconductor wafer into a plurality of power semiconductor dies, wherein the computing device is configured to control the wafer dicing device based on the position data and the history data.

[0019] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The parts in the figures are not necessarily to scale, but emphasis is placed on illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: Fig. 1A-C each schematically and exemplarily show a section of a horizontal projection of a semiconductor wafer; Fig. 2A schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor die; Fig. 2B schematically and exemplarily shows a section of a horizontal projection of a power semiconductor die; Fig. 3A-C each schematically and exemplarily show a section of a vertical cross-section of a semiconductor wafer; Fig. 4 schematically and exemplarily shows a portion of a horizontal projection of a semiconductor wafer according to one or more embodiments; Fig. 5 schematically and exemplarily shows a portion of a horizontal projection of a semiconductor wafer according to one or more embodiments; Fig. 6 schematically and exemplarily shows a portion of a vertical cross-section of a semiconductor wafer according to one or more embodiments; Fig. 7 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor die according to one or more embodiments; Fig. 8 schematically and exemplarily shows a flow diagram of a method for processing a semiconductor wafer according to one or more embodiments; and Fig. 9 schematically and exemplarily a block diagram of a semiconductor wafer separating device according to one or more embodiments DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0022] In this regard, directional terminology such as "top," "bottom," "below," "front," "back," "backward," "leading," "trailing," "over," etc., may be used with reference to the orientation of the figures just described. Because portions of embodiments may be positioned in a variety of orientations, the directional terminology is used for illustrative purposes. It should be understood that other embodiments may be utilized, and structural or logical changes may be made.

[0023] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Features illustrated or described as part of one embodiment may, for example, be used in or combined with other embodiments to obtain yet another embodiment. The present invention is intended to include such modifications and variations. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals throughout the various drawings unless otherwise indicated.

[0024] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may, for example, be the surface of a semiconductor wafer or die. For example, both the (first) lateral direction X and the (second) lateral direction Y mentioned below may be horizontal directions, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0025] The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the vertical direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0026] For the purposes of this specification, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe that a low-resistance electrical connection or a low-resistance current path exists between two regions, areas, zones, sections, or parts of the semiconductor device described herein. Furthermore, for the purposes of this specification, the term "in contact" is intended to describe that a direct physical connection exists between two elements of the respective semiconductor device; for example, a junction between two elements in contact with each other may not include any further intermediate element or the like.

[0027] Furthermore, in the context of this patent specification, the term "electrical insulation," unless otherwise stated, is used in its generally accepted sense and is intended to describe that two or more components are arranged separately from one another and that there is no ohmic connection connecting these components. However, components that are electrically isolated from one another can nevertheless be coupled to one another, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. To give an example, two electrodes of a capacitor can be electrically isolated from one another and simultaneously mechanically and capacitively coupled to one another, for example, by means of insulation, e.g., a dielectric.

[0028] Specific embodiments described in this specification relate to a power semiconductor die, for example, a power semiconductor die that can be used within a power converter or a power supply. Therefore, in one embodiment, such a die may be configured to carry a load current to be supplied to a load and / or provided by a power source. For example, the die may comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, a monolithically integrated transistor cell, a monolithically integrated IGBT cell, a monolithically integrated RC-IGBT cell, a monolithically integrated MOS-gated diode (MGD) cell, a monolithically integrated MOSFET cell, and / or variations thereof. Multiple such diode cells and / or transistor cells may be integrated within the die.

[0029] The term "power semiconductor die" as used in this patent specification is intended to describe a single die, for example, with capabilities for blocking a high voltage and / or conducting a high current. In other words, such a power semiconductor die is designed for high current, typically in the ampere range, for example, up to 5 or 100 A, and / or high voltages, typically above 15 V, more usually up to 40 V and above, for example, up to at least 500 V or more than 500 V, for example, at least 600 V, or at least a couple of kV, for example, in the case of a high-power IGBT.

[0030] For example, the power semiconductor die described below may be a die that may be configured for use as a power component in a low, medium, and / or high voltage application.

[0031] The Fig. 1A-C each schematically and exemplarily illustrate a section of a horizontal projection of a semiconductor wafer 200, the Fig. 2A-B depict a vertical cross-section and a horizontal projection of a power semiconductor die 100, and the Fig. 3A-C each schematically and exemplarily illustrate a section of a horizontal projection of a semiconductor wafer 200.

[0032] In the following, reference is made to all of the above-mentioned figures. Although none of the above-mentioned figures is explicitly described as illustrating an embodiment, it is understood that the figures described with reference to the remaining drawings ( Fig. 4-9) one or more or all of the embodiments described below with reference to the Fig. 1A-3C may contain features described.

[0033] The semiconductor wafer 200 has a semiconductor body 10, as best shown in the Fig. 3A-C). For example, the semiconductor body 10 is based on silicon (Si). In another example, the semiconductor body 10 is based on a different material, for example, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or another material with a wide band gap.

[0034] A thickness of the semiconductor body 10 along the vertical direction Z can be in the range from 5 µm to 300 µm. In one example, the thickness of the semiconductor body 10 is below a maximum value, for example, to enable separation by laser dicing, for example, below 100 µm or below 80 µm. A diameter of the semiconductor wafer (hereinafter also simply referred to as "wafer"), for example along the first lateral direction X, can be in the range from 4 to 16 inches, for example, up to 12 inches, according to one example.

[0035] Again on the Fig. Referring to Figures 1A-C, the wafer 200 may include one or more active regions 210 and one or more separation line regions 220 arranged adjacent to the active regions 210, for example, laterally (horizontally) adjacent to the active regions 210. The active regions 210 and the separation line regions 220 may have a common vertical extent corresponding to the thickness of the semiconductor body 10.

[0036] Both the separation line regions 220 and the active regions 210 form part of the semiconductor body 10. In other words, the semiconductor body 10 may form the main parts of both the separation line regions 220 and the active regions 210.

[0037] For example, each active region 210 comprises at least one power semiconductor die 100 (as shown in the Fig. 2A-B schematically and by way of example). For example, each active region 210 integrates the at least one power semiconductor die 100. Each power semiconductor die 100 may include one or more of the following: a diode, a transistor, a MOSFET, an IGBT, an RC-IGBT, a sensor, a CMOS, or an IC (integrated circuit). Such configurations are well known to those skilled in the art and thus will not be described in further detail herein.

[0038] For example, the processing of the semiconductor wafer 200 occurs primarily on the wafer front side 290; for example, the wafer front side 290 may be subjected to multiple processing steps, e.g., one or more implantation processing steps, one or more epitaxial processing steps, one or more deposition processing steps, one or more lithography processing steps, one or more etching processing steps, and the like. For example, on the wafer back side 280 (see Fig. 3A), a homogeneously formed (i.e., unstructured) backside metallization layer 212 is provided. For example, this metallization layer 212 forms part of a load terminal of each power semiconductor die 100, for example, a drain terminal, a collector terminal, or a cathode terminal.

[0039] The processing of the wafer front side 290 may include the formation of an insulation layer 11 on the semiconductor body 10, as shown in the Fig. 2A-3C. For example, the insulating layer 11 includes an intermediate oxidation layer ("ZWOX"). Furthermore, the insulating layer 11 may include an oxide. For example, the insulating layer 11 includes silicon oxide (SiO2) and / or a borophosphosilicate glass (BPSG). In one example, the insulating layer 11 includes a lower oxidation layer and an upper BPSG layer.

[0040] The insulation layer 11 may cover the semiconductor body 10, for example, not only in the active regions 210, but also at the separation line regions 220. For example, the insulation layer 11 covers substantially the entire semiconductor body 10 of the wafer 200. The insulation layer 11 may be arranged horizontally, for example, such that a transition between the insulation layer 11 and the semiconductor body 10 defines a substantially horizontal plane. For example, both an upper surface 119 and the lower surface 118 of the insulation layer 11 (see FIG. Fig. 3A-C) an essentially horizontal plane.

[0041] Within the active areas 210, for example within their respective active areas (cf. reference number 180 in Fig. 2B), the insulation layer 11 can be locally penetrated by contact means, for example contact strips and / or contact plugs 154 (cf. Fig. 3A-C) arranged and configured to form a portion of the semiconductor body 10, for example a semiconductor source region and / or a semiconductor body region and / or a semiconductor channel region (cf. reference numeral 102 in the Fig. 3A-C) or an electrode (see reference numbers 151, 153 in Fig. 3C). For example, a plurality of trenches 15 may extend along the vertical direction Z into the semiconductor body 10 and may have trench electrodes 151, 153 to be contacted. For example, such trench electrodes may be control electrodes 153 ( Fig. 3C), which may be provided with a control connection structure 150 (cf. Fig. 1C), for example, a gate runner. Furthermore, such trench electrodes may comprise field electrodes 151, which may need to be electrically connected to a load connection structure 110. For example, such a load connection structure 110 and / or such a control connection structure 150 may be arranged above the insulation layer 11, and the contact means 154, which penetrate the insulation layer 11, may serve as an electrical connection between, on the one hand, these connection structures 110, 150, which are arranged on the upper surface 119 of the insulation layer 11, and, on the other hand, the buried components (semiconductor regions and / or trench electrodes) arranged below the lower surface 118 of the insulation layer 11.

[0042] Furthermore, the passivation structure 13 may be arranged above the insulation layer 11, for example, exclusively within the active regions 210. For example, the passivation structure 13 covers the control terminal structure 150 and the load terminal structure 110 mentioned above, for example, to provide electrical insulation between these terminal structures 110, 150.

[0043] In one example, the passivation structure 13 may contain or be made of an insulating material, for example, imide. The passivation structure 13 may be configured to provide encapsulation. Furthermore, the passivation structure 13 may be covered by a further insulating structure 17, which may contain or be made of an epoxy material, for example.

[0044] For example, the passivation structure 13 does not extend into the parting line regions 220, but ends within an edge termination region (cf. reference number 190 in Fig. 2B, also referred to as “high-voltage termination region”) of the power semiconductor die 100 contained in the respective active region 210, for example by means of a termination edge 131.

[0045] As in Fig. 1C, the passivation structure 13 may be arranged over the insulation layer 11 and such that the portion 111 of the insulation layer 11 is left exposed. Furthermore, the passivation structure 13 may be arranged over the insulation layer 11 such that a portion 112 of the insulation layer 11 is covered. For example, the covered insulation layer portions 112 are arranged exclusively within the active areas 210.

[0046] Within the active region 180, the passivation layer 13 may, for example, cover substantially the entire insulation layer 11.

[0047] The exposed insulation layer portion 111 may extend into both the active region 210 and the separation line region 220. For example, the first partial portion 1111 of the exposed insulation layer portion 111 extends into the active region 210. A second partial portion 1112 of the exposed insulation layer portion 111 may be arranged within the separation line region 220.

[0048] As explained above, the parting line region 220 may be intended to be subjected to a separation processing step, wherein, for example, a laser beam or a saw blade may be directed onto the parting line region 220, for example, onto the surface of the second insulation layer portion 1112.

[0049] Thus, in one example, once the processing of the active regions 210 is completed, the wafer 200 may be subjected to a separation processing step, for example, a dicing processing step (also referred to as laser dicing) or a sawing processing step. During this separation processing step, the wafer 200 may be divided along the separation line regions 220 into the separated dies 100, which may then be packaged and shipped to the customer. For example, each separation line region 220 on the second insulation layer portion 1112 has a dicing (sawing) line (only in Fig. 1C, see reference number 222), along which a laser beam or saw blade is aligned to carry out the separation.

[0050] A width of the second insulation layer section 1112 along the first lateral direction X can be within the range of a few tens of µm, for example, within the range of 10 µm to 150 µm, for example, 60 µm. For example, the width of the second insulation layer section 1112 is selected such that a laser beam or a saw blade with a diameter / thickness of, for example, 20 µm and a lateral deviation of, for example, ±20 µm can be guided along the second insulation layer section 1112, for example, without exposing the first insulation layer section 1111 to the laser beam / saw blade.

[0051] For example, the power semiconductor die 100, as shown in Fig. 2A, was a part of the semiconductor wafer 200 and was cut out of the semiconductor wafer 200, whereby the die edge 105 could be formed. As shown in Fig. 2B, the power semiconductor die 100 may include the active region 180 and the edge termination region 190 surrounding the active region 180 and terminated by the die edge 105. The passivation structure 13 may be arranged to cover substantially the entire active region 180 and the edge termination region 190 only partially. Of course, the passivation structure 13 may be partially patterned in the active region 180, for example, to allow external contacts, e.g., bond wires, to contact a load terminal structure and / or a control terminal structure arranged on the insulation layer 11, e.g., the load terminal structure 110. As explained above, the passivation structure 13 described with reference to Fig. 3A may form another load connection structure of the power semiconductor die 100, for example, the load connection structure 120 on the back side of the power semiconductor die 100.

[0052] The Fig. 1B-C both schematically and exemplarily illustrate a portion of a horizontal projection of the semiconductor wafer 200, wherein the portion comprises four adjacent active regions 210. For example, a first separation processing step was performed along the dicing line 222 (see FIG. Fig. 1C) in the separation line regions 220. For example, as a result of such a first separation processing step, the second insulation layer section 1112 (cf. Fig. 1) have been at least partially removed. The hatched area represents the first insulation layer sections 1111, which extend laterally from the respective die edges 105 to the outermost termination edges 131 of the passivation structures 13.

[0053] As explained above, the passivation structure 13 may be structured to expose, for example, a connection structure, for example, the connection structure 150, which may be a control connection structure, and may include, for example, a gate runner. The connection structure 150, which includes, for example, the gate runner, may be at least partially covered by an encapsulation made, for example, of an insulating material, such as imide.

[0054] The Fig. 3A-C each schematically and exemplarily illustrate a section of a vertical cross-section of the semiconductor wafer 200 with two adjacent active regions 210, as already mentioned above.

[0055] Accordingly, a plurality of trenches 15 may extend along the vertical direction Z into the semiconductor body 10. Each of the plurality of trenches 15 may include a trench electrode 151 and a trench insulator 152 that insulates the trench electrode 151 from the semiconductor body 10. The trenches 15 may both be arranged within the active regions 210 and within the separation line region 220.

[0056] For example, a first subset of the plurality of trenches 15 may be arranged in the active region 210, wherein in the Fig. 3A-C only one respective section of the edge termination areas (cf. reference number 190 in Fig. 2B). The first subset may include at least one trench 15 that laterally overlaps with the first insulation layer section 1111. According to the illustrated examples, seven ( Fig. 3A) or six ( Fig. 3B) or four ( Fig. 3C) Trenches 15 laterally with the first insulation layer section 1111 in the active region 210.

[0057] A second subset of the plurality of trenches 15 may be arranged in the separation line region 220, wherein each of the second subset of the plurality of trenches 15 laterally overlaps the second insulation layer portion 1112.

[0058] According to one example, the first subset of the plurality of trenches 15 and the second subset of the plurality of trenches 15 have identical spatial dimensions, for example, with respect to the overall extension along the vertical direction Z and / or with respect to the trench width along the first lateral direction X. Additionally or alternatively, the first subset of the plurality of trenches 15 and the second subset of the plurality of trenches 15 are arranged according to the same trench pattern, for example, with respect to a lateral distance along the first lateral direction X between two adjacent trenches 15 (also referred to herein as a “pitch”). In another example, the trenches 15 within the separation line regions 220 may be arranged according to a larger pitch compared to the trenches 15 within the active regions 210.

[0059] For example, the trench formation process performed to form the trenches within the active region 180 of each power semiconductor die 100 of the active areas 210, for example, to form control trenches, gate trenches, field plate trenches, and the like, is performed in a similar or identical manner within the separation line regions 220 simultaneously, which may be advantageous in terms of uniformity. Thus, although these trenches 15 in the separation line regions 210 are not required for controlling the operation of the power semiconductor dies 100, they may nevertheless be formed within these regions 220 to ensure high uniformity throughout the entire wafer 200.

[0060] Furthermore, a plurality of contact plugs 154 may be used to contact the trench electrodes 151 and / or the semiconductor body 10, wherein each of the contact plugs 154 may extend from the upper surface 119 of the insulation layer 11 to the lower surface 118 of the insulation layer 11. The use of such contact plugs 154 is generally known to those skilled in the art. For example, these contact plugs 154 may be configured as contact strips or as contact needles depending on the design of the power semiconductor dies 100, which may be, for example, a needle trench design or a strip trench design. They may penetrate the insulation layer 11 and extend further along the vertical direction Z than to the lower surface 118 of the insulation layer 11, for example, to contact a region of the semiconductor body 10, for example a source region, a channel region or the body region (reference number 102) within the active region 180.

[0061] As in the Fig. 3A-C, a front-side metallization 110 is arranged above the insulation layer 11 and below the passivation structure 13, wherein the front-side metallization 110 is electrically connected to the semiconductor body 10 in the active region 180 of the power semiconductor die 100. This front-side metallization 110 may form part of a load connection structure of the power semiconductor die 100, for example, part of a source connection structure, an emitter connection structure, or an anode connection structure. As already explained, the active region 180 may be laterally offset from the first insulation layer portion 1111. For example, the contact plugs 154 may be used to provide the electrical connection between the front-side metallization / load connection structure 110 and the semiconductor body 10 and / or between the front-side metallization 110 and the trench electrodes 151.

[0062] According to the regulations in each of the Fig. 3A-C, an interruption structure 14 may be provided, which is covered by the passivation structure 13. For example, the interruption structure 14 may also penetrate the insulation layer 11, for example at the covered insulation layer portion 112. As shown in the Fig. 3A-C, the interrupt structure 14 may comprise an interrupt contact plug 144 or an interrupt contact well 142, wherein the contact plug 144 or the interrupt contact well 142 may electrically contact the semiconductor body 10.

[0063] The interruption structure 14 is configured, for example, to block a lateral peeling of the insulation layer 11, wherein the lateral peeling of the insulation layer may occur during the wafer separation processing stage.

[0064] The total number of trenches 15 included in the separation line region 220 may depend on a trench pattern used to form the trenches 15 in the active region 210. For example, for power semiconductor dies with a lower voltage rating, the trench pattern with a relatively small pitch may be used (see FIG. Fig. 3A-C), while for power semiconductor dies with a higher nominal voltage, the trench can be used with a relatively larger pitch.

[0065] Fig. 4 schematically and exemplarily illustrates a portion of a horizontal projection of a semiconductor wafer 200 according to one or more embodiments. The semiconductor wafer 200 comprises a semiconductor body 10 (in Fig. 4 not visible); an insulation layer 11 on the semiconductor body 10; an active region 210 with a power semiconductor die 100 (in Fig. 4 not visible), wherein the active region 210 forms part of the semiconductor body 10; a separation line region 220 arranged next to the active region 210; a passivation structure 13 arranged above the insulation layer 11 and such that it leaves a portion 111 of the insulation layer 11 exposed, wherein the exposed portion 111 is closed off by a termination edge 131 of the passivation structure 13.

[0066] With regard to optional implementations of the semiconductor body 10, the insulation layer 11, the active region 210, the power semiconductor die 100, the separation line region 210 and the passivation structure 13, reference is made to the above description.

[0067] In one embodiment, the wafer 200 includes an optically detectable reference feature 12 configured to serve as a reference position during a wafer separation processing stage.

[0068] The optically detectable reference feature 12 is (i) contained in the active region 210, (ii) spatially offset from the termination edge 131, and (iii) exposed from the passivation structure 13.

[0069] The optically detectable reference feature 12 can be configured to be detected by a component of a semiconductor wafer separator (cf. Fig. 9) to be optically detected. As used herein, the term "optically detectable" may refer to a configuration that can be detected by processing an image of the wafer 200, wherein the image includes a representation of the optically detectable reference feature 12, for example, an image of the front side 290 of the wafer 200. For example, such an image of the wafer 200 may be captured by a digital camera positioned over the wafer 200. For example, to optically detect the reference feature 12, it is not necessary to process the wafer 200 in addition to placing the wafer 200 within a field of view of the digital camera.

[0070] The course of the separation line region 220 (along which the wafer separation must take place) can be defined with respect to the position of the optically detectable reference feature 12, for example, using corresponding course data. To perform the wafer separation, the position of the optically detectable reference feature 12 can be determined, and based on the determined position, the wafer 200 can be divided into a plurality of separate power semiconductor dies 100 by breaking the wafer 200 along the separation line region 220 (for example, by dicing or sawing).

[0071] In one embodiment, the optically detectable reference feature 12 is completely exposed to the environment, i.e., no component of the wafer 200 is arranged at least above the portion of the insulation layer 11 that covers and / or contains the optically detectable reference feature 12. The optically detectable reference feature 12 is not covered.

[0072] The passivation structure 13 comprises, for example, an opening 132 exposing the optically detectable reference feature 12. The opening 132 may have a maximum lateral extent (for example, in both the first and second lateral directions) that is substantially as large as a width of the separating line region 220, for example, within the range of 20% to 200% of the width of the separating line region 220, which, as stated above, may be in the range of a few tens of µm.

[0073] The opening 132 can be spatially delimited by a closed opening edge 1321 of the passivation structure 13. In one embodiment, a minimum distance between the closed opening edge 1321 and the termination edge 131 is in the range of 5 µm to 50 µm.

[0074] The opening 132 may expose not only the optically detectable reference feature 12, but also a partial section 1113 of the insulation layer 11 (cf. Fig. 5 to 7). As discussed in more detail below, the optically detectable reference feature 12 may, for example, extend into and / or below the portion(s) 1113 of the insulation layer 11 exposed by the opening 132.

[0075] Another opening 133 of the passivation structure 13 may, for example, expose a part of a connection structure of the die 100, for example the load connection structure 110, as mentioned above.

[0076] For example, the passivation structure 13 may have a plurality of openings, and the opening 132 exposing the optically detectable reference feature 12 may be the opening located closest to the termination edge 131.

[0077] Thus, in one embodiment, the optically detectable reference feature 12 is spatially offset from the termination edge 131 of the passivation structure 13 such that it is contained in the active region 210 and not in the separation line region 220. Furthermore, the optically detectable reference feature 12 is not covered by the passivation structure 13, but is left free from the passivation structure 13, thereby allowing a device (e.g., reference numeral 520 in Fig. 9) the optically detectable reference feature 12 is optically detected.

[0078] Fig. 5 schematically and exemplarily illustrates a portion of a horizontal projection of a semiconductor wafer 200 according to one or more embodiments, and Fig. 6 schematically and exemplarily illustrates a portion of a vertical cross-section of the semiconductor wafer 200 according to one or more embodiments, wherein the illustrated cross-section corresponds to a vertical section at the Fig. corresponds to line AA' shown in Figure 5.

[0079] Accordingly, two adjacent active regions 210 may be laterally separated from one another by the exposed portion 111 of the insulation layer 11, which is spatially delimited by the termination edges 131 of the passivation structures 13. The exposed portion 111 of the insulation layer 11 extends into the separation line region 220. For example, the part of the semiconductor body 10 belonging to the separation line region 220 is partially or completely covered by the exposed portion 111 of the insulation layer 11. As already mentioned above, the first partial portions 1111 of the exposed insulation layer portion 111 may extend into the active regions 211, and the second partial portion 1112 of the exposed insulation layer portion 111 may extend into the separation line region 220.

[0080] The optically detectable reference feature 12 is arranged within one of the active regions 210 (wherein the wafer 200 may, of course, comprise one or more additional optically detectable reference features 12, which may be arranged in the same or other active regions 210). As already explained above, the optically detectable reference feature 12 is spatially offset from the termination edge 131. For example, the extension of the separation line region 210 does not include any part of the optically detectable reference feature 12; for example, the optically detectable reference feature 12 does not spatially delimit the extension of the separation line region 210 in terms of structural configuration.

[0081] As in Fig. 6, the optically detectable reference feature 12 may extend into the semiconductor body 10, that is, below the exposed portion 1113 of the insulation layer 11. The optically detectable reference feature 12 may comprise, for example, a trench structure 121 extending into the semiconductor body 10. The trench structure may include one or more separate trenches, or, as shown in the Fig. 6 and Fig. 7, a closed trench structure formed by a continuous trench extending into the semiconductor body 10.

[0082] The wafer 200, for example, the active region 210 and / or the separation line region 220, contains, for example, processed portions that may be formed within a horizontal sublayer 104 of the semiconductor body 10, wherein the horizontal sublayer 104 is arranged below and optionally in contact with the insulation layer 11, and wherein the optically detectable reference feature 12 extends into the horizontal sublayer 104. The horizontal sublayer 104 is an epitaxially grown semiconductor region and / or is arranged above a substrate region 105 of the semiconductor body 105.

[0083] The processed parts of the horizontal sublayer 104 of the semiconductor body 10 may include doped semiconductor regions, for example, a body region 102 (for example, p-doped) and / or a source region (for example, n-doped, not shown), guard ring regions, channel stopper regions (not shown), and the like. The processed parts of the horizontal sublayer 104 of the semiconductor body 10 may further include trenches 15, as already described with reference to FIG. Fig. 3A-C had been explained.

[0084] In one embodiment, the optically detectable reference feature 12 and at least one component of the processed parts 102, 15 have a common vertical extension area of ​​at least 20%, of at least 50% or even of at least 80% of the total extension of the at least one component of the processed parts 102, 15 along the vertical direction Z.

[0085] The trench structure 121 of the optically detectable reference feature 12 is created in the same way, for example, simultaneously with the trenches 15. Thus, the same degree of accuracy applied during the introduction of the trenches 15 can be equally applied to the optically detectable reference feature 12. Thus, the control of the wafer separation processing stage based on the position and / or layout of the optically detectable reference feature 12 can be performed with comparatively high accuracy. However, due to the process, for example, the profile of the termination edge 131 of the passivation structure 13 may exhibit an undesirable deviation of a few micrometers, which would accordingly influence the wafer separation processing stage if it were based on the profile of the termination edge 131.

[0086] The trench(es) of the trench structure 121 may thus, for example, include a trench electrode 1211 that is insulated from the semiconductor body 10 by a trench insulator 1222. Furthermore, the optically detectable reference feature 12 may have substantially the same overall extension along the vertical direction Z (depth) as the plurality of trenches 15. However, since the layout of the trench structure 121 of the optically detectable reference feature 12 may be different from the layout of the trenches 15 (which may, for example, be strip trenches with a similar shape), the overall depth of the trench(es) of the trench structure 121 may differ slightly from the depth of the trenches 15. For example, a width of the trench(es) of the trench structure 121 of the optically detectable reference feature 12 may be greater than the respective width of the trenches 15, and depending on the process, this may result in a greater depth of the trench structure 121.

[0087] It should be obvious that the insulating layer 11 may be transparent; for example, transparent to a detector (cf. reference numeral 520 mentioned below), for example an optical microscope.

[0088] Furthermore, in contrast to the trenches 15, which may be arranged within the active region 210 and which may be intended to contribute to the active operation of the power semiconductor die 100, for example, for the purpose of controlling a load current, the trench structure 121 of the optically detectable reference feature 12, although forming part of the active region 210, does not serve the purpose of controlling the active operation of the power semiconductor die 100, but instead serves, for example exclusively, the purpose of optical detection, for example, localization by means of a semiconductor wafer dicing device and thus serves nothing other than a marker for performing the wafer dicing processing stage.

[0089] The trench electrode(s) 1211 of the trench structure 121 of the optically detectable reference feature 12 may, for example, be electrically potential-free. Thus, the trench electrode(s) 1211 of the trench structure 121 of the optically detectable reference feature 12 is / are not electrically connected to the load connection structure 110 or to the control connection structure 150 of the power semiconductor die 100.

[0090] In one embodiment, the optically detectable reference feature 12 has a non-symmetrical layout in a horizontal cross-section. An example of the non-symmetrical layout is shown in Fig. 6; accordingly, the optically detectable reference feature 12 has a non-symmetrical layout in the form of a closed G-shape in a horizontal cross-section. Of course, other non-symmetrical layouts are also possible, for example, an L-shape or the like. The non-symmetrical layout can facilitate the control of the wafer separation processing stage, since different horizontal (i.e., lateral) directions can be aligned based on one and the same optically detectable reference feature 12. For example, based on the position and layout of the optically detectable reference feature 12, a movement along the scribe lines 220 required to perform the wafer separation can be more reliably controlled based on one and the same optically detectable reference feature 12 in both the first lateral direction X and the second lateral direction Y.

[0091] In general, it is possible that the optically detectable reference feature 12 may be made of one or more materials that are different from both the material of the passivation structure 13 and a metal. Thus, in one embodiment, the optically detectable reference feature 12 is neither a part of the passivation structure 13 nor a part of the connection structures that may be included in the active region 210. As explained above, the optically detectable reference feature 12 may be formed simultaneously with parts implemented in the horizontal sublayer 104, and thus, the optically detectable reference feature 12 may be based on materials such as a multiply doped semiconductor material (e.g., trench electrode 1211) and a semiconductor oxide (e.g., trench insulator 1222).

[0092] In one embodiment, the optically detectable reference feature 12 also does not form part of the insulation layer 11, and the optically detectable reference feature 12 is made of a material different from the material of the insulation layer 11.

[0093] Also recited herein is a power semiconductor die. The power semiconductor die comprises: a semiconductor body; an insulating layer on the semiconductor body; an active region, wherein the active region forms a part of the semiconductor body; a remaining portion of a semiconductor wafer dicing line region disposed adjacent to the active region; a passivation structure disposed over the insulating layer and such that it leaves a portion of the insulating layer exposed, wherein the exposed portion is terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer dicing processing stage. The optically detectable reference feature is: (i) contained within the active region, (ii) spatially offset from the termination edge, and (iii) exposed by the passivation structure.

[0094] Regarding optional implementations of the components of the power semiconductor die (see reference numeral 100 in the drawings), reference is made to the above. What was described above with regard to the semiconductor body 10, the insulation layer 11, the active region 210, the separation line region 220, the passivation structure 13, and the optically detectable reference feature 12 can, for example, equally be applied to the corresponding components of the power semiconductor die mentioned herein. Fig. 7 schematically and exemplarily illustrates a portion of a vertical cross-section of the power semiconductor die 100 according to one or more embodiments.

[0095] For example, the optically detectable reference feature 12 comprises one or more contact plugs 122 extending into the insulating layer 11. For example, the contact plugs 122 penetrate into the insulating layer 11, for example, such that they end coplanar with both the upper surface 119 and the lower surface 118 of the insulating layer 11.

[0096] In one embodiment, the optically detectable reference feature 12, whether part of the entire wafer 200 or the separate die 100, may include both the contact plugs 122 and the above-mentioned trench structure 121. For example, the contact plugs 122 may laterally overlap with the trench structure 121, for example, such that they touch the trenches (for example, the trench electrodes 1211).

[0097] As described above, the optically detectable reference feature 12 may thus have a vertical overlap with the insulation layer 11 and / or the semiconductor body 10. Not illustrated herein, but also possible, is that the optically detectable reference feature 12 alternatively or additionally overlaps with another portion arranged below the passivation structure 13 (but still left free by it), for example, with a diffusion barrier layer or tungsten layer.

[0098] Thus, it should be apparent that the optically detectable reference feature 12 may comprise a structure comprising a portion of a diffusion barrier layer and / or a portion of a tungsten layer instead of or in addition to the trench structure 121. In another embodiment, the optically detectable reference feature 12 may comprise a contact structure instead of or in addition to the trench structure 121, as described, for example, with reference to Fig. 7 was explained as an example.

[0099] Fig. 8 schematically and exemplarily illustrates a flowchart of a method 300 for processing a semiconductor wafer according to one or more embodiments. The method 300 includes providing (in step 310) the semiconductor wafer, wherein the semiconductor wafer comprises: a semiconductor body; an insulation layer on the semiconductor body; an active region including a power semiconductor die, wherein the active region forms part of the semiconductor body; a separation line region arranged adjacent to the active region; a passivation structure arranged over the insulation layer and such that it leaves a portion of the insulation layer exposed, wherein the exposed portion is terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage.The optically detectable reference feature is: (i) contained in the active region, (ii) spatially offset from the termination edge, and (iii) exposed from the passivation structure.

[0100] The method 300 further includes: acquiring (in step 320) position data indicative of a position of the optically detectable reference feature; and controlling (in step 340) a relative movement between the semiconductor wafer and a wafer separator based on the position data.

[0101] Regarding optional implementations of the components of the provided (see step 310) semiconductor wafer (see reference number 200 in the drawings), reference is made to the above. What was described above with regard to the semiconductor body 10, the insulation layer 11, the active region 210, the separation line region 220, the passivation structure 13, and the optically detectable reference feature 12 can, for example, equally be applied to the corresponding components of the semiconductor wafer processed according to the method 300.

[0102] In one embodiment, acquiring 320 the position data comprises locating the optically detectable reference feature 12 and optionally also determining a layout of the optically detectable reference feature 12. Acquiring 320 the position data comprises, for example, performing an optical character recognition (OCR) step; for example, the OCR processing step is performed on an image of the provided wafer 200 captured by a digital camera. The general image processing concepts that can be performed to acquire the position data indicating the position (i.e., location) of the optically detectable reference feature 12 and optionally also indicating the layout of the optically detectable reference feature 12 are known to those skilled in the art and thus will not be explained in further detail herein.

[0103] In another embodiment, the method 300 comprises separating (in step 350) the semiconductor wafer 200 into at least two wafer components (i.e., into at least two separate power semiconductor dies 100) by causing the wafer separator to break (e.g., saw, laser dice, and / or plasma etch) the semiconductor wafer 200 along the separation line region 210 while maintaining the optically detectable reference feature 12.

[0104] Breaking the semiconductor wafer 200 along the separation line region 210 may include a laser dicing processing step and / or a sawing processing step and / or a plasma etching processing step.

[0105] According to one or more embodiments, the optically detectable reference feature 12 is thus retained during the wafer separation processing stage. Thus, one or more of the separated power semiconductor dies 100 may still be provided with at least one respective optically detectable reference feature 12 after completion of the wafer separation processing stage. For example, the respective optically detectable reference feature 12 does not need to be removed thereafter, and the separated power semiconductor dies 100 may be packaged while still comprising the optically detectable reference feature 12. However, during the course of further processing of the separated power semiconductor dies 100, the optically detectable reference feature 12 may then be covered, for example, by means of a molding compound or by another insulation structure.Although the opening 132 of the passivation structure 13 may still expose the optically detectable reference feature 12, the opening 132 may then be filled with an insulating material. However, as shown, the opening does not necessarily have to be filled, but may instead remain empty.

[0106] In a further embodiment, the method 300 further comprises providing (in step 330, which may be performed before, after, or simultaneously with step 320) history data, wherein the history data defines a profile of the separation line region 210 with respect to the position of the optically detectable reference feature 12, and wherein controlling (step 330) the relative movement comprises moving the semiconductor wafer 200 with respect to the wafer separation device based on the history data. The relative movement is effected, for example, by moving the wafer 200 and / or by moving the wafer separation device. Furthermore, controlling 340 the relative movement between the semiconductor wafer 200 and the wafer separation device may be performed independently of the profile of the termination edge 131 of the passivation structure 13.In one embodiment, when dividing the wafer 200 into a plurality of power semiconductor dies 100, the profile of the termination edge 131 of the passivation structure is thus not taken into account.

[0107] Fig.9 schematically and exemplarily illustrates a block diagram of a semiconductor wafer separating device 500 for separating a semiconductor wafer into a plurality of power semiconductor dies according to one or more embodiments. The device 500 comprises a receiving device 510 configured to receive the semiconductor wafer.The semiconductor wafer comprises: a semiconductor body; an insulation layer on the semiconductor body; an active region including a power semiconductor die, the active region forming part of the semiconductor body; a cleavage line region disposed adjacent to the active region; a passivation structure disposed over the insulation layer and such that it leaves a portion of the insulation layer exposed, the exposed portion being terminated by a termination edge of the passivation structure; an optically detectable reference feature configured to serve as a reference position during a wafer separation processing stage. The optically detectable reference feature is: (i) contained within the active region, (ii) spatially offset from the termination edge, and (iii) exposed from the passivation structure.

[0108] The device 500 further comprises: a detector 520 configured to detect position data 521 indicating a position of the optically detectable reference feature; a computing device 530 configured to receive the position data 521 and history data 531, wherein the history data 531 is associated with the semiconductor wafer and defines a profile of the at least one separation line region with respect to the position of the at least one optically detectable reference feature; and a wafer separating device coupled to the computing device 530 and configured to separate the semiconductor wafer into a plurality of power semiconductor dies, wherein the computing device 530 is configured to control the wafer separating device 540 based on the position data 521 and the history data 531.

[0109] Regarding optional implementations of the components of the picked-up (see pick-up device 510) semiconductor wafer (see reference number 200 in the drawings), reference is made to the above. What was described above with regard to the semiconductor body 10, the insulation layer 11, the active region 210, the separation line region 220, the passivation structure 13, and the optically detectable reference feature 12 can, for example, equally be applied to the corresponding components of the semiconductor wafer picked up by the device 500.

[0110] The device 500 can be configured to move the holding device 510 and the wafer separating device 540 relative to one another, for example, by keeping the wafer separating device 540 stationary and moving the holding device 510 (i.e., the wafer 200 held thereby). For this purpose, the device 500 can contain a displacement means (not shown), and the computing device 530 can be configured to control the relative movement by appropriately controlling the displacement means. To control the relative movement, the computing device 530 can be operatively coupled, for example, to the wafer separating device 540 and / or the holding device 510.

[0111] The wafer separator 540 may be configured to perform a laser dicing and / or a sawing and / or a plasma etching processing step to effect wafer separation along the scribe line 220.

[0112] The detector 520 may be configured to capture an image of the wafer 200 and perform an OCR processing step to capture the position data, wherein the position data indicates the position (i.e., the location) of the optically detectable reference feature 12 and optionally also indicates the layout of the optically detectable reference feature 12, as explained above.

[0113] The detector 520 contains, for example, an optical microscope.

[0114] The detector 520 may provide the position data to the computing device 530. The computing device 530 may include a controller for the semiconductor wafer separator 500 and may include multiple (e.g., distributed) computing subunits for performing appropriate control of the semiconductor wafer separator 500.

[0115] The history data 531 can be supplied to the computing unit 530 in any suitable manner, for example, via a communication interface. The history data can be generated, for example, during the semiconductor wafer manufacturing process, for example, after forming the one or more optically detectable reference features 12. For example, each semiconductor wafer is uniquely assigned to a single set of history data 531; once the device 500 has identified the received semiconductor wafer 200, it can determine the history data 531 assigned to it.

[0116] As explained above, the history data may define the path of the scribe line 210 relative to the position / layout of the optically detectable reference feature 12. Thus, the computing device 530 may control the wafer separation processing stage based on the position data 521 and the history data 531.

[0117] According to one or more embodiments described herein, the optically detectable reference feature 12 forms an alignment structure based on which the wafer separation processing step, for example, controlling the relative movement between a wafer separation device and the wafer during wafer separation, can be performed. For example, if the wafer separation is based on a sawing processing step, the optically detectable reference feature 12 forms the sawing alignment structure. Of course, as explained above, the wafer separation may additionally or alternatively be based on a laser dicing processing step and / or the plasma etching processing step.

Claims

[1] Semiconductor wafer (200) comprising: - a semiconductor body (10); - an insulating layer (11) on the semiconductor body (10); - an active region (210) with a power semiconductor die (100), wherein the active region (210) forms part of the semiconductor body (10); - a separation line region (220) arranged adjacent to the active region (210); - a passivation structure (13) arranged above the insulation layer (11) and such that it leaves a portion (111) of the insulation layer (11) exposed, the exposed portion (111) being closed off by a terminating edge (130) of the passivation structure (13); - an optically detectable reference feature (12) configured to serve as a reference position during a wafer separation processing stage, wherein the optically detectable reference feature (12): - is contained in the active area (210), - is spatially offset from the end edge (131), - is free from the passivation structure (13), and wherein: - the optically detectable reference feature (12) comprises a trench structure (121), and wherein the trench structure (121) comprises at least one electrical potential-free trench electrode (1211); and / or - the optically detectable reference feature (12) comprises one or more contact plugs (122) extending into the insulation layer (11). [2] The semiconductor wafer (200) of claim 1, wherein the optically detectable reference feature (12) extends into the semiconductor body (10). [3] A semiconductor wafer (200) according to any one of the preceding claims, further comprising processed parts (102, 15) formed in a horizontal sub-layer (104) of the semiconductor body (10), the horizontal sub-layer (104) being arranged below and in contact with the insulation layer (11), the optically detectable reference feature (12) extending into the horizontal sub-layer (104). [4] The semiconductor wafer (200) of claim 3, wherein the optically detectable reference feature (12) and at least one component of the processed parts (102, 15) have a common vertical extent for at least 20% of the total extent of the at least one component of the processed parts (102, 15) along a vertical direction (Z). [5] The semiconductor wafer (200) of claim 4, wherein the at least one component of the parts includes a plurality of trenches (15), wherein the optically detectable reference feature (12) has substantially the same overall extension along the vertical direction (Z) as the plurality of trenches (15). [6] Semiconductor wafer (200) according to one of the preceding claims, wherein the optically detectable reference feature (12) extends into a partial section (1113) of the insulation layer (11) left exposed by the passivation structure (13). [7] Semiconductor wafer (200) according to one of the preceding claims, wherein the optically detectable reference feature (12) has a non-symmetrical layout in a horizontal cross-section. [8] Semiconductor wafer (200) according to one of the preceding claims, wherein the optically detectable reference feature (12) is made of one or more materials that differ from both the material of the passivation structure (13) and a metal. [9] Semiconductor wafer (200) according to one of the preceding claims, wherein the spatial limitation of the course of the separating line region (210) does not contain any part of the optically detectable reference feature (12). [10] Semiconductor wafer (200) according to one of the preceding claims, wherein the exposed insulation layer (111) at least partially covers the separation line region (220). [11] Semiconductor wafer (200) according to one of the preceding claims, wherein a first partial section (1111) of the exposed insulation layer section (111) extends into the active region (210) and wherein a second partial section (1112) of the exposed insulation layer section (111) extends into the parting line region (220). [12] A method (300) for processing a semiconductor wafer (100), comprising: Providing (310) a semiconductor wafer (200), wherein the semiconductor wafer (200) comprises: - a semiconductor body (10); - an insulating layer (11) on the semiconductor body (10); - an active region (210) with a power semiconductor die (100), wherein the active region (210) forms part of the semiconductor body (10); - a separation line region (220) arranged adjacent to the active region (210); - a passivation structure (13) arranged above the insulation layer (11) and such that it leaves a portion (111) of the insulation layer (11) exposed, the exposed portion (111) being closed off by a terminating edge (131) of the passivation structure (13); - an optically detectable reference feature (12) configured to serve as a reference position during a wafer separation processing stage, wherein the optically detectable reference feature (12) - is contained in the active area (210), - is spatially offset from the end edge (131), - is released from the passivation structure (13); detecting (320) position data indicating a position of the optically detectable reference feature (12); and Controlling (340) a relative movement between the semiconductor wafer (200) and a wafer separator based on the position data; and wherein: - the optically detectable reference feature (12) comprises a trench structure (121), and wherein the trench structure (121) comprises at least one electrical potential-free trench electrode (1211); and / or - the optically detectable reference feature (12) comprises one or more contact plugs (122) extending into the insulation layer (11). [13] The method (300) of claim 12, wherein the detecting (320) of the position data comprises performing an optical character recognition step. [14] The method (300) of claim 12 or 13, further comprising: Providing (330) history data, wherein the history data defines a history of the separation line region (210) with respect to the position of the optically detectable reference feature (12), and wherein controlling (330) the relative movement comprises moving the semiconductor wafer (200) with respect to the wafer separation device based on the history data. [15] Method (300) according to one of the preceding claims 12 to 14, further comprising: Separating (350) the semiconductor wafer (200) into at least two wafer components by causing the wafer separating device to break the semiconductor wafer (200) along the separation line region (210) while maintaining the optically detectable reference feature (12). [16] Method (300) according to one of the preceding claims 12 to 15, wherein the controlling (340) of the relative movement between the semiconductor wafer (200) and the wafer separating device takes place independently of the course of the terminating edge (131) of the passivation structure (13). [17] Power semiconductor die (100), comprising: - a semiconductor body (10); - an insulating layer (11) on the semiconductor body (10); - an active region (210), wherein the active region (210) forms part of the semiconductor body (10); - a remaining portion of a semiconductor wafer separation line region (220) disposed adjacent to the active region (210); - a passivation structure (13) arranged above the insulation layer (11) and such that it leaves a portion (111) of the insulation layer (11) exposed, the exposed portion (111) being closed off by a terminating edge (131) of the passivation structure (13); - an optically detectable reference feature (12), wherein the optically detectable reference feature (12): - is contained in the active area (210), - is spatially offset from the end edge (131), - is released from the passivation structure (13) and wherein: - the optically detectable reference feature (12) comprises a trench structure (121), and wherein the trench structure (121) comprises at least one electrical potential-free trench electrode (1211); and / or - the optically detectable reference feature (12) comprises one or more contact plugs (122) extending into the insulation layer (11). [18] Semiconductor wafer separating device (500) for separating a semiconductor wafer (200) into a plurality of power semiconductor dies (100), the device (500) comprising: - a receiving device (510) configured to receive the semiconductor wafer (200), wherein the semiconductor wafer (200) comprises: - a semiconductor body (10); - an insulating layer (11) on the semiconductor body (10); - a plurality of active regions (210), each comprising a respective power semiconductor die (100), wherein the active region (210) forms part of the semiconductor body (10); - at least one separating line region (220) arranged adjacent to the active regions (210); - a passivation structure (13) arranged above the insulation layer (11) and such that it leaves a portion (111) of the insulation layer (11) exposed, the exposed portion (111) being closed off by a terminating edge (131) of the passivation structure (13); - at least one optically detectable reference feature (12), wherein the at least one optically detectable reference feature (12) - is contained in one or more of the active areas (210), - is spatially offset from the end edge (131), - is released from the passivation structure (13), and wherein: - the optically detectable reference feature (12) comprises a trench structure (121), and wherein the trench structure (121) comprises at least one electrical potential-free trench electrode (1211); and / or - the optically detectable reference feature (12) comprises one or more contact plugs (122) extending into the insulation layer (11); - a detector (520) configured to detect position data (521) indicating a position of the optically detectable reference feature (12); - a computing device (530) configured to receive the position data and history data (531), wherein the history data (531) is associated with the semiconductor wafer (200) and defines a profile of the at least one dividing line region (210) with respect to the position of the at least one optically detectable reference feature (12); - a wafer separator (540) coupled to the computing device (520) and configured to separate the semiconductor wafer (200) into a plurality of power semiconductor dies (100), wherein the computing device is configured to control the wafer separator (540) based on the position data (521) and the history data (531).

Images