Memory circuit configuration and procedure

Abstract

Circuit (100, 200) comprising the following: a data line (114, RBL1, RBL2); a first cell (112, 210A, 210B) identified as a weak cell in a first row (200R1) of a memory arrangement (110), wherein the first cell (112, 210A, 210B) is electrically coupled to the data line (114, RBL1, RBL2); and a second cell (112, 210C, 210D) in a second row (200R2) of the memory arrangement (110), wherein the second cell (112, 210C, 210D) is electrically coupled to the data line (114, RBL1, RBL2), wherein the circuit (100, 200) is configured to transfer data from the first cell (112, 210A, 210B) and the second cell (112, 210C, 210D) to the data line (114, RBL1, RBL2) simultaneously in a first first row (200R1) read operation in response to a received address signal (AS) containing address information corresponding to a first row address (200R1) of the memory arrangement (110).

Description

BACKGROUND

[0001] A memory array data access involves read and write operations, the speeds of which depend on the memory cell type, memory circuit design, operating voltages, operating temperature, and variations in the manufacturing process. The overall speed of a system that incorporates a memory array is partly based on memory access speeds.

[0002] In many applications, memory circuits are operated at low voltages to reduce power consumption and heat generation. As operating voltages decrease, circuit speeds and, consequently, memory access speeds typically decrease as well.

[0003] US Patent 5,956,279 A discloses an SRAM device with a burn-in test circuit. In a burn-in test mode, a number of word lines are selected, and the memory cells coupled to the selected word lines are subjected to repeated read and write operations.

[0004] WO 2006 / 124486 A1 describes a self-test circuit for determining minimum operating voltages. Self-test circuits are also known from US 2005 / 0188289 A1.

[0005] US 2015 / 0155055A1 describes a test procedure for a semiconductor storage device for detecting defective cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as desired for clarity. Fig. Figure 1A is a diagram of a memory circuit according to some embodiments. Fig. 1B and Fig. 1C are curve diagrams of memory circuit operating parameters according to some embodiments. Fig. Figure 2 is a diagram of a memory circuit according to some embodiments. Fig. Figure 3 is a diagram of a memory circuit according to some embodiments. Fig. Figure 4 is a diagram of a memory circuit according to some embodiments. Fig. Figures 5A-5C are diagrams of address decoding circuits according to some embodiments. Fig. Figure 6 is a flowchart of a procedure for reading data from a weak cell according to some embodiments. Fig. Figure 7 is a flowchart of a procedure for configuring a memory circuit according to some embodiments. DETAILED DESCRIPTION

[0007] The present invention provides a circuit with the features of claim 1 and a method with the features of claims 9 and 16, respectively. Exemplary embodiments are given in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples.For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0009] In various embodiments, a weak cell in a row of a memory circuit is identified based on the speed of a test read operation, and address information corresponding to the row's address is stored in a memory device. During subsequent read operations of the row containing the weak cell, data is simultaneously read from the weak cell and from a cell in a second row of the memory circuit based on the stored address information, thereby improving the speeds of the subsequent read operations.

[0010] In various embodiments, a memory circuit comprises a first row of memory cells, which includes a weak cell, and a second row of memory cells, the second row being configured to be activated during read and write operations of the first row of memory cells. By pairing the second row with the first row and allowing the first row to operate at increased read speeds, the overall operating speed of the memory circuit is increased, and a reduced operating voltage of the memory circuit is enabled.

[0011] Fig. Figure 1A is a diagram of a memory circuit 100 according to some embodiments. The memory circuit 100 comprises a memory arrangement 110, an address decoding circuit 120 which is communicatively coupled to the memory arrangement 110 by a read / write (R / W) signal bus 115, a control circuit 130 which is communicatively coupled to the address decoding circuit 120 by a control signal bus 125, and a storage device 140 which is communicatively coupled to the control circuit 130 by the control signal bus 125 and communicatively coupled to the address decoding circuit 120 by a reference address bus 145.

[0012] Two or more circuit elements are considered communicatively coupled if a direct signal connection exists, or if an indirect signal connection exists that includes one or more logic devices, for example, an inverter or a logic gate, between the two or more circuit elements. In some embodiments, signal transmissions between the two or more communicatively coupled circuit elements can be modified by the one or more logic devices, for example, inverted or conditional.

[0013] In some embodiments, the memory circuit 100 is a memory macro. In some embodiments, the memory circuit 100 is a subset of a memory macro that includes one or more additional components, for example, at least one (not shown) memory arrangement in addition to the memory arrangement 110.

[0014] The memory arrangement 110 comprises an arrangement of memory cells 112. The memory cells 112 are electrical, electromechanical, electromagnetic, or other devices configured to store data represented by logical states. The logical states of memory cells 112 can be programmed in a write operation and detected in a read operation.

[0015] In various embodiments, a logical state corresponds to a voltage level of an electric charge stored in a memory cell 112, a physical property, for example a resistance or a magnetic orientation, a component of a memory cell 112, or any other configurable aspect of a memory cell 112.

[0016] In some embodiments, the memory cells 112 are static random access memory (SRAM) cells. In some embodiments, the memory cells 112 are eight-transistor (8T) SRAM memory cells, for example, memory cells 300, which are described below with reference to Fig. 3 will be discussed. In some embodiments, the memory cells are 112 nine-transistor (9T) SRAM memory cells, for example, memory cells 400, which are discussed below with reference to Fig. 4 will be discussed.

[0017] In some embodiments, the memory cells are 112 dynamic random access memory (DRAM) cells.

[0018] Memory cells 112 are arranged as one set of rows 110A and one set of rows 110B. In the Fig. In the embodiment shown in Figure 1A, both the set of lines 110A and the set of lines 110B contain two rows of memory cells 112. In some embodiments, one or both of the sets of lines 110A and 110B comprise one row of memory cells 112.

[0019] In the Fig. In the embodiment shown in Figure 1A, the memory arrangement 110 does not include an additional row of memory cells 112 between the set of rows 110A and the set of rows 110B. In some embodiments, the memory arrangement 110 includes one or more additional rows (not shown) of memory cells 112 between the set of rows 110A and the set of rows 110B.

[0020] In the Fig. In the embodiment shown in Figure 1, the memory circuit 100 has a data storage capacity based solely on the number of lines in the set of lines 110A, and the set of lines 110B is configured as a set of lines that complements the set of lines 110A. In some embodiments, the memory circuit 100 has a data storage capacity based on the total number of lines in the set of lines 110A and the set of lines 110B.

[0021] In the Fig. In the embodiment shown in Figure 1A, the set of lines 110A comprises a total of two rows of memory cells 112. In some embodiments, the set of lines 110A comprises a number of lines greater than two. In some embodiments, the set of lines 110A comprises a number of lines in the range of 4 to 1024. In some embodiments, the set of lines 110A comprises a number of lines in the range of 128 to 512.

[0022] In the Fig. In the embodiment shown in Figure 1A, the set of lines 110B comprises a total of two rows of memory cells 112. In some embodiments, the set of lines 110B comprises a number of lines greater than two. In some embodiments, the set of lines 110B comprises a number of lines in the range of 4 to 32.

[0023] In the Fig. In the embodiment shown in Figure 1A, each line of the set of lines 110A and of the set of lines 110B comprises four memory cells 112. In various embodiments, each line of the set of lines 110A and of the set of lines 110B comprises fewer or more than four memory cells 112. In some embodiments, each line of the set of lines 110A and of the set of lines 110B comprises a number of memory cells 112 in the range of 4 to 128. In some embodiments, each line of the set of lines 110A and of the set of lines 110B comprises a number of memory cells 112 in the range of 32 to 64.

[0024] The read data lines 114 are conductive lines in the memory arrangement 110, which are oriented perpendicular to and intersect each line of the set of lines 110A and of the set of lines 110B. In the Fig. In the embodiment shown in Figure 1A, each memory cell 112 is intersected by a read data line 114. In some embodiments, each memory cell 112 is intersected by more than one read data line 114. The total number of read data lines 114 is based on the number of memory cells 112 in each row of the set of rows 110A and the set of rows 110B, and the type of memory cells 112 in the memory arrangement 110.

[0025] The memory arrangement 110 is configured to store data in memory cells 112, which is received from an external circuit (not shown) via write data lines (not shown), and to output data from memory cells 112 to the external circuit via read data lines 114. In write operations, the received data is stored at row positions activated by corresponding read / write signals 115S received from the R / W signal bus 115. In read operations, the stored data is output from row positions activated by corresponding read / write signals 115S received from the R / W signal bus 115.

[0026] The address decoding circuit 120 comprises a logic circuit configured to generate read / write signals 115S based on control signals 125S received from the control signal bus 125, and to output read / write signals 115S to the R / W signal bus 115. The R / W signal bus 115 comprises several write signal lines corresponding to the memory cell rows of the memory arrangement 110, and several read signal lines, for example, read signal lines RWL1 and RWL2, which are described below with reference to Fig. 2 will be discussed, which correspond to the memory cell rows of the memory arrangement 110.

[0027] Control signals 125S contain line address information that can be used by the address decoding circuit 120 to determine a write signal line on which a specific read / write signal 115S is to be output, indicating that a specific line of the set lines 110A is to be activated in a write operation, and a read signal line on which a specific read / write signal 115S is to be output, indicating that a specific line of the set lines 110A is to be activated in a read operation.

[0028] In various embodiments, the line address information contains a line address of a line of the set lines 110A, a section of a line address of a line of the set lines 110A, or an index or other identifier corresponding to a line address of a line of the set lines 110A.

[0029] In some embodiments, outputting a specific read / write signal 115S, indicating the activation of a particular line in a read or write operation, includes outputting the specific read / write signal 115S, which has a high logic voltage level. In some embodiments, outputting a specific read / write signal 115S, indicating the activation of a particular line in a read or write operation, includes outputting the specific read / write signal 115S, which has a low logic voltage level.

[0030] In some embodiments, the control signals 125S contain additional information which can be used by the address decoding circuit 120 to perform additional operations, for example initiating and terminating write and read operations based on a timing of control signals 125S.

[0031] The R / W signal bus 115 comprises an R / W signal bus 115A, corresponding to the set of lines 110A, and an R / W signal bus 115B, corresponding to the set of lines 110B. The address decoding circuit 120 comprises an address decoding circuit 120A, corresponding to the R / W signal bus 115A, and an address decoding circuit 120B, for example, an address decoding circuit 500, which is described below with reference to Fig. 5 is discussed, which corresponds to the R / W signal bus 115B.

[0032] The address decoding circuit 120A is communicatively coupled to the control circuit 130 via the control signal bus 125 and is configured to generate read / write signals 115S during operation based on the line address information in control signals 125S received from the control signal bus 125 and output them to the R / W signal bus 115A.

[0033] The address decoding circuit 120B is communicatively coupled to the control circuit 130 via the control signal bus 125 and to the storage device 140 via the reference address bus 145. The address decoding circuit 120B is configured to generate read / write signals 115S during operation, based on a comparison of the line address information in the control signals 125S with reference address information stored in the storage device 140 and received from the reference address bus 145, and to output these signals to the R / W signal bus 115B.

[0034] The reference address information contains information that, together with the line address information, can be used by the decoder circuit 120B to determine whether a specific line of the set of lines 110A is activated in a write or read operation. The decoder circuit 120B is configured to respond, when the line determined by the line address information matches the line determined by the reference address information, by generating an activating read / write signal 115S during the write or read operation and outputting it on the R / W signal bus 115B.

[0035] The reference address information can also be used by the decoding circuit 120B to determine a specific write signal line of the R / W signal bus 115B on which the read / write signal 115S is to be output, indicating that a corresponding line of the set of lines 110B is to be activated in the write operation, and a specific read signal line of the R / W signal bus 115B on which the read / write signal 115S is to be output, indicating that a corresponding line of the set of lines 110B is to be activated in the read operation. In some embodiments, the decoding circuit 120B is configured to determine the specific write or read line based on one or more positions on the reference address bus 145 where the reference address information is received.

[0036] In various embodiments, the reference address information contains a line address of a line of the set lines 110A, a section of a line address of a line of the set lines 110A, or an index or other identifier corresponding to a line address of a line of the set lines 110A.

[0037] The control circuit 130 comprises one or more logic circuits configured to control the operation of the memory circuit 100 by receiving input signals on an input bus (not shown) and generating control signals 125S based on the input signals and outputting them on the control signal bus 125.

[0038] Control circuit 130 is configured to generate control signals 125S containing the line address information received by address decoding circuit 120, as discussed above. Control circuit 130 is further configured to generate control signals 125S containing the reference address information and output them to control signal bus 125.

[0039] The storage device 140 comprises a volatile or non-volatile storage medium capable of receiving the reference address information from the control signal bus 125, storing the reference address information, and outputting the reference address information to the reference address bus 145. In some embodiments, storing the reference address information during operation includes retaining the reference address information in the storage device 140 for periods when the storage circuit 100 is in a switched-off state.

[0040] In some embodiments, the storage device 140 comprises non-volatile memory (NVM). An NVM comprises memory elements that can be configured in response to control signals 125S to retain reference address information in the storage device 140 for periods when the memory circuit 100 is in a powered-off state. In some embodiments, an NVM comprises one or more sets of fuses that can be selectively opened in response to control signals 125S, the structure of the opened fuses corresponding to the stored address information. In some embodiments, storing the reference address information during operation involves opening one or more fuses in the storage device 140.

[0041] The memory circuit 100 is thus configured to store the reference address information in the memory device 140 during operation and to transmit the reference address information to the address decoding circuit 120B.

[0042] In a write or read operation in which data is written to or read from the memory cells 112 of a particular line of the set lines 110A, the control circuit 130 outputs control signals 125S containing the line address information corresponding to the particular line to the control signal bus 125, and each of the address decoding circuits 120A and 120B receives control signals 125S containing the relevant line address information from the control signal bus 125.

[0043] During the write operation, the address decoding circuit 120A responds to the receipt of the relevant line address information by outputting the read / write signal 115S, which indicates that the specific line on the write signal line of the R / W signal bus 115A corresponding to the specified line should be activated. In response to the activation signal, the memory cells 112 of the specified line store data from the write data lines according to the logical voltage levels on the corresponding write data lines.

[0044] During the read operation, the address decoding circuit 120A responds to the receipt of the relevant row address information by outputting the read / write signal 115S, which indicates that the specific row on the read signal line of the R / W signal bus 115A corresponding to the specified row should be activated. In response to the activation signal, the memory cells 112 of the specified row transfer data to the read data lines 114. The data transfer during the read operation includes pre-charging the read data lines 114 to a pre-charge voltage level and selectively biasing the read data lines 114 to a bias level based on the logical states of the memory cells 112 in the specified row.

[0045] As discussed above, in both write and read operations, the address decoding circuit 120B responds to the reception of the relevant line address information in control signals 125S by comparing the relevant line address information with the reference address information received from the reference address bus 145. During operation, if the relevant line address information and the reference address information correspond to the same line of the set of lines 110A, the address decoding circuit 120B outputs a corresponding read / write signal 115S, indicating that the first line of the set of lines 110B should be activated on a corresponding write or read signal line of the R / W signal bus 115B.In response to the activation signal, memory cells 112 of the first line of the set lines 110B store data from the write data lines in the write operation and transfer data from memory cells 112 to the read data lines 114 in the read operation.

[0046] The memory circuit 100 is configured to synchronize the write and read operations on the specified line of set lines 110A and the first line of set lines 110B, so that they have approximately the same initiation and termination times. In some embodiments, timing of control signals 125S, output by the control circuit 130 to the control signal bus 125, can be used by the address decoding circuits 120A and 120B to control the initiation and termination times in the write and read operations.

[0047] During the write operation, the data on the write data lines is therefore simultaneously stored in memory cells 112 of the specific line of the set lines 110A and in memory cells 112 of the first line of the set lines 110B.

[0048] During the read operation, the data stored in memory cells 112 of the specified line of the record, lines 110A, and in the first line of the record, lines 110B, are simultaneously transferred from these memory cells to the read data lines 114. Because the data was previously written simultaneously to both the specified line of the record, lines 110A, and the first line of the record, lines 110B, the memory cells 112 of the specified line of the record, lines 110A, have logical states that correspond to the logical states of the corresponding memory cells 112 of the first line of the record, lines 110B.

[0049] In the read operation, a data bit is transferred to a specific read data line 114 by selectively biasing the specific read data line 114 to the bias level using both a corresponding memory cell 112 of the specific line of the set lines 110A and a corresponding memory cell 112 of the first line of the set lines 110B.

[0050] The memory circuit 100 is thereby configured to operate the memory cells 112 in the first line of the set lines 110B as memory cells 112 that are redundant to the memory cells 112 of the specified line of the set lines 110A in the write and read operations.

[0051] The rate at which a data bit is transferred in the read operation is a function of a memory cell current, which causes a specific read data line 114 to be biased to the bias level. Non-restrictive examples of memory cell currents are given below with reference to memory cells 210A-D, 300, and 400. Fig. 2, Fig. 3 and Fig. 4 discussed.

[0052] During the read operation on the specific row of set 110A, each selectively biased read data line 114 is biased by the sum of two memory cell currents: a first current provided by the corresponding memory cell 112 in the specific row of set 110A, and a second current provided by the corresponding redundant memory cell 112 in the first row of set 110B. By providing the second memory cell currents, the redundant memory cells 112 cause the corresponding read data lines 114 to be biased during the read operation using total current levels above the levels of the first memory cell currents. Due to the increased total currents that bias the selectively biased data lines 114, the speed of the read operation on the specific row of set 110A is increased.

[0053] In the read operation, a specific memory cell current has a level based on a difference between the pre-charge voltage level on the corresponding read data line 114 and the bias voltage level, as well as on the resistance of a current path in the specific memory cell 112.

[0054] The difference between the pre-charge and bias levels is a function of the operating voltage of the storage circuit 100. In some embodiments, the pre-charge voltage level is a function of the operating voltage of the storage circuit 100. In some embodiments, the bias level is a function of the operating voltage of the storage circuit 100.

[0055] The current path resistance value is a function of the configuration and physical properties, for example, the dimensions of the structural elements of a transistor and / or the doping concentration values, of the specific memory cell 112. In some embodiments, the current path resistance value is also a function of the operating voltage of the memory circuit 100. In some embodiments, the current path comprises a transistor channel controlled by a gate voltage, and the current path resistance value is a function of the operating voltage of the memory circuit 100, on which the gate voltage is based.

[0056] Because, as discussed above, the memory cell current levels are a function of both the physical properties of the memory cells 112 and the operating voltage level of the memory circuit 100, the read operating speeds are a function of both the physical properties of the memory cells 112 and the operating voltage level of the memory circuit 100. A read operating speed of a memory cell 112 therefore comprises an intrinsic component corresponding to the physical properties and an extrinsic component corresponding to the operating voltage level.

[0057] Due to variations in the manufacturing process, the memory cells 112 have non-uniform physical properties, resulting in non-uniform intrinsic read operation speed components. In some embodiments, the overall speed of the memory circuit 100 is limited based on a memory cell 112 exhibiting the slowest intrinsic read operation speed component.

[0058] In some embodiments, the fluctuations of the intrinsic read operation speed components are described by a statistical distribution. In some embodiments, the fluctuations of the intrinsic read operation speed components are described by a Gaussian distribution.

[0059] Fig. 1B and Fig. 1C are curve diagrams of operating parameters of the memory circuit 100 according to some embodiments. Fig. Figure 1B shows a relationship between an operating frequency FRQ and a minimum operating voltage VCCMIN of the memory circuit 100 in some embodiments. Fig. Figure 1C shows a relationship between an intrinsic read operational speed component SPD of the memory circuit 100 and the minimum operating voltage VCCMIN in some embodiments.

[0060] In Fig. Figure 1B shows the operating frequency FRQ along the x-axis, and the operating voltage VCCMIN along the y-axis. Curve S1 represents the relationship between the operating frequency FRQ and the minimum operating voltage VCCMIN for a lowest intrinsic read operational speed component value SPD1, and curve S2 represents the relationship between the operating frequency FRQ and the minimum operating voltage VCCMIN for an intrinsic read operational speed component value SPD2.

[0061] Curve S1 extends from an operating frequency value FRQ1 and a minimum operating voltage value V2 to an operating frequency value FRQ2 and a minimum operating voltage value V4. Curve S2 extends from the operating frequency value FRQ1 and a minimum operating voltage value V1 to the operating frequency value FRQ2 and a minimum operating voltage value V3.

[0062] The time period within which a read operation in memory cell 112 must be completed without read errors is based on the operating frequency FRQ. That is, as the operating frequency FRQ increases, so does the minimum read operation speed. As discussed above, read operation speeds increase as the operating voltage levels increase. Accordingly, each of the curves S1 and S2 has a positive slope, indicating that, for a given intrinsic read operation speed component value, the minimum operating voltage VCCMIN increases as the operating frequency FRQ increases.

[0063] Because curve S1 corresponds to the slowest intrinsic read operation speed component value SPD1, curve S2 corresponds to the intrinsic read operation speed component value SPD2, whose value is higher than the slowest intrinsic read operation speed component value SPD1. Therefore, for each value of the operating frequency FRQ, curve S1 represents a minimum operating voltage value VCCMIN that is higher than a corresponding minimum operating voltage value VCCMIN represented by curve S2.

[0064] In the Fig. 1B and Fig. In the embodiment shown in Figure 1C, the minimum operating voltage value V3 is greater than the minimum operating voltage value V2. In some embodiments, the minimum operating voltage value V3 is at most as high as the minimum operating voltage value V2.

[0065] In the Fig. 1B and Fig. In the embodiment shown in Figure 1C, the relationships between the operating frequency FRQ, the minimum operating voltage VCCMIN, and the intrinsic read operational speed component SPD are represented by straight lines for illustrative purposes. In various embodiments, one or more relationships between the operating frequency FRQ, the minimum operating voltage VCCMIN, and the intrinsic read operational speed component SPD are represented by curves other than straight lines.

[0066] In Fig. 1C is the intrinsic read operation speed component SPD shown along the x-axis. A curve N in the lower section of Fig. 1C represents a statistical distribution of a number of memory cells 112 as a function of the intrinsic read operation speed component SPD. The curves F1 and F2 in the upper section of Fig. 1C represents the minimum operating voltage VCCMIN as a function of the intrinsic read operation rate component SPD at operating frequency values ​​FRQ1 and FRQ2, respectively.

[0067] The curve N extends from the lowest intrinsic read operation speed component value SPD1 to the highest intrinsic read operation speed component value SPD3. In the Fig. In the embodiment shown in Figure 1C, curve N represents a Gaussian distribution of the physical properties of memory cells 112 based on variations in the manufacturing process. In some embodiments, the physical properties of memory cells 112 based on variations in the manufacturing process are represented by a curve from the lowest intrinsic read operation speed component value SPD1 to the highest intrinsic read operation speed component value SPD3, which represents a different statistical distribution than a Gaussian distribution.

[0068] The lowest intrinsic read operation rate component value SPD1 corresponds to a point on curve F1 representing the minimum operating voltage value V2, and a point on curve F2 representing the minimum operating voltage value V4. The intrinsic read operation rate component value SPD2 corresponds to a point on curve F1 representing the minimum operating voltage value V1, and a point on curve F2 representing the minimum operating voltage value V3.

[0069] The curves F1 and F2 illustrate that, for a given operating frequency FRQ, an increase in the intrinsic read operation speed component SPD from the lowest value SPD1 to the value SPD2 corresponds to a decrease in the minimum operating voltage VCCMIN.

[0070] In some embodiments, a lowest possible value of the operating voltage VCCMIN for the memory circuit 100 is based on the lowest intrinsic read operational speed component SPD1. In such embodiments, increasing the lowest intrinsic read operational speed component value SPD1 to a higher value, for example, the intrinsic read operational speed component value SPD2, decreases the lowest possible value of the operating voltage VCCMIN for a given operating frequency FRQ.

[0071] Due to the redundant memory cell configuration discussed above, the memory circuit 100 is able to increase the currents used to transfer data from the memory cells 112 of the specific row of the set rows 110A to the read data lines 114 in the read operation, effectively increasing the intrinsic read operation speed component value of the memory cells 112 in the specific row of the set rows 110A.

[0072] The memory circuit 100 can therefore be configured to increase the read operation speed of a slowest memory cell 112 by identifying a line comprising a slowest memory cell 112 as the specific line of the set lines 110A and storing the corresponding reference address information in the memory device 140, so that the memory cells 112 of the first line of the set lines 110B are operated in subsequent read operations as memory cells 112 that are redundant for the memory cells 112 of the specific line of the set lines 110A.

[0073] To generate the reference address information stored in the memory device 140 and used to identify the specific line of the set of lines 110A, the control circuit 130 includes a test circuit 132. The test circuit 132 is a circuit configured to allow a determination that the specific line of the set of lines 110A meets a speed criterion during a read operation. In some embodiments, the test circuit 132 is configured such that during operation, some or all of the operations of method 700, described below with reference to Fig. 7 is discussed, and will be carried out using the test circuit 132.

[0074] In some embodiments, the test circuit 132 includes a built-in self-test (BIST) circuit configured to perform one or more write and / or read operations on each line of the set of lines 110A. In some embodiments, the test circuit 132 is configured to determine one or more execution speeds of one or more write and / or read operations on each line of the set of lines 110A.

[0075] In some embodiments, the test circuit 132 is configured to determine one or more execution speeds of one or more write and / or read operations on each line of the set lines 110A by measuring the one or more execution speeds of the one or more write and / or read operations on each line of the set lines 110A. In some embodiments, the test circuit 132 is configured to determine one or more execution speeds of one or more write and / or read operations on each line of the set lines 110A by detecting one or more write or read errors associated with the one or more write and / or read operations on each line of the set lines 110A.

[0076] In some embodiments, the test circuit 132 is configured to determine one or more execution speeds of one or more write and / or read operations on each line of the set of lines 110A, and is thereby able to identify a line containing a weak cell, also referred to as a weak line. During operation, identifying a weak cell involves determining the one or more execution speeds while varying one or more operating parameters of the memory circuit 100.

[0077] In some embodiments, the test circuit 132 is configured to control an operating frequency of the memory circuit 100. In some embodiments, the test circuit 132 is configured to control an operating voltage level of the memory circuit 100. In some embodiments, the test circuit 132 is configured to determine one or more execution speeds of one or more write and / or read operations on each line of the set lines 110A by controlling an operating frequency of the memory circuit 100 and / or an operating voltage level of the memory circuit 100.

[0078] In some embodiments, the test circuit 132 includes an interface configured to allow an (not shown) external circuit and / or a user to determine that the particular line of the set lines 110A meets a speed criterion during a write and / or read operation.

[0079] In some embodiments, the test circuit 132 is configured to measure several speeds corresponding to the one or more write and / or read operations on each line of the set of lines 110A, and to determine, based on a speed of one or more write and / or read operations on the specific line, which is a speed of one or more of the slowest speeds of the several speeds, that the specific line of the set of lines 110A meets the speed criterion.

[0080] Once it has been determined that the specific line of the set lines 110A meets the speed criterion during a write and / or read operation, the control circuit 130 is configured to generate control signals 125S containing the reference address information corresponding to the address of the specific line and output them to the control signal bus 125.

[0081] In some embodiments, the test circuit 132 is configured to determine whether a specific line of the set of lines 110A meets a speed criterion for a single line of the set of lines 110A. In some embodiments, the test circuit 132 is configured to determine whether a specific line of the set of lines 110A meets a speed criterion for multiple lines of the set of lines 110A.

[0082] In some embodiments, the control circuit 130 is configured to generate control signals 125S and output them to the control signal bus 125, which contain reference address information corresponding to several addresses of lines of lines 110A that meet the speed criterion during the write and / or read operation.

[0083] In some embodiments, the storage device 140 is configured to store the reference address information corresponding to multiple addresses of multiple lines of the set lines 110A and to output it to the reference address bus 145.

[0084] In some embodiments, the address decoding circuit 120B is configured to compare relevant line address information in control signals 125S received from the control signal bus 125 with the reference address information corresponding to several addresses of multiple lines of the set of lines 110A received from the reference address bus 145, and to output one read / write signal 115S from multiple read / write signals 115S indicating to activate one of multiple lines of the set of lines 110B on a corresponding write or read signal line of the R / W signal bus 115B.

[0085] In some embodiments, the memory circuit 100 is configured to operate the memory cells 112 in multiple rows of the set of rows 110B as memory cells 112 that are redundant to the memory cells 112 of multiple rows of the set of rows 110A in the write and read operations. In some embodiments, the memory circuit 100 is configured to operate the memory cells 112 in a single row of the set of rows 110B as memory cells 112 that are redundant to the memory cells 112 of a single row of the set of rows 110A in the write and read operations. In some embodiments, the memory circuit 100 is configured to operate the memory cells 112 in multiple rows of the set of rows 110B as memory cells 112 that are redundant to the memory cells 112 of a single row of the set of rows 110A in the write and read operations.

[0086] The in Fig. The embodiment shown in Figure 1A is a non-restrictive example of the memory circuit 100. In some embodiments, the memory circuit 100 has a configuration that differs from that shown in Figure 1A. Fig. 1A differs, and is able to operate one or more lines of the set lines 110B as redundant memory cells 112 to increase the speed of write and / or read operations of one or more lines of the set lines 110A.

[0087] In some embodiments, for example, the memory arrangement 110 comprises the set of lines 110A and the set of lines 110B as a single set of lines of memory cells 112. In some embodiments, for example, the address decoding circuit 120 is a single circuit. In some embodiments, for example, the R / W signal bus 115 is a single bus. In some embodiments, for example, the test circuit 132 is separate from the control circuit 130. In some embodiments, for example, the storage device 140 is part of the address decoding circuit 120. In some embodiments, for example, the storage device 140 is part of the control circuit 130.

[0088] By increasing the speed of the specific row of set rows 110A, which was found to meet the speed criterion when using the redundant row of set rows 110B, the overall operating speed of the memory circuit 100 can be increased by eliminating one of the slowest read operations among several speed operations. Memory circuit 100 can thus have a higher overall operating speed than a memory circuit that does not include a redundant row of memory cells, thereby improving the memory circuit's performance and compatibility with other circuits.Because the speed of the storage circuit typically decreases as the operating voltage decreases for a given operating frequency, an increased speed of the storage circuit allows the storage circuit 100 to be operated at a voltage value lower than that of a storage circuit without increasing the speed of the storage circuit based on a redundant row of memory cells, thereby reducing energy consumption and power-related heat generation.

[0089] Fig. Figure 2 is a diagram of a memory circuit 200 according to some embodiments. The memory circuit 200 can be used as a section of the memory circuit 100, as above with reference to the Fig. 1A-1C was discussed. The memory circuit 200 comprises cells 210A, 210B, 210C, and 210D, each of which can be used as memory cells 112; data lines RBL1 and RBL2, which can be used as read data lines 114; read signal line RWL1, which can be used as a section of the R / W signal bus 115A or 115B; and read signal line RWL2, which can be used as a section of the R / W signal bus 115A or 115B, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0090] A row 200R1 comprises cells 210A and 210B and can be used as one row of either the set of rows 110A or the set of rows 110B, as above with reference to memory circuit 100 and the Fig. 1A-1C was discussed. Row 200R1 is configured to receive a read signal RWL1S from the read signal line RWL1. Row 200R2 comprises cells 210C and 210D and can be used as one row of the other of the set of rows 110A or the set of rows 110B, as discussed above with reference to memory circuit 100 and the Fig. 1A-1C was discussed. Line 200R2 is configured to receive a read signal RWL2S from the read signal line RWL2. Each of the read signals RWL1S and RWL2S can be used as a read / write signal 115S, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0091] Each of the data lines RBL1 and RBL2 runs perpendicular to the read signal lines RWL1 and RWL2 and intersects both rows 200R1 and 200R2. Data line RBL1 intersects row 200R1 at cell 210A and intersects row 200R2 at cell 210C. Data line RBL2 intersects row 200R1 at cell 210B and intersects row 200R2 at cell 210D.

[0092] In the Fig. In the embodiment shown in Figure 2, each of the cells 210A, 210B, 210C, and 210D is electrically coupled to a single data line, for example, data line RBL1 or RBL2, and is electrically coupled to a single read signal line, for example, read signal line RWL1 or RWL2. In some embodiments, each of the cells 210A, 210B, 210C, and 210D is electrically coupled to one or more additional data lines (not shown) and / or is electrically coupled to one or more additional signal lines (not shown).

[0093] In various embodiments, two or more circuit elements are considered to be electrically coupled if there is a direct electrical connection, or if there is an electrical connection that includes another circuit element and can be controlled by it, for example by making it resistive or opening it by a transistor or other switching device.

[0094] Each of the cells 210A, 210B, 210C, and 210D comprises a switching device 212, which is electrically coupled to a data line, for example, data line RBL1 or RBL2, and to a node 214 configured to carry a voltage level. The switching device 212 is communicatively coupled to a read signal line, for example, one of the read signal lines RWL1 or RWL2, such that during operation, the switching device 212 is either open or closed in response to a signal, for example, one of the read signals RWL1S or RWL2S, on the read signal line. The switching device 212 is thereby configured to electrically couple the data line to the node 214 in response to the read signal received on the read signal line.

[0095] In various embodiments, the switching device 212 comprises a transistor, such as a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), an n-type transistor or a p-type transistor, or another device capable of opening and closing in response to a signal.

[0096] In some embodiments, the switching device 212 comprises a transistor having a first terminal electrically coupled to the data line, a second terminal electrically coupled to node 214, and a gate terminal electrically coupled to the signal line. In some embodiments, the switching device 212 comprises a transistor 8TNM1oF memory cell 300, which is described below with reference to Fig. 3 is discussed. In some embodiments, the switching device 212 comprises a transistor 9TNM1 of the memory cell 400, which is discussed below with reference to Fig. 4 will be discussed.

[0097] Each of the cells 210A, 210B, 210C, and 210D is configured to bias the data line toward the voltage level at node 214 during a read operation of the memory arrangement. In some embodiments, biasing the data line toward the voltage level during the read operation involves causing the data line voltage level to approach, but not reach, the voltage level at node 214. In other embodiments, biasing the data line toward the voltage level during the read operation involves causing the data line voltage level to reach the voltage level at node 214.

[0098] In some embodiments, node 214 is configured to carry a predefined voltage level, and each of the cells 210A, 210B, 210C and 210D is thereby configured to bias the data line in the direction of the predefined voltage level during the read operation.

[0099] In some embodiments, node 214 is a grounding node configured to carry a ground reference voltage of the memory arrangement, and each of the cells 210A, 210B, 210C, and 210D is thereby configured to bias the data line toward a ground reference voltage level of the grounding reference node during the read operation. In some embodiments, biasing the data line toward the ground reference voltage level of the grounding reference node during the read operation includes discharging the data line. In some embodiments, biasing the data line toward the ground reference voltage level of the grounding reference node during the read operation includes discharging the data line that was previously charged to a pre-charge voltage level as part of the read operation.

[0100] In some embodiments, node 214 is a power supply node configured to carry an operating voltage of the memory arrangement, and each of the cells 210A, 210B, 210C, and 210D is thereby configured to bias the data line toward an operating voltage level of the power supply node during the read operation. In some embodiments, biasing the data line toward the operating voltage level of the power supply node during the read operation includes charging the data line. In some embodiments, biasing the data line toward the operating voltage level of the power supply node during the read operation includes charging the data line that was previously discharged to the ground reference voltage level as part of the read operation.

[0101] In some embodiments, node 214 is a logic node configured to carry a logic voltage of the memory arrangement, and each of the cells 210A, 210B, 210C, and 210D is thereby configured to bias the data line toward a logic voltage level of the logic node during the read operation. In some embodiments, biasing the data line toward the logic voltage level of the logic node during the read operation includes biasing the data line toward the logic voltage level stored in the memory cell as a result of a previous write operation.

[0102] In the Fig. In the embodiment shown in Figure 2, the switching device 212 is a single switching device that is electrically coupled between the data line and node 214. In some embodiments, each of the cells 210A, 210B, 210C, and 210D comprises an additional switching device (not shown) that is electrically coupled between the data line and node 214. In some embodiments, the additional switching device is configured to electrically couple the data line to node 214 in response to a logical state of cell 210A, 210B, 210C, or 210D.

[0103] By incorporating the switching device 212, which is communicatively coupled to a read signal line, for example one of the read signal lines RWL1 or RWL2, each of the cells 210A, 210B, 210C and 210D is configured to bias the data line in the direction of the voltage level in response to a read signal, for example one of the read signals RWL1S or RWL2S, during the read operation.

[0104] In some embodiments where the switching device 212 comprises an n-type transistor, each of the cells 210A, 210B, 210C, and 210D is configured to bias the data line in the direction of the voltage level in response to the read signal, which has a high logic voltage level during the read operation. In some embodiments where the switching device 212 comprises a p-type transistor, each of the cells 210A, 210B, 210C, and 210D is configured to bias the data line in the direction of the voltage level in response to the read signal, which has a low logic voltage level during the read operation.

[0105] Memory circuit 200 is configured such that the read signals RWL1 and RWL2 have the same logical voltage level during the read operation, as described above with reference to memory circuit 100. Fig. 1A-1C was discussed. In response to the read signals RWL1 and RWL2 with the same logical voltage level, cells 210A and 210C are configured to simultaneously bias the data line RBL1 towards the voltage level at node 214 in the read operation, and cells 210B and 210D are configured to simultaneously bias the data line RBL2 towards the voltage level at node 214 in the read operation.

[0106] The biasing of the data line in the direction of the voltage level in the read operation includes causing a current in the data line, for example a current IB in the data line RBL1, to flow through the switching devices 212 of the cell or cells configured to bias the data line in the direction of the voltage level in the read operation.

[0107] Because cells 210A and 210C are configured to simultaneously bias the data line RBL1 towards the voltage level at node 214 during the read operation, the current IB is the sum of a current I210A flowing through the switching device 212 of cell 210A and a current I210C flowing through the switching device 212 of cell 210C.

[0108] The rate at which data line RBL1 is biased toward the voltage level at node 214 increases by one order of magnitude as the current IB increases. Because current IB includes components from the two cell currents I210A and I210C, current IB is of a larger order of magnitude than a current with a single component from a single cell of the same cell type as cells 210A and 210C. Therefore, data line RBL1 is biased toward the voltage level at node 214 at a rate greater than the rate at which a data line biased by a single cell of the same cell type is biased toward the voltage level at node 214 during a read operation.

[0109] The configuration discussed above allows the memory circuit 200 to offer the advantages mentioned above with reference to the memory circuit 100 and Fig. 1 were discussed.

[0110] Fig. Figure 3 is a diagram of a memory circuit according to some embodiments. Fig. Figure 3 shows a memory cell 300, data lines 8TRBL, 8TWBL and 8TWBLB, a read signal line 8TRWL and a write signal line 8TWWL. The memory cell 300 can be used as memory cells 112, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0111] Memory cell 300 can be used as cells 210A, 210B, 210C and 210D, data line 8TRBL can be used as data lines RBL1 and RBL2, and read signal line 8TRWL can be used as read signal lines RWL1 and RWL2, as described above with reference to memory circuit 200 and Fig. 2 was discussed. The write signal line 8TWWL can be used as a section of the R / W signal bus 115, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. The memory cell 300 comprises the transistor 8TNM1, which can be used as part of the switching device 212 or as the entire switching device 212, as above with reference to the memory circuit 200 and Fig. 2 was discussed.

[0112] Memory cell 300 is an 8T SRAM memory cell comprising a power supply node VCC configured to carry an operating voltage and a reference node GND configured to carry a ground reference voltage. A p-type transistor 8TP1 and an n-type transistor 8TN1 are electrically connected in series between the power supply node VCC and the reference node GND, and a p-type transistor 8TP2 and an n-type transistor 8TN2 are electrically connected in series between the power supply node VCC and the reference node GND.

[0113] The gates of transistors 8TP1 and 8TN1 are electrically coupled to each other and to drains of transistors 8TP2 and 8TN2 at node 8T1, and the gates of transistors 8TP2 and 8TN2 are electrically coupled to each other and to drains of transistors 8TP1 and 8TN1 at node 8T2, thereby configuring memory cell 300 to interlock a first logic voltage level at node 8T1 with a second, complementary logic voltage level at node 8T2.

[0114] An n-type transistor 8TN3 is electrically coupled between node 8T2 and data line 8TWBL and has a gate that is communicatively coupled to the write signal line 8TWWL. Transistor 8TN3 is thus configured to electrically couple node 8T2 to data line 8TWBL in response to a high logic voltage level of a write signal (not labeled) on write signal line 8TWWL during a write operation.

[0115] An n-type transistor 8TN4 is electrically coupled between node 8T1 and data line 8TWBLB and has a gate that is communicatively coupled to the write signal line 8TWWL. This configures transistor 8TN4 to electrically couple node 8T1 to data line 8TWBLB in response to the high logic voltage level of the write signal on write signal line 8TWWL during a write operation.

[0116] An n-type transistor 8TNM1 and an n-type transistor 8TNM2 are electrically connected in series between the data line 8TRBL and the reference node GND. One gate of transistor 8TNM1 is communicatively coupled to the read signal line 8TRWL, and one gate of transistor 8TNM2 is communicatively coupled to node 8T2. Transistors 8TNM1 and 8TNM2 are thus configured to electrically couple the data line 8TRBL to the reference node GND in response to a high logic voltage level on the read signal line 8TRWL and a high logic voltage level at node 8T2.

[0117] In some embodiments, the memory cell 300 is part of a memory macro that includes a read amplifier, the data line 8TRBL is electrically coupled to the read amplifier, and the read amplifier is configured to determine a logical state of the memory cell 300 based on a voltage level on the data line 8TRBL in a read operation of the memory macro.

[0118] In some embodiments, the data line 8TRBL is pre-charged in a read operation to a pre-charge voltage level which is different from a ground reference voltage level of the ground reference voltage at the reference node GND.

[0119] In a read operation where transistors 8TNM1 and 8TNM2 are both switched on, a current I300 flows between the data line 8TRBL and the reference node GND based on a potential difference between the data line 8TRBL and the reference node GND voltage levels and on-state resistance values ​​of each of transistors 8TNM1 and 8TNM2.

[0120] The one-state resistance values ​​of transistors 8TNM1 and 8TNM2 vary with respect to a value of the high logic voltage level applied to the gates of transistors 8TNM1 and 8TNM2, and with respect to the physical properties caused by variations in the manufacturing process.

[0121] Through the configuration and use, as above with reference to the memory circuits 100 and 200 and Fig. 1A and Fig. As discussed in section 2, the memory cell 300 can offer the advantages mentioned above with reference to the memory circuit 100 and the Fig. 1A-1C were discussed.

[0122] Fig. Figure 4 is a diagram of a memory circuit according to some embodiments. Fig. Figure 4 shows a memory cell 400, data lines 9TRBL and 9TWBL, a read signal line 9TRWL, and a write signal line 9TWWL. Memory cell 400 can be used as memory cells 112, as above with reference to memory circuit 100 and the Fig. 1A-1C was discussed.

[0123] Memory cell 400 can be used as cells 210A, 210B, 210C and 210D, data line 9TRBL can be used as data lines RBL1 and RBL2, and read signal line 9TRWL can be used as read signal lines RWL1 and RWL2, as described above with reference to memory circuit 200 and Fig. 2 was discussed. The write signal line 9TWWL can be used as a section of the R / W signal bus 115, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. The memory cell 400 comprises the transistor 9TNM1, which can be used as part of the switching device 212 or as the entire switching device 212, as above with reference to the memory circuit 200 and Fig. 2 was discussed.

[0124] Memory cell 400 is a 9T SRAM memory cell comprising a power supply node VCC configured to carry the operating voltage and a reference node GND configured to carry the ground reference voltage. A p-type transistor 9TP1 and an n-type transistor 9TN1 are electrically connected in series between the power supply node VCC and the reference node GND, and a p-type transistor 9TP2 and an n-type transistor 9TN2 are electrically connected in series between the power supply node VCC and the reference node GND.

[0125] The gates of transistors 9TP1 and 9TN1 are electrically coupled to each other and to the drains of transistors 9TP2 and 9TN2 at node 9T1, and the gates of transistors 9TP2 and 9TN2 are electrically coupled to each other and to the drains of transistors 9TP1 and 9TN1 at node 9T2, whereby memory cell 400 is configured to interlock a first logic voltage level at node 9T1 with a second, complementary logic voltage level at node 9T2.

[0126] An n-type transistor 9TN4 is electrically coupled between node 9T1 and data line 9TWBL and has a gate that is communicatively coupled to the write signal line 9TWWL. The transistor 9TN4 is thus configured to electrically couple node 9T1 to data line 9TWBL in response to a high logic voltage level of a write signal (not labeled) on write signal line 9TWWL during a write operation.

[0127] An n-type transistor 9TNM3 and an n-type transistor 9TNM5 are electrically connected in series between node 9T2 and the reference node GND. One gate of transistor 9TNM3 is communicatively coupled to the write signal line 9TWWL, and one gate of transistor 9TNM5 is communicatively coupled to the data line 9TWBL. Transistors 9TNM3 and 9TNM5 are thus configured to electrically couple node 9T2 to the reference node GND in response to a high logic voltage level on the write signal line 9TWWL and a high logic voltage level on the data line 9TWBL.

[0128] With the configuration discussed above, memory cell 400 is configured to store complementary logical voltage levels at nodes 9T1 and 9T2 in a write operation.

[0129] An n-type transistor 9TNM1 and an n-type transistor 9TNM2 are electrically connected in series between the data line 9TRBL and the reference node GND. One gate of transistor 9TNM1 is communicatively coupled to the read signal line 9TRWL, and one gate of transistor 9TNM2 is communicatively coupled to node 9T2. Transistors 9TNM1 and 9TNM2 are thus configured to electrically couple the data line 9TRBL to the reference node GND in response to a high logic voltage level on the read signal line 9TRWL and a high logic voltage level at node 9T2.

[0130] In some embodiments, the memory cell 400 is part of a memory macro that includes a read amplifier, the data line 9TRBL is electrically coupled to the read amplifier, and the read amplifier is configured to determine a logical state of the memory cell 400 based on a voltage level on the data line 9TRBL in a read operation of the memory macro.

[0131] In some embodiments, the data line 9TRBL is pre-charged in a read operation to a pre-charge voltage level which is different from a ground reference voltage level of the ground reference voltage at reference node GND.

[0132] In a read operation where transistors 9TNM1 and 9TNM2 are both switched on, a current of 1400 flows between the data line 9TRBL and the reference node GND based on a potential difference between the voltage levels of the data line 9TRBL and the reference node GND and the on-state resistance values ​​of each of transistors 9TNM1 and 9TNM2.

[0133] The one-state resistance values ​​of transistors 9TNM1 and 9TNM2 vary with respect to a value of the high logic voltage level applied to the gates of transistors 9TNM1 and 9TNM2, and with respect to the physical properties caused by variations in the manufacturing process.

[0134] Through the configuration and use described above with reference to the memory circuits 100 and 200 and the Fig. As discussed in sections 1A-1C and 2, the 400 memory cell can offer the advantages mentioned above with reference to the 100 memory circuit and the Fig. 1A-1C were discussed.

[0135] Fig. Figure 5A is a diagram of an address decoding circuit 520A according to some embodiments. The address decoding circuit 520A can be used as a section of the address decoding circuit 120A or as the entire address decoding circuit 120A, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0136] The address decoding circuit 520A comprises inverters ASINV(0) and ASINV(1) and AND gates AND1, AND2, AND3, and AND4. The input terminals of inverters ASINV(0) and ASINV(1) are communicatively coupled to the control signal bus 125, and the output terminals of AND gates AND1, AND2, AND3, and AND4 are communicatively coupled to the R / W signal bus 115A, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0137] Inverter ASINV(0) is configured to receive the first bit AS(0) of an address signal at its input, and inverter ASINV(1) is configured to receive the second bit AS(1) of the address signal AS(0) at its input. Inverter ASINV(0) has one output connected to an input of AND gate AND1 and to an input of AND gate AND3. Inverter ASINV(1) has one output connected to an input of AND gate AND1 and to an input of AND gate AND2.

[0138] In addition to the connections to inverters ASINV(0) and ASINV(1), the AND gate AND1 has an output terminal connected to signal line 515A1. This configures the AND gate AND1 to receive an inverted address bit AS(0) and an inverted address bit AS(1) and to output a signal 515AS1 on signal line 515A1. Therefore, signal 515AS1 has a logic high level when both address bits AS(0) and AS(1) have a logic low level, and a logic low level otherwise.

[0139] In addition to the connection to inverter ASINV(1), AND gate AND2 has an input terminal configured to receive a first address bit AS(0) and an output terminal connected to signal line 515A2. This configures AND gate AND2 to receive address bit AS(0) and its inverted counterpart AS(1) and output a signal 515AS2 on signal line 515A2. Therefore, signal 515AS2 has a logic high level when address bit AS(0) has a logic high level and address bit AS(1) has a logic low level, and a logic low level otherwise.

[0140] In addition to the connection to inverter ASINV(0), the AND gate AND3 has an input terminal configured to receive a second address bit AS(1) and an output terminal connected to signal line 515A3. This configures the AND gate AND3 to receive an inverted address bit AS(0) and an inverted address bit AS(1) and to output a signal 515AS3 on signal line 515A3. Therefore, signal 515AS3 has a logic high level when address bit AS(0) has a logic low level, and address bit AS(1) has a logic high level and a logic low level otherwise.

[0141] The AND gate AND4 has one input configured to receive a first address bit AS(0), one input configured to receive a second address bit AS(1), and one output connected to a signal line 515A4. This configures the AND gate AND4 to receive address bits AS(0) and AS(1) and output a signal 515AS4 on signal line 515A4. Therefore, signal 515AS4 has a logic high level when both address bits AS(0) and AS(1) are logic high, and a logic low level otherwise.

[0142] In the Fig. In the embodiment shown in Figure 5A, the address decoding circuit 520A comprises two inverters, ASINV(0) and ASINV(1), and four AND gates, AND1 ... AND4, configured to receive two bits, AS(0) and AS(1), of the address signal, which has two bits. In some embodiments, the address decoding circuit 520A comprises at least one (not shown) inverter in addition to inverters ASINV(0) and ASINV(1) and at least one (not shown) AND gate in addition to AND gates AND1 ... AND4, and the address decoding circuit 520A is thereby configured to receive the address signal, which has a number of bits greater than two. In some embodiments, the address decoding circuit 520A is configured to receive the address signal, which has a number n bits, as shown below with reference to the decoding circuit 520B and Fig. 5C will be discussed.

[0143] With the configuration discussed above, the 520A address decoding circuit is able to output signals, for example, output signals 515AS1 ... 515AS4, which have logic levels corresponding to any possible combination of logic levels of address bits, for example, address bits AS(0) and AS(1). In some embodiments, the 520A address decoding circuit has a different configuration than the one described in Fig. The configuration shown in 5A allows the address decoding circuit 520A to output signals having logical levels corresponding to any possible combination of logical levels of address bits.

[0144] Through the configuration and use discussed above, the 520A decoding circuit can provide the advantages mentioned above with reference to the 100 memory circuit and the Fig. 1A-1C were discussed.

[0145] Fig. Figure 5B is a diagram of an address decoding circuit 520B according to some embodiments. The address decoding circuit 520B can be used as a section of the address decoding circuit 120B or as the entire address decoding circuit 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0146] In addition to the address decoding circuit 520B, it shows Fig. 5B a storage device 540, which can be used as a storage device 140, reference address lines 545RA1 and 545RA2, which can be used as a section of the reference address bus 145 or as the entire reference address bus 145, and a control signal bus 125, each of which is referred above to the storage circuit 100 and the Fig. 1A-1C were discussed.

[0147] The address decoding circuit 520B comprises a first section 520B1, which is communicatively coupled to the memory device 540 by reference address lines 545RA1, and a second section 520B2, which is communicatively coupled to the memory device 540 by reference address lines 545RA2. A non-restrictive example of the first section 520B1 is given below with reference to Fig. 5C discussed.

[0148] Reference address lines 545RA1 are configured to transmit first reference address information, corresponding to the first line of the set lines 110A, to the first section 520B1, and reference address lines 545RA2 are configured to transmit second reference address information, corresponding to the second line of the set lines 110A, to the second section 520B2.

[0149] The first section 520B1 is configured to generate a signal 515BS1 during operation based on a comparison of line address information in control signals 125S received from the control signal bus 125 with the first reference address information stored in the memory device 540 and received from reference address lines 545RA1, and to output this signal on a signal line 515B1. The second section 520B2 is configured to generate a signal 515BS2 during operation based on a comparison of line address information in control signals 125S received from the control signal bus 125 with the second reference address information stored in the memory device 540 and received from reference address lines 545RA2, and to output this signal on a signal line 515B2.

[0150] Each of the first section 520B1 and the second section 520B2 comprises several logic gates configured to receive control signals 125S and the reference address information at multiple input terminals. The multiple logic gates are configured to generate a corresponding signal 515BS1 or 515BS2 during operation, having a first logic level when the line address information in control signals 125S matches the reference address information, and a second logic level when the line address information in control signals 125S does not match the reference address information.

[0151] The address decoder 520B is thereby configured to generate signals 515BS1 and 515BS2 separately and output them on respective signal lines 515B1 and 515B2, with the output signals 515BS1 and 515BS2 being issued selectively in response to line address information, the respective lines of the set corresponding to lines 110A.

[0152] In the Fig. In the embodiment shown in Figure 5B, the address decoder 520B comprises two sections 520B1 and 520B2. In some embodiments, the address decoder 520B comprises at least one (not shown) section in addition to sections 520B1 and 520B2 and is thereby configured to generate at least one (not shown) signal separately in addition to signals 515BS1 and 515BS2 and to output it on at least one (not shown) signal line in addition to signal lines 515B1 and 515B2.

[0153] In various embodiments, sections 520B1 and 520B2 have the same or different configurations, such that the address decoder 520B is configured to generate and output signals 515BS1 and 515BS2 separately. In some embodiments, sections 520B1 and 520B2 jointly utilize a subset or all of their respective circuit elements, such that the address decoder 520B is a single circuit configured to generate and output signals 515BS1 and 515BS2 separately.

[0154] Fig. Figure 5C is a diagram of a non-restrictive example of the address decoding circuit 520B1 according to some embodiments. The address decoding circuit 520B1 comprises n NAND pairs NAND(0) ... NAND(n-1), n ​​inverter pairs INV(0) ... INV(n-1), and a logic tree 510. The input terminals of a first NAND of each NAND pair NAND(0) ... NAND(n-1) are connected to the input terminals of a corresponding inverter pair of the inverter pairs INV(0) ... INV(n-1), and the output terminals of the inverter pair are connected to the input terminals of the second NAND of the NAND pair. The output terminals of each NAND pair NAND(0) ... NAND(n-1) are connected to the logic tree 510, and one output terminal of the logic tree 510 is connected to the signal line 515B1.

[0155] A first input terminal of each NAND gate of NAND pairs NAND(0) ... NAND(n-1) is communicatively coupled to the control signal bus 125, and a second input terminal of each NAND gate of NAND pairs NAND(0) ... NAND(n-1) is communicatively coupled to reference address lines 545RA1. The output terminal 515B1 is communicatively coupled to the R / W signal line 115B, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0156] The number n corresponds to the number of bits in a row address. In some embodiments, the row address has a number of bits n in the range of 2 to 9. In some embodiments, the row address has a number of bits n in the range of 7 or 8. In some embodiments, the row address has a total number of bits greater than n, and n represents a fraction of the total number of bits in the row address.

[0157] The first NAND gate of each NAND pair NAND(0) ... NAND(n-1) is configured to receive a corresponding bit of a reference address RA(0) ... RA(n-1) at a first input and a corresponding bit of an address signal AS(0) ... AS(n-1) at a second input. The second NAND gate of each NAND pair NAND(0) ... NAND(n-1) is configured to receive the corresponding bit of the reference address RA(0) ... RA(n-1), inverted by the first inverter of the corresponding inverter pair INV(0) ... INV(n-1), at a first input and to receive the corresponding bit of the address signal AS(0) ... AS(n-1), inverted by the second inverter of the corresponding inverter pair INV(0) ... INV(n-1), at a second input.

[0158] Each NAND pair NAND(0) ... NAND(n-1) is thereby configured to output one logical high level and one logical low level when the corresponding reference address and address signal bits match, and to output two logical high levels when the corresponding reference address and address signal bits do not match.

[0159] The logic tree 510 comprises several NAND gates 510N arranged in layers and an inverter 510I. A first layer of NAND gates has input terminals configured to receive the logic levels output by NAND pairs NAND(0) ... NAND(n-1), and subsequent layers have input terminals connected to output terminals of previous layers, with a final NAND gate having an output terminal connected to an input terminal of the inverter 510I. The inverter 510I has an output terminal configured to output a signal 515B1S on the signal line 515B1.

[0160] Each level of NAND gates is configured to output logical levels based on input logical levels, characterized in that the 515B1S signal has a first logical level corresponding to the logical levels of NAND pairs NAND(0) ... NAND(n-1) corresponding to a match of all reference address and address signal bits, and has a second logical level corresponding to the logical levels of NAND pairs NAND(0) ... NAND(n-1) corresponding to a mismatch between one or more of the reference address and address signal bits.

[0161] In some embodiments, the first logic level is a high logic level, and the second logic level is a low logic level. In some embodiments, the first logic level is a low logic level, and the second logic level is a high logic level.

[0162] In the Fig. In the embodiment shown in Figure 5C, each logic gate of the NAND tree 510 is a NAND gate 510N. In some embodiments, the logic tree 510 comprises several (not shown) logic gate types.

[0163] Through the configuration and use discussed above, the 520B decoding circuit, comprising sections 520B1 and 520B2, can provide the advantages mentioned above with reference to the 100 memory circuit and the Fig. 1A-1C were discussed.

[0164] Fig. Figure 6 is a flowchart of a method 600 for reading data from a weak cell according to one or more embodiments. The method 600 can be used with a memory circuit, for example, the memory circuits 100, 200, 300, or 400, as described above, each with reference to the Fig. 1A-1C and 2-4 were discussed.

[0165] The order in which the operations of procedure 600 are performed in Fig. Figure 6 is for illustrative purposes only; the operations of procedure 600 can also be performed in sequences that differ from the one shown in Figure 600. Fig. The 6 shown differ. In some embodiments, operations are performed in addition to those shown. Fig. 6 shown before, between, during and / or after the in Fig. The operations shown in section 6 are performed. In some embodiments, the operations of method 600 are a subset of operations of a method for operating a memory circuit.

[0166] In some embodiments of Operation 610, address information corresponding to the address of a first row of a memory arrangement is stored in a memory device. The first row of the memory arrangement comprises the weak cell. Storing the address information includes storing information that can be used by an address decoding circuit to identify a row of the memory arrangement. In some embodiments, storing the address information in the memory device includes storing reference address information in the memory device 140, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0167] In some embodiments, storing the address information includes storing a line address. In some embodiments, storing the address information includes storing a portion of a line address. In some embodiments, storing the address information includes storing an index or other identifier corresponding to a line address.

[0168] Storing the address information includes storing the address information corresponding to a line that has been determined to be a weak line. In some embodiments, storing the address information includes storing the address information corresponding to a line that has been determined to be a weak line, in the manner described for operation 710 of method 700, as described below with reference to Fig. 7 will be discussed.

[0169] In some embodiments, storing the address information includes storing the address information corresponding to the first row of the memory arrangement based on a speed operation using the weak cell. In some embodiments, the first row of the memory arrangement is a row of a set of rows of the memory arrangement, the set of rows corresponds to a set of read operation speeds, which includes one or more slowest speeds, and storing the address information includes the weak cell, which has one or more of the slowest speeds.

[0170] In some embodiments, storing the address information includes storing the address information corresponding to a weak line identified using the control circuit 130 of the memory circuit 100, as described above with reference to the Fig. 1A-1C was discussed.

[0171] In Operation 620, an address signal is received by an address decoding circuit. Receiving the address signal includes receiving address signal information that can be used by the address decoding circuit to identify the first row of the memory arrangement. In some embodiments, receiving the address signal information includes receiving control signals 125S from the control signal bus 125 by the address decoding circuit 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0172] In some embodiments, receiving the address signal information includes receiving a first-line address. In some embodiments, receiving the address signal information includes receiving a portion of the first-line address. In some embodiments, receiving the address signal information includes receiving an index or other identifier corresponding to the first-line address.

[0173] In some embodiments of Operation 630, the address signal is compared with the address information stored in the memory device. Comparing the address signal with the address information stored in the memory device includes comparing the address signal information contained in the address signal with the stored address information.

[0174] In some embodiments, comparing the address signal information with the address information stored in the memory device includes comparing the address signal information with the stored address information using the address decoding circuit 120B, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, comparing the address signal information with the address information stored in the memory device involves comparing an address signal address with a stored address using the address decoding circuit 500, as discussed above with reference to Fig. 5 was discussed.

[0175] In some embodiments, comparing the address signal with the address information stored in the storage device includes determining that the first line address identified by the address signal information matches the first line address identified by the address information stored in the storage device.

[0176] In some embodiments of Operation 640, in response to the address signal containing address information corresponding to the first row address, a data bit is written to the weak cell in the first row of the memory arrangement by programming the weak cell to a first logical state, and a matching data bit is written to a cell in a second row of the memory arrangement by programming the cell in the second row of the memory arrangement to the first logical state.

[0177] In some embodiments, programming the weak cell and the cell in the second row of the memory arrangement to the first logical state includes storing a first logical voltage level in the weak cell and a second logical voltage level in the cell in the second row of the memory arrangement, wherein the first logical voltage level is the same logical voltage level as the second logical voltage level.

[0178] In some embodiments, programming the weak cell and programming the cell in the second row of the memory array are performed simultaneously. In some embodiments, programming the weak cell and programming the cell in the second row of the memory array involves transferring data to both the weak cell and the cell in the second row of the memory array using the same data line. In some embodiments, programming the weak cell and programming the cell in the second row of the memory array are performed as part of a single write operation of the memory array.

[0179] In some embodiments, programming the weak cell comprises programming a memory cell 112 in a row 120A, and programming the cell in the second row of the memory arrangement comprises programming a memory cell 112 in a row 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, both the programming of the weak cell and the programming of the cell in the second row of the memory arrangement involve programming one of the cells 210A, 210B, 210C or 210D, as above with reference to the memory circuit 200 and Fig. 2 was discussed. In some embodiments, both programming the weak cell and programming the cell in the second row of the memory arrangement involve programming a memory cell 300, as discussed above with reference to Fig. 3 was discussed. In some embodiments, both programming the weak cell and programming the cell in the second row of the memory arrangement involve programming a memory cell 400, as discussed above with reference to Fig. 4 was discussed.

[0180] In some embodiments, programming the weak cell includes generating a first write signal using a first address decoding circuit and receiving the first write signal through the first row of the memory arrangement, and programming the cell in the second row of the memory arrangement includes generating a second write signal using a second address decoding circuit and receiving the second write signal through the second row of the memory arrangement.

[0181] In some embodiments, generating the first write signal includes generating a read / write signal 115S using the first address decoding circuit 120A, and generating the second write signal includes generating a read / write signal 115S using the second address decoding circuit 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0182] In some embodiments of Operation 650, in response to the fact that the address signal includes address information corresponding to the first line address, a first read signal is generated by a first address decoding circuit, and a second read signal is generated by a second address decoding circuit.

[0183] In some embodiments, generating the first read signal includes generating a read / write signal 115S using the first address decoding circuit 120A, and generating the second read signal includes generating a read / write signal 115S using the second address decoding circuit 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0184] In operation 660, in response to the fact that the address signal contains address information corresponding to the first row address, the data bit is read from the weak cell, and the matching data bit is simultaneously read from the cell in the second row of the memory arrangement.

[0185] In some embodiments, reading the data bit from the weak cell involves using the weak cell to electrically couple the data line to a first node carrying a bias level, and reading the matching data bit from the cell in the second row involves using the cell in the second row to electrically couple the data line to a second node carrying the bias level. In some embodiments, responding to the address signal, which includes address information corresponding to the first row address, is based on comparing the address signal information with the reference address information stored in the memory device.

[0186] The use of the weak cell to couple the data line to the first node and the use of the cell in the second row to couple the data line to the second node are executed simultaneously. In some embodiments, the use of the weak cell to couple the data line to the first node and the use of the cell in the second row to couple the data line to the second node are performed as part of a single read operation of the memory arrangement.

[0187] In some embodiments, using the weak cell includes using a memory cell 112 in a row 120A, and using the cell in the second row includes using a memory cell 112 in a row 120B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, both the use of the weak cell and the use of the cell in the second row involve the use of one of the cells 210A, 210B, 210C or 210D, as above with reference to the memory circuit 200 and Fig. 2 was discussed. In some embodiments, both the use of the weak cell and the use of the cell in the second row involve the use of a memory cell 300, as above with reference to Fig. 3 was discussed. In some embodiments, both the use of the weak cell and the use of the cell in the second row involve the use of a memory cell 400, as above with reference to Fig. 4 was discussed.

[0188] In some embodiments, the electrical coupling of the data line to the first node and the electrical coupling of the data line to the second node comprise the electrical coupling of a data line 114, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, the electrical coupling of the data line to the first node and the electrical coupling of the data line to the second node includes the electrical coupling of a data line RBL1 or RBL2, as above with reference to the memory circuit 200 and Fig. 2 was discussed. In some embodiments, this includes electrically coupling the data line to the first node and electrically coupling the data line to the second node, the electrical coupling of the data line 8TRBL, as above with reference to Fig. 3 was discussed. In some embodiments, the electrical coupling of the data line to the first node and the electrical coupling of the data line to the second node comprise the electrical coupling of the data line 9TRBL, as above with reference to Fig. 4 was discussed.

[0189] In some embodiments, the bias level is a ground reference level of the memory arrangement, and both using the weak cell and using the second-row cell involve discharging the data line toward the ground reference level. In some embodiments, both using the weak cell and using the second-row cell involve discharging the data line, which has a pre-charge voltage level based on pre-charging the data line as part of a read operation.

[0190] In some embodiments, using the weak cell includes the weak cell receiving the first read signal from the first address decoding circuit, and using the cell in the second row includes the cell in the second row receiving the second read signal from the second address decoding circuit. In some embodiments, receiving the first read signal from the first address decoding circuit includes receiving a read / write signal 115S from the address decoding circuit 120A, and receiving the second read signal from the second address decoding circuit includes receiving a read / write signal 115S from the address decoding circuit 120B, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0191] In some embodiments, receiving the first read signal includes receiving a read / write signal 115S from the R / W signal bus 115A, and receiving the second read signal includes receiving a read / write signal 115S from the R / W signal bus 115B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, receiving the first read signal comprises receiving one of the read signal RWL1S on the read signal line RWL1 and the read signal RWL2S on the read signal line RWL2, and receiving the second read signal comprises receiving the other of the read signal RWL1S on the read signal line RWL1 and the read signal RWL2S on the read signal line RWL2, as discussed above with reference to the memory circuit 200 and Fig. 2 was discussed. In some embodiments, both receiving the first read signal and receiving the second read signal include receiving the read signal on the read signal line 8TRWL, as above with reference to Fig. 3 was discussed. In some embodiments, both receiving the first read signal and receiving the second read signal include receiving the read signal on the read signal line 9TRWL, as above with reference to Fig. 4 was discussed.

[0192] In some embodiments, the use of the weak cell for electrically coupling the data line to the first node is furthermore carried out in response to the first logical voltage level stored in the weak cell, and the use of the cell in the second row for electrically coupling the data line to the second node is furthermore carried out in response to the second logical voltage level stored in the cell in the second row.

[0193] By performing the operations of procedure 600, a data bit is read from a weak cell, and a matching data bit is simultaneously read from a cell in a second row to increase the speed of read operations in one or more rows of a memory arrangement, thereby obtaining the advantages mentioned above with reference to memory circuit 100 and the Fig. 1A-1C were discussed.

[0194] Fig. Figure 7 is a flowchart of a method 700 for configuring a memory circuit according to one or more embodiments. The method 700 can be used with a memory circuit, for example the memory circuit 100, as described above with reference to the Fig. 1A-1C was discussed. In some embodiments, some or all of the operations of method 700 are performed using a test circuit, for example, the test circuit 132, which was discussed above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0195] The order in which the operations of procedure 700 are performed in Fig. Figure 7 is for illustrative purposes only; the operations of procedure 700 can also be performed in sequences that differ from the one shown in Figure 700. Fig. The 7 shown differ. In some embodiments, operations are performed in addition to those shown. Fig. 7 shown before, between, during and / or after the in Fig. The 7 operations shown were performed.

[0196] In some embodiments, the operations of Method 700 are a subset of operations of a method for configuring a memory circuit. In some embodiments, some or all of the operations of Method 700 are performed as part of an initial setup of the memory circuit before normal operation of the memory circuit. In some embodiments, some or all of the operations of Method 700 are performed as part of a maintenance process after a period of normal operation of the memory circuit.

[0197] Operation 710 identifies a weak row of cells in the memory circuit. Identifying the weak row is based on the speed of a test read operation in that weak row, which meets a first speed criterion.

[0198] In some embodiments, the test read operation is a first test read operation from several test read operations, and identifying the weak line comprises performing the several test read operations in several lines of a memory arrangement of the memory circuit, the several lines containing the weak line. In some embodiments, performing the several test read operations comprises performing the several test read operations in the set of lines 110A of the memory arrangement 110, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0199] In some embodiments, performing the multiple test read operations includes measuring one or more execution speeds of the multiple test read operations. In some embodiments, performing the multiple test read operations includes detecting one or more write or read errors.

[0200] In some embodiments, performing the multiple test read operations involves varying an operating frequency of the memory circuit. In some embodiments, the operating frequency is an operating frequency of a system of which the memory circuit is a part. In some embodiments, performing the multiple test read operations involves varying the operating frequency FRQ, as above with reference to memory circuit 100 and the Fig. 1A-1C was discussed.

[0201] In some embodiments, performing the multiple test read operations involves varying the value of an operating voltage. In some embodiments, the operating voltage is the operating voltage of a system of which the memory circuit is a part. In some embodiments, performing the multiple test read operations involves varying the minimum operating voltage VCCMIN, as described above with reference to memory circuit 100 and the Fig. 1A-1C was discussed.

[0202] In some embodiments, the execution of the multiple test read operations is performed by a built-in test circuit of the memory circuit. In some embodiments, the execution of the multiple test read operations is performed by the test circuit 132, as described above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0203] In various embodiments, the execution of the multiple test read operations is performed by a circuit outside the memory circuit, a combination of circuits inside and outside the memory circuit, or in response to a user of the memory circuit.

[0204] In various embodiments, identifying the weak line involves identifying a statistical distribution of multiple speeds corresponding to the multiple test read operations. Non-restrictive examples of statistical distributions include a Gaussian distribution or a statistical distribution represented by a curve N, as above with reference to memory circuit 100 and the Fig. 1A-1C was discussed.

[0205] In some embodiments, identifying the weak line involves identifying one or more of the slowest speeds from among several speeds corresponding to the multiple test read operations. In some embodiments, identifying the weak line based on the speed of the corresponding first test read operation from among the multiple test read operations that satisfies the first speed criterion, namely that the speed of the corresponding first test read operation is one of the one or more slowest speeds.

[0206] In Operation 720, address information corresponding to a weak line address is stored in a memory device of the memory circuit. The storage of the address information is performed in the manner described for Operation 610 of Procedure 600, as above with reference to Fig. 6 was discussed.

[0207] In operation 730, during subsequent read operations in the weak row, data is read simultaneously from the weak row and from a second row of cells of the memory circuit based on the stored address information.

[0208] In some embodiments, reading data from the weak line includes reading data from one line of the set lines 110A, and reading data from the second line includes reading data from one line of the set lines 110B, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0209] In some embodiments, the simultaneous reading of data from the weak row and from the second row is part of configuring the second row of the memory circuit such that it is activated during subsequent read operations and during subsequent write operations.

[0210] In some embodiments, operation 740 determines a value for the operating frequency of the memory circuit and / or a value for the operating voltage of the memory circuit based on the simultaneous reading of data from the weak line and from the second line during the subsequent read operations in the weak line.

[0211] In some embodiments, determining the value of the operating frequency includes determining a value of the operating frequency FRQ, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, determining the operating voltage value includes determining a minimum operating voltage value VCCMIN, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed.

[0212] In some embodiments, the determination of the value includes determining a first value before the second line is activated so that it can be read simultaneously with the weak line, and determining a second value after the second line has been activated so that it can be read simultaneously with the weak line.

[0213] In some embodiments, determining the value involves varying one or both of the operating frequency and the operating voltage while performing multiple test read operations in the rows of cells of the memory circuit.

[0214] In some embodiments, operation 750 repeats some or all of operations 710, 720, 730 or 740 to allow one or more additional rows be read during subsequent read operations in one or more rows of cells of the memory circuit in addition to the weak row.

[0215] In some embodiments, Operation 760 involves feeding the value of the operating frequency of the memory circuit and / or the value of the operating voltage of the memory circuit, which were determined in Operation 740, into the memory circuit.

[0216] In some embodiments, the input of the operating frequency value includes the input of an operating frequency value FRQ, as above with reference to the memory circuit 100 and the Fig. 1A-1C was discussed. In some embodiments, supplying the value of the operating voltage includes supplying a value of the minimum operating voltage VCCMIN, as above with reference to the storage circuit 100 and the Fig. 1A-1C was discussed.

[0217] In some embodiments of Operation 770, the memory circuit is operated with one or both of the values ​​of the operating frequency and the operating voltage of the memory circuit, which were determined in Operation 740 and applied to the memory circuit. Operating the memory circuit includes operating the memory circuit while the second line is activated so that it can be read simultaneously with the weak line during subsequent read operations on the weak line.

[0218] Performing the operations of Procedure 700 to configure a memory circuit enables a higher operating speed and / or a reduced operating voltage of a memory circuit compared to a memory circuit that has not been configured by performing the operations of Procedure 700. As above with reference to Memory Circuit 100 and the Fig. As discussed in 1A-1C, a higher operating frequency improves the performance of the storage circuit and its compatibility with other circuits, and a reduced operating voltage reduces energy consumption and power-related heat generation.

[0219] In some embodiments, a circuit comprises a data line, a first cell in a first row of a memory arrangement, wherein the first cell is electrically coupled to the data line, and a second cell in a second row of the memory arrangement, wherein the second cell is electrically coupled to the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first-row read operation. In some embodiments, the circuit is configured to identify the first row of the memory arrangement as a weak row of the memory arrangement. In some embodiments, the memory includes a self-test circuit configured to identify the first row of the memory arrangement as the weak row based on the speed of a test read operation using the first row.In some embodiments, the self-test circuit is configured to cause address information corresponding to a first-row address to be stored in a memory device. In some embodiments, the circuit is configured to transfer the data by biasing the data line to a first voltage level using both the first and second cells simultaneously. In some embodiments, the first cell comprises a first transistor configured to electrically couple the data line to a first node in response to a first read signal, the second cell comprises a second transistor configured to electrically couple the data line to a second node in response to a second read signal, and both the first and second nodes have the first voltage level.In some embodiments, the first voltage level is a ground reference level of the memory arrangement, and both the first and second nodes are ground nodes configured to carry the ground reference level. In some embodiments, a first address decoding circuit is configured to generate the first read signal in response to an address signal corresponding to a first-row address, and a second address decoding circuit is configured to generate the second read signal by comparing the address signal with address information stored in a memory device, wherein the address information corresponds to the first-row address.

[0220] In some embodiments, a method for reading data from a weak cell comprises receiving an address signal containing address information corresponding to the address of a first row of a memory arrangement, the first row of the memory arrangement comprising the weak cell, and, in response to receiving the address signal, reading a data bit from the weak cell and simultaneously reading a matching data bit from a cell in a second row of the memory arrangement. In some embodiments, reading the data bit from the weak cell comprises electrically coupling a data line to a first node carrying a bias level, and simultaneously reading the matching data bit from the cell in the second row of the memory arrangement comprises electrically coupling the data line to a second node carrying the bias level.In some embodiments, the bias level is a ground reference level of the memory arrangement, and both the electrical coupling of the data line to the first node and the electrical coupling of the data line to the second node involve discharging the data line toward the ground reference level. In some embodiments, reading the data bit from the weak cell involves the weak cell receiving a first read signal from a first address decoding circuit, and simultaneously reading the matching data bit from the cell in the second row of the memory arrangement involves the cell in the second row of the memory arrangement receiving a second read signal from a second address decoding circuit.In some embodiments, the data bit corresponds to a first logical voltage level stored in the weak cell, wherein the matching data bit corresponds to a second logical voltage level stored in the second cell, and the method further comprises programming the weak cell and the cell in the second row of the memory arrangement such that the first logical voltage level is the same as the second logical voltage level. In some embodiments, the simultaneous reading of the matching data bits from the cell in the second row of the memory arrangement comprises comparing the address signal with address information stored in a memory device, wherein the address information corresponds to an address of the first row of the memory arrangement.In some embodiments, the method includes storing the address information in the storage device based on the speed of a read operation using the first line.

[0221] In some embodiments, a method for configuring a memory circuit comprises identifying a weak row of cells of the memory circuit based on the speed of a test read operation in the weak row that satisfies a first speed criterion, storing address information corresponding to an address of the weak row in a storage device, and, during subsequent read operations in the weak row, simultaneously reading data from the weak row and from a second row of cells of the memory circuit based on the stored address information.In some embodiments, the test read operation is a first test read operation among several test read operations, and identifying the weak line involves performing the multiple test read operations in multiple rows of cells of the memory circuit, the multiple rows containing the weak line, and identifying the speed of the first test read operation among the multiple test read operations as one of the slowest speeds of the performed multiple test read operations. In some embodiments, identifying the weak line involves detecting a read error in the test read operation in the weak line. In some embodiments, identifying the weak line involves varying an operating frequency and / or an operating voltage of the memory circuit.In some embodiments, the method includes determining a value of an operating voltage of the memory circuit based on the simultaneous reading of data from the weak line and from the second line during the subsequent read operations in the weak line.

Claims

[1] Circuit (100, 200) comprising the following: a data line (114, RBL1, RBL2); a first cell (112, 210A, 210B) identified as a weak cell in a first row (200R1) of a memory arrangement (110), wherein the first cell (112, 210A, 210B) is electrically coupled to the data line (114, RBL1, RBL2); and a second cell (112, 210C, 210D) in a second row (200R2) of the memory arrangement (110), wherein the second cell (112, 210C, 210D) is electrically coupled to the data line (114, RBL1, RBL2), wherein the circuit (100, 200) is configured to transfer data from the first cell (112, 210A, 210B) and the second cell (112, 210C, 210D) to the data line (114, RBL1, RBL2) simultaneously in a first first row (200R1) read operation in response to a received address signal (AS) containing address information corresponding to a first row address (200R1) of the memory arrangement (110). [2] Circuit (100, 200) according to claim 1, wherein the circuit (100, 200) is configured to identify the first row (200R1) of the memory arrangement (110) as a weak row of the memory arrangement (110). [3] Circuit (100, 200) according to claim 2, further comprising a self-test circuit configured to identify the first row (200R1) of the memory arrangement (110) as the weak row of the memory arrangement (110) based on the speed of a test read operation using the first row (200R1). [4] Circuit (100, 200) according to claim 3, wherein the self-test circuit is configured to cause address information corresponding to the address of the first line (200R1) to be stored in a storage device (140, 540). [5] Circuit (100, 200) according to any of the preceding claims, wherein the circuit (100, 200) is configured to transfer the data by biasing the data line (114, RBL1, RBL2) to a first voltage level using both the first cell (112, 210A, 210B) and the second cell (112, 210C, 210D) simultaneously. [6] Circuit (100, 200) according to claim 5, wherein the first cell (112, 210A, 210B) includes a first transistor (212) configured to electrically couple the data line (114, RBL1, RBL2) to a first node (214) in response to a first read signal (RWL1S), the second cell (112, 210C, 210D) includes a second transistor (212) configured to electrically couple the data line (114, RBL1, RBL2) to a second node (214) in response to a second read signal (RWL2S), and both the first node (214) and the second node (214) have the first voltage level. [7] Circuit (100, 200) according to claim 6, wherein the first voltage level is an earth reference level of the storage arrangement (110), and Both the first node (214) and the second node (214) are earthing nodes configured to carry the earth reference level. [8] Circuit (100, 200) according to claim 6 or 7, further comprising: a first address decoding circuit (120A) configured to generate the first read signal (RWL1S) in response to the address signal (AS) corresponding to a first-row address (200R1); and a second address decoding circuit (120B) configured to generate the second read signal (RWL2S) by comparing the address signal (AS) with address information stored in a memory device (140, 540), the address information being the address of the first line (200R1). [9] Method (600, 700) for reading data from a cell (112, 210A, 210B) identified as a weak cell, wherein the method (600, 700) comprises: Receiving an address signal (AS); and in response to the fact that the address signal (AS) includes address information corresponding to the address of a first row (200R1) of a memory arrangement (110), wherein the first row (200R1) of the memory arrangement (110) includes the weak cell (112, 210A, 210B): Reading a data bit from the weak cell (112, 210A, 210B); and Simultaneous reading of a matching data bit from one cell (112, 210C, 210D) in a second row (200R2) of the memory arrangement (110). [10] Method (600, 700) according to claim 9, wherein The reading of the data bit from the weak cell (112, 210A, 210B) includes the electrical coupling of a data line (114, RBL1, RBL2) with a first node (214) carrying a bias level, and the simultaneous reading of the matching data bit from the cell (112, 210C, 210D) in the second row (200R2) of the memory arrangement (110) includes the electrical coupling of the data line (114, RBL1, RBL2) with a second node (214) that carries the bias level. [11] Method (600, 700) according to claim 10, wherein the bias level is an earth reference level of the storage arrangement (110), and both the electrical coupling of the data line (114, RBL1, RBL2) to the first node (214) and the electrical coupling of the data line (114, RBL1, RBL2) to the second node (214) comprise the discharge of the data line (114, RBL1, RBL2) towards the earth reference level. [12] Method (600, 700) according to one of claims 9 to 11, wherein Reading the data bit from the weak cell (112, 210A, 210B) includes the weak cell (112, 210A, 210B) receiving a first read signal (RWL1S) from a first address decoding circuit (120A), and the simultaneous reading of the matching data bit from the cell (112, 210C, 210D) in the second row (200R2) of the memory arrangement (110) includes the cell (112, 210C, 210D) in the second row (200R2) of the memory arrangement (110) receiving a second read signal (RWL2S) from a second address decoding circuit (120B). [13] Method (600, 700) according to any one of claims 9 to 12, wherein the data bit corresponds to a first logical voltage level stored in the first cell (112, 210A, 210B), the matching data bit corresponds to a second logical voltage level stored in the second cell (112, 210C, 210D), and the method (600, 700) further comprises programming the weak cell (112, 210A, 210B) and the cell (112, 210C, 210D) in the second row (200R2) of the memory arrangement (110) such that the first logical voltage level is the same logical voltage level as the second logical voltage level. [14] Method (600, 700) according to any one of claims 9 to 13, wherein the simultaneous reading of the matching data bit from the cell (112, 210C, 210D) in the second row (200R2) of the memory arrangement (110) comprises comparing the address signal (AS) with address information stored in a memory device (140, 540), wherein the address information corresponds to the address of the first row (200R1). [15] Method (600, 700) according to claim 14, which further comprises storing the address information in the storage device (140, 540) based on a speed of a read operation using the first line (200R1). [16] Method (600, 700) for configuring a memory circuit (100, 200), wherein the method (600, 700) comprises: Identifying a weak row (200R1) of cells of the memory circuit (100, 200) based on a speed of a test read operation of the weak row (200R1) that satisfies a first speed criterion; Storing address information corresponding to a weak line address (200R1) in a storage device (140, 540); and during subsequent read operations of the weak line (200R1), simultaneous reading of data from the weak line (200R1) and from a second line (200R2) of cells of the memory circuit (100, 200) based on the stored address information, wherein the simultaneous reading occurs in response to a received address signal (AS) containing address information corresponding to the address of the weak line (200R1). [17] Method (600, 700) according to claim 16, wherein The test read operation is a first test read operation from several test read operations, and Identifying the weak line includes the following: Performing multiple test read operations in multiple rows (110A, 110B, 200R1, 200R2) of cells of the memory circuit (100, 200), wherein the multiple rows (110A, 110B, 200R1, 200R2) include the weak row (200R1); and Identifying the speed of the first test read operation of the multiple read operations as one of the slowest speeds of the multiple test read operations performed. [18] Method (600, 700) according to claim 16 or 17, wherein identifying the weak line (200R1) comprises detecting a read error in the test read operation of the weak line (200R1). [19] Method (600, 700) according to any one of claims 16 to 18, wherein identifying the weak line (200R1) comprises varying an operating frequency of the memory circuit (100, 200) and / or an operating voltage of the memory circuit (100, 200). [20] Method (600, 700) according to one of claims 16 to 19, which further comprises determining a value of an operating voltage of the memory circuit (100, 200) on the basis of simultaneously reading the data from the weak line (200R1) and from the second line (200R2) during the subsequent read operations of the weak line (200R1).

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