Digital register component and analog-to-digital converter, detecting signal distortion in high-radiation environments

Abstract

Device (100) detecting signal distortion in high-radiation environments, the device (100) comprising: a signal input terminal (1101) receiving a digital signal; and a digital single-event transient detection unit (110) (DSET detection unit), detecting whether information of the digital signal input through the signal input terminal (1101) is / becomes distorted, wherein the DSET detection unit (110) comprises a first output terminal (1125) through which a first detection signal is / is output, wherein the first detection signal is / is used to determine whether at least one of the rising edge time information and the falling edge time information of the digital signal is / is distorted, wherein the DSET detection unit (110) further includes a second output terminal (1145) through which a second detection signal is / is output, wherein the first detection signal is / is used to determine whether the falling edge timing information of the digital signal is / is distorted, and the second detection signal is / is used to determine whether the rising edge timing information of the digital signal is / is distorted, the DSET detection unit (110) comprises: a first DSET detection section (112), comprising a first transistor (1121), a second transistor (1122) and a capacitor (1126; 1146); and a second DSET detection section (114), comprising a third transistor (1141), a fourth transistor (1142) and a capacitor (1126; 1146), wherein the first DSET detection section (112) outputs the first detection signal through the first output terminal (1125), and the second DSET detection section (114) outputs the second detection signal through the second output terminal (1145).

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Korean patent application No. 10-2017-0075146, filed on June 14, 2017, with the Korean Intellectual Property Office.

[0002] This work was partially supported by the Basic Research Program of the National Research Foundation of Korea, funded by the Ministry of Science and ICT (2016 M2 A8 A1952801, 2016 M2 A9 A02945226), and the Korean Health Technology Research and Development Project of the Korea Health Industry Development Institute (KHIDI), funded by the Ministry of Health and Welfare of the Republic of Korea (HI17C0654). BACKGROUND1. AREA

[0003] The present disclosure relates to an apparatus and an analog-to-digital converter, and more particularly to a flip-flop and an analog-to-digital converter capable of detecting signal distortion in high radiation environments. 2. DESCRIPTION OF THE RELATED ART

[0004] In the defense industry or in high-radiation environments, such as those around nuclear reactors or accelerators, in space, or in areas fatal as a result of nuclear accidents, circuits with increased radiation resistance are used for increased accuracy and reliability. In particular, analog-to-digital converter circuits are necessary for converting analog signals into digital signals and for performing additional processing operations, which is why the radiation resistance of such analog-to-digital converter circuits is important.Over the years, circuit techniques aimed at increasing the radiation resistance of analog-to-digital converter circuits have been developed. A typical example of such a circuit technique is a redundancy technique in which a circuit section with a key function is designed as a plurality of pairs for comparing signals and selecting a correct, radiation-unaffected signal. For example, B. Olson applied a redundancy technique known as triple modular redundancy (TMR) to a comparator of a pipeline-type flip-flop circuit. Additionally, dual signal transmission paths have been designed in a digital-to-analog converter circuit or digital-to-analog converter circuit included in an analog-to-digital converter circuit to increase radiation resistance.In addition, algorithms for designing memories have been designed in a dual manner for system-level detection and correction of errors in high-radiation environments.

[0005] However, because such prior art techniques essentially employ a redundancy approach, the number of devices such as transistors, capacitors, or resistors increases, thereby increasing the area occupied by such devices in an integrated circuit. Additionally, parasitic capacitors and resistors increase, reducing the speed and overall performance of a circuit. The lost area and performance is unacceptable due to the demands for significantly increased speed, resolution, and power consumption characteristics during the design stage. Such design goals can be achieved due to increasingly advanced lithography techniques for short-channel transistors. However, since smaller devices consume less power, smaller circuits are inevitably vulnerable to ionizing radiation.Therefore, a considerable amount of research has been directed toward developing improved radiation resistance circuitry that has improved processes that overcome such difficulties of existing radiation-resistant circuitry.

[0006] Fig. Figure 1 is a schematic diagram illustrating registers and a logic stage of a digital circuit unit. Single-event transients (SETs) and single-event upsets (SEUs) refer to phenomena in which signal transmission and stored information are contaminated by external radiation and are considered key factors in the design of radiation-hardened circuits. Specifically, SETs are classified as digital SETs (DSETs) and analog SETs (ASETs) according to the position of a circuit at which radiation impinges. In general, SETs are more difficult to correct than SEUs, in which digital bits are simply altered.

[0007] Further examples of radiation-hardened flip-flop designs and error detection mechanisms that may be suitable for use in radiation-hardened analog-to-digital converters can be found in KWON, Inyong; SUNG, Seung Hwan. Radiation Hardening and Verification Procedure for Compact Flip-Flop Design. In: Transactions of the Korean Nuclear Society Autumn Meeting, 2016, KWON, Inyong, et al. Razorlite: A light-weight register for error detection by observing virtual supply rails. In: IEEE Journal of Solid-State Circuits, 2014, 49th year, no. 9, pp. 2054-2066. ISSN 0018-9200, US 2006 / 0005 091 A1 and DIGGINS, ZJ, et al. Scalability of capacitive hardening for flip-flops in advanced technology nodes. In: IEEE Transactions on Nuclear Science, 2013, Vol. 60, No. 6, pp. 4394-4398. - ISSN 0018-9499. Further examples of analog-to-digital converters are known, for example, from US Pat. No. 9,847,790 B2. [Related document]

[0008] (Patent Document 1) Japanese Patent No. 5354669 OVERVIEW

[0009] Aspects of the present disclosure may provide a flip-flop and an analog-to-digital converter capable of individually detecting digital single event transients (DSETs), analog single event transients (ASETs), and single event upsets (SEUs) and correcting corresponding data.

[0010] In particular, aspects of the present disclosure may provide a flip-flop and an analog-to-digital converter applicable to a digital circuit requiring a flip-flop (e.g., an analog-to-digital converter circuit such as a successive approximation register analog-to-digital converter (SAR ADC)) for detecting radiation-induced changes in signals and information and for restoring or regenerating a corresponding digital code by using a rollback system.

[0011] According to one aspect of the present disclosure, an input stage of a flip-flop detects signal distortion in high-radiation environments. The component may include: a signal input terminal receiving a digital signal; and a digital single event (DSET) detection unit detecting whether information of the digital signal input through the signal input terminal is distorted. The DSET detection unit may include a first output terminal through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted.

[0012] The DSET detection unit further includes a second output terminal through which a second detection signal is output, wherein the first detection signal can be used to determine whether the falling edge timing information of the digital signal is distorted, and the second detection signal can be used to determine whether the rising edge timing information of the detection signal is distorted.

[0013] The DSET detection unit further includes: a first DSET detection section including a first transistor and a second transistor, and a second DSET detection section including a third transistor and a fourth transistor, wherein the first DSET detection section can output the first signal through the first output terminal, and the second DSET detection section can output the second detection signal through the second output terminal

[0014] In a further embodiment, the component may include a signal distortion determining unit that determines, based on changes in the first detection signal or the second detection signal, whether at least one of the rising edge timing information and the falling edge timing information of the detection signal is / becomes distorted.

[0015] In another embodiment, the component may further include a rollback instruction unit that instructs regeneration of the digital signal according to results of the determination performed by the signal distortion determination unit.

[0016] In a further embodiment, the first transistor and the second transistor may be P-type field-effect transistors; the third transistor and the fourth transistor may be N-type field-effect transistors; the digital signal may be input to gates of the second and third transistors; a clock signal may be input to a gate of the first transistor; and an inverse of the clock signal may be input to a gate of the fourth transistor.

[0017] In another embodiment, the first output terminal may be connected to a drain of the first transistor and a source of the second transistor, and the first detection signal may have a high level as a default value.

[0018] In a further embodiment, the capacitor or capacitance may be added to a drain of the first transistor and a source of the second transistor in view of a large amount of charge induced by high-energy radiation.

[0019] In another embodiment, the second output terminal may be connected to a source of the third transistor and a drain of the fourth transistor, and the second detection signal may have a low level as a default value.

[0020] In another embodiment, the capacitor may be added to a source of the third transistor and a drain of the fourth transistor in view of a large amount of charge induced by high-energy radiation.

[0021] According to another aspect of the present disclosure, a flip-flop detects signal distortion in high-radiation environments. The component may include: a signal input terminal receiving a digital signal; and a single-event upset detection unit (SEU) detecting unit detecting whether information of the digital signal input through the signal input terminal is / becomes distorted, wherein the SEU detection unit includes a logic gate and capacitors.

[0022] The SEU detection unit further includes an inverter loop, wherein the logic gate can receive both end signals of the inverter loop through a first input terminal and a second input terminal, respectively.

[0023] The inverter loop includes a first inverter or non-gate or complement gate and a second inverter or non-gate or complement gate, wherein the first input terminal of the logic gate is connected to an input terminal of the first inverter and to an output terminal of the second inverter, and the second input terminal of the logic gate is connected to an output terminal of the first inverter and to an input terminal of the second inverter.

[0024] In a further embodiment, the SEU detection unit may further include two capacitors on the inverter loop which inhibit or prevent the flipping or changing of logic values.

[0025] In another embodiment, the component may further include: a signal distortion determining unit that determines whether signal distortion is caused by radiation based on a detection signal output from the logic gate; and a rollback instructing unit that instructs regeneration of the digital signal according to the determination made by the signal distortion determining unit.

[0026] According to another aspect of the present disclosure, an analog-to-digital converter detects signal distortion in high-radiation environments. The analog-to-digital converter may include: a first digital-to-analog converter section; a second digital-to-analog converter section; and an analog single-event transient (ASET) detection unit receiving output signals of the first and second digital-to-analog converter sections as a first input signal and a second input signal, respectively, wherein the ASET detection unit compares the first and second input signals with a preset reference signal.

[0027] In one embodiment, the ASET detection unit may include: a first comparator outputting a first output signal by comparing the first input signal with the reference signal; and a second comparator outputting a second output signal by comparing the second input signal with the reference signal.

[0028] In another embodiment, the analog-to-digital converter may further include: a signal distortion determining unit comparing the first output signal with the second output signal to determine whether signal distortion is caused by radiation; and a rollback instructing unit instructing regeneration of a digital signal according to results of the determination performed by the signal distortion determining unit.

[0029] In another embodiment, the analog-to-digital converter may further include a successive approximation register (SAR) logic unit, wherein the SAR logic unit may detect whether a digital signal information input to the SAR logic unit is / becomes distorted by a DSET or SEU. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The foregoing and other aspects, features and further advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. Figure 1 is a schematic view illustrating a register and a logic stage of a digital circuit unit; Fig. 2 is a block diagram illustrating an apparatus that detects signal distortion in high radiation environments according to an embodiment of the present disclosure; Fig. 3 is a circuit diagram illustrating a conventional D flip-flop of the related art; Fig. 4 is a circuit diagram illustrating a circuit including a digital single-effect transient (DSET) detection unit of the flip-flop for detecting signal distortion in high radiation environments, according to an embodiment of the present disclosure; Fig. 5 is a simulation graph illustrating detection of DSETs using the flip-flop for detecting signal distortion in high radiation environments, according to an embodiment of the present disclosure; Fig. 6 is a block diagram illustrating an apparatus that detects signal distortion in high radiation environments according to another embodiment of the present disclosure; Fig. 7 is a block diagram illustrating a flip-flop that detects signal distortion in high radiation environments, according to another embodiment of the present disclosure; Fig. 8 is a simulation graph illustrating detection of a DSET using the flip-flop for detecting signal distortion in high radiation environments, according to the further embodiment of the present disclosure; Fig. 9 is a block diagram illustrating an analog-to-digital converter that detects signal distortion in high radiation environments, according to an embodiment of the present disclosure; Fig. 10 is a circuit diagram illustrating a digital-to-analog converter unit and an analog single-event transient (ASET) detection unit of the analog-to-digital converter for detecting signal distortion in high-radiation environments, according to an embodiment of the present disclosure; and Fig. 11 is a simulation graph illustrating detection of an ASET using the analog-to-digital converter to detect signal distortion in high radiation environments, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Embodiments are not described in detail in the following descriptions, with reference to the accompanying drawings. Features of the present disclosure and their methods of carrying out the disclosure will be made clear by the following descriptions, with reference to the accompanying drawings. However, the embodiments may take various forms and should not be construed as limited to the description presented herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Accordingly, the scope of the present invention is to be defined by the following claims. Like reference numerals designate like elements throughout the present disclosure.

[0032] Fig. Figure 2 is a block diagram illustrating an apparatus 100 for detecting signal distortion in high-radiation environments according to an embodiment of the present disclosure. According to the embodiment of the present disclosure, the flip-flop 100 for detecting signal distortion in high-radiation environments includes a digital signal input terminal and a digital single-event transient (DSET) detection unit 110. Additionally, the flip-flop 100 may further include a signal distortion determination unit 120 and a rollback instruction unit 130.

[0033] In the following embodiments, the terms "unit," "section," "module," or "table," or the suffix "-er" or "-or" are used to refer to a software or hardware component, such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), that performs specific tasks. However, these terms are not limited to a software or hardware component. A component referred to by such a term may be configured to reside on an addressable storage medium or configured to execute one or more processors. Therefore, examples of such a component include software components, object-oriented software components, components such asInclude class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided in components and modules can be combined into fewer components and modules or further separated into additional components and modules. Additionally, the components and modules can be implemented to execute one or more CPUs (central processing units) in a device.

[0034] The DSET detection unit 110 detects whether digital signal information input through the signal input terminal is distorted. A digital signal input through the signal input terminal includes rising edge timing information and falling edge timing information. When a DSET occurs in the digital signal due to radiation, the timing information or magnitude information of the digital signal may be altered and sent to a subsequent register. The DSET detection unit 110 is used to detect whether either the rising edge timing information or the falling edge timing information of the digital signal is distorted.

[0035] In detail, the DSET detection unit 110 may include at least one of a first DSET detection section 112 and a second DSET detection section 114. When the DSET detection unit 110 includes both the first DSET detection section 112 and the second DSET detection section 114, the first DSET detection section 112 detects distortion in the rising edge timing information of the digital signal, and the second DSET detection section 114 detects distortion in the falling edge timing information of the digital signal.

[0036] When the first DSET detection section 112 detects distortion in the rising edge timing information of the digital signal, the first DSET detection section 112 outputs a first detection signal through a first output terminal. Additionally, when the second DSET detection section 114 detects distortion in the falling edge timing information of the digital signal, the second DSET detection section 114 outputs a second detection signal through a second output terminal. The first and second detection signals are sent to the signal distortion determination unit 120, and the signal distortion determination unit 120 determines, based on changes in the first and second detection signals, whether at least one of the rising edge timing information and the falling edge timing information of the digital signal is distorted.The signal distortion determining unit 120 sends determination results to the rollback instructing unit 130, and when the rollback instructing unit 130 receives determination results notifying that at least one of the rising edge timing information and the falling edge timing information of the digital signal is distorted, the rollback instructing unit 130 outputs a rollback signal for regenerating the digital signal.

[0037] Fig. 3 is a circuit diagram illustrating an input stage of a related art D flip-flop. Referring to a master latch section in the D flip-flop of Fig. 3, a first inverter applies a current to an inverter loop through a CMOS switch. Fig. 4 is a circuit diagram illustrating a DSET detection unit 110 of the flip-flop 100 for detecting signal distortion in high-radiation environments according to an embodiment of the present disclosure, in which a tri-state buffer replaces the first inverter and the CMOS switch of the related art flip-flop. Distortion in a digital signal caused by a DSET can be detected using a first detection signal and a second detection signal output from a first output terminal and a second output terminal, respectively.

[0038] The circuit diagram of the DSET detection unit 110 of the flip-flop 100 for detecting signal distortion in high-radiation environments will now be described in more detail according to the embodiment of the present disclosure. The first DSET detection section 112 may include a first transistor 1121 and a second transistor 1122, and the second DSET detection section 114 may include a third transistor 1141 and a fourth transistor 1142. The first DSET detection section 112 outputs a first detection signal through a first output terminal 1125, and the second DSET detection section 114 outputs a second detection signal through a second output terminal 1145.

[0039] Referring to Fig. 4, in the circuit of the flip-flop 100 for detecting signal distortion in high-radiation environments according to the embodiment of the present disclosure, the first transistor 1121 and the second transistor 1122 may be P-type field-effect transistors, and the third transistor 1141 and the fourth transistor 1142 may be N-type field-effect transistors. In this case, a digital signal may be input to the gates of the second transistor 1122 and the third transistor 1141, a clock signal may be input to the gate of the first transistor 1121, and the inverse of the clock signal input to the gate of the first transistor 1121 may be input to the gate of the fourth transistor 1142.Additionally, the first output terminal 1125 may be connected to a drain of the first transistor 1121 and a source of the second transistor 1122, and the second output terminal 1145 may be connected to a source of the third transistor 1141 and a drain of the fourth transistor 1142. Furthermore, a capacitor 1126, 1146 may be connected to each output terminal 1125, 1145 to protect against a large amount of charge induced by high-energy radiation.

[0040] Fig. 5 is a simulation graph illustrating detection of DSETs using flip-flop 100 for detecting signal distortion in high radiation environments according to an embodiment of the present disclosure. Fig. 5 illustrates waveforms A to G. Waveform A is a clock waveform input to the DSET detection unit 110, and waveform B is a digital signal D input to a signal input terminal 1101.

[0041] According to a given operation timing, a rising edge or a falling edge occurs in the digital signal D input through the signal input terminal 1101 when the clock waveform A is at a low level. For example, a first rising edge 1 occurs in the waveform B when the waveform A is at a low level, and thus, this rising edge timing information is correct timing information that does not include radiation-induced DSET errors.

[0042] However, a falling edge 2 and a rising edge 3 occur when the clock waveform A is at a high level. This means that despite an intention to input these edges, when the clock waveform A is at a low level, rising edge timing information or falling edge timing information of the digital signal D is / becomes distorted by radiation-induced DSET errors. When the rising edge timing information or falling edge timing information of a digital signal is / becomes distorted as described above, a flip-flop of the related art cannot detect such signal distortion caused by DSET errors. Although a different method is used to detect signal distortion, technical problems are caused as described above in the description of the technical background of the present disclosure.

[0043] However, according to the present disclosure, distortion of falling edge timing information of a digital signal is detected using a first digital signal VVDD (see Fig. 4). When falling edge timing information of the digital signal is / becomes distorted (the falling edge 2 in waveform B), the DSET detection unit 110 of the embodiment outputs a first detection signal VVDD to the signal distortion determination unit 120. Referring to the circuit of the Fig. In the DSET detection unit 110 shown in Figure 4, the first detection signal VVDD is output at a high level as a default state, and when a signal distortion (the falling edge 2 in waveform B) occurs due to a DSET, the first detection signal VVDD changes instantaneously or momentarily to a low level. This is confirmed in the Fig. 5. In addition, capacitor 1126 protects the VVDD signal from a large amount of charge induced by high-energy radiation.

[0044] According to the present disclosure, a distortion of rising edge timing information of a digital signal is similarly detected using a second digital signal VVSS (see Fig. 4). When rising edge timing information of the digital signal is / becomes distorted (the rising edge 3 in waveform B), the DSET detection unit 110 of the embodiment outputs a second detection signal VVSS to the signal distortion determination unit 120. Referring to the circuit of the Fig. 4, the second detection signal VVSS is output at a low level as a default state, and when a signal distortion (the rising edge 3 in waveform B) occurs due to a DSET, the second detection signal VVSS changes instantaneously or momentarily to a high level. This is confirmed in the Fig. 5. In addition, capacitor 1146 protects the VVSS signal from a large amount of charge induced by high-energy radiation.

[0045] As described above, the signal distortion determining unit 120 determines whether at least one of the rising edge timing information or the falling edge timing information of the digital signal is / becomes distorted based on changes in the first detection signal VVDD or the second detection signal VVSS. Referring to the simulation graph of Fig. 5, for example, the signal distortion determination unit 120 may determine that two errors have occurred, as shown in waveform G. These two errors concern the falling edge 2 and the rising edge 3 of waveform B.

[0046] The rollback instruction unit 130 outputs a rollback signal for instructing regeneration of the digital signal according to results of determination by the signal distortion determination unit 120.

[0047] Fig. 6 is a block diagram illustrating an apparatus 200 that detects signal distortion in high radiation environments, according to another embodiment of the present disclosure.

[0048] According to the embodiment of the present disclosure, the flip-flop 200 for detecting signal distortion in high-radiation environments includes a signal input terminal and a single-event upset detection unit (SEU detection unit) 210. Additionally, the flip-flop 200 may further include a signal distortion determination unit 220 and a rollback instruction unit 230. The SEU detection unit 210 includes a logic gate 214 and an inverter loop 212 and detects whether a digital signal input through the signal input terminal is / becomes distorted. SEU refers to information distortion occurring in a digital circuit and may occur when a stored digital value is / becomes altered by radiation incident on an inverter loop of a flip-flop used as a register. Since the position of a flip-flop in which an SEU occurs is close to the most significant bit (MSB), a larger error is generated.

[0049] Fig. 7 is a diagram illustrating a circuit of the SEU detection unit 210 of the flip-flop 200 for detecting signal distortion in high-radiation environments according to another embodiment of the present disclosure. In the flip-flop 200 for detecting signal distortion in high-radiation environments according to the embodiment of the present disclosure, the logic gate 214 of the SEU detection unit 210 may include a logic gate 214, and the inverter loop 212 of the SEU detection unit 210 may include a first inverter 2121 and a second inverter 2122. Additionally, two capacitors 2123, 2124 on the inverter loop may inhibit or prevent flipping of logic values.

[0050] Logic gate 214 receives final signals through both a first input terminal and a second input terminal. The first input terminal of logic gate 214 can be connected to an input terminal of first inverter 2121 and an output terminal of second inverter 2122, and the second input terminal of logic gate 214 can be connected to an output terminal of first inverter 2121 and an input terminal of second inverter 2122.

[0051] The signal distortion determination unit 220 determines whether signal distortion is caused by radiation based on a detection signal output from the logic gate 214. The rollback instruction unit 230 outputs a rollback signal for instructing regeneration of a digital signal according to the results of a determination performed by the signal distortion determination unit 220.

[0052] Fig. Figure 8 is a simulation graph illustrating detection of a DSET using flip-flop 200 for detecting signal distortion in high radiation environments according to another embodiment of the present disclosure. Fig. 7, nodes A and B always have opposite logical values. However, when a charge is induced by incident radiation, nodes A and B may momentarily have logical values ​​(1, 1), and logic gate 214 may therefore output 0.

[0053] In Fig. 8, waveforms C and D are waveforms measured at nodes A and B, respectively, and nodes A and B both have a high level for a moment during a period of time (t) due to a charge induced by SEU. Accordingly, as shown by waveform B in Fig. 8, a detection signal output from logic gate 214 is momentarily low. This change in the detection signal is transmitted to signal distortion determination unit 220. Subsequently, signal distortion determination unit 220 detects that signal distortion has occurred due to SEU, and rollback instruction unit 230 outputs a rollback signal for instructing regeneration of a digital signal based on the results of a determination made by signal distortion determination unit 220.

[0054] Fig. 9 is a block diagram illustrating an analog-to-digital converter 300 that detects signal distortion in high radiation environments, according to an embodiment of the present disclosure, and Fig. 10 is a circuit diagram illustrating a digital-to-analog converter unit 310 and an analog single-event transient (ASET) detection unit 320 of the analog-to-digital converter 300 for detecting signal distortion in high radiation environments according to an embodiment of the present disclosure.

[0055] According to the embodiment of the present disclosure, the analog-to-digital converter 300 for detecting signal distortion in high-radiation environments includes the digital-to-analog conversion unit 310 and the ASET detection unit 320. In addition, the analog-to-digital converter 300 may further include a signal distortion determination unit 330, a rollback instruction unit 340, and a successive approximation register (SAR) logic unit 350. The digital-to-analog conversion unit 310 may include a first digital-to-analog conversion section 312 and a second digital-to-analog conversion section 314, and the ASET detection unit 320 may include a first comparator 322 and a second comparator 324.

[0056] According to the embodiment of the present disclosure, the analog-to-digital converter 300 for detecting signal distortion in high-radiation environments essentially consists of the digital-to-analog converter unit 310 and the two comparators 322 and 324. In detail, two signals output from the first digital-to-analog converter section 312 and the second digital-to-analog converter section 314, respectively, are fully inverted analog signals unless distorted by an ASET. The two signals are input to the ASET detection unit 320 as a first input signal and a second input signal, respectively.

[0057] The ASET detection unit 320 compares a preset reference signal with each of the first and second input signals and outputs the comparison results. Specifically, the first comparator 322 outputs a first output signal by comparing the first input signal with the preset reference signal, and the second comparator 324 outputs a second output signal by comparing the second input signal with the preset reference signal.

[0058] In a general SAR analog-to-digital converter (SAR-ADC), values ​​from two internal digital-to-analog converters (DACs) are input as two input values ​​of a comparator and processed. In this case, however, signal distortion caused by an ASET in the DAC may not be detected. However, according to the present disclosure, an additional reference signal is provided to the ASET detection unit 320, and the first comparator 322 and the second comparator 324 compare a first input signal and a second input signal with the preset reference signal. The ASET detection unit 320 outputs the comparison result values ​​to the signal distortion determination unit 330 as a first output signal and a second output signal.

[0059] According to this aspect of the present disclosure, it is possible to detect whether signal distortion is caused by an ASET using the first and second output signals output by the ASET detection unit 320. This means that the first and second output signals have the same value when signal distortion is not caused by an ASET. However, when one of the first digital-to-analog converter section 312 and the second digital-to-analog converter section 314 is subject to signal distortion due to an ASET, the first and second output signals have different values.

[0060] Fig. 11 is a simulation graph illustrating detection of an ASET using the analog-to-digital converter 300 for detecting signal distortion in high-radiation environments according to an embodiment of the present disclosure. In Fig. Figure 11 shows a first output signal (solid line) and a second output signal (dashed line). An ASET occurs at approximately 1.0 microseconds (1.0 µs), and the first output signal (solid line) and the second output signal (dashed line) have different values ​​after the ASET.

[0061] The signal distortion determination unit 330 compares the first and second output signals to determine whether signal distortion is caused by radiation. If the first and second output signals have different values, the signal distortion determination unit 330 sends a signal to the rollback instruction unit 340 to report this difference, and the rollback instruction unit 340 outputs a rollback signal to instruct regeneration of a digital signal.

[0062] It is more difficult to detect a radiation-induced fault in an analog circuit than in a digital circuit. In particular, in a pipeline-type analog-to-digital converter circuit, comparatively many analog components such as amplifiers and comparators are distributed, so the area of ​​analog circuit sections is large, making fault detection difficult. In the above description, a SAR-ADC was described as an example, and since the area of ​​analog circuit sections in the SAR-ADC is small, the probability of ASET may be low. The analog-to-digital converter 300 that detects signal distortion in high-radiation environments according to the embodiment of the present disclosure is not limited to the SAR-ADC.However, if the analog-to-digital converter 300 that detects signal distortion in high-radiation environments according to the embodiment of the present disclosure is a SAR ADC, the analog-to-digital converter may further include the SAR logic unit 350 capable of detecting whether the digital signal information input to the SAR logic unit 350 is / becomes distorted due to DSET or SEU. That is, the SAR logic unit 350 may include the DSET detection unit 110 and the SEU detection unit 210 shown in FIG. Fig. 2 and Fig. 6, may include. In this case, the method of detecting whether an input digital signal is / becomes distorted due to a DSET or SEU will be described in detail with reference to the accompanying drawings such as. Fig. 2 and 4 to 8, a detailed description of these will not be given here.

[0063] As described above, the flip-flop and analog-to-digital converter of the exemplary embodiments of the present disclosure can individually detect DSETs, ASETs, and SEUs and correct corresponding data. In other words, the flip-flop and analog-to-digital converter can be applied to a digital circuit that uses a flip-flop to detect radiation-induced changes in signals and information and regenerate a corresponding digital code using a rollback system.

[0064] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims. The exemplary embodiments are to be considered in a descriptive sense only and not for purposes of limitation. Accordingly, the scope of the invention is defined not by the detailed description, but by the appended claims.

Claims

[1] A device (100) detecting signal distortion in high radiation environments, the device (100) comprising: a signal input terminal (1101) receiving a digital signal; and a digital single-event transient detection unit (110) (DSET detection unit) detecting whether information of the digital signal input through the signal input terminal (1101) is / becomes distorted, wherein the DSET detection unit (110) comprises a first output terminal (1125) through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted, wherein the DSET detection unit (110) further includes a second output terminal (1145) through which a second detection signal is output, the first detection signal being used to determine whether the falling edge timing information of the digital signal is distorted, and the second detection signal being used to determine whether the rising edge timing information of the digital signal is distorted, wherein the DSET detection unit (110) comprises: a first DSET detection section (112) comprising a first transistor (1121), a second transistor (1122) and a capacitor (1126; 1146); and a second DSET detection section (114) comprising a third transistor (1141), a fourth transistor (1142) and a capacitor (1126; 1146), wherein the first DSET detection section (112) outputs the first detection signal through the first output terminal (1125), and the second DSET detection section (114) outputs the second detection signal through the second output terminal (1145). [2] The apparatus (100;) according to claim 1, further comprising a signal distortion determining unit (120;) determining whether at least one of the rising edge timing information and the falling edge timing information of the digital signal is / becomes distorted based on changes in the first detection signal or the second detection signal. [3] The apparatus (100) according to claim 2, further comprising a rollback instructing unit (130;) instructing regeneration of the digital signal according to results of the determination performed by the signal distortion determining unit (120;). [4] The device (100;) of claim 1, wherein the first transistor (1121) and the second transistor (1122) are P-type field effect transistors, the third transistor (1141) and the fourth transistor (1142) are N-type field-effect transistors, the digital signal is input to gates of the second and third transistors (1122, 1141), and a clock signal is input to a gate of the first transistor (1121), and an inverse clock signal is input to a gate of the fourth transistor (1142). [5] The device (100) according to claim 4, wherein the first output terminal (1125) is connected to a drain of the first transistor (1121) and a source of the second transistor (1122), and the first detection signal has a high level as a default value. [6] The device (100) according to claim 4, wherein the second output terminal (1145) is connected to a source of the third transistor (1141) and a drain of the fourth transistor (1142), and the second detection signal has a low level as a default value. [7] A device (200) detecting signal distortion in high radiation environments, the device (200) comprising: a signal input terminal receiving a digital signal; and a single-event upset detection unit (210) (SEU detection unit) detecting whether information of the digital signal input through the signal input terminal is / becomes distorted, wherein the SEU detection unit (210) comprises a logic gate (214; 2140), capacitors (2123, 2124) and further an inverter loop (212), wherein the logic gate (214; 2140) receives both end signals of the inverter loop (212) through a first input terminal and a second input terminal, respectively, wherein the inverter loop (212) comprises a first inverter (2121) and a second inverter (2122), wherein the first input terminal of the logic gate (214; 2140) is connected to an input terminal of the first inverter (2121) and an output terminal (A; B) of the second inverter (2122), and the second input terminal of the logic gate (214; 2140) is connected to an output terminal (A; B) of the first inverter (2121) and an input terminal of the second inverter (2122). [8] The device (200) of claim 7, further comprising: a signal distortion determining unit (220) determining, based on a detection signal output from a logic gate (214), whether signal distortion is caused by radiation; and a rollback instructing unit (230) instructing regeneration of the digital signal according to results of the determination performed by the signal distortion determining unit (220). [9] The device (200) according to claim 7, wherein the SEU detection unit (210) further comprises an inverter loop (212), wherein two capacitors (2123; 2124) at both end signals of the inverter loop (212) can inhibit or prevent a flipping of logic values. [10] Analog-to-digital converter (300) detecting signal distortion in high radiation environments, the analog-to-digital converter (300) comprising: a first digital-to-analog converter section (312); a second digital-to-analog converter section (314); and an analog single-event transient detection unit (320) (ASET detection unit) receiving output signals of the first and second digital-to-analog converter sections (312, 314) as a first input signal and a second input signal, respectively, wherein the ASET detection unit (320) compares each of the first and second input signals with a preset reference signal. [11] Analog-to-digital converter (300) according to claim 10, wherein the ASET detection unit (320) comprises: a first comparator (322) outputting a first output signal by comparing the first input signal with the reference signal; and a second comparator (324) outputting a second output signal by comparing the second input signal with the reference signal. [12] Analog-to-digital converter (300) according to claim 11, further comprising: a signal distortion determining unit (330) comparing the first output signal with the second output signal to determine whether signal distortion is caused by radiation; and a rollback instructing unit (340) instructing regeneration of a digital signal according to results of the determination performed by the signal distortion determining unit (330). [13] The analog-to-digital converter (300) of claim 10, further comprising a successive approximation register (SAR) logic unit (350), wherein the SAR logic unit (350) detects whether digital signal information input to the SAR logic unit (350) is / becomes distorted by a DSET or SEU.

Images